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| author | michael-west <michael.west@ettus.com> | 2014-09-25 15:46:52 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2014-09-25 17:12:14 -0700 |
| commit | b765df3b1976f30a8b95f5a1ea482517a8000a80 (patch) | |
| tree | 140547343209e14d49ed5aa88369e7d44c3f2298 /fpga/usrp1 | |
| parent | d4f487af3fc04a4cd3685f454988f86650e2ef46 (diff) | |
| download | uhd-b765df3b1976f30a8b95f5a1ea482517a8000a80.tar.gz uhd-b765df3b1976f30a8b95f5a1ea482517a8000a80.tar.bz2 uhd-b765df3b1976f30a8b95f5a1ea482517a8000a80.zip | |
x300: added reset and resync of ADCs and DACs when changing reference clock
Diffstat (limited to 'fpga/usrp1')
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