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| author | Thomas Tsou <ttsou@vt.edu> | 2010-08-16 17:03:06 -0700 |
|---|---|---|
| committer | Thomas Tsou <ttsou@vt.edu> | 2010-08-16 18:42:58 -0700 |
| commit | 43e5480dee9f6068ffe84bf1b86526189043ee87 (patch) | |
| tree | aae8369b8f3fea9ec1a987ca05bdaffc8cebcb3e /fpga/usrp1/toplevel | |
| parent | cc6bbf949f8e4eabefdccf8d8cc4d9ed803ce40e (diff) | |
| download | uhd-43e5480dee9f6068ffe84bf1b86526189043ee87.tar.gz uhd-43e5480dee9f6068ffe84bf1b86526189043ee87.tar.bz2 uhd-43e5480dee9f6068ffe84bf1b86526189043ee87.zip | |
usrp1: Remove hard coded clock values
Get clock values from clock control, where the master setting lives.
Diffstat (limited to 'fpga/usrp1/toplevel')
0 files changed, 0 insertions, 0 deletions