Removed copy of FPGA source files.

1 files changed, 0 insertions, 160 deletions

diff --git a/fpga/usrp1/toplevel/sizetest/sizetest.csf b/fpga/usrp1/toplevel/sizetest/sizetest.csf
deleted file mode 100644
index 4b724e7f5..000000000
--- a/fpga/usrp1/toplevel/sizetest/sizetest.csf
+++ /dev/null
@@ -1,160 +0,0 @@
-COMPILER_SETTINGS
-{
-	IO_PLACEMENT_OPTIMIZATION = OFF;
-	ENABLE_DRC_SETTINGS = OFF;
-	PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF;
-	PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF;
-	PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF;
-	DRC_FANOUT_EXCEEDING = 30;
-	DRC_REPORT_FANOUT_EXCEEDING = OFF;
-	DRC_TOP_FANOUT = 50;
-	DRC_REPORT_TOP_FANOUT = OFF;
-	RUN_DRC_DURING_COMPILATION = OFF;
-	ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON;
-	ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF;
-	ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF;
-	ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF;
-	SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF;
-	MERGE_HEX_FILE = OFF;
-	TRUE_WYSIWYG_FLOW = OFF;
-	SEED = 1;
-	FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY;
-	FAMILY = Cyclone;
-	DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
-	DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
-	DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
-	DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
-	DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1";
-	DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1";
-	DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
-	DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
-	DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
-	DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
-	DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
-	DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
-	DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
-	DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
-	DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
-	DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB";
-	DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3";
-	DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
-	DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
-	DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4";
-	DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3";
-	DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS";
-	DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS";
-	DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS";
-	STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
-	PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
-	PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2";
-	STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1";
-	FAST_FIT_COMPILATION = OFF;
-	SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF;
-	OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = OFF;
-	OPTIMIZE_TIMING = OFF;
-	OPTIMIZE_HOLD_TIMING = OFF;
-	COMPILATION_LEVEL = FULL;
-	SAVE_DISK_SPACE = ON;
-	SPEED_DISK_USAGE_TRADEOFF = NORMAL;
-	LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF;
-	SIGNALPROBE_ALLOW_OVERUSE = OFF;
-	FOCUS_ENTITY_NAME = |sizetest;
-	FIT_ONLY_ONE_ATTEMPT = OFF;
-}
-DEFAULT_DEVICE_OPTIONS
-{
-	GENERATE_CONFIG_HEXOUT_FILE = OFF;
-	GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON;
-	GENERATE_CONFIG_JBC_FILE = OFF;
-	GENERATE_CONFIG_JAM_FILE = OFF;
-	GENERATE_CONFIG_ISC_FILE = OFF;
-	GENERATE_CONFIG_SVF_FILE = OFF;
-	GENERATE_JBC_FILE_COMPRESSED = ON;
-	GENERATE_JBC_FILE = OFF;
-	GENERATE_JAM_FILE = OFF;
-	GENERATE_ISC_FILE = OFF;
-	GENERATE_SVF_FILE = OFF;
-	RESERVE_PIN = "AS INPUT TRI-STATED";
-	RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND";
-	HEXOUT_FILE_COUNT_DIRECTION = UP;
-	HEXOUT_FILE_START_ADDRESS = 0;
-	GENERATE_HEX_FILE = OFF;
-	GENERATE_RBF_FILE = OFF;
-	GENERATE_TTF_FILE = OFF;
-	RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
-	RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED";
-	RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO";
-	RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO";
-	RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO";
-	DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF;
-	AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
-	EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
-	FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
-	MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
-	STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
-	APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
-	STRATIX_CONFIGURATION_DEVICE = AUTO;
-	CYCLONE_CONFIGURATION_DEVICE = AUTO;
-	FLEX10K_CONFIGURATION_DEVICE = AUTO;
-	FLEX6K_CONFIGURATION_DEVICE = AUTO;
-	MERCURY_CONFIGURATION_DEVICE = AUTO;
-	EXCALIBUR_CONFIGURATION_DEVICE = AUTO;
-	APEX20K_CONFIGURATION_DEVICE = AUTO;
-	USE_CONFIGURATION_DEVICE = ON;
-	ENABLE_INIT_DONE_OUTPUT = OFF;
-	FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
-	ENABLE_DEVICE_WIDE_OE = OFF;
-	ENABLE_DEVICE_WIDE_RESET = OFF;
-	RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
-	AUTO_RESTART_CONFIGURATION = OFF;
-	ENABLE_VREFB_PIN = OFF;
-	ENABLE_VREFA_PIN = OFF;
-	SECURITY_BIT = OFF;
-	USER_START_UP_CLOCK = OFF;
-	APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
-	FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
-	FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
-	MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
-	EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
-	CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL";
-	STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
-	APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
-	STRATIX_UPDATE_MODE = STANDARD;
-	USE_CHECKSUM_AS_USERCODE = OFF;
-	MAX7000_USE_CHECKSUM_AS_USERCODE = OFF;
-	MAX7000_JTAG_USER_CODE = FFFFFFFF;
-	FLEX10K_JTAG_USER_CODE = 7F;
-	MERCURY_JTAG_USER_CODE = FFFFFFFF;
-	APEX20K_JTAG_USER_CODE = FFFFFFFF;
-	STRATIX_JTAG_USER_CODE = FFFFFFFF;
-	MAX7000S_JTAG_USER_CODE = FFFF;
-	RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO";
-	FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
-	FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
-	ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
-	MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
-	ENABLE_JTAG_BST_SUPPORT = OFF;
-	CONFIGURATION_CLOCK_DIVISOR = 1;
-	CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ";
-	CLOCK_SOURCE = INTERNAL;
-	COMPRESSION_MODE = OFF;
-	ON_CHIP_BITSTREAM_DECOMPRESSION = OFF;
-}
-AUTO_SLD_HUB_ENTITY
-{
-	AUTO_INSERT_SLD_HUB_ENTITY = ENABLE;
-	HUB_INSTANCE_NAME = SLD_HUB_INST;
-	HUB_ENTITY_NAME = SLD_HUB;
-}
-CHIP(sizetest)
-{
-	DEVICE = EP1C12Q240C8;
-	DEVICE_FILTER_PACKAGE = "ANY QFP";
-	DEVICE_FILTER_PIN_COUNT = 240;
-	DEVICE_FILTER_SPEED_GRADE = ANY;
-}
-SIGNALTAP_LOGIC_ANALYZER_SETTINGS
-{
-	ENABLE_SIGNALTAP = Off;
-	AUTO_ENABLE_SMART_COMPILE = On;
-}