diff options
| author | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
| commit | fd3e84941de463fa1a7ebab0a69515b4bf2614cd (patch) | |
| tree | 3fa721a13d41d2c0451d663a59a220a38fd5e614 /fpga/usrp1/toplevel/mrfm | |
| parent | 3b66804e41891e358c790b453a7a59ec7462dba4 (diff) | |
| download | uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.gz uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.bz2 uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.zip | |
Removed copy of FPGA source files.
Diffstat (limited to 'fpga/usrp1/toplevel/mrfm')
| -rw-r--r-- | fpga/usrp1/toplevel/mrfm/.gitignore | 17 | ||||
| -rw-r--r-- | fpga/usrp1/toplevel/mrfm/biquad_2stage.v | 131 | ||||
| -rw-r--r-- | fpga/usrp1/toplevel/mrfm/biquad_6stage.v | 137 | ||||
| -rw-r--r-- | fpga/usrp1/toplevel/mrfm/mrfm.csf | 444 | ||||
| -rw-r--r-- | fpga/usrp1/toplevel/mrfm/mrfm.esf | 14 | ||||
| -rw-r--r-- | fpga/usrp1/toplevel/mrfm/mrfm.psf | 312 | ||||
| -rw-r--r-- | fpga/usrp1/toplevel/mrfm/mrfm.py | 129 | ||||
| -rw-r--r-- | fpga/usrp1/toplevel/mrfm/mrfm.qpf | 29 | ||||
| -rw-r--r-- | fpga/usrp1/toplevel/mrfm/mrfm.qsf | 411 | ||||
| -rw-r--r-- | fpga/usrp1/toplevel/mrfm/mrfm.v | 199 | ||||
| -rw-r--r-- | fpga/usrp1/toplevel/mrfm/mrfm.vh | 21 | ||||
| -rw-r--r-- | fpga/usrp1/toplevel/mrfm/mrfm_compensator.v | 80 | ||||
| -rwxr-xr-x | fpga/usrp1/toplevel/mrfm/mrfm_fft.py | 319 | ||||
| -rw-r--r-- | fpga/usrp1/toplevel/mrfm/mrfm_proc.v | 96 | ||||
| -rw-r--r-- | fpga/usrp1/toplevel/mrfm/shifter.v | 106 |
15 files changed, 0 insertions, 2445 deletions
diff --git a/fpga/usrp1/toplevel/mrfm/.gitignore b/fpga/usrp1/toplevel/mrfm/.gitignore deleted file mode 100644 index fe06aad0d..000000000 --- a/fpga/usrp1/toplevel/mrfm/.gitignore +++ /dev/null @@ -1,17 +0,0 @@ -/*.qws -/*.eqn -/*.done -/*.htm -/*.rpt -/*.ini -/*.fsf -/*.jam -/*.jbc -/*.pin -/*.pof -/*.sof -/*.rbf -/*.ttf -/*.summary -/a.out -/db diff --git a/fpga/usrp1/toplevel/mrfm/biquad_2stage.v b/fpga/usrp1/toplevel/mrfm/biquad_2stage.v deleted file mode 100644 index 9b769014d..000000000 --- a/fpga/usrp1/toplevel/mrfm/biquad_2stage.v +++ /dev/null @@ -1,131 +0,0 @@ -`include "mrfm.vh" - -module biquad_2stage (input clock, input reset, input strobe_in, - input serial_strobe, input [6:0] serial_addr, input [31:0] serial_data, - input wire [15:0] sample_in, output reg [15:0] sample_out, output wire [63:0] debugbus); - - wire [3:0] coeff_addr, coeff_wr_addr; - wire [3:0] data_addr, data_wr_addr; - reg [3:0] cur_offset, data_addr_int, data_wr_addr_int; - - wire [15:0] coeff, coeff_wr_data, data, data_wr_data; - wire coeff_wr; - reg data_wr; - - wire [30:0] product; - wire [33:0] accum; - wire [15:0] scaled_accum; - - wire [7:0] shift; - reg [3:0] phase; - wire enable_mult, enable_acc, latch_out, select_input; - reg done, clear_acc; - - setting_reg #(`FR_MRFM_IIR_COEFF) sr_coeff(.clock(clock),.reset(reset), - .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out({coeff_wr_addr,coeff_wr_data}),.changed(coeff_wr)); - - setting_reg #(`FR_MRFM_IIR_SHIFT) sr_shift(.clock(clock),.reset(reset), - .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out(shift),.changed()); - - ram16 coeff_ram(.clock(clock),.write(coeff_wr),.wr_addr(coeff_wr_addr),.wr_data(coeff_wr_data), - .rd_addr(coeff_addr),.rd_data(coeff)); - - ram16 data_ram(.clock(clock),.write(data_wr),.wr_addr(data_wr_addr),.wr_data(data_wr_data), - .rd_addr(data_addr),.rd_data(data)); - - mult mult (.clock(clock),.x(data),.y(coeff),.product(product),.enable_in(enable_mult),.enable_out() ); - - acc acc (.clock(clock),.reset(reset),.clear(clear_acc),.enable_in(enable_acc),.enable_out(), - .addend(product),.sum(accum) ); - - shifter shifter (.in(accum),.out(scaled_accum),.shift(shift)); - - assign data_wr_data = select_input ? sample_in : scaled_accum; - assign enable_mult = 1'b1; - - always @(posedge clock) - if(reset) - cur_offset <= #1 4'd0; - else if(latch_out) - cur_offset <= #1 cur_offset + 4'd1; - - assign data_addr = data_addr_int + cur_offset; - assign data_wr_addr = data_wr_addr_int + cur_offset; - - always @(posedge clock) - if(reset) - done <= #1 1'b0; - else if(latch_out) - done <= #1 1'b1; - else if(strobe_in) - done <= #1 1'b0; - - always @(posedge clock) - if(reset) - phase <= #1 4'd0; - else if(strobe_in) - phase <= #1 4'd0; - else if(!done) - phase <= #1 phase + 4'd1; - - assign coeff_addr = phase; - - always @(phase) - case(phase) - 4'd01 : data_addr_int = 4'd00; 4'd02 : data_addr_int = 4'd01; 4'd03 : data_addr_int = 4'd02; - 4'd04 : data_addr_int = 4'd03; 4'd05 : data_addr_int = 4'd04; - - 4'd07 : data_addr_int = 4'd03; 4'd08 : data_addr_int = 4'd04; 4'd09 : data_addr_int = 4'd05; - 4'd10 : data_addr_int = 4'd06; 4'd11 : data_addr_int = 4'd07; - default : data_addr_int = 4'd00; - endcase // case(phase) - - always @(phase) - case(phase) - 4'd0 : data_wr_addr_int = 4'd2; - 4'd8 : data_wr_addr_int = 4'd5; - 4'd14 : data_wr_addr_int = 4'd8; - default : data_wr_addr_int = 4'd0; - endcase // case(phase) - - always @(phase) - case(phase) - 4'd0, 4'd8, 4'd14 : data_wr = 1'b1; - default : data_wr = 1'b0; - endcase // case(phase) - - assign select_input = (phase == 4'd0); - - always @(phase) - case(phase) - 4'd0, 4'd1, 4'd2, 4'd3, 4'd9, 4'd15 : clear_acc = 1'd1; - default : clear_acc = 1'b0; - endcase // case(phase) - - assign enable_acc = ~clear_acc; - assign latch_out = (phase == 4'd14); - - always @(posedge clock) - if(reset) - sample_out <= #1 16'd0; - else if(latch_out) - sample_out <= #1 scaled_accum; - - //////////////////////////////////////////////////////// - // Debug - - wire [3:0] debugmux; - - setting_reg #(`FR_MRFM_DEBUG) sr_debugmux(.clock(clock),.reset(reset), - .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out(debugmux),.changed()); - - assign debugbus[15:0] = debugmux[0] ? {coeff_addr,data_addr,data_wr_addr,cur_offset} : {phase,data_addr_int,data_wr_addr_int,cur_offset}; - assign debugbus[31:16] = debugmux[1] ? scaled_accum : {clock, strobe_in, data_wr, enable_mult, enable_acc, clear_acc, latch_out,select_input,done, data_addr_int}; - assign debugbus[47:32] = debugmux[2] ? sample_out : coeff; - assign debugbus[63:48] = debugmux[3] ? sample_in : data; - -endmodule // biquad_2stage - diff --git a/fpga/usrp1/toplevel/mrfm/biquad_6stage.v b/fpga/usrp1/toplevel/mrfm/biquad_6stage.v deleted file mode 100644 index 2b0c511ce..000000000 --- a/fpga/usrp1/toplevel/mrfm/biquad_6stage.v +++ /dev/null @@ -1,137 +0,0 @@ -`include "mrfm.vh" - -module mrfm_iir (input clock, input reset, input strobe_in, - input serial_strobe, input [6:0] serial_addr, input [31:0] serial_data, - input wire [15:0] sample_in, output reg [15:0] sample_out); - - wire [5:0] coeff_addr, coeff_wr_addr; - wire [4:0] data_addr, data_wr_addr; - reg [4:0] cur_offset, data_addr_int, data_wr_addr_int; - - wire [15:0] coeff, coeff_wr_data, data, data_wr_data; - wire coeff_wr; - reg data_wr; - - wire [30:0] product; - wire [33:0] accum; - wire [15:0] scaled_accum; - - wire [7:0] shift; - reg [5:0] phase; - wire enable_mult, enable_acc, latch_out, select_input; - reg done, clear_acc; - - setting_reg #(`FR_MRFM_IIR_COEFF) sr_coeff(.clock(clock),.reset(reset), - .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out({coeff_wr_addr,coeff_wr_data}),.changed(coeff_wr)); - - setting_reg #(`FR_MRFM_IIR_SHIFT) sr_shift(.clock(clock),.reset(reset), - .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out(shift),.changed()); - - ram64 coeff_ram(.clock(clock),.write(coeff_wr),.wr_addr(coeff_wr_addr),.wr_data(coeff_wr_data), - .rd_addr(coeff_addr),.rd_data(coeff)); - - ram32 data_ram(.clock(clock),.write(data_wr),.wr_addr(data_wr_addr),.wr_data(data_wr_data), - .rd_addr(data_addr),.rd_data(data)); - - mult mult (.clock(clock),.x(data),.y(coeff),.product(product),.enable_in(enable_mult),.enable_out() ); - - acc acc (.clock(clock),.reset(reset),.clear(clear_acc),.enable_in(enable_acc),.enable_out(), - .addend(product),.sum(accum) ); - - shifter shifter (.in(accum),.out(scaled_accum),.shift(shift)); - - assign data_wr_data = select_input ? sample_in : scaled_accum; - assign enable_mult = 1'b1; - - always @(posedge clock) - if(reset) - cur_offset <= #1 5'd0; - else if(latch_out) - cur_offset <= #1 cur_offset + 5'd1; - - assign data_addr = data_addr_int + cur_offset; - assign data_wr_addr = data_wr_addr_int + cur_offset; - - always @(posedge clock) - if(reset) - done <= #1 1'b0; - else if(latch_out) - done <= #1 1'b1; - else if(strobe_in) - done <= #1 1'b0; - - always @(posedge clock) - if(reset) - phase <= #1 6'd0; - else if(strobe_in) - phase <= #1 6'd0; - else if(!done) - phase <= #1 phase + 6'd1; - - always @(phase) - case(phase) - 6'd0 : data_addr_int = 5'd0; - default : data_addr_int = 5'd0; - endcase // case(phase) - - assign coeff_addr = phase; - - always @(phase) - case(phase) - 6'd01 : data_addr_int = 5'd00; 6'd02 : data_addr_int = 5'd01; 6'd03 : data_addr_int = 5'd02; - 6'd04 : data_addr_int = 5'd03; 6'd05 : data_addr_int = 5'd04; - - 6'd07 : data_addr_int = 5'd03; 6'd08 : data_addr_int = 5'd04; 6'd09 : data_addr_int = 5'd05; - 6'd10 : data_addr_int = 5'd06; 6'd11 : data_addr_int = 5'd07; - - 6'd13 : data_addr_int = 5'd06; 6'd14 : data_addr_int = 5'd07; 6'd15 : data_addr_int = 5'd08; - 6'd16 : data_addr_int = 5'd09; 6'd17 : data_addr_int = 5'd10; - - 6'd19 : data_addr_int = 5'd09; 6'd20 : data_addr_int = 5'd10; 6'd21 : data_addr_int = 5'd11; - 6'd22 : data_addr_int = 5'd12; 6'd23 : data_addr_int = 5'd13; - - 6'd25 : data_addr_int = 5'd12; 6'd26 : data_addr_int = 5'd13; 6'd27 : data_addr_int = 5'd14; - 6'd28 : data_addr_int = 5'd15; 6'd29 : data_addr_int = 5'd16; - - 6'd31 : data_addr_int = 5'd15; 6'd32 : data_addr_int = 5'd16; 6'd33 : data_addr_int = 5'd17; - 6'd34 : data_addr_int = 5'd18; 6'd35 : data_addr_int = 5'd19; - - default : data_addr_int = 5'd00; - endcase // case(phase) - - always @(phase) - case(phase) - 6'd0 : data_wr_addr_int = 5'd2; - 6'd8 : data_wr_addr_int = 5'd5; - 6'd14 : data_wr_addr_int = 5'd8; - 6'd20 : data_wr_addr_int = 5'd11; - 6'd26 : data_wr_addr_int = 5'd14; - 6'd32 : data_wr_addr_int = 5'd17; - 6'd38 : data_wr_addr_int = 5'd20; - default : data_wr_addr_int = 5'd0; - endcase // case(phase) - - always @(phase) - case(phase) - 6'd0, 6'd8, 6'd14, 6'd20, 6'd26, 6'd32, 6'd38: data_wr = 1'b1; - default : data_wr = 1'b0; - endcase // case(phase) - - always @(phase) - case(phase) - 6'd0, 6'd1, 6'd2, 6'd3, 6'd9, 6'd15, 6'd21, 6'd27, 6'd33 : clear_acc = 1'd1; - default : clear_acc = 1'b0; - endcase // case(phase) - - assign enable_acc = ~clear_acc; - assign latch_out = (phase == 6'd38); - - always @(posedge clock) - if(reset) - sample_out <= #1 16'd0; - else if(latch_out) - sample_out <= #1 scaled_accum; - -endmodule // mrfm_iir diff --git a/fpga/usrp1/toplevel/mrfm/mrfm.csf b/fpga/usrp1/toplevel/mrfm/mrfm.csf deleted file mode 100644 index 2c30b996b..000000000 --- a/fpga/usrp1/toplevel/mrfm/mrfm.csf +++ /dev/null @@ -1,444 +0,0 @@ -COMPILER_SETTINGS -{ - IO_PLACEMENT_OPTIMIZATION = OFF; - ENABLE_DRC_SETTINGS = OFF; - PHYSICAL_SYNTHESIS_REGISTER_RETIMING = OFF; - PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION = OFF; - PHYSICAL_SYNTHESIS_COMBO_LOGIC = OFF; - DRC_FANOUT_EXCEEDING = 30; - DRC_REPORT_FANOUT_EXCEEDING = OFF; - DRC_TOP_FANOUT = 50; - DRC_REPORT_TOP_FANOUT = OFF; - RUN_DRC_DURING_COMPILATION = OFF; - ADV_NETLIST_OPT_RETIME_CORE_AND_IO = ON; - ADV_NETLIST_OPT_SYNTH_USE_FITTER_INFO = OFF; - ADV_NETLIST_OPT_SYNTH_GATE_RETIME = OFF; - ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP = OFF; - SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES = OFF; - MERGE_HEX_FILE = OFF; - TRUE_WYSIWYG_FLOW = OFF; - SEED = 1; - FINAL_PLACEMENT_OPTIMIZATION = AUTOMATICALLY; - FAMILY = Cyclone; - DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2"; - DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1"; - DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; - DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB"; - DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB"; - DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4"; - DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4"; - DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3"; - DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS"; - DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS"; - DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS"; - STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; - PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2"; - PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2"; - STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1"; - FAST_FIT_COMPILATION = OFF; - SIGNALPROBE_DURING_NORMAL_COMPILATION = OFF; - OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON; - OPTIMIZE_TIMING = "NORMAL COMPILATION"; - OPTIMIZE_HOLD_TIMING = OFF; - COMPILATION_LEVEL = FULL; - SAVE_DISK_SPACE = OFF; - SPEED_DISK_USAGE_TRADEOFF = NORMAL; - LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF; - SIGNALPROBE_ALLOW_OVERUSE = OFF; - FOCUS_ENTITY_NAME = |mrfm; - ROUTING_BACK_ANNOTATION_MODE = OFF; - INC_PLC_MODE = OFF; - FIT_ONLY_ONE_ATTEMPT = OFF; -} -DEFAULT_DEVICE_OPTIONS -{ - GENERATE_CONFIG_HEXOUT_FILE = OFF; - GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_JBC_FILE = OFF; - GENERATE_CONFIG_JAM_FILE = OFF; - GENERATE_CONFIG_ISC_FILE = OFF; - GENERATE_CONFIG_SVF_FILE = OFF; - GENERATE_JBC_FILE_COMPRESSED = ON; - GENERATE_JBC_FILE = OFF; - GENERATE_JAM_FILE = OFF; - GENERATE_ISC_FILE = OFF; - GENERATE_SVF_FILE = OFF; - RESERVE_PIN = "AS INPUT TRI-STATED"; - RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND"; - HEXOUT_FILE_COUNT_DIRECTION = UP; - HEXOUT_FILE_START_ADDRESS = 0; - GENERATE_HEX_FILE = OFF; - GENERATE_RBF_FILE = OFF; - GENERATE_TTF_FILE = OFF; - RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; - RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; - AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; - EPROM_USE_CHECKSUM_AS_USERCODE = OFF; - FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIGURATION_DEVICE = AUTO; - CYCLONE_CONFIGURATION_DEVICE = AUTO; - FLEX10K_CONFIGURATION_DEVICE = AUTO; - FLEX6K_CONFIGURATION_DEVICE = AUTO; - MERCURY_CONFIGURATION_DEVICE = AUTO; - EXCALIBUR_CONFIGURATION_DEVICE = AUTO; - APEX20K_CONFIGURATION_DEVICE = AUTO; - USE_CONFIGURATION_DEVICE = ON; - ENABLE_INIT_DONE_OUTPUT = OFF; - FLEX10K_ENABLE_LOCK_OUTPUT = OFF; - ENABLE_DEVICE_WIDE_OE = OFF; - ENABLE_DEVICE_WIDE_RESET = OFF; - RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; - AUTO_RESTART_CONFIGURATION = OFF; - ENABLE_VREFB_PIN = OFF; - ENABLE_VREFA_PIN = OFF; - SECURITY_BIT = OFF; - USER_START_UP_CLOCK = OFF; - APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - CYCLONE_CONFIGURATION_SCHEME = "ACTIVE SERIAL"; - STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - STRATIX_UPDATE_MODE = STANDARD; - USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_JTAG_USER_CODE = 7F; - MERCURY_JTAG_USER_CODE = FFFFFFFF; - APEX20K_JTAG_USER_CODE = FFFFFFFF; - STRATIX_JTAG_USER_CODE = FFFFFFFF; - MAX7000S_JTAG_USER_CODE = FFFF; - RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; - ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; - ENABLE_JTAG_BST_SUPPORT = OFF; - CONFIGURATION_CLOCK_DIVISOR = 1; - CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; - CLOCK_SOURCE = INTERNAL; - COMPRESSION_MODE = OFF; - ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; -} -AUTO_SLD_HUB_ENTITY -{ - AUTO_INSERT_SLD_HUB_ENTITY = ENABLE; - HUB_INSTANCE_NAME = SLD_HUB_INST; - HUB_ENTITY_NAME = SLD_HUB; -} -SIGNALTAP_LOGIC_ANALYZER_SETTINGS -{ - ENABLE_SIGNALTAP = Off; - AUTO_ENABLE_SMART_COMPILE = On; -} -CHIP(mrfm) -{ - DEVICE = EP1C12Q240C8; - DEVICE_FILTER_PACKAGE = "ANY QFP"; - DEVICE_FILTER_PIN_COUNT = 240; - DEVICE_FILTER_SPEED_GRADE = ANY; - AUTO_RESTART_CONFIGURATION = OFF; - RELEASE_CLEARS_BEFORE_TRI_STATES = OFF; - USER_START_UP_CLOCK = OFF; - ENABLE_DEVICE_WIDE_RESET = OFF; - ENABLE_DEVICE_WIDE_OE = OFF; - ENABLE_INIT_DONE_OUTPUT = OFF; - FLEX10K_ENABLE_LOCK_OUTPUT = OFF; - ENABLE_JTAG_BST_SUPPORT = OFF; - MAX7000_ENABLE_JTAG_BST_SUPPORT = ON; - APEX20K_JTAG_USER_CODE = FFFFFFFF; - MERCURY_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_JTAG_USER_CODE = 7F; - MAX7000_JTAG_USER_CODE = FFFFFFFF; - MAX7000S_JTAG_USER_CODE = FFFF; - STRATIX_JTAG_USER_CODE = FFFFFFFF; - APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - APEXII_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - CYCLONE_CONFIGURATION_SCHEME = "PASSIVE SERIAL"; - USE_CONFIGURATION_DEVICE = OFF; - APEX20K_CONFIGURATION_DEVICE = AUTO; - MERCURY_CONFIGURATION_DEVICE = AUTO; - FLEX6K_CONFIGURATION_DEVICE = AUTO; - FLEX10K_CONFIGURATION_DEVICE = AUTO; - EXCALIBUR_CONFIGURATION_DEVICE = AUTO; - STRATIX_CONFIGURATION_DEVICE = AUTO; - CYCLONE_CONFIGURATION_DEVICE = AUTO; - STRATIX_UPDATE_MODE = STANDARD; - APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF; - AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON; - DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE = OFF; - COMPRESSION_MODE = OFF; - ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF; - FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON; - EPROM_USE_CHECKSUM_AS_USERCODE = OFF; - USE_CHECKSUM_AS_USERCODE = OFF; - MAX7000_USE_CHECKSUM_AS_USERCODE = OFF; - GENERATE_TTF_FILE = OFF; - GENERATE_RBF_FILE = ON; - GENERATE_HEX_FILE = OFF; - SECURITY_BIT = OFF; - ENABLE_VREFA_PIN = OFF; - ENABLE_VREFB_PIN = OFF; - GENERATE_SVF_FILE = OFF; - GENERATE_ISC_FILE = OFF; - GENERATE_JAM_FILE = OFF; - GENERATE_JBC_FILE = OFF; - GENERATE_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_SVF_FILE = OFF; - GENERATE_CONFIG_ISC_FILE = OFF; - GENERATE_CONFIG_JAM_FILE = OFF; - GENERATE_CONFIG_JBC_FILE = OFF; - GENERATE_CONFIG_JBC_FILE_COMPRESSED = ON; - GENERATE_CONFIG_HEXOUT_FILE = OFF; - ON_CHIP_BITSTREAM_DECOMPRESSION = OFF; - BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF; - HEXOUT_FILE_START_ADDRESS = 0; - HEXOUT_FILE_COUNT_DIRECTION = UP; - RESERVE_ALL_UNUSED_PINS = "AS INPUT TRI-STATED"; - STRATIX_DEVICE_IO_STANDARD = LVTTL; - CLOCK_SOURCE = INTERNAL; - CONFIGURATION_CLOCK_FREQUENCY = "10 MHZ"; - CONFIGURATION_CLOCK_DIVISOR = 1; - RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_RDYNBUSY_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_DATA0_AFTER_CONFIGURATION = "AS INPUT TRI-STATED"; - RESERVE_NCEO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - RESERVE_ASDO_AFTER_CONFIGURATION = "USE AS REGULAR IO"; - SCLK : LOCATION = Pin_101; - SDI : LOCATION = Pin_100; - SEN : LOCATION = Pin_98; - SLD : LOCATION = Pin_95; - adc1_data[0] : LOCATION = Pin_5; - adc1_data[10] : LOCATION = Pin_235; - adc1_data[11] : LOCATION = Pin_234; - adc1_data[1] : LOCATION = Pin_4; - adc1_data[2] : LOCATION = Pin_3; - adc1_data[3] : LOCATION = Pin_2; - adc1_data[4] : LOCATION = Pin_1; - adc1_data[4] : IO_STANDARD = LVTTL; - adc1_data[5] : LOCATION = Pin_240; - adc1_data[6] : LOCATION = Pin_239; - adc1_data[7] : LOCATION = Pin_238; - adc1_data[8] : LOCATION = Pin_237; - adc1_data[9] : LOCATION = Pin_236; - adc2_data[0] : LOCATION = Pin_20; - adc2_data[10] : LOCATION = Pin_8; - adc2_data[11] : LOCATION = Pin_7; - adc2_data[1] : LOCATION = Pin_19; - adc2_data[2] : LOCATION = Pin_18; - adc2_data[3] : LOCATION = Pin_17; - adc2_data[4] : LOCATION = Pin_16; - adc2_data[5] : LOCATION = Pin_15; - adc2_data[6] : LOCATION = Pin_14; - adc2_data[7] : LOCATION = Pin_13; - adc2_data[8] : LOCATION = Pin_12; - adc2_data[9] : LOCATION = Pin_11; - adc3_data[0] : LOCATION = Pin_200; - adc3_data[10] : LOCATION = Pin_184; - adc3_data[11] : LOCATION = Pin_183; - adc3_data[1] : LOCATION = Pin_197; - adc3_data[2] : LOCATION = Pin_196; - adc3_data[3] : LOCATION = Pin_195; - adc3_data[4] : LOCATION = Pin_194; - adc3_data[5] : LOCATION = Pin_193; - adc3_data[6] : LOCATION = Pin_188; - adc3_data[7] : LOCATION = Pin_187; - adc3_data[8] : LOCATION = Pin_186; - adc3_data[9] : LOCATION = Pin_185; - adc4_data[0] : LOCATION = Pin_222; - adc4_data[10] : LOCATION = Pin_203; - adc4_data[11] : LOCATION = Pin_202; - adc4_data[1] : LOCATION = Pin_219; - adc4_data[2] : LOCATION = Pin_217; - adc4_data[3] : LOCATION = Pin_216; - adc4_data[4] : LOCATION = Pin_215; - adc4_data[5] : LOCATION = Pin_214; - adc4_data[6] : LOCATION = Pin_213; - adc4_data[7] : LOCATION = Pin_208; - adc4_data[8] : LOCATION = Pin_207; - adc4_data[9] : LOCATION = Pin_206; - adc_oeb[0] : LOCATION = Pin_228; - adc_oeb[1] : LOCATION = Pin_21; - adc_oeb[2] : LOCATION = Pin_181; - adc_oeb[3] : LOCATION = Pin_218; - adc_otr[0] : LOCATION = Pin_233; - adc_otr[1] : LOCATION = Pin_6; - adc_otr[2] : LOCATION = Pin_182; - adc_otr[3] : LOCATION = Pin_201; - adclk0 : LOCATION = Pin_224; - adclk1 : LOCATION = Pin_226; - clk0 : LOCATION = Pin_28; - clk0 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk0 : IO_STANDARD = LVTTL; - clk1 : LOCATION = Pin_29; - clk1 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk1 : IO_STANDARD = LVTTL; - clk3 : LOCATION = Pin_152; - clk3 : RESERVE_PIN = "AS INPUT TRI-STATED"; - clk3 : IO_STANDARD = LVTTL; - clk_120mhz : LOCATION = Pin_153; - clk_120mhz : IO_STANDARD = LVTTL; - clk_out : LOCATION = Pin_63; - clk_out : IO_STANDARD = LVTTL; - dac1_data[0] : LOCATION = Pin_165; - dac1_data[10] : LOCATION = Pin_177; - dac1_data[11] : LOCATION = Pin_178; - dac1_data[12] : LOCATION = Pin_179; - dac1_data[13] : LOCATION = Pin_180; - dac1_data[1] : LOCATION = Pin_166; - dac1_data[2] : LOCATION = Pin_167; - dac1_data[3] : LOCATION = Pin_168; - dac1_data[4] : LOCATION = Pin_169; - dac1_data[5] : LOCATION = Pin_170; - dac1_data[6] : LOCATION = Pin_173; - dac1_data[7] : LOCATION = Pin_174; - dac1_data[8] : LOCATION = Pin_175; - dac1_data[9] : LOCATION = Pin_176; - dac2_data[0] : LOCATION = Pin_159; - dac2_data[10] : LOCATION = Pin_163; - dac2_data[11] : LOCATION = Pin_139; - dac2_data[12] : LOCATION = Pin_164; - dac2_data[13] : LOCATION = Pin_138; - dac2_data[1] : LOCATION = Pin_158; - dac2_data[2] : LOCATION = Pin_160; - dac2_data[3] : LOCATION = Pin_156; - dac2_data[4] : LOCATION = Pin_161; - dac2_data[5] : LOCATION = Pin_144; - dac2_data[6] : LOCATION = Pin_162; - dac2_data[7] : LOCATION = Pin_141; - dac2_data[8] : LOCATION = Pin_143; - dac2_data[9] : LOCATION = Pin_140; - dac3_data[0] : LOCATION = Pin_122; - dac3_data[10] : LOCATION = Pin_134; - dac3_data[11] : LOCATION = Pin_135; - dac3_data[12] : LOCATION = Pin_136; - dac3_data[13] : LOCATION = Pin_137; - dac3_data[1] : LOCATION = Pin_123; - dac3_data[2] : LOCATION = Pin_124; - dac3_data[3] : LOCATION = Pin_125; - dac3_data[4] : LOCATION = Pin_126; - dac3_data[5] : LOCATION = Pin_127; - dac3_data[6] : LOCATION = Pin_128; - dac3_data[7] : LOCATION = Pin_131; - dac3_data[8] : LOCATION = Pin_132; - dac3_data[9] : LOCATION = Pin_133; - dac4_data[0] : LOCATION = Pin_104; - dac4_data[10] : LOCATION = Pin_118; - dac4_data[11] : LOCATION = Pin_119; - dac4_data[12] : LOCATION = Pin_120; - dac4_data[13] : LOCATION = Pin_121; - dac4_data[1] : LOCATION = Pin_105; - dac4_data[2] : LOCATION = Pin_106; - dac4_data[3] : LOCATION = Pin_107; - dac4_data[4] : LOCATION = Pin_108; - dac4_data[5] : LOCATION = Pin_113; - dac4_data[6] : LOCATION = Pin_114; - dac4_data[7] : LOCATION = Pin_115; - dac4_data[8] : LOCATION = Pin_116; - dac4_data[9] : LOCATION = Pin_117; - enable_rx : LOCATION = Pin_88; - enable_tx : LOCATION = Pin_93; - gndbus[0] : LOCATION = Pin_223; - gndbus[0] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[0] : IO_STANDARD = LVTTL; - gndbus[1] : LOCATION = Pin_225; - gndbus[1] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[1] : IO_STANDARD = LVTTL; - gndbus[2] : LOCATION = Pin_227; - gndbus[2] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[2] : IO_STANDARD = LVTTL; - gndbus[3] : LOCATION = Pin_62; - gndbus[3] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[3] : IO_STANDARD = LVTTL; - gndbus[4] : LOCATION = Pin_64; - gndbus[4] : RESERVE_PIN = "AS INPUT TRI-STATED"; - gndbus[4] : IO_STANDARD = LVTTL; - misc_pins[0] : LOCATION = Pin_87; - misc_pins[0] : IO_STANDARD = LVTTL; - misc_pins[10] : LOCATION = Pin_76; - misc_pins[10] : IO_STANDARD = LVTTL; - misc_pins[11] : LOCATION = Pin_74; - misc_pins[11] : IO_STANDARD = LVTTL; - misc_pins[1] : LOCATION = Pin_86; - misc_pins[1] : IO_STANDARD = LVTTL; - misc_pins[2] : LOCATION = Pin_85; - misc_pins[2] : IO_STANDARD = LVTTL; - misc_pins[3] : LOCATION = Pin_84; - misc_pins[3] : IO_STANDARD = LVTTL; - misc_pins[4] : LOCATION = Pin_83; - misc_pins[4] : IO_STANDARD = LVTTL; - misc_pins[5] : LOCATION = Pin_82; - misc_pins[5] : IO_STANDARD = LVTTL; - misc_pins[6] : LOCATION = Pin_79; - misc_pins[6] : IO_STANDARD = LVTTL; - misc_pins[7] : LOCATION = Pin_78; - misc_pins[7] : IO_STANDARD = LVTTL; - misc_pins[8] : LOCATION = Pin_77; - misc_pins[8] : IO_STANDARD = LVTTL; - misc_pins[9] : LOCATION = Pin_75; - misc_pins[9] : IO_STANDARD = LVTTL; - reset : LOCATION = Pin_94; - usbclk : LOCATION = Pin_55; - usbctl[0] : LOCATION = Pin_56; - usbctl[1] : LOCATION = Pin_54; - usbctl[2] : LOCATION = Pin_53; - usbctl[3] : LOCATION = Pin_58; - usbctl[4] : LOCATION = Pin_57; - usbctl[5] : LOCATION = Pin_44; - usbdata[0] : LOCATION = Pin_73; - usbdata[10] : LOCATION = Pin_41; - usbdata[11] : LOCATION = Pin_39; - usbdata[12] : LOCATION = Pin_38; - usbdata[12] : IO_STANDARD = LVTTL; - usbdata[13] : LOCATION = Pin_37; - usbdata[14] : LOCATION = Pin_24; - usbdata[15] : LOCATION = Pin_23; - usbdata[1] : LOCATION = Pin_68; - usbdata[2] : LOCATION = Pin_67; - usbdata[3] : LOCATION = Pin_66; - usbdata[4] : LOCATION = Pin_65; - usbdata[5] : LOCATION = Pin_61; - usbdata[6] : LOCATION = Pin_60; - usbdata[7] : LOCATION = Pin_59; - usbdata[8] : LOCATION = Pin_43; - usbdata[9] : LOCATION = Pin_42; - usbrdy[0] : LOCATION = Pin_45; - usbrdy[1] : LOCATION = Pin_46; - usbrdy[2] : LOCATION = Pin_47; - usbrdy[3] : LOCATION = Pin_48; - usbrdy[4] : LOCATION = Pin_49; - usbrdy[5] : LOCATION = Pin_50; - clear_status : LOCATION = Pin_99; -} diff --git a/fpga/usrp1/toplevel/mrfm/mrfm.esf b/fpga/usrp1/toplevel/mrfm/mrfm.esf deleted file mode 100644 index 72b84e39e..000000000 --- a/fpga/usrp1/toplevel/mrfm/mrfm.esf +++ /dev/null @@ -1,14 +0,0 @@ -SIMULATOR_SETTINGS -{ - ESTIMATE_POWER_CONSUMPTION = OFF; - GLITCH_INTERVAL = 1NS; - GLITCH_DETECTION = OFF; - SIMULATION_COVERAGE = ON; - CHECK_OUTPUTS = OFF; - SETUP_HOLD_DETECTION = OFF; - POWER_ESTIMATION_START_TIME = "0 NS"; - ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON; - SIMULATION_MODE = TIMING; - START_TIME = 0NS; - USE_COMPILER_SETTINGS = mrfm; -} diff --git a/fpga/usrp1/toplevel/mrfm/mrfm.psf b/fpga/usrp1/toplevel/mrfm/mrfm.psf deleted file mode 100644 index 678a7faa2..000000000 --- a/fpga/usrp1/toplevel/mrfm/mrfm.psf +++ /dev/null @@ -1,312 +0,0 @@ -DEFAULT_DESIGN_ASSISTANT_SETTINGS -{ - HCPY_ALOAD_SIGNALS = OFF; - HCPY_VREF_PINS = OFF; - HCPY_CAT = OFF; - HCPY_ILLEGAL_HC_DEV_PKG = OFF; - ACLK_RULE_IMSZER_ADOMAIN = OFF; - ACLK_RULE_SZER_BTW_ACLK_DOMAIN = OFF; - ACLK_RULE_NO_SZER_ACLK_DOMAIN = OFF; - ACLK_CAT = OFF; - SIGNALRACE_RULE_ASYNCHPIN_SYNCH_CLKPIN = OFF; - SIGNALRACE_CAT = OFF; - NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED = OFF; - NONSYNCHSTRUCT_RULE_SRLATCH = OFF; - NONSYNCHSTRUCT_RULE_DLATCH = OFF; - NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR = OFF; - NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN = OFF; - NONSYNCHSTRUCT_RULE_RIPPLE_CLK = OFF; - NONSYNCHSTRUCT_RULE_DELAY_CHAIN = OFF; - NONSYNCHSTRUCT_RULE_REG_LOOP = OFF; - NONSYNCHSTRUCT_RULE_COMBLOOP = OFF; - NONSYNCHSTRUCT_CAT = OFF; - NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE = OFF; - TIMING_RULE_COIN_CLKEDGE = OFF; - TIMING_RULE_SHIFT_REG = OFF; - TIMING_RULE_HIGH_FANOUTS = OFF; - TIMING_CAT = OFF; - RESET_RULE_ALL = OFF; - RESET_RULE_IMSYNCH_ASYNCH_DOMAIN = OFF; - RESET_RULE_UNSYNCH_ASYNCH_DOMAIN = OFF; - RESET_RULE_REG_ASNYCH = OFF; - RESET_RULE_COMB_ASYNCH_RESET = OFF; - RESET_RULE_IMSYNCH_EXRESET = OFF; - RESET_RULE_UNSYNCH_EXRESET = OFF; - RESET_RULE_INPINS_RESETNET = OFF; - RESET_CAT = OFF; - CLK_RULE_ALL = OFF; - CLK_RULE_MIX_EDGES = OFF; - CLK_RULE_CLKNET_CLKSPINES = OFF; - CLK_RULE_INPINS_CLKNET = OFF; - CLK_RULE_GATING_SCHEME = OFF; - CLK_RULE_INV_CLOCK = OFF; - CLK_RULE_COMB_CLOCK = OFF; - CLK_CAT = OFF; - HCPY_EXCEED_USER_IO_USAGE = OFF; - HCPY_EXCEED_RAM_USAGE = OFF; - NONSYNCHSTRUCT_RULE_ASYN_RAM = OFF; - SIGNALRACE_RULE_TRISTATE = OFF; - ASSG_RULE_MISSING_TIMING = OFF; - ASSG_RULE_MISSING_FMAX = OFF; - ASSG_CAT = OFF; -} -SYNTHESIS_FITTING_SETTINGS -{ - AUTO_SHIFT_REGISTER_RECOGNITION = ON; - AUTO_DSP_RECOGNITION = ON; - AUTO_RAM_RECOGNITION = ON; - REMOVE_DUPLICATE_LOGIC = ON; - AUTO_TURBO_BIT = ON; - AUTO_MERGE_PLLS = ON; - AUTO_OPEN_DRAIN_PINS = ON; - AUTO_PARALLEL_EXPANDERS = ON; - AUTO_FAST_OUTPUT_ENABLE_REGISTERS = OFF; - AUTO_FAST_OUTPUT_REGISTERS = OFF; - AUTO_FAST_INPUT_REGISTERS = OFF; - AUTO_CASCADE_CHAINS = ON; - AUTO_CARRY_CHAINS = ON; - AUTO_DELAY_CHAINS = ON; - MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH = 4; - PARALLEL_EXPANDER_CHAIN_LENGTH = 16; - CASCADE_CHAIN_LENGTH = 2; - STRATIX_CARRY_CHAIN_LENGTH = 70; - MERCURY_CARRY_CHAIN_LENGTH = 48; - FLEX10K_CARRY_CHAIN_LENGTH = 32; - FLEX6K_CARRY_CHAIN_LENGTH = 32; - CARRY_CHAIN_LENGTH = 48; - CARRY_OUT_PINS_LCELL_INSERT = ON; - NORMAL_LCELL_INSERT = ON; - AUTO_LCELL_INSERTION = ON; - ALLOW_XOR_GATE_USAGE = ON; - AUTO_PACKED_REGISTERS_STRATIX = NORMAL; - AUTO_PACKED_REGISTERS = OFF; - AUTO_PACKED_REG_CYCLONE = NORMAL; - FLEX10K_OPTIMIZATION_TECHNIQUE = AREA; - FLEX6K_OPTIMIZATION_TECHNIQUE = AREA; - MERCURY_OPTIMIZATION_TECHNIQUE = AREA; - APEX20K_OPTIMIZATION_TECHNIQUE = SPEED; - MAX7000_OPTIMIZATION_TECHNIQUE = SPEED; - STRATIX_OPTIMIZATION_TECHNIQUE = SPEED; - CYCLONE_OPTIMIZATION_TECHNIQUE = AREA; - FLEX10K_TECHNOLOGY_MAPPER = LUT; - FLEX6K_TECHNOLOGY_MAPPER = LUT; - MERCURY_TECHNOLOGY_MAPPER = LUT; - APEX20K_TECHNOLOGY_MAPPER = LUT; - MAX7000_TECHNOLOGY_MAPPER = "PRODUCT TERM"; - STRATIX_TECHNOLOGY_MAPPER = LUT; - AUTO_IMPLEMENT_IN_ROM = OFF; - AUTO_GLOBAL_MEMORY_CONTROLS = OFF; - AUTO_GLOBAL_REGISTER_CONTROLS = ON; - AUTO_GLOBAL_OE = ON; - AUTO_GLOBAL_CLOCK = ON; - USE_LPM_FOR_AHDL_OPERATORS = ON; - LIMIT_AHDL_INTEGERS_TO_32_BITS = OFF; - ENABLE_BUS_HOLD_CIRCUITRY = OFF; - WEAK_PULL_UP_RESISTOR = OFF; - TURBO_BIT = ON; - MAX7000_IGNORE_SOFT_BUFFERS = OFF; - IGNORE_SOFT_BUFFERS = ON; - MAX7000_IGNORE_LCELL_BUFFERS = AUTO; - IGNORE_LCELL_BUFFERS = OFF; - IGNORE_ROW_GLOBAL_BUFFERS = OFF; - IGNORE_GLOBAL_BUFFERS = OFF; - IGNORE_CASCADE_BUFFERS = OFF; - IGNORE_CARRY_BUFFERS = OFF; - REMOVE_DUPLICATE_REGISTERS = ON; - REMOVE_REDUNDANT_LOGIC_CELLS = OFF; - ALLOW_POWER_UP_DONT_CARE = ON; - PCI_IO = OFF; - NOT_GATE_PUSH_BACK = ON; - SLOW_SLEW_RATE = OFF; - DSP_BLOCK_BALANCING = AUTO; - STATE_MACHINE_PROCESSING = AUTO; -} -DEFAULT_HARDCOPY_SETTINGS -{ - HARDCOPY_EXTERNAL_CLOCK_JITTER = "0.0 NS"; -} -DEFAULT_TIMING_REQUIREMENTS -{ - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - RUN_ALL_TIMING_ANALYSES = ON; - IGNORE_CLOCK_SETTINGS = OFF; - DEFAULT_HOLD_MULTICYCLE = "SAME AS MULTICYCLE"; - CUT_OFF_IO_PIN_FEEDBACK = ON; - CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; - CUT_OFF_READ_DURING_WRITE_PATHS = ON; - CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS = ON; - DO_MIN_ANALYSIS = ON; - DO_MIN_TIMING = OFF; - NUMBER_OF_PATHS_TO_REPORT = 200; - NUMBER_OF_DESTINATION_TO_REPORT = 10; - NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT = 10; - MAX_SCC_SIZE = 50; -} -HDL_SETTINGS -{ - VERILOG_INPUT_VERSION = VERILOG_2001; - ENABLE_IP_DEBUG = OFF; - VHDL_INPUT_VERSION = VHDL93; - VHDL_SHOW_LMF_MAPPING_MESSAGES = OFF; -} -PROJECT_INFO(mrfm) -{ - ORIGINAL_QUARTUS_VERSION = 3.0; - PROJECT_CREATION_TIME_DATE = "00:14:04 JULY 13, 2003"; - LAST_QUARTUS_VERSION = 3.0; - SHOW_REGISTRATION_MESSAGE = ON; - USER_LIBRARIES = "e:\usrp\fpga\megacells"; -} -THIRD_PARTY_EDA_TOOLS(mrfm) -{ - EDA_DESIGN_ENTRY_SYNTHESIS_TOOL = "<NONE>"; - EDA_SIMULATION_TOOL = "<NONE>"; - EDA_TIMING_ANALYSIS_TOOL = "<NONE>"; - EDA_BOARD_DESIGN_TOOL = "<NONE>"; - EDA_FORMAL_VERIFICATION_TOOL = "<NONE>"; - EDA_RESYNTHESIS_TOOL = "<NONE>"; -} -EDA_TOOL_SETTINGS(eda_design_synthesis) -{ - EDA_INPUT_GND_NAME = GND; - EDA_INPUT_VCC_NAME = VCC; - EDA_SHOW_LMF_MAPPING_MESSAGES = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_INPUT_DATA_FORMAT = EDIF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_simulation) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_timing_analysis) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - EDA_LAUNCH_CMD_LINE_TOOL = OFF; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_board_design) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_formal_verification) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - RESYNTHESIS_RETIMING = FULL; -} -EDA_TOOL_SETTINGS(eda_palace) -{ - EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION = OFF; - EDA_TRUNCATE_LONG_HIERARCHY_PATHS = OFF; - EDA_MAINTAIN_DESIGN_HIERARCHY = OFF; - EDA_WRITE_DEVICE_CONTROL_PORTS = OFF; - EDA_GENERATE_FUNCTIONAL_NETLIST = OFF; - EDA_FLATTEN_BUSES = OFF; - EDA_MAP_ILLEGAL_CHARACTERS = OFF; - EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE = OFF; - EDA_RUN_TOOL_AUTOMATICALLY = OFF; - EDA_OUTPUT_DATA_FORMAT = NONE; - RESYNTHESIS_RETIMING = FULL; - RESYNTHESIS_PHYSICAL_SYNTHESIS = NORMAL; - RESYNTHESIS_OPTIMIZATION_EFFORT = NORMAL; - USE_GENERATED_PHYSICAL_CONSTRAINTS = ON; -} -CLOCK(clk_120mhz) -{ - FMAX_REQUIREMENT = "120.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(usbclk) -{ - FMAX_REQUIREMENT = "48.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(SCLK) -{ - FMAX_REQUIREMENT = "1.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(adclk0) -{ - FMAX_REQUIREMENT = "60.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} -CLOCK(adclk1) -{ - FMAX_REQUIREMENT = "60.0 MHz"; - INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS = OFF; - DUTY_CYCLE = 50; - DIVIDE_BASE_CLOCK_PERIOD_BY = 1; - MULTIPLY_BASE_CLOCK_PERIOD_BY = 1; - INVERT_BASE_CLOCK = OFF; -} diff --git a/fpga/usrp1/toplevel/mrfm/mrfm.py b/fpga/usrp1/toplevel/mrfm/mrfm.py deleted file mode 100644 index 100db69eb..000000000 --- a/fpga/usrp1/toplevel/mrfm/mrfm.py +++ /dev/null @@ -1,129 +0,0 @@ -#!/usr/bin/env python -# -# This is mrfm_fft_sos.py -# Modification of Matt's mrfm_fft.py that reads filter coefs from file -# -# Copyright 2004,2005 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -from gnuradio import gr, gru -from gnuradio import usrp - -class source_c(usrp.source_c): - def __init__(self,fpga_filename): - usrp.source_c.__init__(self,which=0, decim_rate=64, nchan=2, mux=0x32103210, mode=0, - fpga_filename=fpga_filename) - - self._write_9862(0,2,0x80) # Bypass ADC buffer, minimum gain - self._write_9862(0,3,0x80) # Bypass ADC buffer, minimum gain - - self._write_9862(0,8,0) # TX PWR Down - self._write_9862(0,10,0) # DAC offset - self._write_9862(0,11,0) # DAC offset - self._write_9862(0,14,0x80) # gain - self._write_9862(0,16,0xff) # pga - self._write_9862(0,18,0x0c) # TX IF - self._write_9862(0,19,0x01) # TX Digital - self._write_9862(0,20,0x00) # TX Mod - - # max/min values are +/-2, so scale is set to make 2 = 32767 - - self._write_fpga_reg(69,0x0e) # debug mux - self._write_fpga_reg(5,-1) - self._write_fpga_reg(7,-1) - self._write_oe(0,0xffff, 0xffff) - self._write_oe(1,0xffff, 0xffff) - self._write_fpga_reg(14,0xf) - - self.decim = None - - def set_coeffs(self,frac_bits,b20,b10,b00,a20,a10,b21,b11,b01,a21,a11): - def make_val(address,value): - return (address << 16) | (value & 0xffff) - - # gain, scale already included in a's and b's from file - - self._write_fpga_reg(67,make_val(1,b20)) - self._write_fpga_reg(67,make_val(2,b10)) - self._write_fpga_reg(67,make_val(3,b00)) - self._write_fpga_reg(67,make_val(4,a20)) - self._write_fpga_reg(67,make_val(5,a10)) - - self._write_fpga_reg(67,make_val(7,b21)) - self._write_fpga_reg(67,make_val(8,b11)) - self._write_fpga_reg(67,make_val(9,b01)) - self._write_fpga_reg(67,make_val(10,a21)) - self._write_fpga_reg(67,make_val(11,a11)) - - self._write_fpga_reg(68,frac_bits) # Shift - - print "Biquad 0 : b2=%d b1=%d b0=%d a2=%d a1=%d" % (b20,b10,b00,a20,a10) - print "Biquad 1 : b2=%d b1=%d b0=%d a2=%d a1=%d" % (b21,b11,b01,a21,a11) - - def set_decim_rate(self,rate=None): - i=2 - turn=1 - a=1 - b=1 - while (rate>1) and (i<257): - if (rate/i) * i == rate: - if turn == 1: - if a*i<257: - a = a * i - turn = 0 - elif b*i<257: - b = b * i - turn = 0 - else: - print "Failed to set DECIMATOR" - return self.decim - elif b*i<257: - b = b * i - turn = 1 - elif a*i<257: - a = a * i - turn = 1 - else: - print "Failed to set DECIMATOR" - return self.decim - rate=rate/i - continue - i = i + 1 - if rate > 1: - print "Failed to set DECIMATOR" - return self.decim - else: - self.decim = a*b - print "a = %d b = %d" % (a,b) - self._write_fpga_reg(64,(a-1)*256+(b-1)) # Set actual decimation - - def decim_rate(self): - return self.decim - - def set_center_freq(self,freq): - self._write_fpga_reg(65,int(-freq/64e6*65536*65536)) # set center freq - - def set_compensator(self,a11,a12,a21,a22,shift): - self._write_fpga_reg(70,a11) - self._write_fpga_reg(71,a12) - self._write_fpga_reg(72,a21) - self._write_fpga_reg(73,a22) - self._write_fpga_reg(74,shift) # comp shift - diff --git a/fpga/usrp1/toplevel/mrfm/mrfm.qpf b/fpga/usrp1/toplevel/mrfm/mrfm.qpf deleted file mode 100644 index 959140875..000000000 --- a/fpga/usrp1/toplevel/mrfm/mrfm.qpf +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (C) 1991-2004 Altera Corporation -# Any megafunction design, and related netlist (encrypted or decrypted), -# support information, device programming or simulation file, and any other -# associated documentation or information provided by Altera or a partner -# under Altera's Megafunction Partnership Program may be used only -# to program PLD devices (but not masked PLD devices) from Altera. Any -# other use of such megafunction design, netlist, support information, -# device programming or simulation file, or any other related documentation -# or information is prohibited for any other purpose, including, but not -# limited to modification, reverse engineering, de-compiling, or use with -# any other silicon devices, unless such use is explicitly licensed under -# a separate agreement with Altera or a megafunction partner. Title to the -# intellectual property, including patents, copyrights, trademarks, trade -# secrets, or maskworks, embodied in any such megafunction design, netlist, -# support information, device programming or simulation file, or any other -# related documentation or information provided by Altera or a megafunction -# partner, remains with Altera, the megafunction partner, or their respective -# licensors. No other licenses, including any licenses needed under any third -# party's intellectual property, are provided herein. - - - -QUARTUS_VERSION = "4.0" -DATE = "17:10:11 December 20, 2004" - - -# Active Revisions - -PROJECT_REVISION = "mrfm" diff --git a/fpga/usrp1/toplevel/mrfm/mrfm.qsf b/fpga/usrp1/toplevel/mrfm/mrfm.qsf deleted file mode 100644 index ba1ae0223..000000000 --- a/fpga/usrp1/toplevel/mrfm/mrfm.qsf +++ /dev/null @@ -1,411 +0,0 @@ -# Copyright (C) 1991-2005 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. - - -# The default values for assignments are stored in the file -# mrfm_assignment_defaults.qdf -# If this file doesn't exist, and for assignments not listed, see file -# assignment_defaults.qdf - -# Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. - - -# Project-Wide Assignments -# ======================== -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13, 2003" -set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP2" - -# Pin & Location Assignments -# ========================== -set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED" -set_location_assignment PIN_29 -to SCLK -set_location_assignment PIN_117 -to SDI -set_location_assignment PIN_28 -to usbclk -set_location_assignment PIN_107 -to usbctl[0] -set_location_assignment PIN_106 -to usbctl[1] -set_location_assignment PIN_105 -to usbctl[2] -set_location_assignment PIN_100 -to usbdata[0] -set_location_assignment PIN_84 -to usbdata[10] -set_location_assignment PIN_83 -to usbdata[11] -set_location_assignment PIN_82 -to usbdata[12] -set_location_assignment PIN_79 -to usbdata[13] -set_location_assignment PIN_78 -to usbdata[14] -set_location_assignment PIN_77 -to usbdata[15] -set_location_assignment PIN_99 -to usbdata[1] -set_location_assignment PIN_98 -to usbdata[2] -set_location_assignment PIN_95 -to usbdata[3] -set_location_assignment PIN_94 -to usbdata[4] -set_location_assignment PIN_93 -to usbdata[5] -set_location_assignment PIN_88 -to usbdata[6] -set_location_assignment PIN_87 -to usbdata[7] -set_location_assignment PIN_86 -to usbdata[8] -set_location_assignment PIN_85 -to usbdata[9] -set_location_assignment PIN_104 -to usbrdy[0] -set_location_assignment PIN_101 -to usbrdy[1] -set_location_assignment PIN_76 -to FX2_1 -set_location_assignment PIN_75 -to FX2_2 -set_location_assignment PIN_74 -to FX2_3 -set_location_assignment PIN_116 -to io_rx_a[0] -set_location_assignment PIN_115 -to io_rx_a[1] -set_location_assignment PIN_114 -to io_rx_a[2] -set_location_assignment PIN_113 -to io_rx_a[3] -set_location_assignment PIN_108 -to io_rx_a[4] -set_location_assignment PIN_195 -to io_rx_a[5] -set_location_assignment PIN_196 -to io_rx_a[6] -set_location_assignment PIN_197 -to io_rx_a[7] -set_location_assignment PIN_200 -to io_rx_a[8] -set_location_assignment PIN_201 -to io_rx_a[9] -set_location_assignment PIN_202 -to io_rx_a[10] -set_location_assignment PIN_203 -to io_rx_a[11] -set_location_assignment PIN_206 -to io_rx_a[12] -set_location_assignment PIN_207 -to io_rx_a[13] -set_location_assignment PIN_208 -to io_rx_a[14] -set_location_assignment PIN_214 -to io_rx_b[0] -set_location_assignment PIN_215 -to io_rx_b[1] -set_location_assignment PIN_216 -to io_rx_b[2] -set_location_assignment PIN_217 -to io_rx_b[3] -set_location_assignment PIN_218 -to io_rx_b[4] -set_location_assignment PIN_219 -to io_rx_b[5] -set_location_assignment PIN_222 -to io_rx_b[6] -set_location_assignment PIN_223 -to io_rx_b[7] -set_location_assignment PIN_224 -to io_rx_b[8] -set_location_assignment PIN_225 -to io_rx_b[9] -set_location_assignment PIN_226 -to io_rx_b[10] -set_location_assignment PIN_227 -to io_rx_b[11] -set_location_assignment PIN_228 -to io_rx_b[12] -set_location_assignment PIN_233 -to io_rx_b[13] -set_location_assignment PIN_234 -to io_rx_b[14] -set_location_assignment PIN_175 -to io_tx_a[0] -set_location_assignment PIN_176 -to io_tx_a[1] -set_location_assignment PIN_177 -to io_tx_a[2] -set_location_assignment PIN_178 -to io_tx_a[3] -set_location_assignment PIN_179 -to io_tx_a[4] -set_location_assignment PIN_180 -to io_tx_a[5] -set_location_assignment PIN_181 -to io_tx_a[6] -set_location_assignment PIN_182 -to io_tx_a[7] -set_location_assignment PIN_183 -to io_tx_a[8] -set_location_assignment PIN_184 -to io_tx_a[9] -set_location_assignment PIN_185 -to io_tx_a[10] -set_location_assignment PIN_186 -to io_tx_a[11] -set_location_assignment PIN_187 -to io_tx_a[12] -set_location_assignment PIN_188 -to io_tx_a[13] -set_location_assignment PIN_193 -to io_tx_a[14] -set_location_assignment PIN_73 -to io_tx_b[0] -set_location_assignment PIN_68 -to io_tx_b[1] -set_location_assignment PIN_67 -to io_tx_b[2] -set_location_assignment PIN_66 -to io_tx_b[3] -set_location_assignment PIN_65 -to io_tx_b[4] -set_location_assignment PIN_64 -to io_tx_b[5] -set_location_assignment PIN_63 -to io_tx_b[6] -set_location_assignment PIN_62 -to io_tx_b[7] -set_location_assignment PIN_61 -to io_tx_b[8] -set_location_assignment PIN_60 -to io_tx_b[9] -set_location_assignment PIN_59 -to io_tx_b[10] -set_location_assignment PIN_58 -to io_tx_b[11] -set_location_assignment PIN_57 -to io_tx_b[12] -set_location_assignment PIN_56 -to io_tx_b[13] -set_location_assignment PIN_55 -to io_tx_b[14] -set_location_assignment PIN_152 -to master_clk -set_location_assignment PIN_144 -to rx_a_a[0] -set_location_assignment PIN_143 -to rx_a_a[1] -set_location_assignment PIN_141 -to rx_a_a[2] -set_location_assignment PIN_140 -to rx_a_a[3] -set_location_assignment PIN_139 -to rx_a_a[4] -set_location_assignment PIN_138 -to rx_a_a[5] -set_location_assignment PIN_137 -to rx_a_a[6] -set_location_assignment PIN_136 -to rx_a_a[7] -set_location_assignment PIN_135 -to rx_a_a[8] -set_location_assignment PIN_134 -to rx_a_a[9] -set_location_assignment PIN_133 -to rx_a_a[10] -set_location_assignment PIN_132 -to rx_a_a[11] -set_location_assignment PIN_23 -to rx_a_b[0] -set_location_assignment PIN_21 -to rx_a_b[1] -set_location_assignment PIN_20 -to rx_a_b[2] -set_location_assignment PIN_19 -to rx_a_b[3] -set_location_assignment PIN_18 -to rx_a_b[4] -set_location_assignment PIN_17 -to rx_a_b[5] -set_location_assignment PIN_16 -to rx_a_b[6] -set_location_assignment PIN_15 -to rx_a_b[7] -set_location_assignment PIN_14 -to rx_a_b[8] -set_location_assignment PIN_13 -to rx_a_b[9] -set_location_assignment PIN_12 -to rx_a_b[10] -set_location_assignment PIN_11 -to rx_a_b[11] -set_location_assignment PIN_131 -to rx_b_a[0] -set_location_assignment PIN_128 -to rx_b_a[1] -set_location_assignment PIN_127 -to rx_b_a[2] -set_location_assignment PIN_126 -to rx_b_a[3] -set_location_assignment PIN_125 -to rx_b_a[4] -set_location_assignment PIN_124 -to rx_b_a[5] -set_location_assignment PIN_123 -to rx_b_a[6] -set_location_assignment PIN_122 -to rx_b_a[7] -set_location_assignment PIN_121 -to rx_b_a[8] -set_location_assignment PIN_120 -to rx_b_a[9] -set_location_assignment PIN_119 -to rx_b_a[10] -set_location_assignment PIN_118 -to rx_b_a[11] -set_location_assignment PIN_8 -to rx_b_b[0] -set_location_assignment PIN_7 -to rx_b_b[1] -set_location_assignment PIN_6 -to rx_b_b[2] -set_location_assignment PIN_5 -to rx_b_b[3] -set_location_assignment PIN_4 -to rx_b_b[4] -set_location_assignment PIN_3 -to rx_b_b[5] -set_location_assignment PIN_2 -to rx_b_b[6] -set_location_assignment PIN_240 -to rx_b_b[7] -set_location_assignment PIN_239 -to rx_b_b[8] -set_location_assignment PIN_238 -to rx_b_b[9] -set_location_assignment PIN_237 -to rx_b_b[10] -set_location_assignment PIN_236 -to rx_b_b[11] -set_location_assignment PIN_156 -to SDO -set_location_assignment PIN_153 -to SEN_FPGA -set_location_assignment PIN_159 -to tx_a[0] -set_location_assignment PIN_160 -to tx_a[1] -set_location_assignment PIN_161 -to tx_a[2] -set_location_assignment PIN_162 -to tx_a[3] -set_location_assignment PIN_163 -to tx_a[4] -set_location_assignment PIN_164 -to tx_a[5] -set_location_assignment PIN_165 -to tx_a[6] -set_location_assignment PIN_166 -to tx_a[7] -set_location_assignment PIN_167 -to tx_a[8] -set_location_assignment PIN_168 -to tx_a[9] -set_location_assignment PIN_169 -to tx_a[10] -set_location_assignment PIN_170 -to tx_a[11] -set_location_assignment PIN_173 -to tx_a[12] -set_location_assignment PIN_174 -to tx_a[13] -set_location_assignment PIN_38 -to tx_b[0] -set_location_assignment PIN_39 -to tx_b[1] -set_location_assignment PIN_41 -to tx_b[2] -set_location_assignment PIN_42 -to tx_b[3] -set_location_assignment PIN_43 -to tx_b[4] -set_location_assignment PIN_44 -to tx_b[5] -set_location_assignment PIN_45 -to tx_b[6] -set_location_assignment PIN_46 -to tx_b[7] -set_location_assignment PIN_47 -to tx_b[8] -set_location_assignment PIN_48 -to tx_b[9] -set_location_assignment PIN_49 -to tx_b[10] -set_location_assignment PIN_50 -to tx_b[11] -set_location_assignment PIN_53 -to tx_b[12] -set_location_assignment PIN_54 -to tx_b[13] -set_location_assignment PIN_158 -to TXSYNC_A -set_location_assignment PIN_37 -to TXSYNC_B -set_location_assignment PIN_235 -to io_rx_b[15] -set_location_assignment PIN_24 -to io_tx_b[15] -set_location_assignment PIN_213 -to io_rx_a[15] -set_location_assignment PIN_194 -to io_tx_a[15] -set_location_assignment PIN_1 -to MYSTERY_SIGNAL - -# Timing Assignments -# ================== -set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF - -# Analysis & Synthesis Assignments -# ================================ -set_global_assignment -name SAVE_DISK_SPACE OFF -set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240 -set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>" -set_global_assignment -name FAMILY Cyclone -set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED -set_global_assignment -name TOP_LEVEL_ENTITY mrfm -set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells" -set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON - -# Fitter Assignments -# ================== -set_global_assignment -name DEVICE EP1C12Q240C8 -set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED" -set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF -set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION" -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name IO_PLACEMENT_OPTIMIZATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA -set_global_assignment -name INC_PLC_MODE OFF -set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF -set_instance_assignment -name IO_STANDARD LVTTL -to usbdata[12] -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 - -# Timing Analysis Assignments -# =========================== -set_global_assignment -name MAX_SCC_SIZE 50 - -# EDA Netlist Writer Assignments -# ============================== -set_global_assignment -name EDA_SIMULATION_TOOL "<None>" -set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<NONE>" -set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<NONE>" -set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<NONE>" -set_global_assignment -name EDA_RESYNTHESIS_TOOL "<NONE>" - -# Assembler Assignments -# ===================== -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" -set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF - -# Simulator Assignments -# ===================== -set_global_assignment -name START_TIME "0 ns" -set_global_assignment -name GLITCH_INTERVAL "1 ns" - -# Design Assistant Assignments -# ============================ -set_global_assignment -name DRC_REPORT_TOP_FANOUT OFF -set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING OFF -set_global_assignment -name ASSG_CAT OFF -set_global_assignment -name ASSG_RULE_MISSING_FMAX OFF -set_global_assignment -name ASSG_RULE_MISSING_TIMING OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM OFF -set_global_assignment -name CLK_CAT OFF -set_global_assignment -name CLK_RULE_COMB_CLOCK OFF -set_global_assignment -name CLK_RULE_INV_CLOCK OFF -set_global_assignment -name CLK_RULE_GATING_SCHEME OFF -set_global_assignment -name CLK_RULE_INPINS_CLKNET OFF -set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES OFF -set_global_assignment -name CLK_RULE_MIX_EDGES OFF -set_global_assignment -name RESET_CAT OFF -set_global_assignment -name RESET_RULE_INPINS_RESETNET OFF -set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET OFF -set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET OFF -set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET OFF -set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN OFF -set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN OFF -set_global_assignment -name TIMING_CAT OFF -set_global_assignment -name TIMING_RULE_SHIFT_REG OFF -set_global_assignment -name TIMING_RULE_COIN_CLKEDGE OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE OFF -set_global_assignment -name NONSYNCHSTRUCT_CAT OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH OFF -set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED OFF -set_global_assignment -name SIGNALRACE_CAT OFF -set_global_assignment -name ACLK_CAT OFF -set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN OFF -set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN OFF -set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN OFF -set_global_assignment -name HCPY_CAT OFF -set_global_assignment -name HCPY_VREF_PINS OFF - -# SignalTap II Assignments -# ======================== -set_global_assignment -name HUB_ENTITY_NAME SLD_HUB -set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST -set_global_assignment -name ENABLE_SIGNALTAP OFF - -# LogicLock Region Assignments -# ============================ -set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF - -# ----------------- -# start CLOCK(SCLK) - - # Timing Assignments - # ================== -set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK -set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK -set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK - -# end CLOCK(SCLK) -# --------------- - -# ----------------------- -# start CLOCK(master_clk) - - # Timing Assignments - # ================== -set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk -set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk -set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk - -# end CLOCK(master_clk) -# --------------------- - -# ------------------- -# start CLOCK(usbclk) - - # Timing Assignments - # ================== -set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk -set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk -set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk - -# end CLOCK(usbclk) -# ----------------- - -# ---------------------- -# start ENTITY(mrfm) - - # Timing Assignments - # ================== -set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK -set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk -set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk - -# end ENTITY(mrfm) -# -------------------- - - -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name VERILOG_FILE mrfm.vh -set_global_assignment -name VERILOG_FILE biquad_2stage.v -set_global_assignment -name VERILOG_FILE mrfm_compensator.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v -set_global_assignment -name VERILOG_FILE mrfm_proc.v -set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v -set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v -set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v -set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v -set_global_assignment -name VERILOG_FILE mrfm.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v -set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v -set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
\ No newline at end of file diff --git a/fpga/usrp1/toplevel/mrfm/mrfm.v b/fpga/usrp1/toplevel/mrfm/mrfm.v deleted file mode 100644 index 6b7442ef3..000000000 --- a/fpga/usrp1/toplevel/mrfm/mrfm.v +++ /dev/null @@ -1,199 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2006 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -// Top level module for a full setup with DUCs and DDCs - -// Uncomment the following to include optional circuitry - -`include "mrfm.vh" -`include "../../common/fpga_regs_common.v" -`include "../../common/fpga_regs_standard.v" - -module mrfm -(output MYSTERY_SIGNAL, - input master_clk, - input SCLK, - input SDI, - inout SDO, - input SEN_FPGA, - - input FX2_1, - output FX2_2, - output FX2_3, - - input wire [11:0] rx_a_a, - input wire [11:0] rx_b_a, - input wire [11:0] rx_a_b, - input wire [11:0] rx_b_b, - - output wire [13:0] tx_a, - output wire [13:0] tx_b, - - output wire TXSYNC_A, - output wire TXSYNC_B, - - // USB interface - input usbclk, - input wire [2:0] usbctl, - output wire [1:0] usbrdy, - inout [15:0] usbdata, // NB Careful, inout - - // These are the general purpose i/o's that go to the daughterboard slots - inout wire [15:0] io_tx_a, - inout wire [15:0] io_tx_b, - inout wire [15:0] io_rx_a, - inout wire [15:0] io_rx_b - ); - wire [15:0] debugdata,debugctrl; - assign MYSTERY_SIGNAL = 1'b0; - - wire clk64; - - wire WR = usbctl[0]; - wire RD = usbctl[1]; - wire OE = usbctl[2]; - - wire have_space, have_pkt_rdy; - assign usbrdy[0] = have_space; - assign usbrdy[1] = have_pkt_rdy; - - wire tx_underrun, rx_overrun; - wire clear_status = FX2_1; - assign FX2_2 = rx_overrun; - assign FX2_3 = tx_underrun; - - wire [15:0] usbdata_out; - - wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux; - - wire tx_realsignals; - wire [3:0] rx_numchan; - - wire [15:0] tx_debugbus, rx_debugbus; - - wire enable_tx, enable_rx; - wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset; - wire [7:0] settings; - - // Tri-state bus macro - bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) ); - - assign clk64 = master_clk; - - wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; - wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx; - - wire serial_strobe; - wire [6:0] serial_addr; - wire [31:0] serial_data; - - ///////////////////////////////////////////////////////////////////////////////////////////////////// - - setting_reg #(`FR_TX_MUX) - sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan})); - - ////////////////////////////////////////////////////////////////////////////////////////////////////// - // Signal Processing Chain - - reg [15:0] adc0; - wire [15:0] dac0; - wire [15:0] i,q,ip,qp; - wire strobe_out; - wire sync_out; - - always @(posedge clk64) - adc0 <= #1 {rx_a_a[11],rx_a_a[11:0],3'b0}; - - wire [15:0] adc0_corr; - rx_dcoffset #(0)rx_dcoffset0(.clock(clk64),.enable(1'b1),.reset(reset),.adc_in(adc0),.adc_out(adc0_corr), - .serial_addr(7'd0),.serial_data(32'd0),.serial_strobe(1'b0)); - - //wire [63:0] filt_debug = 64'd0; - - mrfm_proc mrfm_proc(.clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .signal_in(adc0_corr),.signal_out(dac0),.sync_out(sync_out), - .i(i),.q(q),.ip(ip),.qp(qp),.strobe_out(strobe_out), - .debugbus( /* filt_debug */ )); - - wire txsync = 1'b0; - assign TXSYNC_A = txsync; - assign TXSYNC_B = txsync; - - assign tx_a = dac0[15:2]; - - ////////////////////////////////////////////////////////////////////////////////////////////////// - // Data Collection on RX Buffer - - assign rx_numchan[0] = 1'b0; - setting_reg #(`FR_RX_MUX) sr_rxmux(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr), - .in(serial_data),.out(rx_numchan[3:1])); - - rx_buffer rx_buffer - ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset), - .usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun), - .channels(rx_numchan), - .ch_0(i),.ch_1(q), - .ch_2(ip),.ch_3(qp), - .ch_4(16'd0),.ch_5(16'd0), - .ch_6(16'd0),.ch_7(16'd0), - .rxclk(clk64),.rxstrobe(strobe_out), - .clear_status(clear_status), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .debugbus(rx_debugbus) ); - - ////////////////////////////////////////////////////////////////////////////// - // Control Functions - - wire [31:0] capabilities = 32'd2; - - serial_io serial_io - ( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI), - .enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a) ); - - wire [15:0] reg_0,reg_1,reg_2,reg_3; - master_control master_control - ( .master_clk(clk64),.usbclk(usbclk), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset), - .tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset), - .enable_tx(enable_tx),.enable_rx(enable_rx), - .interp_rate(interp_rate),.decim_rate(decim_rate), - .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp), - .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim), - .tx_empty(tx_empty), - .debug_0({15'd0,sync_out}), //filt_debug[63:48]), - .debug_1({15'd0,sync_out}), //filt_debug[47:32]), - .debug_2({15'd0,sync_out}), //filt_debug[31:16]), - .debug_3({15'd0,sync_out}), //filt_debug[15:0]), - .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) ); - - io_pins io_pins - (.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b), - .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3), - .clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)); - -endmodule // mrfm - diff --git a/fpga/usrp1/toplevel/mrfm/mrfm.vh b/fpga/usrp1/toplevel/mrfm/mrfm.vh deleted file mode 100644 index 808342d8d..000000000 --- a/fpga/usrp1/toplevel/mrfm/mrfm.vh +++ /dev/null @@ -1,21 +0,0 @@ - - -// MRFM Register defines - -`define FR_MRFM_DECIM 7'd64 -`define FR_MRFM_FREQ 7'd65 -`define FR_MRFM_PHASE 7'd66 -`define FR_MRFM_IIR_COEFF 7'd67 -`define FR_MRFM_IIR_SHIFT 7'd68 -`define FR_MRFM_DEBUG 7'd69 -`define FR_MRFM_COMP_A11 7'd70 -`define FR_MRFM_COMP_A12 7'd71 -`define FR_MRFM_COMP_A21 7'd72 -`define FR_MRFM_COMP_A22 7'd73 -`define FR_MRFM_COMP_SHIFT 7'd74 -`define FR_USER_11 7'd75 -`define FR_USER_12 7'd76 -`define FR_USER_13 7'd77 -`define FR_USER_14 7'd78 -`define FR_USER_15 7'd79 - diff --git a/fpga/usrp1/toplevel/mrfm/mrfm_compensator.v b/fpga/usrp1/toplevel/mrfm/mrfm_compensator.v deleted file mode 100644 index f44b73b2f..000000000 --- a/fpga/usrp1/toplevel/mrfm/mrfm_compensator.v +++ /dev/null @@ -1,80 +0,0 @@ - - -module mrfm_compensator (input clock, input reset, input strobe_in, - input serial_strobe, input [6:0] serial_addr, input [31:0] serial_data, - input [15:0] i_in, input [15:0] q_in, output reg [15:0] i_out, output reg [15:0] q_out); - - wire [15:0] a11,a12,a21,a22; - reg [15:0] i_in_reg, q_in_reg; - wire [30:0] product; - reg [3:0] phase; - wire [15:0] data,coeff; - wire [7:0] shift; - wire [33:0] accum; - wire [15:0] scaled_accum; - wire enable_acc; - - setting_reg #(`FR_MRFM_COMP_A11) sr_a11(.clock(clock),.reset(reset), - .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out(a11),.changed()); - setting_reg #(`FR_MRFM_COMP_A12) sr_a12(.clock(clock),.reset(reset), - .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out(a12),.changed()); - setting_reg #(`FR_MRFM_COMP_A21) sr_a21(.clock(clock),.reset(reset), - .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out(a21),.changed()); - setting_reg #(`FR_MRFM_COMP_A22) sr_a22(.clock(clock),.reset(reset), - .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out(a22),.changed()); - setting_reg #(`FR_MRFM_COMP_SHIFT) sr_cshift(.clock(clock),.reset(reset), - .strobe(serial_strobe),.addr(serial_addr),.in(serial_data), - .out(shift),.changed()); - - mult mult (.clock(clock),.x(data),.y(coeff),.product(product),.enable_in(1'b1),.enable_out() ); - acc acc (.clock(clock),.reset(reset),.clear(clear_acc),.enable_in(enable_acc),.enable_out(), - .addend(product),.sum(accum) ); - shifter shifter (.in(accum),.out(scaled_accum),.shift(shift)); - - always @(posedge clock) - if(reset) - begin - i_in_reg <= #1 16'd0; - q_in_reg <= #1 16'd0; - end - else if(strobe_in) - begin - i_in_reg <= #1 i_in; - q_in_reg <= #1 q_in; - end - - always @(posedge clock) - if(reset) - phase <= #1 4'd0; - else if(strobe_in) - phase <= #1 4'd1; - else if(strobe_in != 4'd8) - phase <= #1 phase + 4'd1; - - assign data = ((phase == 4'd1)||(phase === 4'd4)) ? i_in_reg : - ((phase == 4'd2)||(phase == 4'd5)) ? q_in_reg : 16'd0; - - assign coeff = (phase == 4'd1) ? a11 : (phase == 4'd2) ? a12 : - (phase == 4'd4) ? a21 : (phase == 4'd5) ? a22 : 16'd0; - - assign clear_acc = (phase == 4'd0) || (phase == 4'd1) || (phase == 4'd4) || (phase==4'd8); - assign enable_acc = ~clear_acc; - - always @(posedge clock) - if(reset) - i_out <= #1 16'd0; - else if(phase == 4'd4) - i_out <= #1 scaled_accum; - - always @(posedge clock) - if(reset) - q_out <= #1 16'd0; - else if(phase == 4'd7) - q_out <= #1 scaled_accum; - - -endmodule // mrfm_compensator diff --git a/fpga/usrp1/toplevel/mrfm/mrfm_fft.py b/fpga/usrp1/toplevel/mrfm/mrfm_fft.py deleted file mode 100755 index a4db0a53d..000000000 --- a/fpga/usrp1/toplevel/mrfm/mrfm_fft.py +++ /dev/null @@ -1,319 +0,0 @@ -#!/usr/bin/env python -# -# This is mrfm_fft_sos.py -# Modification of Matt's mrfm_fft.py that reads filter coefs from file -# -# Copyright 2004,2005 Free Software Foundation, Inc. -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -from gnuradio import gr, gru -from gnuradio import usrp -from gnuradio import eng_notation -from gnuradio.eng_option import eng_option -from gnuradio.wxgui import stdgui, fftsink, waterfallsink, scopesink, form, slider -from optparse import OptionParser -import wx -import sys -import mrfm - - -def pick_subdevice(u): - """ - The user didn't specify a subdevice on the command line. - If there's a daughterboard on A, select A. - If there's a daughterboard on B, select B. - Otherwise, select A. - """ - if u.db[0][0].dbid() >= 0: # dbid is < 0 if there's no d'board or a problem - return (0, 0) - if u.db[1][0].dbid() >= 0: - return (1, 0) - return (0, 0) - -def read_ints(filename): - try: - f = open(filename) - ints = [ int(i) for i in f.read().split() ] - f.close() - return ints - except: - return [] - -class app_flow_graph(stdgui.gui_flow_graph): - def __init__(self, frame, panel, vbox, argv): - stdgui.gui_flow_graph.__init__(self) - - self.frame = frame - self.panel = panel - - parser = OptionParser(option_class=eng_option) - parser.add_option("-R", "--rx-subdev-spec", type="subdev", default=None, - help="select USRP Rx side A or B (default=first one with a daughterboard)") - parser.add_option("-d", "--decim", type="int", default=16, - help="set fgpa decimation rate to DECIM [default=%default]") - parser.add_option("-f", "--freq", type="eng_float", default=None, - help="set frequency to FREQ", metavar="FREQ") - parser.add_option("-g", "--gain", type="eng_float", default=None, - help="set gain in dB (default is midpoint)") - parser.add_option("-W", "--waterfall", action="store_true", default=False, - help="Enable waterfall display") - parser.add_option("-8", "--width-8", action="store_true", default=False, - help="Enable 8-bit samples across USB") - parser.add_option("-S", "--oscilloscope", action="store_true", default=False, - help="Enable oscilloscope display") - parser.add_option("-F", "--filename", default=None, - help="Name of file with filter coefficients") - parser.add_option("-C", "--cfilename", default=None, - help="Name of file with compensator coefficients") - parser.add_option("-B", "--bitstream", default="mrfm.rbf", - help="Name of FPGA Bitstream file (.rbf)") - parser.add_option("-n", "--frame-decim", type="int", default=20, - help="set oscope frame decimation factor to n [default=12]") - (options, args) = parser.parse_args() - if len(args) != 0: - parser.print_help() - sys.exit(1) - - self.show_debug_info = True - - # default filter coefs - b00 = b01 = 16384 - b10 = b20 = a10 = a20 = b11 = b21 = a11 = a21 = 0 - - ba = read_ints(options.filename) - if len(ba) >= 6: - b00 = ba[0]; b10 = ba[1]; b20 = ba[2]; a10 = ba[4]; a20 = ba[5] - if len(ba) >= 12: - b01 = ba[6]; b11 = ba[7]; b21 = ba[8]; a11 = ba[10]; a21=ba[11] - print b00, b10, b20, a10, a20, b01, b11, b21, a11, a21 - - # default compensator coefficients - c11 = c22 = 1 - c12 = c21 = cscale = 0 - - cs = read_ints(options.cfilename) - if len(cs) >= 5: - c11 = cs[0]; c12 = cs[1]; c21 = cs[2]; c22 = cs[3]; cscale = cs[4] - print c11, c12, c21, c22, cscale - - # build the graph - self.u = mrfm.source_c(options.bitstream) - - self.u.set_decim_rate(options.decim) - self.u.set_center_freq(options.freq) - - frac_bits = 14 - self.u.set_coeffs(frac_bits,b20,b10,b00,a20,a10,b21,b11,b01,a21,a11) - - self.u.set_compensator(c11,c12,c21,c22,cscale) - - if options.rx_subdev_spec is None: - options.rx_subdev_spec = pick_subdevice(self.u) - self.u.set_mux(usrp.determine_rx_mux_value(self.u, options.rx_subdev_spec)) - - if options.width_8: - width = 8 - shift = 8 - format = self.u.make_format(width, shift) - print "format =", hex(format) - r = self.u.set_format(format) - print "set_format =", r - - # determine the daughterboard subdevice we're using - self.subdev = usrp.selected_subdev(self.u, options.rx_subdev_spec) - - #input_rate = self.u.adc_freq() / self.u.decim_rate() - input_rate = self.u.adc_freq() / options.decim - - # fft_rate = 15 - fft_rate = 5 - - self.deint = gr.deinterleave(gr.sizeof_gr_complex) - self.connect(self.u,self.deint) - - if options.waterfall: - self.scope1=waterfallsink.waterfall_sink_c (self, panel, fft_size=1024, sample_rate=input_rate, - fft_rate=fft_rate) - self.scope2=waterfallsink.waterfall_sink_c (self, panel, fft_size=1024, sample_rate=input_rate, - fft_rate=fft_rate) - - elif options.oscilloscope: - self.scope1 = scopesink.scope_sink_c(self, panel, sample_rate=input_rate,frame_decim=options.frame_decim) # added option JPJ 4/21/2006 - self.scope2 = scopesink.scope_sink_c(self, panel, sample_rate=input_rate,frame_decim=options.frame_decim) - - else: - self.scope1 = fftsink.fft_sink_c (self, panel, fft_size=1024, sample_rate=input_rate, - fft_rate=fft_rate) - self.scope2 = fftsink.fft_sink_c (self, panel, fft_size=1024, sample_rate=input_rate, - fft_rate=fft_rate) - - # Show I, I' on top scope panel, Q, Q' on bottom - #self.fin = gr.complex_to_float() - #self.fout = gr.complex_to_float() - - #self.connect((self.deint,0), self.fin) - #self.connect((self.deint,1), self.fout) - - #self.ii = gr.float_to_complex() - #self.qq = gr.float_to_complex() - - #self.connect((self.fin,0), (self.ii,0)) - #self.connect((self.fout,0), (self.ii,1)) - #self.connect((self.fin,1), (self.qq,0)) - #self.connect((self.fout,1), (self.qq,1)) - - #self.connect(self.ii, self.scope1) - #self.connect(self.qq, self.scope2) - - self.connect ((self.deint,0),self.scope1) - self.connect ((self.deint,1),self.scope2) - - self._build_gui(vbox) - - # set initial values - - if options.gain is None: - # if no gain was specified, use the mid-point in dB - g = self.subdev.gain_range() - options.gain = float(g[0]+g[1])/2 - - if options.freq is None: - # if no freq was specified, use the mid-point - r = self.subdev.freq_range() - options.freq = float(r[0]+r[1])/2 - - self.set_gain(options.gain) - - if not(self.set_freq(options.freq)): - self._set_status_msg("Failed to set initial frequency") - - if self.show_debug_info: - self.myform['decim'].set_value(self.u.decim_rate()) - self.myform['fs@usb'].set_value(self.u.adc_freq() / self.u.decim_rate()) - self.myform['dbname'].set_value(self.subdev.name()) - - - def _set_status_msg(self, msg): - self.frame.GetStatusBar().SetStatusText(msg, 0) - - def _build_gui(self, vbox): - - def _form_set_freq(kv): - return self.set_freq(kv['freq']) - - vbox.Add(self.scope1.win, 10, wx.EXPAND) - vbox.Add(self.scope2.win, 10, wx.EXPAND) - - # add control area at the bottom - self.myform = myform = form.form() - hbox = wx.BoxSizer(wx.HORIZONTAL) - hbox.Add((5,0), 0, 0) - myform['freq'] = form.float_field( - parent=self.panel, sizer=hbox, label="Center freq", weight=1, - callback=myform.check_input_and_call(_form_set_freq, self._set_status_msg)) - - hbox.Add((5,0), 0, 0) - g = self.subdev.gain_range() - myform['gain'] = form.slider_field(parent=self.panel, sizer=hbox, label="Gain", - weight=3, - min=int(g[0]), max=int(g[1]), - callback=self.set_gain) - - hbox.Add((5,0), 0, 0) - vbox.Add(hbox, 0, wx.EXPAND) - - self._build_subpanel(vbox) - - def _build_subpanel(self, vbox_arg): - # build a secondary information panel (sometimes hidden) - - # FIXME figure out how to have this be a subpanel that is always - # created, but has its visibility controlled by foo.Show(True/False) - - if not(self.show_debug_info): - return - - panel = self.panel - vbox = vbox_arg - myform = self.myform - - #panel = wx.Panel(self.panel, -1) - #vbox = wx.BoxSizer(wx.VERTICAL) - - hbox = wx.BoxSizer(wx.HORIZONTAL) - hbox.Add((5,0), 0) - myform['decim'] = form.static_float_field( - parent=panel, sizer=hbox, label="Decim") - - hbox.Add((5,0), 1) - myform['fs@usb'] = form.static_float_field( - parent=panel, sizer=hbox, label="Fs@USB") - - hbox.Add((5,0), 1) - myform['dbname'] = form.static_text_field( - parent=panel, sizer=hbox) - - hbox.Add((5,0), 1) - myform['baseband'] = form.static_float_field( - parent=panel, sizer=hbox, label="Analog BB") - - hbox.Add((5,0), 1) - myform['ddc'] = form.static_float_field( - parent=panel, sizer=hbox, label="DDC") - - hbox.Add((5,0), 0) - vbox.Add(hbox, 0, wx.EXPAND) - - - - def set_freq(self, target_freq): - """ - Set the center frequency we're interested in. - - @param target_freq: frequency in Hz - @rypte: bool - - Tuning is a two step process. First we ask the front-end to - tune as close to the desired frequency as it can. Then we use - the result of that operation and our target_frequency to - determine the value for the digital down converter. - """ - r = self.u.tune(0, self.subdev, target_freq) - - if r: - self.myform['freq'].set_value(target_freq) # update displayed value - if self.show_debug_info: - self.myform['baseband'].set_value(r.baseband_freq) - self.myform['ddc'].set_value(r.dxc_freq) - return True - - return False - - def set_gain(self, gain): - self.myform['gain'].set_value(gain) # update displayed value - self.subdev.set_gain(gain) - - -def main (): - app = stdgui.stdapp(app_flow_graph, "USRP FFT", nstatus=1) - app.MainLoop() - -if __name__ == '__main__': - main () diff --git a/fpga/usrp1/toplevel/mrfm/mrfm_proc.v b/fpga/usrp1/toplevel/mrfm/mrfm_proc.v deleted file mode 100644 index 7da934a6e..000000000 --- a/fpga/usrp1/toplevel/mrfm/mrfm_proc.v +++ /dev/null @@ -1,96 +0,0 @@ - -`include "mrfm.vh" -`include "../../common/fpga_regs_common.v" -`include "../../common/fpga_regs_standard.v" - -module mrfm_proc (input clock, input reset, input enable, - input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe, - input [15:0] signal_in, output wire [15:0] signal_out, output wire sync_out, - output wire [15:0] i, output wire [15:0] q, - output wire [15:0] ip, output wire [15:0] qp, - output wire strobe_out, output wire [63:0] debugbus); - - // Strobes - wire sample_strobe, strobe_0, strobe_1, strobe_2; - assign sample_strobe = 1'b1; - wire [7:0] rate_0, rate_1, rate_2; - - setting_reg #(`FR_MRFM_DECIM) sr_decim(.clock(clock),.reset(reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out({rate_2,rate_1,rate_0})); - - strobe_gen strobe_gen_0 - ( .clock(clock),.reset(reset),.enable(enable), - .rate(rate_0),.strobe_in(sample_strobe),.strobe(strobe_0) ); - strobe_gen strobe_gen_1 - ( .clock(clock),.reset(reset),.enable(enable), - .rate(rate_1),.strobe_in(strobe_0),.strobe(strobe_1) ); - - wire [31:0] phase; - - assign sync_out = phase[31]; - wire [15:0] i_decim_0, i_decim_1, i_decim_2; - wire [15:0] q_decim_0, q_decim_1, q_decim_2; - - wire [15:0] i_interp_0, i_interp_1, i_interp_2; - wire [15:0] q_interp_0, q_interp_1, q_interp_2; - - wire [15:0] i_filt, q_filt, i_comp, q_comp; - - assign ip=i_comp; - assign qp=q_comp; - - phase_acc #(`FR_MRFM_FREQ,`FR_MRFM_PHASE,32) rx_phase_acc - (.clk(clock),.reset(reset),.enable(enable), - .serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe), - .strobe(sample_strobe),.phase(phase) ); - - cordic rx_cordic (.clock(clock),.reset(reset),.enable(enable), - .xi(signal_in),.yi(16'd0),.zi(phase[31:16]), - .xo(i_decim_0),.yo(q_decim_0),.zo() ); - - cic_decim cic_decim_i_0 (.clock(clock),.reset(reset),.enable(enable), - .rate(rate_0),.strobe_in(sample_strobe),.strobe_out(strobe_0), - .signal_in(i_decim_0),.signal_out(i_decim_1)); - cic_decim cic_decim_i_1 (.clock(clock),.reset(reset),.enable(enable), - .rate(rate_1),.strobe_in(strobe_0),.strobe_out(strobe_1), - .signal_in(i_decim_1),.signal_out(i)); - - cic_decim cic_decim_q_0 (.clock(clock),.reset(reset),.enable(enable), - .rate(rate_0),.strobe_in(sample_strobe),.strobe_out(strobe_0), - .signal_in(q_decim_0),.signal_out(q_decim_1)); - cic_decim cic_decim_q_1 (.clock(clock),.reset(reset),.enable(enable), - .rate(rate_1),.strobe_in(strobe_0),.strobe_out(strobe_1), - .signal_in(q_decim_1),.signal_out(q)); - - assign strobe_out = strobe_1; - - biquad_2stage iir_i (.clock(clock),.reset(reset),.strobe_in(strobe_1), - .serial_strobe(serial_strobe),.serial_addr(serial_addr),.serial_data(serial_data), - .sample_in(i),.sample_out(i_filt),.debugbus(debugbus)); - - biquad_2stage iir_q (.clock(clock),.reset(reset),.strobe_in(strobe_1), - .serial_strobe(serial_strobe),.serial_addr(serial_addr),.serial_data(serial_data), - .sample_in(q),.sample_out(q_filt),.debugbus()); - - mrfm_compensator compensator (.clock(clock),.reset(reset),.strobe_in(strobe_1), - .serial_strobe(serial_strobe),.serial_addr(serial_addr),.serial_data(serial_data), - .i_in(i_filt),.q_in(q_filt),.i_out(i_comp),.q_out(q_comp)); - - cic_interp cic_interp_i_0 (.clock(clock),.reset(reset),.enable(enable), - .rate(rate_1),.strobe_in(strobe_1),.strobe_out(strobe_0), - .signal_in(i_comp),.signal_out(i_interp_0)); - cic_interp cic_interp_i_1 (.clock(clock),.reset(reset),.enable(enable), - .rate(rate_0),.strobe_in(strobe_0),.strobe_out(sample_strobe), - .signal_in(i_interp_0),.signal_out(i_interp_1)); - - cic_interp cic_interp_q_0 (.clock(clock),.reset(reset),.enable(enable), - .rate(rate_1),.strobe_in(strobe_1),.strobe_out(strobe_0), - .signal_in(q_comp),.signal_out(q_interp_0)); - cic_interp cic_interp_q_1 (.clock(clock),.reset(reset),.enable(enable), - .rate(rate_0),.strobe_in(strobe_0),.strobe_out(sample_strobe), - .signal_in(q_interp_0),.signal_out(q_interp_1)); - - cordic tx_cordic (.clock(clock),.reset(reset),.enable(enable), - .xi(i_interp_1),.yi(q_interp_1),.zi(-phase[31:16]), - .xo(signal_out),.yo(),.zo() ); - -endmodule // mrfm_proc diff --git a/fpga/usrp1/toplevel/mrfm/shifter.v b/fpga/usrp1/toplevel/mrfm/shifter.v deleted file mode 100644 index dd4d4b527..000000000 --- a/fpga/usrp1/toplevel/mrfm/shifter.v +++ /dev/null @@ -1,106 +0,0 @@ -// -*- verilog -*- -// -// USRP - Universal Software Radio Peripheral -// -// Copyright (C) 2005,2006 Matt Ettus -// -// This program is free software; you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation; either version 2 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program; if not, write to the Free Software -// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA -// - -module shifter(input wire [33:0] in, output wire [15:0] out, input wire [7:0] shift); - // Wish we could do assign out = in[15+shift:shift]; - - reg [15:0] quotient, remainder; - wire [15:0] out_unclipped; - reg [18:0] msbs; - wire in_range; - - always @* - case(shift) - 0 : quotient = in[15:0]; - 1 : quotient = in[16:1]; - 2 : quotient = in[17:2]; - 3 : quotient = in[18:3]; - 4 : quotient = in[19:4]; - 5 : quotient = in[20:5]; - 6 : quotient = in[21:6]; - 7 : quotient = in[22:7]; - 8 : quotient = in[23:8]; - 9 : quotient = in[24:9]; - 10 : quotient = in[25:10]; - 11 : quotient = in[26:11]; - 12 : quotient = in[27:12]; - 13 : quotient = in[28:13]; - 14 : quotient = in[29:14]; - 15 : quotient = in[30:15]; - 16 : quotient = in[31:16]; - 17 : quotient = in[32:17]; - 18 : quotient = in[33:18]; - default : quotient = in[15:0]; - endcase // case(shift) - - always @* - case(shift) - 0 : remainder = 16'b0; - 1 : remainder = {in[0],15'b0}; - 2 : remainder = {in[1:0],14'b0}; - 3 : remainder = {in[2:0],13'b0}; - 4 : remainder = {in[3:0],12'b0}; - 5 : remainder = {in[4:0],11'b0}; - 6 : remainder = {in[5:0],10'b0}; - 7 : remainder = {in[6:0],9'b0}; - 8 : remainder = {in[7:0],8'b0}; - 9 : remainder = {in[8:0],7'b0}; - 10 : remainder = {in[9:0],6'b0}; - 11 : remainder = {in[10:0],5'b0}; - 12 : remainder = {in[11:0],4'b0}; - 13 : remainder = {in[12:0],3'b0}; - 14 : remainder = {in[13:0],2'b0}; - 15 : remainder = {in[14:0],1'b0}; - 16 : remainder = in[15:0]; - 17 : remainder = in[16:1]; - 18 : remainder = in[17:2]; - default : remainder = 16'b0; - endcase // case(shift) - - always @* - case(shift) - 0 : msbs = in[33:15]; - 1 : msbs = {in[33],in[33:16]}; - 2 : msbs = {{2{in[33]}},in[33:17]}; - 3 : msbs = {{3{in[33]}},in[33:18]}; - 4 : msbs = {{4{in[33]}},in[33:19]}; - 5 : msbs = {{5{in[33]}},in[33:20]}; - 6 : msbs = {{6{in[33]}},in[33:21]}; - 7 : msbs = {{7{in[33]}},in[33:22]}; - 8 : msbs = {{8{in[33]}},in[33:23]}; - 9 : msbs = {{9{in[33]}},in[33:24]}; - 10 : msbs = {{10{in[33]}},in[33:25]}; - 11 : msbs = {{11{in[33]}},in[33:26]}; - 12 : msbs = {{12{in[33]}},in[33:27]}; - 13 : msbs = {{13{in[33]}},in[33:28]}; - 14 : msbs = {{14{in[33]}},in[33:29]}; - 15 : msbs = {{15{in[33]}},in[33:30]}; - 16 : msbs = {{16{in[33]}},in[33:31]}; - 17 : msbs = {{17{in[33]}},in[33:32]}; - 18 : msbs = {{18{in[33]}},in[33]}; - default : msbs = in[33:15]; - endcase // case(shift) - - assign in_range = &msbs | ~(|msbs); - assign out_unclipped = quotient + (in[33] & |remainder); - assign out = in_range ? out_unclipped : {in[33],{15{~in[33]}}}; - -endmodule // shifter |