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authorJosh Blum <josh@joshknows.com>2010-04-15 11:24:41 -0700
committerJosh Blum <josh@joshknows.com>2010-04-15 11:24:41 -0700
commit3a196c5d614fbec9b1010b3082245614ba5e0dc9 (patch)
tree784f075298f5d86c9e7429ce0ff977deaf4315c8 /fpga/usrp1/sdr_lib/setting_reg_masked.v
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Merge branch 'udp'
Diffstat (limited to 'fpga/usrp1/sdr_lib/setting_reg_masked.v')
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diff --git a/fpga/usrp1/sdr_lib/setting_reg_masked.v b/fpga/usrp1/sdr_lib/setting_reg_masked.v
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+
+
+module setting_reg_masked
+ ( input clock, input reset, input strobe, input wire [6:0] addr,
+ input wire [31:0] in, output reg [31:0] out, output reg changed);
+/* upper 16 bits are mask, lower 16 bits are value
+ * Note that you get a 16 bit register, not a 32 bit one */
+
+ parameter my_addr = 0;
+
+ always @(posedge clock)
+ if(reset)
+ begin
+ out <= #1 32'd0;
+ changed <= #1 1'b0;
+ end
+ else
+ if(strobe & (my_addr==addr))
+ begin
+ out <= #1 (out & ~in[31:16]) | (in[15:0] & in[31:16] );
+ changed <= #1 1'b1;
+ end
+ else
+ changed <= #1 1'b0;
+
+endmodule // setting_reg_masked