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authorJosh Blum <josh@joshknows.com>2011-09-28 13:27:33 -0700
committerJosh Blum <josh@joshknows.com>2011-09-28 13:27:33 -0700
commit4226748ddda610eafaf5c6c32be206c336232b80 (patch)
tree93795f42993ba85ffe4b1d4b539bc72eccd638d5 /fpga/usrp1/sdr_lib/rx_buffer.v
parentc2122833e25ffe6e8e6918874afe7a3c9a92bc87 (diff)
parent24b07e1b0dbe8ab9d72c46f65c14c34e84347554 (diff)
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Merge branch 'fpga_master' into uhd_master
Conflicts: fpga/usrp1/toplevel/usrp_std/usrp_std.v
Diffstat (limited to 'fpga/usrp1/sdr_lib/rx_buffer.v')
-rw-r--r--fpga/usrp1/sdr_lib/rx_buffer.v4
1 files changed, 2 insertions, 2 deletions
diff --git a/fpga/usrp1/sdr_lib/rx_buffer.v b/fpga/usrp1/sdr_lib/rx_buffer.v
index d17294b98..5541d2912 100644
--- a/fpga/usrp1/sdr_lib/rx_buffer.v
+++ b/fpga/usrp1/sdr_lib/rx_buffer.v
@@ -22,8 +22,8 @@
// Interface to Cypress FX2 bus
// A packet is 512 Bytes, the fifo has 4096 lines of 18 bits each
-`include "../../firmware/include/fpga_regs_common.v"
-`include "../../firmware/include/fpga_regs_standard.v"
+`include "../common/fpga_regs_common.v"
+`include "../common/fpga_regs_standard.v"
module rx_buffer
( // Read/USB side