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author | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:24 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:24 -0700 |
commit | 05d77f772317de5d925301aa11bb9a880656dd05 (patch) | |
tree | 0910bfb9265fab1644a3d3a1706719f1b038d193 /fpga/usrp1/sdr_lib/ram64.v | |
parent | 16818dc98e97b69a028c47e66ebfb16e32565533 (diff) | |
download | uhd-05d77f772317de5d925301aa11bb9a880656dd05.tar.gz uhd-05d77f772317de5d925301aa11bb9a880656dd05.tar.bz2 uhd-05d77f772317de5d925301aa11bb9a880656dd05.zip |
moved usrp1 and usrp2 fpga dirs into fpga subdirectory
Diffstat (limited to 'fpga/usrp1/sdr_lib/ram64.v')
-rw-r--r-- | fpga/usrp1/sdr_lib/ram64.v | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/fpga/usrp1/sdr_lib/ram64.v b/fpga/usrp1/sdr_lib/ram64.v new file mode 100644 index 000000000..084545808 --- /dev/null +++ b/fpga/usrp1/sdr_lib/ram64.v @@ -0,0 +1,16 @@ + + +module ram64 (input clock, input write, + input [5:0] wr_addr, input [15:0] wr_data, + input [5:0] rd_addr, output reg [15:0] rd_data); + + reg [15:0] ram_array [0:63]; + + always @(posedge clock) + rd_data <= #1 ram_array[rd_addr]; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + +endmodule // ram64 |