Removed copy of FPGA source files.

1 files changed, 0 insertions, 16 deletions

diff --git a/fpga/usrp1/sdr_lib/ram.v b/fpga/usrp1/sdr_lib/ram.v
deleted file mode 100644
index fb64cdeae..000000000
--- a/fpga/usrp1/sdr_lib/ram.v
+++ /dev/null
@@ -1,16 +0,0 @@
-
-
-module ram (input clock, input write, 
-	    input [4:0] wr_addr, input [15:0] wr_data,
-	    input [4:0] rd_addr, output reg [15:0] rd_data);
-
-   reg [15:0] 		ram_array [0:31];
-
-   always @(posedge clock)
-     rd_data <= #1 ram_array[rd_addr];
-
-   always @(posedge clock)
-     if(write)
-       ram_array[wr_addr] <= #1 wr_data;
-
-endmodule // ram