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authorJosh Blum <josh@joshknows.com>2010-04-15 11:24:41 -0700
committerJosh Blum <josh@joshknows.com>2010-04-15 11:24:41 -0700
commit3a196c5d614fbec9b1010b3082245614ba5e0dc9 (patch)
tree784f075298f5d86c9e7429ce0ff977deaf4315c8 /fpga/usrp1/sdr_lib/hb/ram32_2sum.v
parentcbf7a0916f0455743d8446a8edc0f0775e3e63ed (diff)
parent05d77f772317de5d925301aa11bb9a880656dd05 (diff)
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Merge branch 'udp'
Diffstat (limited to 'fpga/usrp1/sdr_lib/hb/ram32_2sum.v')
-rw-r--r--fpga/usrp1/sdr_lib/hb/ram32_2sum.v22
1 files changed, 22 insertions, 0 deletions
diff --git a/fpga/usrp1/sdr_lib/hb/ram32_2sum.v b/fpga/usrp1/sdr_lib/hb/ram32_2sum.v
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+++ b/fpga/usrp1/sdr_lib/hb/ram32_2sum.v
@@ -0,0 +1,22 @@
+
+
+module ram32_2sum (input clock, input write,
+ input [4:0] wr_addr, input [15:0] wr_data,
+ input [4:0] rd_addr1, input [4:0] rd_addr2,
+ output reg [15:0] sum);
+
+ reg [15:0] ram_array [0:31];
+ wire [16:0] sum_int;
+
+ always @(posedge clock)
+ if(write)
+ ram_array[wr_addr] <= #1 wr_data;
+
+ assign sum_int = ram_array[rd_addr1] + ram_array[rd_addr2];
+
+ always @(posedge clock)
+ sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]);
+
+
+endmodule // ram32_2sum
+