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authorMartin Braun <martin.braun@ettus.com>2014-10-07 11:25:20 +0200
committerMartin Braun <martin.braun@ettus.com>2014-10-07 11:25:20 +0200
commitfd3e84941de463fa1a7ebab0a69515b4bf2614cd (patch)
tree3fa721a13d41d2c0451d663a59a220a38fd5e614 /fpga/usrp1/sdr_lib/hb/ram16_2sum.v
parent3b66804e41891e358c790b453a7a59ec7462dba4 (diff)
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Removed copy of FPGA source files.
Diffstat (limited to 'fpga/usrp1/sdr_lib/hb/ram16_2sum.v')
-rw-r--r--fpga/usrp1/sdr_lib/hb/ram16_2sum.v27
1 files changed, 0 insertions, 27 deletions
diff --git a/fpga/usrp1/sdr_lib/hb/ram16_2sum.v b/fpga/usrp1/sdr_lib/hb/ram16_2sum.v
deleted file mode 100644
index 559b06fd5..000000000
--- a/fpga/usrp1/sdr_lib/hb/ram16_2sum.v
+++ /dev/null
@@ -1,27 +0,0 @@
-
-
-module ram16_2sum (input clock, input write,
- input [3:0] wr_addr, input [15:0] wr_data,
- input [3:0] rd_addr1, input [3:0] rd_addr2,
- output reg [15:0] sum);
-
- reg signed [15:0] ram_array [0:15];
- reg signed [15:0] a,b;
- wire signed [16:0] sum_int;
-
- always @(posedge clock)
- if(write)
- ram_array[wr_addr] <= #1 wr_data;
-
- always @(posedge clock)
- begin
- a <= #1 ram_array[rd_addr1];
- b <= #1 ram_array[rd_addr2];
- end
-
- assign sum_int = {a[15],a} + {b[15],b};
-
- always @(posedge clock)
- sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]);
-
-endmodule // ram16_2sum