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authorJosh Blum <josh@joshknows.com>2010-04-15 11:24:41 -0700
committerJosh Blum <josh@joshknows.com>2010-04-15 11:24:41 -0700
commit3a196c5d614fbec9b1010b3082245614ba5e0dc9 (patch)
tree784f075298f5d86c9e7429ce0ff977deaf4315c8 /fpga/usrp1/sdr_lib/dpram.v
parentcbf7a0916f0455743d8446a8edc0f0775e3e63ed (diff)
parent05d77f772317de5d925301aa11bb9a880656dd05 (diff)
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Merge branch 'udp'
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+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
+//
+
+
+
+module dpram(wclk,wdata,waddr,wen,rclk,rdata,raddr);
+ parameter depth = 4;
+ parameter width = 16;
+ parameter size = 16;
+
+ input wclk;
+ input [width-1:0] wdata;
+ input [depth-1:0] waddr;
+ input wen;
+
+ input rclk;
+ output reg [width-1:0] rdata;
+ input [depth-1:0] raddr;
+
+ reg [width-1:0] ram [0:size-1];
+
+ always @(posedge wclk)
+ if(wen)
+ ram[waddr] <= #1 wdata;
+
+ always @(posedge rclk)
+ rdata <= #1 ram[raddr];
+
+endmodule // dpram