Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

11 files changed, 506 insertions, 0 deletions

diff --git a/fpga/usrp1/models/bustri.v b/fpga/usrp1/models/bustri.v
new file mode 100644
index 000000000..6e5a0f74c
--- /dev/null
+++ b/fpga/usrp1/models/bustri.v
@@ -0,0 +1,17 @@
+
+// Model for tristate bus on altera
+// FIXME do we really need to use a megacell for this?
+
+module bustri (data,
+	       enabledt,
+	       tridata);
+   
+   input [15:0]  data;
+   input 	 enabledt;
+   inout [15:0]  tridata;
+   
+   assign 	 tridata = enabledt ? data :16'bz;
+   
+endmodule // bustri
+
+
diff --git a/fpga/usrp1/models/fifo.v b/fpga/usrp1/models/fifo.v
new file mode 100644
index 000000000..0ade49e9c
--- /dev/null
+++ b/fpga/usrp1/models/fifo.v
@@ -0,0 +1,82 @@
+// Model of FIFO in Altera
+
+module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+		    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+   
+   parameter width = 16;
+   parameter depth = 1024;
+   parameter addr_bits = 10;
+   
+   //`define rd_req 0;  // Set this to 0 for rd_ack, 1 for rd_req
+   
+   input [width-1:0] data;
+   input 	     wrreq;
+   input 	     rdreq;
+   input 	     rdclk;
+   input 	     wrclk;
+   input 	     aclr;
+   output [width-1:0] q;
+   output 	      rdfull;
+   output 	      rdempty;
+   output reg [addr_bits-1:0]  rdusedw;
+   output wrfull;
+   output wrempty;
+   output reg [addr_bits-1:0]  wrusedw;
+   
+   reg [width-1:0] mem [0:depth-1];
+   reg [addr_bits-1:0] 	      rdptr;
+   reg [addr_bits-1:0] 	      wrptr;
+   
+`ifdef rd_req
+   reg [width-1:0]    q;
+`else
+   wire [width-1:0]   q;
+`endif
+   
+   integer 	      i;
+   
+   always @( aclr)
+     begin
+	wrptr <= #1 0;
+	rdptr <= #1 0;
+	for(i=0;i<depth;i=i+1)
+	  mem[i] <= #1 0;
+     end
+   
+   always @(posedge wrclk)
+     if(wrreq)
+       begin
+	  wrptr <= #1 wrptr+1;
+	  mem[wrptr] <= #1 data;
+       end
+   
+   always @(posedge rdclk)
+     if(rdreq)
+       begin
+   	  rdptr <= #1 rdptr+1;
+`ifdef rd_req
+	  q <= #1 mem[rdptr];
+`endif
+       end
+   
+`ifdef rd_req
+`else
+   assign q = mem[rdptr];
+`endif
+   
+   // Fix these
+   always @(posedge wrclk)
+     wrusedw <= #1 wrptr - rdptr;
+   
+   always @(posedge rdclk)
+     rdusedw <= #1 wrptr - rdptr;
+   
+   assign wrempty = (wrusedw == 0);
+   assign wrfull = (wrusedw == depth-1);
+   
+   assign rdempty = (rdusedw == 0);
+   assign rdfull = (rdusedw == depth-1);
+   
+endmodule // fifo
+
+
diff --git a/fpga/usrp1/models/fifo_1c_1k.v b/fpga/usrp1/models/fifo_1c_1k.v
new file mode 100644
index 000000000..d11040b54
--- /dev/null
+++ b/fpga/usrp1/models/fifo_1c_1k.v
@@ -0,0 +1,81 @@
+// Model of FIFO in Altera
+
+module fifo_1c_1k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+		    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+   parameter width = 32;
+   parameter depth = 1024;
+   //`define rd_req 0;  // Set this to 0 for rd_ack, 1 for rd_req
+      
+   input [31:0] data;
+   input 	wrreq;
+   input 	rdreq;
+   input 	rdclk;
+   input 	wrclk;
+   input 	aclr;
+   output [31:0] q;
+   output 	 rdfull;
+   output 	 rdempty;
+   output [9:0]  rdusedw;
+   output 	 wrfull;
+   output 	 wrempty;
+   output [9:0]  wrusedw;
+   
+   reg [width-1:0] mem [0:depth-1];
+   reg [7:0] 	   rdptr;
+   reg [7:0] 	   wrptr;
+   
+`ifdef rd_req
+   reg [width-1:0] q;
+`else
+   wire [width-1:0] q;
+`endif
+   
+   reg [9:0] 	    rdusedw;
+   reg [9:0] 	    wrusedw;
+   
+   integer 	    i;
+
+   always @( aclr)
+     begin
+	wrptr <= #1 0;
+	rdptr <= #1 0;
+	for(i=0;i<depth;i=i+1)
+	  mem[i] <= #1 0;
+     end
+   
+   always @(posedge wrclk)
+     if(wrreq)
+       begin
+	  wrptr <= #1 wrptr+1;
+	  mem[wrptr] <= #1 data;
+       end
+   
+   always @(posedge rdclk)
+     if(rdreq)
+       begin
+   	  rdptr <= #1 rdptr+1;
+`ifdef rd_req
+	  q <= #1 mem[rdptr];
+`endif
+       end
+   
+`ifdef rd_req
+`else
+   assign q = mem[rdptr];
+`endif
+   
+   // Fix these
+   always @(posedge wrclk)
+     wrusedw <= #1 wrptr - rdptr;
+   
+   always @(posedge rdclk)
+     rdusedw <= #1 wrptr - rdptr;
+
+   assign wrempty = (wrusedw == 0);
+   assign wrfull = (wrusedw == depth-1);
+
+   assign rdempty = (rdusedw == 0);
+   assign rdfull = (rdusedw == depth-1);
+   
+endmodule // fifo_1c_1k
diff --git a/fpga/usrp1/models/fifo_1c_2k.v b/fpga/usrp1/models/fifo_1c_2k.v
new file mode 100644
index 000000000..5c3acfef5
--- /dev/null
+++ b/fpga/usrp1/models/fifo_1c_2k.v
@@ -0,0 +1,81 @@
+// Model of FIFO in Altera
+
+module fifo_1c_2k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+		    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+   parameter width = 32;
+   parameter depth = 2048;
+   //`define rd_req 0;  // Set this to 0 for rd_ack, 1 for rd_req
+      
+   input [31:0] data;
+   input 	wrreq;
+   input 	rdreq;
+   input 	rdclk;
+   input 	wrclk;
+   input 	aclr;
+   output [31:0] q;
+   output 	 rdfull;
+   output 	 rdempty;
+   output [10:0]  rdusedw;
+   output 	 wrfull;
+   output 	 wrempty;
+   output [10:0]  wrusedw;
+   
+   reg [width-1:0] mem [0:depth-1];
+   reg [7:0] 	   rdptr;
+   reg [7:0] 	   wrptr;
+   
+`ifdef rd_req
+   reg [width-1:0] q;
+`else
+   wire [width-1:0] q;
+`endif
+   
+   reg [10:0] 	    rdusedw;
+   reg [10:0] 	    wrusedw;
+   
+   integer 	    i;
+
+   always @( aclr)
+     begin
+	wrptr <= #1 0;
+	rdptr <= #1 0;
+	for(i=0;i<depth;i=i+1)
+	  mem[i] <= #1 0;
+     end
+   
+   always @(posedge wrclk)
+     if(wrreq)
+       begin
+	  wrptr <= #1 wrptr+1;
+	  mem[wrptr] <= #1 data;
+       end
+   
+   always @(posedge rdclk)
+     if(rdreq)
+       begin
+   	  rdptr <= #1 rdptr+1;
+`ifdef rd_req
+	  q <= #1 mem[rdptr];
+`endif
+       end
+   
+`ifdef rd_req
+`else
+   assign q = mem[rdptr];
+`endif
+   
+   // Fix these
+   always @(posedge wrclk)
+     wrusedw <= #1 wrptr - rdptr;
+   
+   always @(posedge rdclk)
+     rdusedw <= #1 wrptr - rdptr;
+
+   assign wrempty = (wrusedw == 0);
+   assign wrfull = (wrusedw == depth-1);
+   
+   assign rdempty = (rdusedw == 0);
+   assign rdfull = (rdusedw == depth-1);
+   
+endmodule // fifo_1c_2k
diff --git a/fpga/usrp1/models/fifo_1c_4k.v b/fpga/usrp1/models/fifo_1c_4k.v
new file mode 100644
index 000000000..3e5ddd052
--- /dev/null
+++ b/fpga/usrp1/models/fifo_1c_4k.v
@@ -0,0 +1,76 @@
+// Model of FIFO in Altera
+
+module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+		    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+
+   parameter width = 32;
+   parameter depth = 4096;
+   //`define rd_req 0;  // Set this to 0 for rd_ack, 1 for rd_req
+      
+   input [31:0] data;
+   input 	wrreq;
+   input 	rdreq;
+   input 	rdclk;
+   input 	wrclk;
+   input 	aclr;
+   output [31:0] q;
+   output 	 rdfull;
+   output 	 rdempty;
+   output [7:0]  rdusedw;
+   output 	 wrfull;
+   output 	 wrempty;
+   output [7:0]  wrusedw;
+   
+   reg [width-1:0] mem [0:depth-1];
+   reg [7:0] 	   rdptr;
+   reg [7:0] 	   wrptr;
+   
+`ifdef rd_req
+   reg [width-1:0] q;
+`else
+   wire [width-1:0] q;
+`endif
+   
+   reg [7:0] 	    rdusedw;
+   reg [7:0] 	    wrusedw;
+   
+   integer 	    i;
+
+   always @( aclr)
+     begin
+	wrptr <= #1 0;
+	rdptr <= #1 0;
+	for(i=0;i<depth;i=i+1)
+	  mem[i] <= #1 0;
+     end
+   
+   always @(posedge wrclk)
+     if(wrreq)
+       begin
+	  wrptr <= #1 wrptr+1;
+	  mem[wrptr] <= #1 data;
+       end
+   
+   always @(posedge rdclk)
+     if(rdreq)
+       begin
+   	  rdptr <= #1 rdptr+1;
+`ifdef rd_req
+	  q <= #1 mem[rdptr];
+`endif
+       end
+   
+`ifdef rd_req
+`else
+   assign q = mem[rdptr];
+`endif
+   
+   // Fix these
+   always @(posedge wrclk)
+     wrusedw <= #1 wrptr - rdptr;
+   
+   always @(posedge rdclk)
+     rdusedw <= #1 wrptr - rdptr;
+   
+   
+endmodule // fifo_1c_4k
diff --git a/fpga/usrp1/models/fifo_1k.v b/fpga/usrp1/models/fifo_1k.v
new file mode 100644
index 000000000..acfa4d176
--- /dev/null
+++ b/fpga/usrp1/models/fifo_1k.v
@@ -0,0 +1,24 @@
+
+
+module fifo_1k
+  (  input [15:0] data,
+     input 	wrreq,
+     input 	rdreq,
+     input 	rdclk,
+     input 	wrclk,
+     input 	aclr,
+     output [15:0] q,
+     output 	 rdfull,
+     output 	 rdempty,
+     output [9:0] rdusedw,
+     output 	 wrfull,
+     output 	 wrempty,
+     output [9:0]  wrusedw
+     );
+
+fifo #(.width(16),.depth(1024),.addr_bits(10)) fifo_1k 
+  ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+   
+endmodule // fifo_1k
+   
diff --git a/fpga/usrp1/models/fifo_2k.v b/fpga/usrp1/models/fifo_2k.v
new file mode 100644
index 000000000..50cd7811d
--- /dev/null
+++ b/fpga/usrp1/models/fifo_2k.v
@@ -0,0 +1,24 @@
+
+
+module fifo_2k
+  (  input [15:0] data,
+     input 	wrreq,
+     input 	rdreq,
+     input 	rdclk,
+     input 	wrclk,
+     input 	aclr,
+     output [15:0] q,
+     output 	 rdfull,
+     output 	 rdempty,
+     output [10:0] rdusedw,
+     output 	 wrfull,
+     output 	 wrempty,
+     output [10:0]  wrusedw
+     );
+
+fifo #(.width(16),.depth(2048),.addr_bits(11)) fifo_2k 
+  ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+   
+endmodule // fifo_1k
+   
diff --git a/fpga/usrp1/models/fifo_4k.v b/fpga/usrp1/models/fifo_4k.v
new file mode 100644
index 000000000..1fa4ba0a7
--- /dev/null
+++ b/fpga/usrp1/models/fifo_4k.v
@@ -0,0 +1,24 @@
+
+
+module fifo_4k
+  (  input [15:0] data,
+     input 	wrreq,
+     input 	rdreq,
+     input 	rdclk,
+     input 	wrclk,
+     input 	aclr,
+     output [15:0] q,
+     output 	 rdfull,
+     output 	 rdempty,
+     output [11:0] rdusedw,
+     output 	 wrfull,
+     output 	 wrempty,
+     output [11:0]  wrusedw
+     );
+
+fifo #(.width(16),.depth(4096),.addr_bits(12)) fifo_4k 
+  ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+   
+endmodule // fifo_1k
+   
diff --git a/fpga/usrp1/models/fifo_4k_18.v b/fpga/usrp1/models/fifo_4k_18.v
new file mode 100644
index 000000000..3efbf74f0
--- /dev/null
+++ b/fpga/usrp1/models/fifo_4k_18.v
@@ -0,0 +1,26 @@
+
+
+module fifo_4k_18
+  (input  [17:0] data,
+   input         wrreq,
+   input         wrclk,
+   output 	 wrfull,
+   output 	 wrempty,
+   output [11:0] wrusedw,
+
+   output [17:0] q,
+   input         rdreq,
+   input         rdclk,
+   output 	 rdfull,
+   output 	 rdempty,
+   output [11:0] rdusedw,
+
+   input 	 aclr );
+
+fifo #(.width(18),.depth(4096),.addr_bits(12)) fifo_4k 
+  ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
+    rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
+   
+endmodule // fifo_4k_18
+
+   
diff --git a/fpga/usrp1/models/pll.v b/fpga/usrp1/models/pll.v
new file mode 100644
index 000000000..1d0cc7966
--- /dev/null
+++ b/fpga/usrp1/models/pll.v
@@ -0,0 +1,33 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Very simple model for the PLL in the RX buffer
+
+module pll (inclk0,c0);
+   
+   input	  inclk0;
+   output	  c0;
+
+   assign 	  c0 = #9 inclk0;
+      
+endmodule // pll
+
+
diff --git a/fpga/usrp1/models/ssram.v b/fpga/usrp1/models/ssram.v
new file mode 100644
index 000000000..fd7339970
--- /dev/null
+++ b/fpga/usrp1/models/ssram.v
@@ -0,0 +1,38 @@
+
+// Model of Pipelined [ZBT] Synchronous SRAM
+
+module ssram(clock,addr,data,wen,ce);
+   parameter addrbits = 19;
+   parameter depth = 524288;
+
+   input clock;
+   input [addrbits-1:0] addr;
+   inout [35:0] data;
+   input wen;
+   input ce;
+
+   reg [35:0] ram [0:depth-1];
+   
+   reg read_d1,read_d2;
+   reg write_d1,write_d2;
+   reg [addrbits-1:0] addr_d1,addr_d2;
+   
+   always @(posedge clock)
+     begin
+	read_d1 <= #1 ce & ~wen;
+	write_d1 <= #1 ce & wen;
+	addr_d1 <= #1 addr;
+	read_d2 <= #1 read_d1;
+	write_d2 <= #1 write_d1;
+	addr_d2 <= #1 addr_d1;
+	if(write_d2)
+	  ram[addr_d2] = data;
+     end // always @ (posedge clock)
+
+   data = (ce & read_d2) ? ram[addr_d2] : 36'bz;
+
+   always @(posedge clock)
+     if(~ce & (write_d2 | write_d1 | wen))
+       $display("$time ERROR:  RAM CE not asserted during write cycle");
+   
+endmodule // ssram