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| author | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
| commit | fd3e84941de463fa1a7ebab0a69515b4bf2614cd (patch) | |
| tree | 3fa721a13d41d2c0451d663a59a220a38fd5e614 /fpga/usrp1/models/bustri.v | |
| parent | 3b66804e41891e358c790b453a7a59ec7462dba4 (diff) | |
| download | uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.gz uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.bz2 uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.zip | |
Removed copy of FPGA source files.
Diffstat (limited to 'fpga/usrp1/models/bustri.v')
| -rw-r--r-- | fpga/usrp1/models/bustri.v | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/fpga/usrp1/models/bustri.v b/fpga/usrp1/models/bustri.v deleted file mode 100644 index 6e5a0f74c..000000000 --- a/fpga/usrp1/models/bustri.v +++ /dev/null @@ -1,17 +0,0 @@ - -// Model for tristate bus on altera -// FIXME do we really need to use a megacell for this? - -module bustri (data, - enabledt, - tridata); - - input [15:0] data; - input enabledt; - inout [15:0] tridata; - - assign tridata = enabledt ? data :16'bz; - -endmodule // bustri - - |