Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 152 insertions, 0 deletions

diff --git a/fpga/usrp1/inband_lib/packet_builder.v b/fpga/usrp1/inband_lib/packet_builder.v
new file mode 100755
index 000000000..2c9122394
--- /dev/null
+++ b/fpga/usrp1/inband_lib/packet_builder.v
@@ -0,0 +1,152 @@
+module packet_builder #(parameter NUM_CHAN = 2)(
+    // System
+    input rxclk,
+    input reset,
+	 input [31:0] timestamp_clock,
+	 input [3:0] channels,
+    // ADC side
+    input [15:0]chan_fifodata,
+    input [NUM_CHAN:0]chan_empty,
+    input [9:0]chan_usedw,
+    output reg [3:0]rd_select,
+    output reg chan_rdreq,
+    // FX2 side
+    output reg WR,
+    output reg [15:0]fifodata,
+    input have_space, 
+    input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2,
+    input wire [31:0]rssi_3, output wire [7:0] debugbus,
+    input [NUM_CHAN:0] underrun);
+    
+    
+    // States
+    `define IDLE                     3'd0
+    `define HEADER1                  3'd1
+    `define HEADER2                  3'd2
+    `define TIMESTAMP                3'd3
+    `define FORWARD                  3'd4
+	
+    `define MAXPAYLOAD 504
+    
+    `define PAYLOAD_LEN 8:0
+    `define TAG 12:9
+    `define MBZ 15:13
+    
+    `define CHAN 4:0
+    `define RSSI 10:5
+    `define BURST 12:11
+    `define DROPPED 13
+    `define UNDERRUN 14
+    `define OVERRUN 15
+    
+    reg [NUM_CHAN:0] overrun;
+    reg [2:0] state;
+    reg [8:0] read_length;
+    reg [8:0] payload_len;
+    reg timestamp_complete;
+    reg [3:0] check_next;
+	
+    wire [31:0] true_rssi;
+    wire [4:0] true_channel;
+    wire ready_to_send;
+
+    assign debugbus = {chan_empty[0], rd_select[0], have_space, 
+                       (chan_usedw >= 10'd504), (chan_usedw ==0),  
+                       ready_to_send, state[1:0]};
+
+    assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
+							((rd_select[0]) ? rssi_1:rssi_0);
+    assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1});
+    assign ready_to_send = (chan_usedw >= 10'd504) || (chan_usedw == 0) || 
+                           ((rd_select == NUM_CHAN)&&(chan_usedw > 0));
+		
+    always @(posedge rxclk)
+    begin
+        if (reset)
+          begin
+            overrun <= 0;
+            WR <= 0;
+            rd_select <= 0;
+            chan_rdreq <= 0;
+            timestamp_complete <= 0;
+            check_next <= 0;
+            state <= `IDLE;
+          end
+        else case (state)
+            `IDLE: begin
+		chan_rdreq <= #1 0;
+		//check if the channel is full
+		if(~chan_empty[check_next])
+		  begin
+                    if (have_space)
+                      begin
+                        //transmit if the usb buffer have space
+                       //check if we should send
+                       if (ready_to_send)
+                           state <= #1 `HEADER1;
+						    
+                       overrun[check_next] <= 0;
+                      end
+                  else
+                    begin
+                      state <= #1 `IDLE;
+                      overrun[check_next] <= 1;
+                    end
+                  rd_select <= #1 check_next;
+                end
+                check_next <= #1 (check_next == channels ? 4'd0 : check_next + 4'd1);
+            end
+            
+            `HEADER1: begin
+                fifodata[`PAYLOAD_LEN] <= #1 9'd504;
+                payload_len <= #1 9'd504;
+                fifodata[`TAG] <= #1 0;
+                fifodata[`MBZ] <= #1 0;
+                WR <= #1 1;
+                
+                state <= #1 `HEADER2;
+                read_length <= #1 0;
+            end
+            
+            `HEADER2: begin
+                fifodata[`CHAN] <= #1 true_channel;
+                fifodata[`RSSI] <= #1 true_rssi[5:0];
+                fifodata[`BURST] <= #1 0;
+                fifodata[`DROPPED] <= #1 0;
+                fifodata[`UNDERRUN] <= #1 (check_next == 0) ? 1'b0 : underrun[true_channel];
+                fifodata[`OVERRUN] <= #1 (check_next == 0) ? 1'b0 : overrun[true_channel];
+                state <= #1 `TIMESTAMP;
+            end
+            
+            `TIMESTAMP: begin
+                fifodata <= #1 (timestamp_complete ? timestamp_clock[31:16] : timestamp_clock[15:0]);
+                timestamp_complete <= #1 ~timestamp_complete;
+                
+                if (~timestamp_complete)
+                    chan_rdreq <= #1 1;
+                
+                state <= #1 (timestamp_complete ? `FORWARD : `TIMESTAMP);
+            end
+            
+            `FORWARD: begin
+                read_length <= #1 read_length + 9'd2;
+                fifodata <= #1 (read_length >= payload_len ? 16'hDEAD : chan_fifodata);
+                
+                if (read_length >= `MAXPAYLOAD)
+                  begin
+                    WR <= #1 0;
+                    state <= #1 `IDLE;
+					chan_rdreq <= #1 0;
+                  end
+                else if (read_length == payload_len - 4)
+                    chan_rdreq <= #1 0;
+            end
+            
+            default: begin
+				//handling error state
+                state <= `IDLE;
+            end
+            endcase
+    end
+endmodule
+