diff options
| author | Wade Fife <wade.fife@ettus.com> | 2021-06-09 10:09:22 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2021-06-17 08:16:59 -0500 |
| commit | 4dc2b7010c0f3e41758b8192636ef7672caae0f7 (patch) | |
| tree | ddd120f8750bc08b4c4ff935a3b03888f5e89a89 /fpga/docs | |
| parent | 9ff2dd8e41e6f34d99cba28640ab00290906cae6 (diff) | |
| download | uhd-4dc2b7010c0f3e41758b8192636ef7672caae0f7.tar.gz uhd-4dc2b7010c0f3e41758b8192636ef7672caae0f7.tar.bz2 uhd-4dc2b7010c0f3e41758b8192636ef7672caae0f7.zip | |
fpga: tools: Add ip target to simulation makefiles
Allow building of just the IP by running "make ip" in simulation
directories.
Diffstat (limited to 'fpga/docs')
| -rw-r--r-- | fpga/docs/usrp3/sim/running_testbenches.md | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/fpga/docs/usrp3/sim/running_testbenches.md b/fpga/docs/usrp3/sim/running_testbenches.md index 2b56af86d..136834bc6 100644 --- a/fpga/docs/usrp3/sim/running_testbenches.md +++ b/fpga/docs/usrp3/sim/running_testbenches.md @@ -15,6 +15,7 @@ all supported simulator targets. Currently, the following targets will work: ipclean: Cleanup all IP intermediate files clean: Cleanup all simulator intermediate files cleanall: Cleanup everything! + ip: Generate the IP required for this simulation xsim: Run the simulation using the Xilinx Vivado Simulator xclean: Cleanup Xilinx Vivado Simulator intermediate files vsim: Run the simulation using ModelSim simulator via Vivado |