Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 87 insertions, 0 deletions

diff --git a/fpga/docs/usrp3/vivado_env_utils.md b/fpga/docs/usrp3/vivado_env_utils.md
new file mode 100644
index 000000000..ad5c6266e
--- /dev/null
+++ b/fpga/docs/usrp3/vivado_env_utils.md
@@ -0,0 +1,87 @@
+# Vivado Environment Utilities
+
+## Environment Setup
+
+- Navigate to `usrp3/top/{project}` where project is:
+  + x300: For USRP X300 and USRP X310
+  + e3xx: For USRP E310
+  + e320: For USRP E320
+  + n3xx: For USRP N300/N310/N320
+
+- To setup up the Ettus Research Xilinx build environment run
+  + `source setupenv.sh` (If Vivado is installed in the default path /opt/Xilinx/Vivado) _OR_
+  + `source setupenv.sh --vivado-path=<VIVADO_PATH>` (where VIVADO_PATH is a non-default installation path)
+
+- This should not only enable building USRP FPGAs but also make the following utlities available
+
+## ModelSim Specific
+
+The setupenv.sh script will search the system for ModelSim installations and setup everything to run it natively and
+within Vivado. The currently support versions of ModelSim are PE, DE, SE, DE-64, SE-64.
+
+The following functions are also available in the environment:
+
+    build_simlibs: Build ModelSim simulation libraries for Vivado
+
+## IP Management
+
+### Create Vivado IP
+
+    viv_create_new_ip: Create a new Vivado IP instance and a Makefile for it
+
+    Usage: viv_create_new_ip <IP Name> <IP Location> <IP VLNV> <Product>
+    - <IP Name>: Name of the IP instance
+    - <IP Location>: Base location for IP
+    - <IP VLNV>: The vendor, library, name, and version (VLNV) string for the IP as defined by Xilinx
+    - <Product>: Product to generate IP for
+
+### Modify existing Vivado IP
+
+    viv_modify_ip: Modify an existing Vivado IP instance
+
+    Usage: viv_modify_ip <IP XCI Path>
+    - <IP XCI Path>: Path to the IP XCI file.
+
+### List supported Vivado IP
+
+    viv_ls_ip: List the items in the Vivado IP catalog
+
+    Usage: viv_ls_ip <Product>
+    - <Product>: Product to generate IP for.
+
+### Upgrade IP to the environment version of Vivado
+
+    viv_upgrade_ip: Upgrade one or more Xilinx IP targets
+
+    Usage: viv_upgrade_ip <IP Directory> [--recursive]
+    - <IP Directory>: Path to the IP XCI file.
+
+## Hardware Management
+
+### Launch Vivado Hardware Console
+
+    viv_hw_console: Launch the Tcl hardware console
+
+    Usage: viv_upgrade_ip
+
+### List connected JTAG devices
+
+    viv_jtag_list: List all devices (and their addresses) that are connected to the system using the Xilinx platform cable
+
+    Usage: viv_jtag_list
+
+### Program device over JTAG
+
+    viv_jtag_program: Downloads a bitfile to an FPGA device using Vivado
+
+    Usage: viv_jtag_program <Bitfile Path> [<Device Address> = 0:0]
+    - <Bitfile Path>: Path to a .bit FPGA configuration file
+    - <Device Address>: Address to the device in the form <Target>:<Device>
+                        Run viv_jtag_list to get a list of connected devices
+
+### Probe Xilinx bitfile
+
+    probe_bitfile: Probe a Xilinx bit file and report header information
+
+    Usage: probe_bitfile <Bitfile Path>
+    - <Bitfile Path>: Path to a .bit FPGA configuration file