Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 133 insertions, 0 deletions

diff --git a/fpga/docs/usrp3/sim/running_testbenches.md b/fpga/docs/usrp3/sim/running_testbenches.md
new file mode 100644
index 000000000..2e2068e5e
--- /dev/null
+++ b/fpga/docs/usrp3/sim/running_testbenches.md
@@ -0,0 +1,133 @@
+# Running a Testbench
+
+Each executable testbench has its own Makefile that automatically pulls in support
+for all supported simulators. The build infrastructure supports the following simulators:
+
+ - Xilinx Vivado (XSim)
+ - Mentor Graphics ModelSim (may require an additional license)
+
+
+In general running ``make <sim_target>`` will run the
+simulation and report results in the console. Running ``make help`` will print out
+all supported simulator targets. Currently, the following targets will work:
+
+    Supported Targets:
+    ipclean:    Cleanup all IP intermediate files
+    clean:      Cleanup all simulator intermediate files
+    cleanall:   Cleanup everything!
+    xsim:       Run the simulation using the Xilinx Vivado Simulator
+    xclean:     Cleanup Xilinx Vivado Simulator intermediate files
+    vsim:       Run the simulation using Modelsim
+    vclean:     Cleanup Modelsim intermediate files
+
+
+## Using Xilinx Vivado XSim
+
+XSim is the built-in simulator in the Xilinx Vivado toolchain. If you already met the
+prerequisites for building an FPGA image, then you don't need to install anything else.
+
+Follow these steps to run a testbench:
+
+ - Navigate to the directory that contains the top level testbench and Makefile
+ - Run the setenv.sh script for the USRP product that you are trying to simulate
+
+   ``$ source <repo>/usrp3/top/<product>/setupenv.sh``
+
+   This step is required even if the simulation is generic because the toolchain requires
+   an FPGA part number to load simulation models.
+ - Run the simulator specific target
+
+   ``$ make xsim``
+
+
+## Using Mentor Graphics ModelSim
+
+ModelSim is a third-party simulation tool that is compatible with Vivado and the USRP
+FPGA build infrastructure.
+
+Use the following one-time setup to install and configure Modelsim on your system
+
+ - Install Modelsim from the [Mentor Graphics](http://www.mentor.com/) website. 
+   It is recommended that you install it to the default location (/opt/mentor/modelsim)
+ - Run the setenv.sh script for the USRP product that you are trying to simulate
+
+   ``$ source <repo>/usrp3/top/<product>/setupenv.sh``
+
+   This step is required even if the simulation is generic because the toolchain requires
+   an FPGA part number to load simulation models.
+ - Build the Xilinx simulation libraries
+   ``$ build_simlibs``
+
+
+To validate that everything was install properly run ``setupenv.sh`` again. You should see the following
+
+    Setting up X3x0 FPGA build environment (64-bit)...
+    - Vivado: Found (/opt/Xilinx/Vivado/2014.4/bin)
+    - Modelsim: Found (/opt/mentor/modelsim/modeltech/bin)
+    - Modelsim Compiled Libs: Found (/opt/Xilinx/Vivado/2014.4/modelsim)
+    
+    Environment successfully initialized.
+
+Follow these steps to run a testbench:
+
+ - Navigate to the directory that contains the top level testbench and Makefile
+ - Run the setenv.sh script for the USRP product that you are trying to simulate
+
+   ``$ source <repo>/usrp3/top/<product>/setupenv.sh``
+
+   This step is required even if the simulation is generic because the toolchain requires
+   an FPGA part number to load simulation models.
+ - Run the simulator specific target
+
+   ``$ make vsim``
+
+
+## Troubleshooting
+
+#### Vivado Not Found
+
+If running the setupenv.sh script return an error like the following:
+
+    Vivado: Not found! (ERROR.. Builds and simulations will not work)
+
+then it is possible that Vivado was not installed or it was not installed in the default
+location. If Vivado is installed in a non-default location, just run the following:
+
+  ``$ source <repo>/usrp3/top/<product>/setupenv.sh --vivado-path=<PATH>``
+
+#### Modelsim Not Found
+
+If running the setupenv.sh script return an error like the following:
+
+    Setting up X3x0 FPGA build environment (64-bit)...
+    - Vivado: Found (/opt/Xilinx/Vivado/2014.4/bin)
+    - Modelsim: Not found! (WARNING.. Simulations with vsim will not work)
+    
+    Environment successfully initialized.
+
+or something like this (even when Modelsim is installed)
+
+    Setting up X3x0 FPGA build environment (64-bit)...
+    - Vivado: Found (/opt/Xilinx/Vivado/2014.4/bin)
+    
+    Environment successfully initialized.
+
+then it is possible that Modelsim was not installed or it was not installed in the default
+location. If Modelsim is installed in a non-default location, just run the following:
+
+  ``$ source <repo>/usrp3/top/<product>/setupenv.sh --modelsim-path=<PATH>``
+
+#### Modelsim Simulation Libraries Not Found
+
+If running the setupenv.sh script return an error like the following:
+
+    Setting up X3x0 FPGA build environment (64-bit)...
+    - Vivado: Found (/opt/Xilinx/Vivado/2014.4/bin)
+    - Modelsim: Found (/opt/mentor/modelsim/modeltech/bin)
+    - Modelsim Compiled Libs: Not found! (Run build_simlibs to generate them.)
+    
+    Environment successfully initialized.
+
+just run the following
+
+    $ build_simlibs
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