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authorHumberto Jimenez <humberto.jimenez@ni.com>2022-02-21 16:40:40 -0600
committerHumberto Jimenez <31545256+hjimenez-ni@users.noreply.github.com>2022-03-15 08:49:25 -0500
commit232a9a7345f0264602caba0caf2b96dd0856aed6 (patch)
treef475c37f111750cd5bfbc968c66b6942e66df48f /fpga/.ci/fpga-pipeline-pr.yml
parent4fc2e3beeed4759dc108a670350276ae5554e072 (diff)
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fpga: ci: Add stages-based pipeline
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diff --git a/fpga/.ci/fpga-pipeline-pr.yml b/fpga/.ci/fpga-pipeline-pr.yml
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+#
+# Copyright 2022 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: LGPL-3.0-or-later
+#
+# Description:
+#
+# This pipeline is used to build FPGAs and run testbenches for PRs.
+#
+# See https://aka.ms/yaml for pipeline YAML documentation.
+#
+
+parameters:
+- name: run_testbenches
+ type: boolean
+ displayName: Run Testbenches
+ default: true
+- name: clean_ip_build
+ type: boolean
+ displayName: Clean IP Build
+ default: false
+- name: build_x410
+ type: boolean
+ displayName: Build X410
+ default: true
+- name: x410_targets_matrix
+ type: object
+ displayName: X410 Targets
+ default:
+ X410_XG_100:
+ target_name: X410_XG_100
+ timeout: 480
+ X410_X4_200:
+ target_name: X410_X4_200
+ timeout: 480
+ X410_CG_400:
+ target_name: X410_CG_400
+ timeout: 480
+- name: package_images
+ type: boolean
+ displayName: Package Images
+ default: false
+
+trigger: none
+
+pr:
+ branches:
+ include:
+ - master
+ paths:
+ include:
+ - fpga/usrp3/lib
+ - fpga/usrp3/top/x400
+ - fpga/.ci
+
+extends:
+ template: templates/stages-fpga-pipeline.yml
+ parameters:
+ run_testbenches: ${{ parameters.run_testbenches }}
+ package_images: ${{ parameters.package_images }}
+ build_x410: ${{ parameters.build_x410 }}
+ x410_targets_matrix: ${{ parameters.x410_targets_matrix }}
+ publish_int_files: true
+ clean_ip_build: ${{ parameters.clean_ip_build }}