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authorNicholas Corgan <nick.corgan@ettus.com>2014-08-15 12:57:10 -0700
committerNicholas Corgan <nick.corgan@ettus.com>2014-08-20 09:42:26 -0700
commit2de96cd57c3f19bfa778ccad280ad19170af0967 (patch)
tree88e5235bbbc1df0dd5d6ce1883203a09f3e07ea3 /firmware/octoclock/lib/enc28j60.c
parent9fb6c2919ad9e7e736c837186861b362ba80cdfa (diff)
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OctoClock: bugfixes/improvements
* Fixed Ethernet initialization problem * Improved external reference detection * Added gratuitous ARP, sent upon power-up * Tweaked host-side timing for initialization and firmware burning * Fixed logic for dealing with firmware incompatibility * Misc efficiency/reliability improvements to firmware's network code
Diffstat (limited to 'firmware/octoclock/lib/enc28j60.c')
-rw-r--r--firmware/octoclock/lib/enc28j60.c19
1 files changed, 17 insertions, 2 deletions
diff --git a/firmware/octoclock/lib/enc28j60.c b/firmware/octoclock/lib/enc28j60.c
index 0e8c1fa3c..f0bbee0e7 100644
--- a/firmware/octoclock/lib/enc28j60.c
+++ b/firmware/octoclock/lib/enc28j60.c
@@ -198,8 +198,23 @@ void enc28j60Init(u08* macaddr)
// perform system reset
enc28j60WriteOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
- // check CLKRDY bit to see if reset is complete
- _delay_us(51);
+
+ /*
+ * "After sending an SPI Reset command, the PHY
+ * clock is stopped but the ESTAT.CLKRDY bit is not
+ * cleared. Therefore, polling the CLKRDY bit will not
+ * work to detect if the PHY is ready.
+ *
+ * Additionally, the hardware start-up time of 300 us
+ * may expire before the device is ready to operate.
+ *
+ * Work around
+ * After issuing the Reset command, wait at least
+ * 1 ms in firmware for the device to be ready."
+ *
+ * Source: http://ww1.microchip.com/downloads/en/DeviceDoc/80349c.pdf
+ */
+ _delay_ms(1);
// do bank 0 stuff
// initialize receive buffer