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| author | Marcus Müller <marcus.mueller@ettus.com> | 2017-01-16 15:54:57 +0100 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2017-06-29 15:53:15 -0700 |
| commit | d9bcf00f69313b6dd42346d6af340a1a9874ba9f (patch) | |
| tree | 62185d7ea2c20952d60cf8f6a558866ecf1d54bf /firmware/fx2/common/syncdelay.h | |
| parent | c77bd0c46a598d5e69b179d76a3df6091e982129 (diff) | |
| download | uhd-d9bcf00f69313b6dd42346d6af340a1a9874ba9f.tar.gz uhd-d9bcf00f69313b6dd42346d6af340a1a9874ba9f.tar.bz2 uhd-d9bcf00f69313b6dd42346d6af340a1a9874ba9f.zip | |
made FX2 EEPROMS and firmware build with modern SDCC 3.6
Diffstat (limited to 'firmware/fx2/common/syncdelay.h')
| -rw-r--r-- | firmware/fx2/common/syncdelay.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/firmware/fx2/common/syncdelay.h b/firmware/fx2/common/syncdelay.h index 0af7d099f..cca96add7 100644 --- a/firmware/fx2/common/syncdelay.h +++ b/firmware/fx2/common/syncdelay.h @@ -23,7 +23,7 @@ #define _SYNCDELAY_H_ /* - * Magic delay required between access to certain xdata registers (TRM page 15-106). + * Magic delay required between access to certain __xdata registers (TRM page 15-106). * For our configuration, 48 MHz FX2 / 48 MHz IFCLK, we need three cycles. Each * NOP is a single cycle.... * @@ -58,8 +58,8 @@ /* * FIXME ensure that the peep hole optimizer isn't screwing us */ -#define SYNCDELAY _asm nop; nop; nop; _endasm -#define NOP _asm nop; _endasm +#define SYNCDELAY __asm nop; nop; nop; __endasm +#define NOP __asm nop; __endasm #endif /* _SYNCDELAY_H_ */ |