diff options
author | Martin Braun <martin.braun@ettus.com> | 2015-07-14 14:51:14 -0700 |
---|---|---|
committer | Martin Braun <martin.braun@ettus.com> | 2015-07-14 14:51:14 -0700 |
commit | 7c6bc34f625e3945458a0a2a281850513a02ef08 (patch) | |
tree | 0e34c196d4aceae4cae6d7e22708ded67f558c31 /firmware/e300/battery/adc.c | |
parent | bb940ccabb94daa685b4869f44c00844eeeb905b (diff) | |
parent | 5f4470a8fb340677f2d0b557f4670bc7506fc38a (diff) | |
download | uhd-7c6bc34f625e3945458a0a2a281850513a02ef08.tar.gz uhd-7c6bc34f625e3945458a0a2a281850513a02ef08.tar.bz2 uhd-7c6bc34f625e3945458a0a2a281850513a02ef08.zip |
Merge branch 'maint'
Conflicts:
fpga-src
host/CMakeLists.txt
host/cmake/Modules/UHDVersion.cmake
host/lib/usrp/b200/b200_impl.hpp
host/lib/usrp/e300/e300_fpga_defs.hpp
host/lib/usrp/x300/x300_fw_common.h
Diffstat (limited to 'firmware/e300/battery/adc.c')
-rw-r--r-- | firmware/e300/battery/adc.c | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/firmware/e300/battery/adc.c b/firmware/e300/battery/adc.c new file mode 100644 index 000000000..998408066 --- /dev/null +++ b/firmware/e300/battery/adc.c @@ -0,0 +1,58 @@ +/* USRP E310 Firmware Atmel AVR ADC driver + * Copyright (C) 2014 Ettus Research + * This file is part of the USRP E310 Firmware + * The USRP E310 Firmware is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * The USRP E310 Firmware is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * You should have received a copy of the GNU General Public License + * along with the USRP E310 Firmware. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <avr/io.h> + +#include "adc.h" +#include "utils.h" + +void adc_init(void) +{ + /* disable digital input on PC0 (ADC0) */ + DIDR0 |= 0x1; + + /* set to AVcc reference, left aligned and ADC0 */ + ADMUX = (1 << REFS0) + | (0 << ADLAR) + | (0 << MUX0); + + /* prescale clock by 128 */ + ADCSRA = BIT(ADPS2) | BIT(ADPS1) | BIT(ADPS0); +} + +uint16_t adc_single_shot(void) +{ + uint16_t value; + + /* turn on ADC */ + ADCSRA |= (1 << ADEN); + + /* start conversion */ + ADCSRA |= (1 << ADSC); + + /* busy wait for conversion */ + while (ADCSRA & (1 << ADSC)) { + }; + + /* we need to first read the lower bits, + * which will lock the value until higher bits are read */ + value = (ADCL << 0); + value |= (ADCH << 8); + + /* turn adc of again */ + ADCSRA &= ~(1 << ADEN); + + return value; +} |