diff options
| author | Matt Ettus <matt@ettus.com> | 2009-09-03 10:37:35 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2009-09-03 10:37:35 -0700 |
| commit | 14036fe6e3bdcc62efbad909a15959f22b63a41f (patch) | |
| tree | ffe34ac2ca39abc3d599fb52174c855969d23a0d /coregen/fifo_xlnx_2Kx36_2clk.xco | |
| parent | c811e886f5dbf61056834b3ef307ace1d5348aae (diff) | |
| download | uhd-14036fe6e3bdcc62efbad909a15959f22b63a41f.tar.gz uhd-14036fe6e3bdcc62efbad909a15959f22b63a41f.tar.bz2 uhd-14036fe6e3bdcc62efbad909a15959f22b63a41f.zip | |
made a new block ram based fifo, 64 (65) elements long, all fifos now have "enhanced level logic" for accurate fullness. Maybe this will help...
Diffstat (limited to 'coregen/fifo_xlnx_2Kx36_2clk.xco')
| -rw-r--r-- | coregen/fifo_xlnx_2Kx36_2clk.xco | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/coregen/fifo_xlnx_2Kx36_2clk.xco b/coregen/fifo_xlnx_2Kx36_2clk.xco index 3afc64a10..e25ad38da 100644 --- a/coregen/fifo_xlnx_2Kx36_2clk.xco +++ b/coregen/fifo_xlnx_2Kx36_2clk.xco @@ -1,7 +1,7 @@ ############################################################## # -# Xilinx Core Generator version K.37 -# Date: Mon Jul 14 23:45:29 2008 +# Xilinx Core Generator version K.39 +# Date: Thu Sep 3 17:25:43 2009 # ############################################################## # @@ -39,7 +39,7 @@ CSET almost_empty_flag=false CSET almost_full_flag=false CSET component_name=fifo_xlnx_2Kx36_2clk CSET data_count=false -CSET data_count_width=11 +CSET data_count_width=12 CSET disable_timing_violations=false CSET dout_reset_value=0 CSET empty_threshold_assert_value=4 @@ -61,22 +61,22 @@ CSET programmable_empty_type=No_Programmable_Empty_Threshold CSET programmable_full_type=No_Programmable_Full_Threshold CSET read_clock_frequency=1 CSET read_data_count=true -CSET read_data_count_width=11 +CSET read_data_count_width=12 CSET reset_pin=true CSET reset_type=Asynchronous_Reset CSET underflow_flag=false CSET underflow_sense=Active_High -CSET use_dout_reset=false +CSET use_dout_reset=true CSET use_embedded_registers=false -CSET use_extra_logic=false +CSET use_extra_logic=true CSET valid_flag=false CSET valid_sense=Active_High CSET write_acknowledge_flag=false CSET write_acknowledge_sense=Active_High CSET write_clock_frequency=1 CSET write_data_count=true -CSET write_data_count_width=11 +CSET write_data_count_width=12 # END Parameters GENERATE -# CRC: a8b698f5 +# CRC: 2ae9f6ef |