More xilinx fifos, more clean up of our fifos

1 files changed, 39 insertions, 0 deletions

diff --git a/coregen/fifo_xlnx_16x19_2clk_readme.txt b/coregen/fifo_xlnx_16x19_2clk_readme.txt
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+++ b/coregen/fifo_xlnx_16x19_2clk_readme.txt
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+The following files were generated for 'fifo_xlnx_16x19_2clk' in directory 
+/home/matt/gnuradio.git/usrp2/fpga/coregen/:
+
+fifo_xlnx_16x19_2clk.ngc:
+   Binary Xilinx implementation netlist file containing the information
+   required to implement the module in a Xilinx (R) FPGA.
+
+fifo_xlnx_16x19_2clk.v:
+   Verilog wrapper file provided to support functional simulation.
+   This file contains simulation model customization data that is
+   passed to a parameterized simulation model for the core.
+
+fifo_xlnx_16x19_2clk.veo:
+   VEO template file containing code that can be used as a model for
+   instantiating a CORE Generator module in a Verilog design.
+
+fifo_xlnx_16x19_2clk.xco:
+   CORE Generator input file containing the parameters used to
+   regenerate a core.
+
+fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt:
+   Please see the core data sheet.
+
+fifo_xlnx_16x19_2clk_flist.txt:
+   Text file listing all of the output files produced when a customized
+   core was generated in the CORE Generator.
+
+fifo_xlnx_16x19_2clk_readme.txt:
+   Text file indicating the files generated and how they are used.
+
+fifo_xlnx_16x19_2clk_xmdf.tcl:
+   ISE Project Navigator interface file. ISE uses this file to determine
+   how the files output by CORE Generator for the core can be integrated
+   into your ISE project.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+