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authorJosh Blum <josh@joshknows.com>2010-01-22 11:56:55 -0800
committerJosh Blum <josh@joshknows.com>2010-01-22 11:56:55 -0800
commit7bf8a6df381a667134b55701993c6770d32bc76b (patch)
tree4a298fb5450f7277b5aaf5210740ae18f818c9aa /control_lib/ram_2port.v
parent8f2c33eab9396185df259639082b7d1618585973 (diff)
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Moved usrp2 fpga files into usrp2 subdir.
Diffstat (limited to 'control_lib/ram_2port.v')
-rw-r--r--control_lib/ram_2port.v42
1 files changed, 0 insertions, 42 deletions
diff --git a/control_lib/ram_2port.v b/control_lib/ram_2port.v
deleted file mode 100644
index 6c8332b9c..000000000
--- a/control_lib/ram_2port.v
+++ /dev/null
@@ -1,42 +0,0 @@
-
-
-module ram_2port
- #(parameter DWIDTH=32,
- parameter AWIDTH=9)
- (input clka,
- input ena,
- input wea,
- input [AWIDTH-1:0] addra,
- input [DWIDTH-1:0] dia,
- output reg [DWIDTH-1:0] doa,
-
- input clkb,
- input enb,
- input web,
- input [AWIDTH-1:0] addrb,
- input [DWIDTH-1:0] dib,
- output reg [DWIDTH-1:0] dob);
-
- reg [DWIDTH-1:0] ram [(1<<AWIDTH)-1:0];
- integer i;
- initial
- for(i=0;i<(1<<AWIDTH);i=i+1)
- ram[i] <= {AWIDTH{1'b0}};
-
- always @(posedge clka) begin
- if (ena)
- begin
- if (wea)
- ram[addra] <= dia;
- doa <= ram[addra];
- end
- end
- always @(posedge clkb) begin
- if (enb)
- begin
- if (web)
- ram[addrb] <= dib;
- dob <= ram[addrb];
- end
- end
-endmodule // ram_2port