aboutsummaryrefslogtreecommitdiffstats
path: root/control_lib/newfifo/fifo19_to_ll8.v
diff options
context:
space:
mode:
authormatt <matt@221aa14e-8319-0410-a670-987f0aec2ac5>2009-03-30 02:54:51 +0000
committermatt <matt@221aa14e-8319-0410-a670-987f0aec2ac5>2009-03-30 02:54:51 +0000
commita4b5b6839293b624e66a5fbcbc6bb822cadfb3b5 (patch)
treed18e7db5445e9f029711e3eb8468be666efdf12e /control_lib/newfifo/fifo19_to_ll8.v
parent9e643a57af8f84f6008607d0554896d0206c7cf5 (diff)
downloaduhd-a4b5b6839293b624e66a5fbcbc6bb822cadfb3b5.tar.gz
uhd-a4b5b6839293b624e66a5fbcbc6bb822cadfb3b5.tar.bz2
uhd-a4b5b6839293b624e66a5fbcbc6bb822cadfb3b5.zip
new fifos copied over from other project
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10709 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'control_lib/newfifo/fifo19_to_ll8.v')
-rw-r--r--control_lib/newfifo/fifo19_to_ll8.v53
1 files changed, 53 insertions, 0 deletions
diff --git a/control_lib/newfifo/fifo19_to_ll8.v b/control_lib/newfifo/fifo19_to_ll8.v
new file mode 100644
index 000000000..4707f7523
--- /dev/null
+++ b/control_lib/newfifo/fifo19_to_ll8.v
@@ -0,0 +1,53 @@
+
+module fifo19_to_ll8
+ (input clk, input reset, input clear,
+ input [18:0] f19_data,
+ input f19_src_rdy_i,
+ output f19_dst_rdy_o,
+
+ output reg [7:0] ll_data,
+ output ll_sof_n,
+ output ll_eof_n,
+ output ll_src_rdy_n,
+ input ll_dst_rdy_n);
+
+ wire ll_sof, ll_eof, ll_src_rdy;
+ assign ll_sof_n = ~ll_sof;
+ assign ll_eof_n = ~ll_eof;
+ assign ll_src_rdy_n = ~ll_src_rdy;
+ wire ll_dst_rdy = ~ll_dst_rdy_n;
+
+ wire f19_sof = f19_data[16];
+ wire f19_eof = f19_data[17];
+ wire f19_occ = f19_data[18];
+
+ wire advance, end_early;
+ reg state;
+
+ always @(posedge clk)
+ if(reset)
+ state <= 0;
+ else
+ if(advance)
+ if(ll_eof)
+ state <= 0;
+ else
+ state <= state + 1;
+
+ always @*
+ case(state)
+ 0 : ll_data = f19_data[15:8];
+ 1 : ll_data = f19_data[7:0];
+ default : ll_data = f19_data[15:8];
+ endcase // case (state)
+
+ assign ll_sof = (state==0) & f19_sof;
+ assign ll_eof = f19_eof & ((f19_occ==1)|(state==1));
+
+ assign ll_src_rdy = f19_src_rdy_i;
+
+ assign advance = ll_src_rdy & ll_dst_rdy;
+ assign f19_dst_rdy_o = advance & ((state==1)|ll_eof);
+
+endmodule // fifo19_to_ll8
+