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author | matt <matt@221aa14e-8319-0410-a670-987f0aec2ac5> | 2009-03-30 02:54:51 +0000 |
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committer | matt <matt@221aa14e-8319-0410-a670-987f0aec2ac5> | 2009-03-30 02:54:51 +0000 |
commit | a4b5b6839293b624e66a5fbcbc6bb822cadfb3b5 (patch) | |
tree | d18e7db5445e9f029711e3eb8468be666efdf12e /control_lib/newfifo/fifo18_to_ll8.v | |
parent | 9e643a57af8f84f6008607d0554896d0206c7cf5 (diff) | |
download | uhd-a4b5b6839293b624e66a5fbcbc6bb822cadfb3b5.tar.gz uhd-a4b5b6839293b624e66a5fbcbc6bb822cadfb3b5.tar.bz2 uhd-a4b5b6839293b624e66a5fbcbc6bb822cadfb3b5.zip |
new fifos copied over from other project
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10709 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'control_lib/newfifo/fifo18_to_ll8.v')
-rw-r--r-- | control_lib/newfifo/fifo18_to_ll8.v | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/control_lib/newfifo/fifo18_to_ll8.v b/control_lib/newfifo/fifo18_to_ll8.v new file mode 100644 index 000000000..4653244ef --- /dev/null +++ b/control_lib/newfifo/fifo18_to_ll8.v @@ -0,0 +1,58 @@ + +module fifo18_to_ll8 + (input clk, input reset, input clear, + input [35:0] f18_data, + input f18_src_rdy_i, + output f18_dst_rdy_o, + + output reg [7:0] ll_data, + output ll_sof_n, + output ll_eof_n, + output ll_src_rdy_n, + input ll_dst_rdy_n); + + wire ll_sof, ll_eof, ll_src_rdy; + assign ll_sof_n = ~ll_sof; + assign ll_eof_n = ~ll_eof; + assign ll_src_rdy_n = ~ll_src_rdy; + wire ll_dst_rdy = ~ll_dst_rdy_n; + + wire f18_sof = f18_data[32]; + wire f18_eof = f18_data[33]; + wire f18_occ = f18_data[35:34]; + wire advance, end_early; + reg [1:0] state; + assign debug = {29'b0,state}; + + always @(posedge clk) + if(reset) + state <= 0; + else + if(advance) + if(ll_eof) + state <= 0; + else + state <= state + 1; + + always @* + case(state) + 0 : ll_data = f18_data[31:24]; + 1 : ll_data = f18_data[23:16]; + 2 : ll_data = f18_data[15:8]; + 3 : ll_data = f18_data[7:0]; + default : ll_data = f18_data[31:24]; + endcase // case (state) + + assign ll_sof = (state==0) & f18_sof; + assign ll_eof = f18_eof & (((state==0)&(f18_occ==1)) | + ((state==1)&(f18_occ==2)) | + ((state==2)&(f18_occ==3)) | + (state==3)); + + assign ll_src_rdy = f18_src_rdy_i; + + assign advance = ll_src_rdy & ll_dst_rdy; + assign f18_dst_rdy_o = advance & ((state==3)|ll_eof); + assign debug = state; + +endmodule // ll8_to_fifo36 |