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author | Johnathan Corgan <jcorgan@corganenterprises.com> | 2009-08-31 12:08:30 -0700 |
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committer | Johnathan Corgan <jcorgan@corganenterprises.com> | 2009-08-31 12:08:30 -0700 |
commit | 91636cbac2b3edfba45321f1050d0b90b34ab696 (patch) | |
tree | 881275cf214d4cebcc122c60905510f3e6a5226c /control_lib/newfifo/cascadefifo_2clock.v | |
parent | aa37ca0b3b716e23e51f04b6f199ecacf89fe479 (diff) | |
download | uhd-91636cbac2b3edfba45321f1050d0b90b34ab696.tar.gz uhd-91636cbac2b3edfba45321f1050d0b90b34ab696.tar.bz2 uhd-91636cbac2b3edfba45321f1050d0b90b34ab696.zip |
Merged SVN matt/new_eth r10782:11633 into new_eth
* svn diff http://gnuradio.org/svn/branches/developers/matt/new_eth
-r10782:11633
* Patch applied with no conflicts or fuzz.
Diffstat (limited to 'control_lib/newfifo/cascadefifo_2clock.v')
-rw-r--r-- | control_lib/newfifo/cascadefifo_2clock.v | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/control_lib/newfifo/cascadefifo_2clock.v b/control_lib/newfifo/cascadefifo_2clock.v new file mode 100644 index 000000000..2abbbf3b5 --- /dev/null +++ b/control_lib/newfifo/cascadefifo_2clock.v @@ -0,0 +1,27 @@ + +module cascadefifo_2clock + #(parameter DWIDTH=32, AWIDTH=9) + (input wclk, input [DWIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [AWIDTH-1:0] level_wclk, + input rclk, output [DWIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [AWIDTH-1:0] level_rclk, + input arst); + + wire [DWIDTH-1:0] data_int1, data_int2; + wire src_rdy_int1, src_rdy_int2, dst_rdy_int1, dst_rdy_int2; + + fifo_short #(.WIDTH(DWIDTH)) shortfifo + (.clk(wclk), .reset(arst), .clear(0), + .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), + .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1) ); + + newfifo_2clock #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) fifo_2clock + (.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .level_wclk(level_wclk), + .rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .level_rclk(level_rclk), + .arst(arst) ); + + fifo_short #(.WIDTH(DWIDTH)) shortfifo2 + (.clk(rclk), .reset(arst), .clear(0), + .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2), + .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i) ); + +endmodule // fifo_2clock_casc + |