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| author | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
| commit | 7bf8a6df381a667134b55701993c6770d32bc76b (patch) | |
| tree | 4a298fb5450f7277b5aaf5210740ae18f818c9aa /control_lib/clock_control_tb.v | |
| parent | 8f2c33eab9396185df259639082b7d1618585973 (diff) | |
| download | uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.gz uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.bz2 uhd-7bf8a6df381a667134b55701993c6770d32bc76b.zip | |
Moved usrp2 fpga files into usrp2 subdir.
Diffstat (limited to 'control_lib/clock_control_tb.v')
| -rw-r--r-- | control_lib/clock_control_tb.v | 35 |
1 files changed, 0 insertions, 35 deletions
diff --git a/control_lib/clock_control_tb.v b/control_lib/clock_control_tb.v deleted file mode 100644 index 4e705cf23..000000000 --- a/control_lib/clock_control_tb.v +++ /dev/null @@ -1,35 +0,0 @@ - - -module clock_control_tb(); - - clock_control clock_control - (.reset(reset), - .aux_clk(aux_clk), - .clk_fpga(clk_fpga), - .clk_en(clk_en), - .clk_sel(clk_sel), - .clk_func(clk_func), - .clk_status(clk_status), - - .sen(sen), - .sclk(sclk), - .sdi(sdi), - .sdo(sdo) - ); - - reg reset, aux_clk; - - wire [1:0] clk_sel, clk_en; - - initial reset = 1'b1; - initial #1000 reset = 1'b0; - - initial aux_clk = 1'b0; - always #10 aux_clk = ~aux_clk; - - initial $dumpfile("clock_control_tb.vcd"); - initial $dumpvars(0,clock_control_tb); - - initial #10000 $finish; - -endmodule // clock_control_tb |