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| author | Josh Blum <josh@joshknows.com> | 2012-01-27 11:52:19 -0800 |
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| committer | Josh Blum <josh@joshknows.com> | 2012-01-27 11:52:19 -0800 |
| commit | e633f884d728c24e6f5749d5821b9c62ec8fd17e (patch) | |
| tree | 1a6542a5646efd51399e0c55520985135a92ee5c /README.txt | |
| parent | cbea8a3b14412b513b54167b745307a102f2fe68 (diff) | |
| download | uhd-e633f884d728c24e6f5749d5821b9c62ec8fd17e.tar.gz uhd-e633f884d728c24e6f5749d5821b9c62ec8fd17e.tar.bz2 uhd-e633f884d728c24e6f5749d5821b9c62ec8fd17e.zip | |
dsp rework: renamed dsp signals for frontend IO
Diffstat (limited to 'README.txt')
| -rw-r--r-- | README.txt | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/README.txt b/README.txt new file mode 100644 index 000000000..bfdf317c1 --- /dev/null +++ b/README.txt @@ -0,0 +1,31 @@ +######################################################################## +## Welcome to the USRP FPGA source code tree +######################################################################## + +usrp1/ + + Description: generation 1 products + + Devices: USRP classic only + + Tools: Quartus from Altera + + Project file: usrp1/toplevel/usrp_std/ + +usrp2/ + + Description: generation 2 products + + Devices: USRP2, N2XX, B100, E1XX + + Tools: ISE from Xilinx, GNU make + + Build Instructions: + 1) ensure that xtclsh is in the $PATH + 2) cd usrp2/top/<project-directory> + 3) make -f Makefile.<device> bin + 4) bin file in build-<device>/*.bin + + Customize the DSP: + Implement design in usrp2/custom/custom_*.v + Instructions are included in the module. |