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author | Matt Ettus <matt@ettus.com> | 2011-03-16 21:23:47 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2011-05-26 17:31:21 -0700 |
commit | fd2f7f333a643f070a9f9c19228ea83c15c875fb (patch) | |
tree | 0566cc530823d797d0c9ef2816b6e9abaa3679a7 | |
parent | f04a393d48266f5d3e4f35aaddf12ab3214ae8b4 (diff) | |
download | uhd-fd2f7f333a643f070a9f9c19228ea83c15c875fb.tar.gz uhd-fd2f7f333a643f070a9f9c19228ea83c15c875fb.tar.bz2 uhd-fd2f7f333a643f070a9f9c19228ea83c15c875fb.zip |
u1p: revert change to address bus width
-rw-r--r-- | usrp2/top/u1plus/u1plus_core.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index 0fbc2f593..8e83c01ff 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -54,7 +54,7 @@ module u1plus_core // ///////////////////////////////////////////////////////////////////////////////////// // GPIF Slave to Wishbone Master localparam dw = 16; - localparam aw = 16; + localparam aw = 11; localparam sw = 2; wire [dw-1:0] m0_dat_mosi, m0_dat_miso; @@ -361,7 +361,7 @@ module u1plus_core wb_readback_mux_16LE readback_mux_32 (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s7_stb), - .wb_adr_i(s7_adr), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack), + .wb_adr_i({5'b0,s7_adr}), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack), .word00(vita_time[63:32]), .word01(vita_time[31:0]), .word02(vita_time_pps[63:32]), .word03(vita_time_pps[31:0]), |