u2/u2p: shortfifos in fifo36_to_ll8, no more _n junk

2 files changed, 45 insertions, 36 deletions

diff --git a/usrp2/fifo/fifo36_to_ll8.v b/usrp2/fifo/fifo36_to_ll8.v
index 9604d0e38..61e2967f9 100644
--- a/usrp2/fifo/fifo36_to_ll8.v
+++ b/usrp2/fifo/fifo36_to_ll8.v
@@ -5,24 +5,31 @@ module fifo36_to_ll8
    input f36_src_rdy_i,
    output f36_dst_rdy_o,
 
-   output reg [7:0] ll_data,
-   output ll_sof_n,
-   output ll_eof_n,
-   output ll_src_rdy_n,
-   input ll_dst_rdy_n,
+   output [7:0] ll_data,
+   output ll_sof,
+   output ll_eof,
+   output ll_src_rdy,
+   input ll_dst_rdy,
 
    output [31:0] debug);
 
-   wire  ll_sof, ll_eof, ll_src_rdy;
-   assign ll_sof_n = ~ll_sof;
-   assign ll_eof_n = ~ll_eof;
-   assign ll_src_rdy_n = ~ll_src_rdy;
-   wire ll_dst_rdy = ~ll_dst_rdy_n;
+   // Shortfifo on input to guarantee no deadlock
+   wire [35:0] 	 f36_data_int;
+   wire 	 f36_src_rdy_int, f36_dst_rdy_int;
+   reg [7:0] 	 ll_data_int;
+   wire 	 ll_sof_int, ll_eof_int, ll_src_rdy_int, ll_dst_rdy_int;
+   
+   fifo_short #(.WIDTH(36)) head_fifo
+     (.clk(clk),.reset(reset),.clear(clear),
+      .datain(f36_data), .src_rdy_i(f36_src_rdy_i), .dst_rdy_o(f36_dst_rdy_o),
+      .dataout(f36_data_int), .src_rdy_o(f36_src_rdy_int), .dst_rdy_i(f36_dst_rdy_int),
+      .space(),.occupied() );
 
-   wire   f36_sof = f36_data[32];
-   wire   f36_eof = f36_data[33];
-   wire   f36_occ = f36_data[35:34];
-   wire advance, end_early;
+   // Actual fifo36 to ll8, can deadlock if not connected to shortfifo
+   wire   f36_sof_int = f36_data_int[32];
+   wire   f36_eof_int = f36_data_int[33];
+   wire   f36_occ_int = f36_data_int[35:34];
+   wire   advance, end_early;
    reg [1:0] state;
    assign debug    = {29'b0,state};
 
@@ -31,29 +38,37 @@ module fifo36_to_ll8
        state 	  <= 0;
      else
        if(advance)
-	 if(ll_eof)
+	 if(ll_eof_int)
 	   state  <= 0;
 	 else
 	   state  <= state + 1;
 
    always @*
      case(state)
-       0 : ll_data = f36_data[31:24];
-       1 : ll_data = f36_data[23:16];
-       2 : ll_data = f36_data[15:8];
-       3 : ll_data = f36_data[7:0];
-       default : ll_data = f36_data[31:24];
+       0 : ll_data_int = f36_data_int[31:24];
+       1 : ll_data_int = f36_data_int[23:16];
+       2 : ll_data_int = f36_data_int[15:8];
+       3 : ll_data_int = f36_data_int[7:0];
+       default : ll_data_int = f36_data_int[31:24];
        endcase // case (state)
    
-   assign ll_sof 	 = (state==0) & f36_sof;
-   assign ll_eof 	 = f36_eof & (((state==0)&(f36_occ==1)) |
-			       ((state==1)&(f36_occ==2)) |
-			       ((state==2)&(f36_occ==3)) |
+   assign ll_sof_int 	 = (state==0) & f36_sof_int;
+   assign ll_eof_int 	 = f36_eof_int & (((state==0)&(f36_occ_int==1)) |
+			       ((state==1)&(f36_occ_int==2)) |
+			       ((state==2)&(f36_occ_int==3)) |
 			       (state==3));
    
-   assign ll_src_rdy 	 = f36_src_rdy_i;
-
-   assign advance 	 = ll_src_rdy & ll_dst_rdy;
-   assign f36_dst_rdy_o  = advance & ((state==3)|ll_eof);
+   assign ll_src_rdy_int = f36_src_rdy_int;
    
+   assign advance 	 = ll_src_rdy_int & ll_dst_rdy_int;
+   assign f36_dst_rdy_int= advance & ((state==3)|ll_eof_int);
+
+   // Short FIFO on output to guarantee no deadlock
+   ll8_shortfifo tail_fifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(ll_data_int), .sof_i(ll_sof_int), .eof_i(ll_eof_int),
+      .error_i(0), .src_rdy_i(ll_src_rdy_int), .dst_rdy_o(ll_dst_rdy_int),
+      .dataout(ll_data), .sof_o(ll_sof), .eof_o(ll_eof),
+      .error_o(), .src_rdy_o(ll_src_rdy), .dst_rdy_i(ll_dst_rdy));
+
 endmodule // ll8_to_fifo36
diff --git a/usrp2/simple_gemac/simple_gemac_wrapper.v b/usrp2/simple_gemac/simple_gemac_wrapper.v
index cb0ec1c71..d64ff638a 100644
--- a/usrp2/simple_gemac/simple_gemac_wrapper.v
+++ b/usrp2/simple_gemac/simple_gemac_wrapper.v
@@ -106,7 +106,6 @@ module simple_gemac_wrapper
    // TX FIFO Chain
    wire 	  tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
    wire 	  tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2;
-   wire 	  tx_ll_sof2_n, tx_ll_eof2_n, tx_ll_src_rdy2_n, tx_ll_dst_rdy2_n;
    wire [7:0] 	  tx_ll_data, tx_ll_data2;
    wire [35:0] 	  tx_f36_data_int1;
    wire 	  tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1;
@@ -119,14 +118,9 @@ module simple_gemac_wrapper
    fifo36_to_ll8 fifo36_to_ll8
      (.clk(tx_clk), .reset(tx_reset), .clear(clear),
       .f36_data(tx_f36_data_int1), .f36_src_rdy_i(tx_f36_src_rdy_int1), .f36_dst_rdy_o(tx_f36_dst_rdy_int1),
-      .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n),
-      .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(tx_ll_dst_rdy2_n));
+      .ll_data(tx_ll_data2), .ll_sof(tx_ll_sof2), .ll_eof(tx_ll_eof2),
+      .ll_src_rdy(tx_ll_src_rdy2), .ll_dst_rdy(tx_ll_dst_rdy2));
 
-   assign tx_ll_sof2 	    = ~tx_ll_sof2_n;
-   assign tx_ll_eof2 	    = ~tx_ll_eof2_n;
-   assign tx_ll_src_rdy2    = ~tx_ll_src_rdy2_n;
-   assign tx_ll_dst_rdy2_n  = ~tx_ll_dst_rdy2;
-   
    ll8_shortfifo tx_sfifo
      (.clk(tx_clk), .reset(tx_reset), .clear(clear),
       .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),