rfnoc: Support for new backend iface plus fixes

- Add support for new backend iface with max_async_msgs and mtu
  moved to after the noc ID
- Fixed offsets for block info registers

4 files changed, 43 insertions, 33 deletions

diff --git a/host/lib/include/uhdlib/rfnoc/chdr_ctrl_endpoint.hpp b/host/lib/include/uhdlib/rfnoc/chdr_ctrl_endpoint.hpp
index c13955888..afaa22306 100644
--- a/host/lib/include/uhdlib/rfnoc/chdr_ctrl_endpoint.hpp
+++ b/host/lib/include/uhdlib/rfnoc/chdr_ctrl_endpoint.hpp
@@ -7,7 +7,7 @@
 #ifndef INCLUDED_LIBUHD_RFNOC_CHDR_CTRL_ENDPOINT_HPP
 #define INCLUDED_LIBUHD_RFNOC_CHDR_CTRL_ENDPOINT_HPP
 
-#include <uhdlib/rfnoc/chdr/chdr_types.hpp>
+#include <uhdlib/rfnoc/chdr/chdr_packet.hpp>
 #include <uhdlib/rfnoc/ctrlport_endpoint.hpp>
 #include <uhdlib/rfnoc/xports.hpp>
 #include <functional>
diff --git a/host/lib/include/uhdlib/rfnoc/client_zero.hpp b/host/lib/include/uhdlib/rfnoc/client_zero.hpp
index 8eb2d6397..c6d3e879b 100644
--- a/host/lib/include/uhdlib/rfnoc/client_zero.hpp
+++ b/host/lib/include/uhdlib/rfnoc/client_zero.hpp
@@ -8,8 +8,11 @@
 #define INCLUDED_LIBUHD_CLIENT_ZERO_HPP
 
 #include <uhd/rfnoc/register_iface_holder.hpp>
+#include <uhdlib/rfnoc/chdr_ctrl_endpoint.hpp>
 #include <chrono>
 #include <cstdint>
+#include <functional>
+#include <memory>
 #include <string>
 #include <vector>
 
@@ -40,7 +43,8 @@ public:
         uint8_t num_inputs;
         uint8_t num_outputs;
         uint8_t ctrl_fifo_size;
-        uint8_t mtu;
+        uint8_t ctrl_max_async_msgs;
+        uint8_t data_mtu;
     };
 
     //! Return the RFNoC protocol version for this motherboard
diff --git a/host/lib/rfnoc/client_zero.cpp b/host/lib/rfnoc/client_zero.cpp
index 91140f9e8..82c44eaf4 100644
--- a/host/lib/rfnoc/client_zero.cpp
+++ b/host/lib/rfnoc/client_zero.cpp
@@ -103,7 +103,7 @@ uint32_t client_zero::get_noc_id(uint16_t portno)
 {
     _check_port_number(portno);
     // The NOC ID is the second entry in the port's register space
-    return regs().peek32(_get_port_base_addr(portno) + 1);
+    return regs().peek32(_get_port_base_addr(portno) + 4);
 }
 
 bool client_zero::get_flush_active(uint16_t portno)
@@ -175,16 +175,18 @@ void client_zero::reset_chdr(uint16_t portno)
 client_zero::block_config_info client_zero::get_block_info(uint16_t portno)
 {
     _check_port_number(portno);
-    // The configuration information is in the port's first register
-    uint32_t config_reg_val = regs().peek32(_get_port_base_addr(portno));
-    return {uhd::narrow_cast<uint8_t>((config_reg_val & 0x000000FF) >> 0),
-        uhd::narrow_cast<uint8_t>((config_reg_val & 0x00003F00) >> 8),
-        uhd::narrow_cast<uint8_t>((config_reg_val & 0x000FC000) >> 14),
-        uhd::narrow_cast<uint8_t>((config_reg_val & 0x03F00000) >> 20),
-        uhd::narrow_cast<uint8_t>((config_reg_val & 0xFC000000) >> 26)};
+    // The block and ctrl information is in the port's first register
+    uint32_t config_reg_val = regs().peek32(_get_port_base_addr(portno) + 0);
+    // The block and ctrl information is in the port's third register
+    uint32_t data_reg_val = regs().peek32(_get_port_base_addr(portno) + 8);
+    return {uhd::narrow_cast<uint8_t>((config_reg_val & 0x0000003F) >> 0),
+        uhd::narrow_cast<uint8_t>((config_reg_val & 0x00000FC0) >> 6),
+        uhd::narrow_cast<uint8_t>((config_reg_val & 0x0003F000) >> 12),
+        uhd::narrow_cast<uint8_t>((config_reg_val & 0x00FC0000) >> 18),
+        uhd::narrow_cast<uint8_t>((config_reg_val & 0xFF000000) >> 24),
+        uhd::narrow_cast<uint8_t>((data_reg_val & 0x000000FC) >> 2)};
 }
 
-
 uint32_t client_zero::_get_port_base_addr(uint16_t portno)
 {
     return REGS_PER_PORT * portno * 4;
@@ -209,5 +211,5 @@ uint32_t client_zero::_get_flush_status_flags(uint16_t portno)
 {
     _check_port_number(portno);
     // The flush status flags are in the third register of the port
-    return regs().peek32(_get_port_base_addr(portno) + 2);
+    return regs().peek32(_get_port_base_addr(portno) + 8);
 }
diff --git a/host/tests/client_zero_test.cpp b/host/tests/client_zero_test.cpp
index d7f50ec52..46358422f 100644
--- a/host/tests/client_zero_test.cpp
+++ b/host/tests/client_zero_test.cpp
@@ -41,16 +41,18 @@ public:
     size_t register_block(const size_t num_in,
         const size_t num_out,
         const size_t ctrl_fifo_size,
+        const size_t ctrl_max_async_msgs,
         const size_t mtu,
         const uint32_t noc_id)
     {
         const uint32_t block_offset =
             (1 + NUM_STREAM_ENDPOINTS + num_registered_blocks) * SLOT_OFFSET;
-        read_memory[block_offset] = BLOCK_PROTOVER | (num_in & 0x3F) << 8
-                                    | (num_out & 0x3F) << 14
-                                    | (ctrl_fifo_size & 0x3F) << 20 | (mtu & 0x3F) << 26;
-        read_memory[block_offset + 1] = noc_id;
-        read_memory[block_offset + 2] = 0x2; // flush flags: active is low, done is high
+        read_memory[block_offset + 0] =
+            (BLOCK_PROTOVER & 0x3F) | (num_in & 0x3F) << 6 | (num_out & 0x3F) << 12
+            | (ctrl_fifo_size & 0x3F) << 18 | (ctrl_max_async_msgs & 0xFF) << 24;
+        read_memory[block_offset + 4] = noc_id;
+        read_memory[block_offset + 8] = (mtu & 0x3F) << 2
+                                        | 0x2; // flush flags: active is low, done is high
         num_registered_blocks++;
         set_port_cnt_reg(num_registered_blocks);
         return num_registered_blocks - 1;
@@ -112,7 +114,7 @@ public:
      * Memory banks and defaults
      *************************************************************************/
     uint16_t GLOBAL_PROTOVER      = 23; // 16 bits
-    uint8_t BLOCK_PROTOVER        = 42; // 8 bits
+    uint8_t BLOCK_PROTOVER        = 42; // 6 bits
     uint8_t STATIC_ROUTER_PRESENT = 1; // 1 bit
     uint8_t CHDR_XBAR_PRESENT     = 1; // 1 bit
     uint16_t NUM_XPORTS           = 3 & 0x3FF; // 10 bits
@@ -137,24 +139,25 @@ BOOST_AUTO_TEST_CASE(simple_read_if_chdr_pkt)
 {
     constexpr uint16_t DEVICE_ID      = 0xBEEF;
     constexpr uint16_t CTRL_FIFO_SIZE = 5; // in words
+    constexpr uint16_t CTRL_MAX_ASYNC_MSGS = 2;
     constexpr uint16_t MTU            = 40; // FIXME in words?
     auto mock_reg_iface = std::make_shared<client_zero_test_iface>(DEVICE_ID);
 
     // Prime the pump: We add some blocks and connections
-    size_t sep0_id = 0;
-    size_t sep1_id = 1;
-    size_t radio0_id =
-        mock_reg_iface->register_block(1, 1, CTRL_FIFO_SIZE, MTU, 0x12AD1000);
-    size_t ddc0_id =
-        mock_reg_iface->register_block(1, 1, CTRL_FIFO_SIZE, MTU, 0xDDC00000);
-    size_t duc0_id =
-        mock_reg_iface->register_block(1, 1, CTRL_FIFO_SIZE, MTU, 0xD11C0000);
-    size_t radio1_id =
-        mock_reg_iface->register_block(1, 1, CTRL_FIFO_SIZE, MTU, 0x12AD1000);
-    size_t ddc1_id =
-        mock_reg_iface->register_block(1, 1, CTRL_FIFO_SIZE, MTU, 0xDDC00000);
-    size_t duc1_id =
-        mock_reg_iface->register_block(1, 1, CTRL_FIFO_SIZE, MTU, 0xD11C0000);
+    size_t sep0_id   = 0;
+    size_t sep1_id   = 1;
+    size_t radio0_id = mock_reg_iface->register_block(
+        1, 1, CTRL_FIFO_SIZE, CTRL_MAX_ASYNC_MSGS, MTU, 0x12AD1000);
+    size_t ddc0_id = mock_reg_iface->register_block(
+        1, 1, CTRL_FIFO_SIZE, CTRL_MAX_ASYNC_MSGS, MTU, 0xDDC00000);
+    size_t duc0_id = mock_reg_iface->register_block(
+        1, 1, CTRL_FIFO_SIZE, CTRL_MAX_ASYNC_MSGS, MTU, 0xD11C0000);
+    size_t radio1_id = mock_reg_iface->register_block(
+        1, 1, CTRL_FIFO_SIZE, CTRL_MAX_ASYNC_MSGS, MTU, 0x12AD1000);
+    size_t ddc1_id = mock_reg_iface->register_block(
+        1, 1, CTRL_FIFO_SIZE, CTRL_MAX_ASYNC_MSGS, MTU, 0xDDC00000);
+    size_t duc1_id = mock_reg_iface->register_block(
+        1, 1, CTRL_FIFO_SIZE, CTRL_MAX_ASYNC_MSGS, MTU, 0xD11C0000);
     // Connect SEP -> DUC -> RADIO -> DDC -> SEP
     mock_reg_iface->add_connection(sep0_id, 0, duc0_id, 0);
     mock_reg_iface->add_connection(duc0_id, 0, radio0_id, 0);
@@ -220,5 +223,6 @@ BOOST_AUTO_TEST_CASE(simple_read_if_chdr_pkt)
     BOOST_CHECK_EQUAL(mock_config.num_inputs, 1);
     BOOST_CHECK_EQUAL(mock_config.num_outputs, 1);
     BOOST_CHECK_EQUAL(mock_config.ctrl_fifo_size, CTRL_FIFO_SIZE);
-    BOOST_CHECK_EQUAL(mock_config.mtu, MTU);
+    BOOST_CHECK_EQUAL(mock_config.ctrl_max_async_msgs, CTRL_MAX_ASYNC_MSGS);
+    BOOST_CHECK_EQUAL(mock_config.data_mtu, MTU);
 }