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| author | bstapleton <brent.stapleton@ettus.com> | 2017-06-27 17:49:18 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2017-06-29 16:11:30 -0700 |
| commit | a7c1ee2ec7d6673611851f9c55d716359212b729 (patch) | |
| tree | 2cbcc9aa34ae6c61a4de2810b4da73c714a05684 | |
| parent | c6a5387cec22cfadc805e39548535307b17d1524 (diff) | |
| download | uhd-a7c1ee2ec7d6673611851f9c55d716359212b729.tar.gz uhd-a7c1ee2ec7d6673611851f9c55d716359212b729.tar.bz2 uhd-a7c1ee2ec7d6673611851f9c55d716359212b729.zip | |
UBX: Added error handling for setting the dboard clock rate.
Setting daughterboard clock rate while using UBX on X300 caused an error. Added handling, now throws a warning that the phase will vary.
| -rw-r--r-- | host/lib/usrp/dboard/db_ubx.cpp | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/host/lib/usrp/dboard/db_ubx.cpp b/host/lib/usrp/dboard/db_ubx.cpp index 3dd0b1c84..d9abef599 100644 --- a/host/lib/usrp/dboard/db_ubx.cpp +++ b/host/lib/usrp/dboard/db_ubx.cpp @@ -295,6 +295,7 @@ public: _tx_target_pfd_freq = pfd_freq_max; if (_rev >= 1) { + bool can_set_clock_rate = true; // set dboard clock rates to as close to the max PFD freq as possible if (_iface->get_clock_rate(dboard_iface::UNIT_RX) > pfd_freq_max) { @@ -305,10 +306,15 @@ public: if (rate <= pfd_freq_max and rate > highest_rate) highest_rate = rate; } - _iface->set_clock_rate(dboard_iface::UNIT_RX, highest_rate); + try { + _iface->set_clock_rate(dboard_iface::UNIT_RX, highest_rate); + } catch (const uhd::not_implemented_error &) { + UHD_MSG(warning) << "Unable to set dboard clock rate - phase will vary" << std::endl; + can_set_clock_rate = false; + } _rx_target_pfd_freq = highest_rate; } - if (_iface->get_clock_rate(dboard_iface::UNIT_TX) > pfd_freq_max) + if (can_set_clock_rate and _iface->get_clock_rate(dboard_iface::UNIT_TX) > pfd_freq_max) { std::vector<double> rates = _iface->get_clock_rates(dboard_iface::UNIT_TX); double highest_rate = 0.0; @@ -317,7 +323,11 @@ public: if (rate <= pfd_freq_max and rate > highest_rate) highest_rate = rate; } - _iface->set_clock_rate(dboard_iface::UNIT_TX, highest_rate); + try { + _iface->set_clock_rate(dboard_iface::UNIT_TX, highest_rate); + } catch (const uhd::not_implemented_error &) { + UHD_MSG(warning) << "Unable to set dboard clock rate - phase will vary" << std::endl; + } _tx_target_pfd_freq = highest_rate; } } |