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authorMatt Ettus <matt@ettus.com>2011-02-25 15:17:31 -0800
committerMatt Ettus <matt@ettus.com>2011-02-25 15:17:31 -0800
commit98a1a03de054306f57be68e1b498c1d39a954472 (patch)
tree1faff6b576e6890a7ead1416296dea587a59d1d0
parent87f8f6fca6742a4263b636aa5632f228fccd18f2 (diff)
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fifo36_mux now has shortfifos on the input ports as well as output
-rw-r--r--usrp2/fifo/fifo36_mux.v37
-rw-r--r--usrp2/gpmc/fifo_to_gpmc_async.v5
-rw-r--r--usrp2/gpmc/gpmc_async.v4
3 files changed, 28 insertions, 18 deletions
diff --git a/usrp2/fifo/fifo36_mux.v b/usrp2/fifo/fifo36_mux.v
index c6fd40f27..fa4243efe 100644
--- a/usrp2/fifo/fifo36_mux.v
+++ b/usrp2/fifo/fifo36_mux.v
@@ -10,6 +10,19 @@ module fifo36_mux
input [35:0] data1_i, input src1_rdy_i, output dst1_rdy_o,
output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
+ wire [35:0] data0_int, data1_int;
+ wire src0_rdy_int, dst0_rdy_int, src1_rdy_int, dst1_rdy_int;
+
+ fifo_short #(.WIDTH(36)) mux_fifo_in0
+ (.clk(clk), .reset(reset), .clear(clear),
+ .datain(data0_i), .src_rdy_i(src0_rdy_i), .dst_rdy_o(dst0_rdy_i),
+ .dataout(data0_int), .src_rdy_o(src0_rdy_int), .dst_rdy_i(dst0_rdy_int));
+
+ fifo_short #(.WIDTH(36)) mux_fifo_in1
+ (.clk(clk), .reset(reset), .clear(clear),
+ .datain(data1_i), .src_rdy_i(src1_rdy_i), .dst_rdy_o(dst1_rdy_i),
+ .dataout(data1_int), .src_rdy_o(src1_rdy_int), .dst_rdy_i(dst1_rdy_int));
+
localparam MUX_IDLE0 = 0;
localparam MUX_DATA0 = 1;
localparam MUX_IDLE1 = 2;
@@ -17,8 +30,8 @@ module fifo36_mux
reg [1:0] state;
- wire eof0 = data0_i[33];
- wire eof1 = data1_i[33];
+ wire eof0 = data0_int[33];
+ wire eof1 = data1_int[33];
wire [35:0] data_int;
wire src_rdy_int, dst_rdy_int;
@@ -29,33 +42,33 @@ module fifo36_mux
else
case(state)
MUX_IDLE0 :
- if(src0_rdy_i)
+ if(src0_rdy_int)
state <= MUX_DATA0;
- else if(src1_rdy_i)
+ else if(src1_rdy_int)
state <= MUX_DATA1;
MUX_DATA0 :
- if(src0_rdy_i & dst_rdy_int & eof0)
+ if(src0_rdy_int & dst_rdy_int & eof0)
state <= prio ? MUX_IDLE0 : MUX_IDLE1;
MUX_IDLE1 :
- if(src1_rdy_i)
+ if(src1_rdy_int)
state <= MUX_DATA1;
- else if(src0_rdy_i)
+ else if(src0_rdy_int)
state <= MUX_DATA0;
MUX_DATA1 :
- if(src1_rdy_i & dst_rdy_int & eof1)
+ if(src1_rdy_int & dst_rdy_int & eof1)
state <= MUX_IDLE0;
default :
state <= MUX_IDLE0;
endcase // case (state)
- assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_int : 0;
- assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_int : 0;
- assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0;
- assign data_int = (state==MUX_DATA0) ? data0_i : data1_i;
+ assign dst0_rdy_int = (state==MUX_DATA0) ? dst_rdy_int : 0;
+ assign dst1_rdy_int = (state==MUX_DATA1) ? dst_rdy_int : 0;
+ assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_int : (state==MUX_DATA1) ? src1_rdy_int : 0;
+ assign data_int = (state==MUX_DATA0) ? data0_int : data1_int;
fifo_short #(.WIDTH(36)) mux_fifo
(.clk(clk), .reset(reset), .clear(clear),
diff --git a/usrp2/gpmc/fifo_to_gpmc_async.v b/usrp2/gpmc/fifo_to_gpmc_async.v
index cf8b6e861..9a8e37ce9 100644
--- a/usrp2/gpmc/fifo_to_gpmc_async.v
+++ b/usrp2/gpmc/fifo_to_gpmc_async.v
@@ -1,9 +1,4 @@
-// Assumes an asynchronous GPMC cycle
-// If a packet bigger or smaller than we are told is sent, behavior is undefined.
-// If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error.
-// If there is a bus error, we should be reset
-
module fifo_to_gpmc_async
(input clk, input reset, input clear,
input [17:0] data_i, input src_rdy_i, output dst_rdy_o,
diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v
index 053df5b18..02bf45b8a 100644
--- a/usrp2/gpmc/gpmc_async.v
+++ b/usrp2/gpmc/gpmc_async.v
@@ -215,7 +215,9 @@ module gpmc_async
wire [0:17] dummy18;
-assign debug = {dummy18, timedrx_src_rdy_int, timedrx_dst_rdy_int,
+assign debug = {8'd0,
+ test_rate,
+ pkt_src_enable, pkt_sink_enable, timedrx_src_rdy_int, timedrx_dst_rdy_int,
timedrx_src_rdy, timedrx_dst_rdy,
testrx_src_rdy, testrx_dst_rdy,
rx_src_rdy, rx_dst_rdy,