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| author | Josh Blum <josh@joshknows.com> | 2011-08-28 21:36:47 +0000 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-08-31 18:44:34 -0700 |
| commit | 87f69e9784d269fffbaa430726b4d31659034ae6 (patch) | |
| tree | a655656016a7b458e6eb105e2a5018f1ef613d05 | |
| parent | bbeb2189d587c0edc12873a1b5940ee0030148db (diff) | |
| download | uhd-87f69e9784d269fffbaa430726b4d31659034ae6.tar.gz uhd-87f69e9784d269fffbaa430726b4d31659034ae6.tar.bz2 uhd-87f69e9784d269fffbaa430726b4d31659034ae6.zip | |
e100: add FIFO clear and kernel clear to loopback
| -rw-r--r-- | host/usrp_e_utils/usrp-e-loopback.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/host/usrp_e_utils/usrp-e-loopback.cpp b/host/usrp_e_utils/usrp-e-loopback.cpp index 5b1003440..6b5ebd55f 100644 --- a/host/usrp_e_utils/usrp-e-loopback.cpp +++ b/host/usrp_e_utils/usrp-e-loopback.cpp @@ -259,6 +259,15 @@ int main(int argc, char *argv[]){ //set the mode to loopback poke16(E100_REG_MISC_XFER_RATE, (1<<8) | (1<<9)); + //clear FIFO state in FPGA and kernel + poke32(E100_REG_CLEAR_RX, 0); + poke32(E100_REG_CLEAR_TX, 0); + ::close(fp); + if ((fp = ::open("/dev/usrp_e0", O_RDWR)) < 0){ + std::cerr << "Open failed" << std::endl; + return -1; + } + //setup the ring buffer setup_ring(); |