build: Python 3 compatibility for build scripts

4 files changed, 16 insertions, 16 deletions

diff --git a/host/CMakeLists.txt b/host/CMakeLists.txt
index 63fbf6032..def2bd237 100644
--- a/host/CMakeLists.txt
+++ b/host/CMakeLists.txt
@@ -301,7 +301,7 @@ LIBUHD_REGISTER_COMPONENT("Tests" ENABLE_TESTS ON "ENABLE_LIBUHD" OFF)
 ########################################################################
 SET(HAS_FPGA_SUBMODULE FALSE)
 EXECUTE_PROCESS(
-    COMMAND ${PYTHON_EXECUTABLE} -c "import os; print os.path.abspath(os.path.join('${CMAKE_SOURCE_DIR}', '..', 'fpga-src'))"
+    COMMAND ${PYTHON_EXECUTABLE} -c "import os; print(os.path.abspath(os.path.join('${CMAKE_SOURCE_DIR}', '..', 'fpga-src')))"
     OUTPUT_VARIABLE FPGA_SUBMODULE_DIR
     OUTPUT_STRIP_TRAILING_WHITESPACE
 )
diff --git a/host/cmake/Modules/UHDVersion.cmake b/host/cmake/Modules/UHDVersion.cmake
index aefe516d6..b8b256834 100644
--- a/host/cmake/Modules/UHDVersion.cmake
+++ b/host/cmake/Modules/UHDVersion.cmake
@@ -38,7 +38,7 @@ SET(UHD_VERSION_DEVEL TRUE)
 FUNCTION(DEPAD_NUM input_num output_num)
     EXECUTE_PROCESS(
         WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
-        COMMAND ${PYTHON_EXECUTABLE} -c "print int('${input_num}')"
+        COMMAND ${PYTHON_EXECUTABLE} -c "print(int('${input_num}'))"
         OUTPUT_VARIABLE depadded_num OUTPUT_STRIP_TRAILING_WHITESPACE
     )
     SET(${output_num} ${depadded_num} PARENT_SCOPE)
@@ -69,12 +69,12 @@ EXECUTE_PROCESS(
 IF(_git_describe_result EQUAL 0)
     EXECUTE_PROCESS(
         WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}
-        COMMAND ${PYTHON_EXECUTABLE} -c "print '${_git_describe}'.split('-')[-2]"
+        COMMAND ${PYTHON_EXECUTABLE} -c "print('${_git_describe}'.split('-')[-2])"
         OUTPUT_VARIABLE UHD_GIT_COUNT OUTPUT_STRIP_TRAILING_WHITESPACE
     )
     EXECUTE_PROCESS(
         WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}
-        COMMAND ${PYTHON_EXECUTABLE} -c "print '${_git_describe}'.split('-')[-1]"
+        COMMAND ${PYTHON_EXECUTABLE} -c "print('${_git_describe}'.split('-')[-1])"
         OUTPUT_VARIABLE UHD_GIT_HASH OUTPUT_STRIP_TRAILING_WHITESPACE
     )
 ENDIF()
diff --git a/host/lib/ic_reg_maps/common.py b/host/lib/ic_reg_maps/common.py
index 0351d54a1..5c0cfc109 100755
--- a/host/lib/ic_reg_maps/common.py
+++ b/host/lib/ic_reg_maps/common.py
@@ -109,8 +109,8 @@ def to_num(arg): return int(eval(arg))
 class reg:
     def __init__(self, reg_des):
         try: self.parse(reg_des)
-        except Exception, e:
-            raise Exception, 'Error parsing register description: "%s"\nWhat: %s'%(reg_des, e)
+        except Exception as e:
+            raise Exception('Error parsing register description: "%s"\nWhat: %s'%(reg_des, e))
 
     def parse(self, reg_des):
         x = re.match('^(\w*)\s*(\w*)\[(.*)\]\s*(\w*)\s*(.*)$', reg_des)
@@ -153,8 +153,8 @@ class reg:
 class mreg:
     def __init__(self, mreg_des, regs):
         try: self.parse(mreg_des, regs)
-        except Exception, e:
-            raise Exception, 'Error parsing meta register description: "%s"\nWhat: %s'%(mreg_des, e)
+        except Exception as e:
+            raise Exception('Error parsing meta register description: "%s"\nWhat: %s'%(mreg_des, e))
 
     def parse(self, mreg_des, regs):
         x = re.match('^~(\w*)\s+(.*)\s*$', mreg_des)
diff --git a/host/lib/transport/nirio/lvbitx/process-lvbitx.py b/host/lib/transport/nirio/lvbitx/process-lvbitx.py
index ab9625608..7887c3997 100755
--- a/host/lib/transport/nirio/lvbitx/process-lvbitx.py
+++ b/host/lib/transport/nirio/lvbitx/process-lvbitx.py
@@ -1,6 +1,6 @@
 #!/usr/bin/python
 #
-# Copyright 2013-2014 Ettus Research LLC
+# Copyright 2013-2015 Ettus Research LLC
 #
 # This program is free software: you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -35,7 +35,7 @@ parser.add_option("--output-src-path", type="string", dest="output_src_path", he
 
 # Args
 if (len(args) < 1):
-    print 'ERROR: Please specify the input LVBITX file name'
+    print('ERROR: Please specify the input LVBITX file name')
     sys.exit(1)
 
 lvbitx_filename = args[0]
@@ -44,16 +44,16 @@ autogen_src_path = os.path.abspath(options.output_src_path) if (options.output_s
 class_name = os.path.splitext(os.path.basename(input_filename))[0]
 
 if (not os.path.isfile(input_filename)):
-    print 'ERROR: FPGA File ' + input_filename + ' could not be accessed or is not a file.'
+    print('ERROR: FPGA File ' + input_filename + ' could not be accessed or is not a file.')
     sys.exit(1)
 if (options.merge_bin is not None and not os.path.isfile(os.path.abspath(options.merge_bin))):
-    print 'ERROR: FPGA Bin File ' + options.merge_bin + ' could not be accessed or is not a file.'
+    print('ERROR: FPGA Bin File ' + options.merge_bin + ' could not be accessed or is not a file.')
     sys.exit(1)
 if (not os.path.exists(autogen_src_path)):
-    print 'ERROR: Output path ' + autogen_src_path + ' could not be accessed.'
+    print('ERROR: Output path ' + autogen_src_path + ' could not be accessed.')
     sys.exit(1)
 if (options.output_lvbitx_path is not None and input_filename == os.path.join(autogen_src_path, class_name + '.lvbitx')):
-    print 'ERROR: Input and output LVBITX files were the same. Choose a difference input file or output path.'
+    print('ERROR: Input and output LVBITX files were the same. Choose a difference input file or output path.')
     sys.exit(1)
 
 # Get XML Tree Node
@@ -122,7 +122,7 @@ def map_SubType_to_ScalarType(SubType):
     elif SubType == 'U64':
         ScalarType = 'RIO_SCALAR_TYPE_UQ'
     else:
-        print 'ERROR: No corresponding nirio_scalar_type_t value for SubType ' + SubType + ' .'
+        print('ERROR: No corresponding nirio_scalar_type_t value for SubType ' + SubType + ' .')
         sys.exit(1)
     return ScalarType;
 
@@ -187,7 +187,7 @@ codegen_transform['lvbitx_signature'] = str.upper(root.find('SignatureRegister')
 # Write BIN file
 bitstream = base64.b64decode(root.find('Bitstream').text)
 if (options.output_lvbitx_path is not None and hashlib.md5(bitstream).hexdigest() != root.find('BitstreamMD5').text):
-    print 'ERROR: The MD5 sum for the output LVBITX was incorrect. Make sure that the bitstream in the input LVBITX or BIN file is valid.'
+    print('ERROR: The MD5 sum for the output LVBITX was incorrect. Make sure that the bitstream in the input LVBITX or BIN file is valid.')
     sys.exit(1)
 if (options.output_bin):
     fpga_bin_file = open(os.path.join(options.output_lvbitx_path, class_name + '.bin'), 'w')