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| author | Matt Ettus <matt@ettus.com> | 2011-06-16 16:13:55 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-06-16 16:13:55 -0700 |
| commit | 792818725732fd18cd6af214d43d651749c52276 (patch) | |
| tree | b03d3269ec2b1d211f364722b7b636ba0138fe26 | |
| parent | 10d489c3aee1b09dec3171f70251c95e744c5afc (diff) | |
| download | uhd-792818725732fd18cd6af214d43d651749c52276.tar.gz uhd-792818725732fd18cd6af214d43d651749c52276.tar.bz2 uhd-792818725732fd18cd6af214d43d651749c52276.zip | |
u1e: core compile now works as a fullchip lint
| -rwxr-xr-x | usrp2/top/E1x0/core_compile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/top/E1x0/core_compile b/usrp2/top/E1x0/core_compile index dc0cd081e..02d7f006e 100755 --- a/usrp2/top/E1x0/core_compile +++ b/usrp2/top/E1x0/core_compile @@ -1,3 +1,3 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac -y $XILINX/verilog/src/unisims u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models |