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| author | Robin Coxe <robin.coxe@ettus.com> | 2018-06-25 15:38:00 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2018-06-26 16:14:01 -0700 |
| commit | 74c41781390ba0352431167d97ecec22c88e2336 (patch) | |
| tree | 32e142c70526f76f11ec9ca583df2b4df334ca8a | |
| parent | 523994c793c8e63f7b30657e06ce3588de0855c1 (diff) | |
| download | uhd-74c41781390ba0352431167d97ecec22c88e2336.tar.gz uhd-74c41781390ba0352431167d97ecec22c88e2336.tar.bz2 uhd-74c41781390ba0352431167d97ecec22c88e2336.zip | |
Update ISE/Vivado versions in images.dox
| -rw-r--r-- | host/docs/images.dox | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/host/docs/images.dox b/host/docs/images.dox index c6f48bc65..21ff0ea22 100644 --- a/host/docs/images.dox +++ b/host/docs/images.dox @@ -78,17 +78,18 @@ The build commands for a particular image can be found in \subsection images_building_xilinx Xilinx FPGA builds -USRP Xilinx FPGA images are built with two different versions of ISE, +USRP Xilinx FPGA images are built with either Vivado or one of two versions of ISE, depending on the device. The build requires that you have a UNIX-like environment with `Make`. -Make sure that `xtclsh` from the Xilinx ISE bin directory is in your `$PATH`. +Make sure that `xtclsh` from the Xilinx Vivado or ISE bin directory is in your `$PATH`. -- Xilinx ISE 14.7: USRP X3x0 Series, USRP B2x0 +- Vivado 2017.4: USRP N3x0, USRP E3x0, USRP X3x0 +- Xilinx ISE 14.7: USRP B2x0, USRP B200mini, B200mini-i, B205mini-i, USRP N2x0 See `<uhd-repo-path>/fpga/usrp3/top/`. -- Xilinx ISSE 12.2: USRP N2x0, USRP B1x0, USRP E1x0, USRP2 +- Xilinx ISE 12.2: USRP B1x0, USRP E1x0, USRP2 [All of these devices are EOL as of 2018] See `<uhd-repo-path>/fpga/usrp2/top/`. |