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| author | Josh Blum <josh@joshknows.com> | 2012-10-01 17:11:37 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-10-05 13:41:22 -0700 |
| commit | 503d95c58373a81ca7404162318f2658cf4c3642 (patch) | |
| tree | 70da49cca875b9b1c08907043907eaf2b3ddb9c2 | |
| parent | 38ec062b628e39397999d86fb3a68438aa586d5a (diff) | |
| download | uhd-503d95c58373a81ca7404162318f2658cf4c3642.tar.gz uhd-503d95c58373a81ca7404162318f2658cf4c3642.tar.bz2 uhd-503d95c58373a81ca7404162318f2658cf4c3642.zip | |
b100: fix RX ADC I and Q inversion
| -rw-r--r-- | usrp2/top/B100/B100.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/usrp2/top/B100/B100.v b/usrp2/top/B100/B100.v index dcda974b4..e333e82aa 100644 --- a/usrp2/top/B100/B100.v +++ b/usrp2/top/B100/B100.v @@ -143,13 +143,13 @@ module B100 always @(posedge clk_fpga) if(rxsync_0) begin - rx_i <= rx_b; - rx_q <= rx_a; + rx_i <= ~rx_b; + rx_q <= ~rx_a; end else begin - rx_i <= rx_a; - rx_q <= rx_b; + rx_i <= ~rx_a; + rx_q <= ~rx_b; end // ///////////////////////////////////////////////////////////////////////// |