Merge branch 'usrp_e100' into next

Conflicts:
	images/Makefile

139 files changed, 11210 insertions, 232 deletions

diff --git a/fpga/usrp2/control_lib/Makefile.srcs b/fpga/usrp2/control_lib/Makefile.srcs
index bc8e4d5bc..383ed97d8 100644
--- a/fpga/usrp2/control_lib/Makefile.srcs
+++ b/fpga/usrp2/control_lib/Makefile.srcs
@@ -42,4 +42,7 @@ pic.v \
 longfifo.v \
 shortfifo.v \
 medfifo.v \
+nsgpio16LE.v \
+settings_bus_16LE.v \
+atr_controller16.v \
 ))
diff --git a/fpga/usrp2/control_lib/atr_controller16.v b/fpga/usrp2/control_lib/atr_controller16.v
new file mode 100644
index 000000000..3d8b5b1e9
--- /dev/null
+++ b/fpga/usrp2/control_lib/atr_controller16.v
@@ -0,0 +1,60 @@
+
+// Automatic transmit/receive switching of control pins to daughterboards
+// Store everything in registers for now, but could use a RAM for more
+// complex state machines in the future
+
+module atr_controller16
+  (input clk_i, input rst_i,
+   input [5:0] adr_i, input [1:0] sel_i, input [15:0] dat_i, output reg [15:0] dat_o,
+   input we_i, input stb_i, input cyc_i, output reg ack_o,
+   input run_rx, input run_tx, input [31:0] master_time,
+   output [31:0] ctrl_lines);
+   
+   reg [3:0] state;
+   reg [31:0] atr_ram [0:15];  // DP distributed RAM
+
+   wire [3:0] sel_int = { (sel_i[1] & adr_i[1]), (sel_i[0] & adr_i[1]),
+			  (sel_i[1] & ~adr_i[1]), (sel_i[0] & ~adr_i[1]) };
+   
+   // WB Interface
+   always @(posedge clk_i)
+     if(we_i & stb_i & cyc_i)
+       begin
+	  if(sel_int[3])
+	    atr_ram[adr_i[5:2]][31:24] <= dat_i[15:8];
+	  if(sel_int[2])
+	    atr_ram[adr_i[5:2]][23:16] <= dat_i[7:0];
+	  if(sel_int[1])
+	    atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8];
+	  if(sel_int[0])
+	    atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0];
+       end // if (we_i & stb_i & cyc_i)
+
+   always @(posedge clk_i)
+     dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0];
+   
+   always @(posedge clk_i)
+     ack_o <= stb_i & cyc_i & ~ack_o;
+
+   // Control side of DP RAM
+   assign     ctrl_lines = atr_ram[state];
+
+   // Put a more complex state machine with time delays and multiple states here
+   //  if daughterboard requires more complex sequencing
+   localparam ATR_IDLE = 4'd0;
+   localparam ATR_TX = 4'd1;
+   localparam ATR_RX = 4'd2;
+   localparam ATR_FULL_DUPLEX = 4'd3;
+   
+   always @(posedge clk_i)
+     if(rst_i)
+       state <= ATR_IDLE;
+     else
+       case ({run_rx,run_tx})
+	 2'b00 : state <= ATR_IDLE;
+	 2'b01 : state <= ATR_TX;
+	 2'b10 : state <= ATR_RX;
+	 2'b11 : state <= ATR_FULL_DUPLEX;
+       endcase // case({run_rx,run_tx})
+   
+endmodule // atr_controller16
diff --git a/fpga/usrp2/control_lib/newfifo/fifo_pacer.v b/fpga/usrp2/control_lib/newfifo/fifo_pacer.v
new file mode 100644
index 000000000..1bf03ab6e
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/fifo_pacer.v
@@ -0,0 +1,24 @@
+
+
+module fifo_pacer
+  (input clk,
+   input reset,
+   input [7:0] rate,
+   input enable,
+   input src1_rdy_i, output dst1_rdy_o,
+   output src2_rdy_o, input dst2_rdy_i,
+   output underrun, overrun);
+
+   wire   strobe;
+   
+   cic_strober strober (.clock(clk), .reset(reset), .enable(enable),
+			.rate(rate), .strobe_fast(1), .strobe_slow(strobe));
+
+   wire   all_ready = src1_rdy_i & dst2_rdy_i;
+   assign dst1_rdy_o = all_ready & strobe;
+   assign src2_rdy_o = dst1_rdy_o;
+
+   assign underrun = strobe & ~src1_rdy_i;
+   assign overrun = strobe & ~dst2_rdy_i;
+   
+endmodule // fifo_pacer
diff --git a/fpga/usrp2/control_lib/newfifo/packet32_tb.v b/fpga/usrp2/control_lib/newfifo/packet32_tb.v
new file mode 100644
index 000000000..82bb09c29
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/packet32_tb.v
@@ -0,0 +1,27 @@
+
+
+module packet32_tb();
+
+   wire [35:0] data;
+   wire       src_rdy, dst_rdy;
+
+   wire       clear = 0;
+   reg 	      clk = 0;
+   reg 	      reset = 1;
+
+   always #10 clk <= ~clk;
+   initial #1000 reset <= 0;
+
+   initial $dumpfile("packet32_tb.vcd");
+   initial $dumpvars(0,packet32_tb);
+
+   wire [31:0] total, crc_err, seq_err, len_err;
+   
+   packet_generator32 pkt_gen (.clk(clk), .reset(reset), .clear(clear),
+			       .data_o(data), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
+
+   packet_verifier32 pkt_ver (.clk(clk), .reset(reset), .clear(clear),
+			      .data_i(data), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
+			      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+endmodule // packet32_tb
diff --git a/fpga/usrp2/control_lib/newfifo/packet_generator.v b/fpga/usrp2/control_lib/newfifo/packet_generator.v
new file mode 100644
index 000000000..6e8b45ccd
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/packet_generator.v
@@ -0,0 +1,59 @@
+
+
+module packet_generator
+  (input clk, input reset, input clear,
+   output reg [7:0] data_o, output sof_o, output eof_o, 
+   output src_rdy_o, input dst_rdy_i);
+
+   localparam len = 32'd2000;
+
+   reg [31:0] state;
+   reg [31:0] seq;
+   wire [31:0] crc_out;
+   wire        calc_crc = src_rdy_o & dst_rdy_i & ~(state[31:2] == 30'h3FFF_FFFF);
+   
+	
+   always @(posedge clk)
+     if(reset | clear)
+       seq <= 0;
+     else
+       if(eof_o & src_rdy_o & dst_rdy_i)
+	 seq <= seq + 1;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       state <= 0;
+     else
+       if(src_rdy_o & dst_rdy_i)
+	 if(state == (len - 1))
+	   state <= 32'hFFFF_FFFC;
+	 else
+	   state <= state + 1;
+
+   always @*
+     case(state)
+       0 :   data_o <= len[7:0];
+       1 :   data_o <= len[15:8];
+       2 :   data_o <= len[23:16];
+       3 :   data_o <= len[31:24];
+       4 :   data_o <= seq[7:0];
+       5 :   data_o <= seq[15:8];
+       6 :   data_o <= seq[23:16];
+       7 :   data_o <= seq[31:24];
+       32'hFFFF_FFFC : data_o <= crc_out[31:24];
+       32'hFFFF_FFFD : data_o <= crc_out[23:16];
+       32'hFFFF_FFFE : data_o <= crc_out[15:8];
+       32'hFFFF_FFFF : data_o <= crc_out[7:0];
+       default : data_o <= state[7:0];
+     endcase // case (state)
+   
+   assign src_rdy_o = 1;
+   assign sof_o = (state == 0);
+   assign eof_o = (state == 32'hFFFF_FFFF);
+
+   wire        clear_crc = eof_o & src_rdy_o & dst_rdy_i;
+   
+   crc crc(.clk(clk), .reset(reset), .clear(clear_crc), .data(data_o), 
+	   .calc(calc_crc), .crc_out(crc_out), .match());
+   
+endmodule // packet_generator
diff --git a/fpga/usrp2/control_lib/newfifo/packet_generator32.v b/fpga/usrp2/control_lib/newfifo/packet_generator32.v
new file mode 100644
index 000000000..6f8004964
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/packet_generator32.v
@@ -0,0 +1,21 @@
+
+
+module packet_generator32
+  (input clk, input reset, input clear,
+   output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
+
+   wire [7:0] 	     ll_data;
+   wire 	     ll_sof, ll_eof, ll_src_rdy, ll_dst_rdy_n;
+   
+   packet_generator pkt_gen
+     (.clk(clk), .reset(reset), .clear(clear),
+      .data_o(ll_data), .sof_o(ll_sof), .eof_o(ll_eof),
+      .src_rdy_o(ll_src_rdy), .dst_rdy_i(~ll_dst_rdy_n));
+
+   ll8_to_fifo36 ll8_to_f36
+     (.clk(clk), .reset(reset), .clear(clear),
+      .ll_data(ll_data), .ll_sof_n(~ll_sof), .ll_eof_n(~ll_eof),
+      .ll_src_rdy_n(~ll_src_rdy), .ll_dst_rdy_n(ll_dst_rdy_n),
+      .f36_data(data_o), .f36_src_rdy_o(src_rdy_o), .f36_dst_rdy_i(dst_rdy_i));
+   
+endmodule // packet_generator32
diff --git a/fpga/usrp2/control_lib/newfifo/packet_tb.v b/fpga/usrp2/control_lib/newfifo/packet_tb.v
new file mode 100644
index 000000000..3c423d2ba
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/packet_tb.v
@@ -0,0 +1,29 @@
+
+
+module packet_tb();
+
+   wire [7:0] data;
+   wire       sof, eof, src_rdy, dst_rdy;
+
+   wire       clear = 0;
+   reg 	      clk = 0;
+   reg 	      reset = 1;
+
+   always #10 clk <= ~clk;
+   initial #1000 reset <= 0;
+
+   initial $dumpfile("packet_tb.vcd");
+   initial $dumpvars(0,packet_tb);
+
+   wire [31:0] total, crc_err, seq_err, len_err;
+   
+   packet_generator pkt_gen (.clk(clk), .reset(reset), .clear(clear),
+			     .data_o(data), .sof_o(sof), .eof_o(eof),
+			     .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
+
+   packet_verifier pkt_ver (.clk(clk), .reset(reset), .clear(clear),
+			    .data_i(data), .sof_i(sof), .eof_i(eof),
+			    .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
+			    .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+endmodule // packet_tb
diff --git a/fpga/usrp2/control_lib/newfifo/packet_verifier.v b/fpga/usrp2/control_lib/newfifo/packet_verifier.v
new file mode 100644
index 000000000..b49ad1bbb
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/packet_verifier.v
@@ -0,0 +1,61 @@
+
+
+// Packet format --
+//    Line 1 -- Length, 32 bits
+//    Line 2 -- Sequence number, 32 bits
+//    Last line -- CRC, 32 bits
+
+module packet_verifier
+  (input clk, input reset, input clear,
+   input [7:0] data_i, input sof_i, input eof_i, input src_rdy_i, output dst_rdy_o,
+
+   output reg [31:0] total, 
+   output reg [31:0] crc_err, 
+   output reg [31:0] seq_err, 
+   output reg [31:0] len_err);
+
+   reg [31:0] 	     seq_num;
+   reg [31:0] 	     length;
+   wire 	     first_byte, last_byte;
+   reg 		     second_byte, last_byte_d1;
+
+   wire 	     calc_crc = src_rdy_i & dst_rdy_o;
+   
+   crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i), 
+	   .calc(calc_crc), .crc_out(), .match(match_crc));
+
+   assign first_byte = src_rdy_i & dst_rdy_o & sof_i;
+   assign last_byte = src_rdy_i & dst_rdy_o & eof_i;
+   assign dst_rdy_o = ~last_byte_d1;
+
+   // stubs for now
+   wire 	     match_seq = 1;
+   wire 	     match_len = 1;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       last_byte_d1 <= 0;
+     else 
+       last_byte_d1 <= last_byte;
+
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  total <= 0;
+	  crc_err <= 0;
+	  seq_err <= 0;
+	  len_err <= 0;
+       end
+     else
+       if(last_byte_d1)
+	 begin
+	    total <= total + 1;
+	    if(~match_crc)
+	      crc_err <= crc_err + 1;
+	    else if(~match_seq)
+	      seq_err <= seq_err + 1;
+	    else if(~match_len)
+	      seq_err <= len_err + 1;
+	 end
+   
+endmodule // packet_verifier
diff --git a/fpga/usrp2/control_lib/newfifo/packet_verifier32.v b/fpga/usrp2/control_lib/newfifo/packet_verifier32.v
new file mode 100644
index 000000000..06a13d242
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/packet_verifier32.v
@@ -0,0 +1,30 @@
+
+
+module packet_verifier32
+  (input clk, input reset, input clear,
+   input [35:0] data_i, input src_rdy_i, output dst_rdy_o,
+   output [31:0] total, output [31:0] crc_err, output [31:0] seq_err, output [31:0] len_err);
+
+   wire [7:0] 	     ll_data;
+   wire 	     ll_sof_n, ll_eof_n, ll_src_rdy_n, ll_dst_rdy;
+   wire [35:0] 	     data_int;
+   wire 	     src_rdy_int, dst_rdy_int;
+   
+   fifo_short #(.WIDTH(36)) fifo_short
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+      .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int));
+   
+   fifo36_to_ll8 f36_to_ll8
+     (.clk(clk), .reset(reset), .clear(clear),
+      .f36_data(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int),
+      .ll_data(ll_data), .ll_sof_n(ll_sof_n), .ll_eof_n(ll_eof_n),
+      .ll_src_rdy_n(ll_src_rdy_n), .ll_dst_rdy_n(~ll_dst_rdy));
+   
+   packet_verifier pkt_ver
+     (.clk(clk), .reset(reset), .clear(clear),
+      .data_i(ll_data), .sof_i(~ll_sof_n), .eof_i(~ll_eof_n),
+      .src_rdy_i(~ll_src_rdy_n), .dst_rdy_o(ll_dst_rdy),
+      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+endmodule // packet_verifier32
diff --git a/fpga/usrp2/control_lib/nsgpio16LE.v b/fpga/usrp2/control_lib/nsgpio16LE.v
new file mode 100644
index 000000000..8aef0c7ae
--- /dev/null
+++ b/fpga/usrp2/control_lib/nsgpio16LE.v
@@ -0,0 +1,123 @@
+// Modified from code originally by Richard Herveille, his copyright is below
+
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  OpenCores Simple General Purpose IO core                   ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2002 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+
+module nsgpio16LE
+  (input clk_i, input rst_i, 
+   input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [15:0] dat_i, 
+   output reg [15:0] dat_o, output reg ack_o,
+   input [31:0] atr, input [31:0] debug_0, input [31:0] debug_1, 
+   inout [31:0] gpio
+   );
+
+   reg [31:0] 	ctrl, line, ddr, dbg, lgpio;
+   
+   wire 	wb_acc = cyc_i & stb_i;            // WISHBONE access
+   wire 	wb_wr  = wb_acc & we_i;            // WISHBONE write access
+
+   always @(posedge clk_i or posedge rst_i)
+     if (rst_i)
+       begin
+          ctrl <= 32'h0;
+          line <= 32'h0;
+	  ddr <= 32'h0;
+	  dbg <= 32'h0;
+       end
+     else if (wb_wr)
+       case( adr_i[3:1] )
+	 3'b000 : 
+           line[15:0] <= dat_i;
+	 3'b001 : 
+           line[31:16] <= dat_i;
+	 3'b010 :
+	   ddr[15:0] <= dat_i;
+	 3'b011 :
+	   ddr[31:16] <= dat_i;
+	 3'b100 :
+	   ctrl[15:0] <= dat_i;
+	 3'b101 :
+	   ctrl[31:16] <= dat_i;
+	 3'b110 :
+	   dbg[15:0] <= dat_i;
+	 3'b111 :
+	   dbg[31:16] <= dat_i;
+       endcase // case ( adr_i[3:1] )
+   
+   always @(posedge clk_i)
+     case (adr_i[3:1])
+       3'b000 :
+	 dat_o <= lgpio[15:0];
+       3'b001 :
+	 dat_o <= lgpio[31:16];
+       3'b010 :
+	 dat_o <= ddr[15:0];
+       3'b011 :
+	 dat_o <= ddr[31:16];
+       3'b100 :
+	 dat_o <= ctrl[15:0];
+       3'b101 :
+	 dat_o <= ctrl[31:16];
+       3'b110 :
+	 dat_o <= dbg[15:0];
+       3'b111 :
+	 dat_o <= dbg[31:16];
+     endcase // case (adr_i[3:1])
+   
+   
+   always @(posedge clk_i or posedge rst_i)
+     if (rst_i)
+       ack_o <= 1'b0;
+     else
+       ack_o <= wb_acc & !ack_o;
+   
+   // latch GPIO input pins
+   always @(posedge clk_i)
+     lgpio <= gpio;
+   
+   // assign GPIO outputs
+   integer   n;
+   reg [31:0] igpio; // temporary internal signal
+   
+   always @(ctrl or line or debug_1 or debug_0 or atr or ddr or dbg)
+     for(n=0;n<32;n=n+1)
+       igpio[n] <= ddr[n] ? (dbg[n] ? (ctrl[n] ? debug_1[n] : debug_0[n]) : 
+			     (ctrl[n] ?  atr[n] : line[n]) )
+	 : 1'bz;
+   
+   assign     gpio = igpio;
+   
+endmodule
+
diff --git a/fpga/usrp2/control_lib/ram_2port_mixed_width.v b/fpga/usrp2/control_lib/ram_2port_mixed_width.v
new file mode 100644
index 000000000..fae7d8de3
--- /dev/null
+++ b/fpga/usrp2/control_lib/ram_2port_mixed_width.v
@@ -0,0 +1,120 @@
+
+module ram_2port_mixed_width
+  (input clk16,
+   input en16,
+   input we16,
+   input [10:0] addr16,
+   input [15:0] di16,
+   output [15:0] do16,
+   input clk32,
+   input en32,
+   input we32,
+   input [9:0] addr32,
+   input [31:0] di32,
+   output [31:0] do32);
+
+   wire 	 en32a = en32 & ~addr32[9];
+   wire 	 en32b = en32 & addr32[9];
+   wire 	 en16a = en16 & ~addr16[10];
+   wire 	 en16b = en16 & addr16[10];
+
+   wire [31:0] 	 do32a, do32b;
+   wire [15:0] 	 do16a, do16b;
+   
+   assign do32 = addr32[9] ? do32b : do32a;
+   assign do16 = addr16[10] ? do16b : do16a;
+   
+   RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000),
+		       .INIT_B(18'h00000),
+		       .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+		       .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+		       .SRVAL_B(18'h00000),      // Port B output value upon SSR assertion
+		       .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+		       .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE
+		       ) 
+   RAMB16BWE_S36_S18_0 (.DOA(do32a),       // Port A 32-bit Data Output
+			.DOB(do16a),       // Port B 16-bit Data Output
+			.DOPA(),     // Port A 4-bit Parity Output
+			.DOPB(),     // Port B 2-bit Parity Output
+			.ADDRA(addr32[8:0]),   // Port A 9-bit Address Input
+			.ADDRB(addr16[9:0]),   // Port B 10-bit Address Input
+			.CLKA(clk32),     // Port A 1-bit Clock
+			.CLKB(clk16),     // Port B 1-bit Clock
+			.DIA(di32),       // Port A 32-bit Data Input
+			.DIB(di16),       // Port B 16-bit Data Input
+			.DIPA(0),     // Port A 4-bit parity Input
+			.DIPB(0),     // Port-B 2-bit parity Input
+			.ENA(en32a),       // Port A 1-bit RAM Enable Input
+			.ENB(en16a),       // Port B 1-bit RAM Enable Input
+			.SSRA(0),     // Port A 1-bit Synchronous Set/Reset Input
+			.SSRB(0),     // Port B 1-bit Synchronous Set/Reset Input
+			.WEA({4{we32}}),       // Port A 4-bit Write Enable Input
+			.WEB({2{we16}})        // Port B 2-bit Write Enable Input
+			);
+
+   RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000),
+		       .INIT_B(18'h00000),
+		       .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+		       .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion
+		       .SRVAL_B(18'h00000),      // Port B output value upon SSR assertion
+		       .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
+		       .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE
+		       ) 
+   RAMB16BWE_S36_S18_1 (.DOA(do32b),       // Port A 32-bit Data Output
+			.DOB(do16b),       // Port B 16-bit Data Output
+			.DOPA(),     // Port A 4-bit Parity Output
+			.DOPB(),     // Port B 2-bit Parity Output
+			.ADDRA(addr32[8:0]),   // Port A 9-bit Address Input
+			.ADDRB(addr16[9:0]),   // Port B 10-bit Address Input
+			.CLKA(clk32),     // Port A 1-bit Clock
+			.CLKB(clk16),     // Port B 1-bit Clock
+			.DIA(di32),       // Port A 32-bit Data Input
+			.DIB(di16),       // Port B 16-bit Data Input
+			.DIPA(0),     // Port A 4-bit parity Input
+			.DIPB(0),     // Port-B 2-bit parity Input
+			.ENA(en32b),       // Port A 1-bit RAM Enable Input
+			.ENB(en16b),       // Port B 1-bit RAM Enable Input
+			.SSRA(0),     // Port A 1-bit Synchronous Set/Reset Input
+			.SSRB(0),     // Port B 1-bit Synchronous Set/Reset Input
+			.WEA({4{we32}}),       // Port A 4-bit Write Enable Input
+			.WEB({2{we16}})        // Port B 2-bit Write Enable Input
+			);
+
+endmodule // ram_2port_mixed_width
+
+
+
+   
+// ISE 10.1.03 chokes on the following
+   
+/*
+   
+   reg [31:0] 	       ram [(1<<AWIDTH)-1:0];
+   integer 	       i;
+   initial
+     for(i=0;i<512;i=i+1)
+       ram[i] <= 32'b0;
+   
+   always @(posedge clk16)
+     if (en16)
+       begin
+          if (we16)
+            if(addr16[0])
+	      ram[addr16[10:1]][15:0] <= di16;
+	    else
+	      ram[addr16[10:1]][31:16] <= di16;
+	  do16 <= addr16[0] ? ram[addr16[10:1]][15:0] : ram[addr16[10:1]][31:16];
+       end
+
+   always @(posedge clk32)
+     if (en32)
+       begin
+          if (we32)
+            ram[addr32] <= di32;
+          do32 <= ram[addr32];
+       end
+
+endmodule // ram_2port_mixed_width
+
+ 
+ */
diff --git a/fpga/usrp2/control_lib/settings_bus.v b/fpga/usrp2/control_lib/settings_bus.v
index fc960e456..aec179516 100644
--- a/fpga/usrp2/control_lib/settings_bus.v
+++ b/fpga/usrp2/control_lib/settings_bus.v
@@ -10,7 +10,7 @@ module settings_bus
      input wb_stb_i,
      input wb_we_i,
      output reg wb_ack_o,
-     output strobe,
+     output reg strobe,
      output reg [7:0] addr,
      output reg [31:0] data);
 
@@ -19,18 +19,18 @@ module settings_bus
    always @(posedge wb_clk)
      if(wb_rst)
        begin
-	  stb_int <= 1'b0;
+	  strobe <= 1'b0;
 	  addr <= 8'd0;
 	  data <= 32'd0;
        end
-     else if(wb_we_i & wb_stb_i)
+     else if(wb_we_i & wb_stb_i & ~wb_ack_o)
        begin
-	  stb_int <= 1'b1;
+	  strobe <= 1'b1;
 	  addr <= wb_adr_i[9:2];
 	  data <= wb_dat_i;
        end
      else
-       stb_int <= 1'b0;
+       strobe <= 1'b0;
 
    always @(posedge wb_clk)
      if(wb_rst)
@@ -38,11 +38,4 @@ module settings_bus
      else
        wb_ack_o <= wb_stb_i & ~wb_ack_o;
 
-   always @(posedge wb_clk)
-     stb_int_d1 <= stb_int;
-
-   //assign strobe = stb_int & ~stb_int_d1;
-   assign strobe = stb_int & wb_ack_o;
-          
 endmodule // settings_bus
-
diff --git a/fpga/usrp2/control_lib/settings_bus_16LE.v b/fpga/usrp2/control_lib/settings_bus_16LE.v
new file mode 100644
index 000000000..76061e9e0
--- /dev/null
+++ b/fpga/usrp2/control_lib/settings_bus_16LE.v
@@ -0,0 +1,54 @@
+
+// Grab settings off the wishbone bus, send them out to settings bus
+// 16 bits little endian, but all registers need to be written 32 bits at a time.
+// This means that you write the low 16 bits first and then the high 16 bits.
+// The setting regs are strobed when the high 16 bits are written
+
+module settings_bus_16LE
+  #(parameter AWIDTH=16, RWIDTH=8)
+    (input wb_clk, 
+     input wb_rst, 
+     input [AWIDTH-1:0] wb_adr_i,
+     input [15:0] wb_dat_i,
+     input wb_stb_i,
+     input wb_we_i,
+     output reg wb_ack_o,
+     output strobe,
+     output reg [7:0] addr,
+     output reg [31:0] data);
+
+   reg 		       stb_int;
+   
+   always @(posedge wb_clk)
+     if(wb_rst)
+       begin
+	  stb_int <= 1'b0;
+	  addr <= 8'd0;
+	  data <= 32'd0;
+       end
+     else if(wb_we_i & wb_stb_i)
+       begin
+	  addr <= wb_adr_i[RWIDTH+1:2];  // Zero pad high bits
+	  if(wb_adr_i[1])
+	    begin
+	       stb_int <= 1'b1;     // We now have both halves
+	       data[31:16] <= wb_dat_i;
+	    end
+	  else
+	    begin
+	       stb_int <= 1'b0;     // Don't strobe, we need other half
+	       data[15:0] <= wb_dat_i;
+	    end
+       end
+     else
+       stb_int <= 1'b0;
+
+   always @(posedge wb_clk)
+     if(wb_rst)
+       wb_ack_o <= 0;
+     else
+       wb_ack_o <= wb_stb_i & ~wb_ack_o;
+
+   assign strobe = stb_int & wb_ack_o;
+          
+endmodule // settings_bus_16LE
diff --git a/fpga/usrp2/control_lib/simple_uart.v b/fpga/usrp2/control_lib/simple_uart.v
index 22f0e70a2..0dd58b5f5 100644
--- a/fpga/usrp2/control_lib/simple_uart.v
+++ b/fpga/usrp2/control_lib/simple_uart.v
@@ -1,11 +1,12 @@
 
 module simple_uart
   #(parameter TXDEPTH = 1,
-    parameter RXDEPTH = 1)
-    (input clk_i, input rst_i,
-     input we_i, input stb_i, input cyc_i, output reg ack_o,
-     input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
-     output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o);
+    parameter RXDEPTH = 1,
+    parameter CLKDIV_DEFAULT = 16'd0)
+   (input clk_i, input rst_i,
+    input we_i, input stb_i, input cyc_i, output reg ack_o,
+    input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
+    output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o);
    
    // Register Map
    localparam SUART_CLKDIV = 0;
@@ -30,7 +31,7 @@ module simple_uart
    
    always @(posedge clk_i)
      if (rst_i)
-       clkdiv <= 0;
+       clkdiv <= CLKDIV_DEFAULT;
      else if (wb_wr)
        case(adr_i)
 	 SUART_CLKDIV : clkdiv <= dat_i[15:0];
diff --git a/fpga/usrp2/fifo/.gitignore b/fpga/usrp2/fifo/.gitignore
index cba7efc8e..866f1faad 100644
--- a/fpga/usrp2/fifo/.gitignore
+++ b/fpga/usrp2/fifo/.gitignore
@@ -1 +1,3 @@
+*.vcd
+*.lxt
 a.out
diff --git a/fpga/usrp2/fifo/fifo19_to_fifo36.v b/fpga/usrp2/fifo/fifo19_to_fifo36.v
index 5f9aeff9b..0e6bcea68 100644
--- a/fpga/usrp2/fifo/fifo19_to_fifo36.v
+++ b/fpga/usrp2/fifo/fifo19_to_fifo36.v
@@ -1,26 +1,31 @@
 
+// Parameter LE tells us if we are little-endian.  
+// Little-endian means send lower 16 bits first.
+// Default is big endian (network order), send upper bits first.
+
 module fifo19_to_fifo36
-  (input clk, input reset, input clear,
-   input [18:0] f19_datain,
-   input f19_src_rdy_i,
-   output f19_dst_rdy_o,
+  #(parameter LE=0)
+   (input clk, input reset, input clear,
+    input [18:0] f19_datain,
+    input f19_src_rdy_i,
+    output f19_dst_rdy_o,
 
-   output [35:0] f36_dataout,
-   output f36_src_rdy_o,
-   input f36_dst_rdy_i,
-   output [31:0] debug
-   );
+    output [35:0] f36_dataout,
+    output f36_src_rdy_o,
+    input f36_dst_rdy_i,
+    output [31:0] debug
+    );
 
-   reg 	 f36_sof, f36_eof, f36_occ;
+   reg 		  f36_sof, f36_eof, f36_occ;
    
-   reg [1:0] state;
-   reg [15:0] dat0, dat1;
+   reg [1:0] 	  state;
+   reg [15:0] 	  dat0, dat1;
 
-   wire f19_sof  = f19_datain[16];
-   wire f19_eof  = f19_datain[17];
-   wire f19_occ  = f19_datain[18];
+   wire 	  f19_sof  = f19_datain[16];
+   wire 	  f19_eof  = f19_datain[17];
+   wire 	  f19_occ  = f19_datain[18];
 
-   wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i;
+   wire 	  xfer_out = f36_src_rdy_o & f36_dst_rdy_i;
 
    always @(posedge clk)
      if(f19_src_rdy_i & ((state==0)|xfer_out))
@@ -68,7 +73,8 @@ module fifo19_to_fifo36
        dat0 		   <= f19_datain;
    
    assign    f19_dst_rdy_o  = xfer_out | (state != 2);
-   assign    f36_dataout    = {f36_occ,f36_eof,f36_sof,dat0,dat1};
+   assign    f36_dataout    = LE ? {f36_occ,f36_eof,f36_sof,dat1,dat0} :
+			      {f36_occ,f36_eof,f36_sof,dat0,dat1};
    assign    f36_src_rdy_o  = (state == 2);
 
    assign    debug = state;
diff --git a/fpga/usrp2/fifo/fifo36_to_fifo18.v b/fpga/usrp2/fifo/fifo36_to_fifo18.v
deleted file mode 100644
index b636ab9ca..000000000
--- a/fpga/usrp2/fifo/fifo36_to_fifo18.v
+++ /dev/null
@@ -1,40 +0,0 @@
-
-module fifo36_to_fifo18
-  (input clk, input reset, input clear,
-   input [35:0] f36_datain,
-   input f36_src_rdy_i,
-   output f36_dst_rdy_o,
-   
-   output [17:0] f18_dataout,
-   output f18_src_rdy_o,
-   input f18_dst_rdy_i );
-
-   wire   f36_sof  = f36_datain[32];
-   wire   f36_eof  = f36_datain[33];
-   wire   f36_occ  = f36_datain[35:34];
-
-   reg phase;
-
-   wire half_line 	   = f36_eof & ((f36_occ==1)|(f36_occ==2));
-   
-   assign f18_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16];
-   assign f18_dataout[16]  = phase ? 0 : f36_sof;
-   assign f18_dataout[17]  = phase ? f36_eof : half_line;
-   
-   assign f18_src_rdy_o    = f36_src_rdy_i;
-   assign f36_dst_rdy_o    = (phase | half_line) & f18_dst_rdy_i;
-	
-   wire f18_xfer 	   = f18_src_rdy_o & f18_dst_rdy_i;
-   wire f36_xfer 	   = f36_src_rdy_i & f36_dst_rdy_o;
-
-   always @(posedge clk)
-     if(reset)
-       phase 		  <= 0;
-     else if(f36_xfer)
-       phase 		  <= 0;
-     else if(f18_xfer)
-       phase 		  <= 1;
-   
-       
-endmodule // fifo36_to_fifo18
-
diff --git a/fpga/usrp2/fifo/fifo36_to_fifo19.v b/fpga/usrp2/fifo/fifo36_to_fifo19.v
index de249aaeb..517a2a476 100644
--- a/fpga/usrp2/fifo/fifo36_to_fifo19.v
+++ b/fpga/usrp2/fifo/fifo36_to_fifo19.v
@@ -1,33 +1,38 @@
 
-module fifo36_to_fifo19
-  (input clk, input reset, input clear,
-   input [35:0] f36_datain,
-   input f36_src_rdy_i,
-   output f36_dst_rdy_o,
-   
-   output [18:0] f19_dataout,
-   output f19_src_rdy_o,
-   input f19_dst_rdy_i );
+// Parameter LE tells us if we are little-endian.  
+// Little-endian means send lower 16 bits first.
+// Default is big endian (network order), send upper bits first.
 
+module fifo36_to_fifo19
+  #(parameter LE=0)
+   (input clk, input reset, input clear,
+    input [35:0] f36_datain,
+    input f36_src_rdy_i,
+    output f36_dst_rdy_o,
+    
+    output [18:0] f19_dataout,
+    output f19_src_rdy_o,
+    input f19_dst_rdy_i );
+   
    wire   f36_sof  = f36_datain[32];
    wire   f36_eof  = f36_datain[33];
    wire   f36_occ  = f36_datain[35:34];
-
-   reg phase;
-
-   wire half_line 	   = f36_eof & ((f36_occ==1)|(f36_occ==2));
    
-   assign f19_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16];
+   reg 	  phase;
+   
+   wire   half_line 	   = f36_eof & ((f36_occ==1)|(f36_occ==2));
+   
+   assign f19_dataout[15:0] = (LE ^ phase) ? f36_datain[15:0] : f36_datain[31:16];
    assign f19_dataout[16]  = phase ? 0 : f36_sof;
    assign f19_dataout[17]  = phase ? f36_eof : half_line;
    assign f19_dataout[18]  = f19_dataout[17] & ((f36_occ==1)|(f36_occ==3));
    
    assign f19_src_rdy_o    = f36_src_rdy_i;
    assign f36_dst_rdy_o    = (phase | half_line) & f19_dst_rdy_i;
-	
-   wire f19_xfer 	   = f19_src_rdy_o & f19_dst_rdy_i;
-   wire f36_xfer 	   = f36_src_rdy_i & f36_dst_rdy_o;
-
+   
+   wire   f19_xfer 	   = f19_src_rdy_o & f19_dst_rdy_i;
+   wire   f36_xfer 	   = f36_src_rdy_i & f36_dst_rdy_o;
+   
    always @(posedge clk)
      if(reset)
        phase 		  <= 0;
@@ -36,6 +41,5 @@ module fifo36_to_fifo19
      else if(f19_xfer)
        phase 		  <= 1;
    
-       
+   
 endmodule // fifo36_to_fifo19
-
diff --git a/fpga/usrp2/fifo/fifo36_to_ll8.v b/fpga/usrp2/fifo/fifo36_to_ll8.v
index 0dee1dfc6..9604d0e38 100644
--- a/fpga/usrp2/fifo/fifo36_to_ll8.v
+++ b/fpga/usrp2/fifo/fifo36_to_ll8.v
@@ -55,6 +55,5 @@ module fifo36_to_ll8
 
    assign advance 	 = ll_src_rdy & ll_dst_rdy;
    assign f36_dst_rdy_o  = advance & ((state==3)|ll_eof);
-   assign debug 	 = state;
    
 endmodule // ll8_to_fifo36
diff --git a/fpga/usrp2/gpmc/.gitignore b/fpga/usrp2/gpmc/.gitignore
new file mode 100644
index 000000000..3e14fa4f7
--- /dev/null
+++ b/fpga/usrp2/gpmc/.gitignore
@@ -0,0 +1,2 @@
+*.gif
+
diff --git a/fpga/usrp2/gpmc/Makefile.srcs b/fpga/usrp2/gpmc/Makefile.srcs
new file mode 100644
index 000000000..bff6ae3e0
--- /dev/null
+++ b/fpga/usrp2/gpmc/Makefile.srcs
@@ -0,0 +1,20 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+##################################################
+# SERDES Sources
+##################################################
+GPMC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../gpmc/, \
+dbsm.v \
+edge_sync.v \
+fifo_to_gpmc_async.v \
+fifo_to_gpmc_sync.v \
+fifo_watcher.v \
+gpmc_async.v \
+gpmc_sync.v \
+gpmc_to_fifo_async.v \
+gpmc_to_fifo_sync.v \
+gpmc_wb.v \
+ram_to_fifo.v \
+))
diff --git a/fpga/usrp2/gpmc/burst_data_write.txt b/fpga/usrp2/gpmc/burst_data_write.txt
new file mode 100644
index 000000000..3b5dfc785
--- /dev/null
+++ b/fpga/usrp2/gpmc/burst_data_write.txt
@@ -0,0 +1,16 @@
+# OMAP burst writes to FPGA
+
+CLK=0,nWE=1,nCS=1,nOE=1,DATA=Z.
+CLK=1.
+CLK=0,nWE=0,nCS=0,DATA=WR_DATA1.
+CLK=1.
+CLK=0,nWE=0,nCS=0,DATA=WR_DATA2.
+CLK=1.
+CLK=0,nWE=0,nCS=0,DATA=WR_DATA3.
+CLK=1.
+CLK=0,nWE=0,nCS=0,DATA=WR_DATA4.
+CLK=1.
+CLK=0,nWE=1,nCS=1,DATA=Z.
+CLK=1.
+
+
diff --git a/fpga/usrp2/gpmc/dbsm.v b/fpga/usrp2/gpmc/dbsm.v
new file mode 100644
index 000000000..530af7205
--- /dev/null
+++ b/fpga/usrp2/gpmc/dbsm.v
@@ -0,0 +1,80 @@
+
+module bsm
+  (input clk, input reset, input clear,
+   input write_done,
+   input read_done,
+   output readable,
+   output writeable);
+
+   reg 	  state;
+   localparam ST_WRITEABLE = 0;
+   localparam ST_READABLE = 1;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       state <= ST_WRITEABLE;
+     else
+       case(state)
+	 ST_WRITEABLE :
+	   if(write_done)
+	     state <= ST_READABLE;
+	 ST_READABLE :
+	   if(read_done)
+	     state <= ST_WRITEABLE;
+       endcase // case (state)
+
+   assign readable = (state == ST_READABLE);
+   assign writeable = (state == ST_WRITEABLE);
+   
+endmodule // bsm
+
+module dbsm
+  (input clk, input reset, input clear,
+   output reg read_sel, output read_ready, input read_done,
+   output reg write_sel, output write_ready, input write_done);
+
+   localparam NUM_BUFS = 2;
+
+   wire       [NUM_BUFS-1:0] readable, writeable, read_done_buf, write_done_buf;
+   
+   // Two of these buffer state machines
+   genvar     i;
+   generate
+      for(i=0;i<NUM_BUFS;i=i+1)
+	begin : BSMS
+	   bsm bsm(.clk(clk), .reset(reset), .clear(clear),
+		   .write_done((write_sel == i) & write_done),
+		   .read_done((read_sel == i) & read_done),
+		   .readable(readable[i]), .writeable(writeable[i]));
+	end
+   endgenerate
+   
+   reg 	 full;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  write_sel <= 0;
+	  full <= 0;
+       end
+     else
+       if(write_done & writeable[write_sel])
+	 if(write_sel ==(NUM_BUFS-1))
+	   write_sel <= 0;
+	 else
+	   write_sel <= write_sel + 1;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       read_sel <= 0;
+     else
+       if(read_done & readable[read_sel])
+	 if(read_sel==(NUM_BUFS-1))
+	   read_sel <= 0;
+	 else
+	   read_sel <= read_sel + 1;
+          
+   assign write_ready = writeable[write_sel];
+   assign read_ready = readable[read_sel];
+
+endmodule // dbsm
diff --git a/fpga/usrp2/gpmc/edge_sync.v b/fpga/usrp2/gpmc/edge_sync.v
new file mode 100644
index 000000000..5d9417c08
--- /dev/null
+++ b/fpga/usrp2/gpmc/edge_sync.v
@@ -0,0 +1,22 @@
+
+
+module edge_sync
+  #(parameter POSEDGE = 1)
+   (input clk,
+    input rst,
+    input sig,
+    output trig);
+   
+   reg [1:0] delay;
+   
+   always @(posedge clk)
+     if(rst)
+       delay <= 2'b00;
+     else
+       delay <= {delay[0],sig};
+   
+   assign trig = POSEDGE ? (delay==2'b01) : (delay==2'b10);
+   
+endmodule // edge_sync
+
+
diff --git a/fpga/usrp2/gpmc/fifo_to_gpmc_async.v b/fpga/usrp2/gpmc/fifo_to_gpmc_async.v
new file mode 100644
index 000000000..cf8b6e861
--- /dev/null
+++ b/fpga/usrp2/gpmc/fifo_to_gpmc_async.v
@@ -0,0 +1,37 @@
+
+// Assumes an asynchronous GPMC cycle
+//   If a packet bigger or smaller than we are told is sent, behavior is undefined.
+//   If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error.
+//   If there is a bus error, we should be reset
+
+module fifo_to_gpmc_async
+  (input clk, input reset, input clear,
+   input [17:0] data_i, input src_rdy_i, output dst_rdy_o,
+   output [15:0] EM_D, input EM_NCS, input EM_NOE,
+   input [15:0] frame_len);
+
+   // Synchronize the async control signals
+   reg [2:0] 	cs_del, oe_del;
+   reg [15:0] 	counter;
+   
+   always @(posedge clk)
+     if(reset)
+       begin
+	  cs_del <= 3'b11;
+	  oe_del <= 3'b11;
+       end
+     else
+       begin
+	  cs_del <= { cs_del[1:0], EM_NCS };
+	  oe_del <= { oe_del[1:0], EM_NOE };
+       end
+
+   wire do_read = ( (~cs_del[1] | ~cs_del[2]) & (oe_del[1:0] == 2'b01));  // change output on trailing edge
+   wire first_read = (counter == 0);
+   wire last_read = ((counter+1) == frame_len);
+
+   assign EM_D = data_i[15:0];
+
+   assign dst_rdy_o = do_read;
+
+endmodule // fifo_to_gpmc_async
diff --git a/fpga/usrp2/gpmc/fifo_to_gpmc_sync.v b/fpga/usrp2/gpmc/fifo_to_gpmc_sync.v
new file mode 100644
index 000000000..ef59d7137
--- /dev/null
+++ b/fpga/usrp2/gpmc/fifo_to_gpmc_sync.v
@@ -0,0 +1,26 @@
+
+// Assumes a GPMC cycle with GPMC clock, as in the timing diagrams
+//   If a packet bigger or smaller than we are told is sent, behavior is undefined.
+//   If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error.
+//   If there is a bus error, we should be reset
+
+module fifo_to_gpmc_sync
+  (input arst,
+   input [17:0] data_i, input src_rdy_i, output dst_rdy_o,
+   input EM_CLK, output [15:0] EM_D, input EM_NCS, input EM_NOE,
+   output fifo_ready, 
+   output reg bus_error);
+
+   assign EM_D = data_i[15:0];
+   wire       read_access = ~EM_NCS & ~EM_NOE;
+
+   assign dst_rdy_o = read_access;
+
+   always @(posedge EM_CLK or posedge arst)
+     if(arst)
+       bus_error <= 0;
+     else if(dst_rdy_o & ~src_rdy_i)
+       bus_error <= 1;
+   
+
+endmodule // fifo_to_gpmc_sync
diff --git a/fpga/usrp2/gpmc/fifo_watcher.v b/fpga/usrp2/gpmc/fifo_watcher.v
new file mode 100644
index 000000000..fe4e35de3
--- /dev/null
+++ b/fpga/usrp2/gpmc/fifo_watcher.v
@@ -0,0 +1,56 @@
+
+
+module fifo_watcher
+  (input clk, input reset, input clear,
+   input src_rdy1, input dst_rdy1, input sof1, input eof1,
+   input src_rdy2, input dst_rdy2, input sof2, input eof2,
+   output reg have_packet, output [15:0] length, output reg bus_error,
+   output [31:0] debug);
+
+   wire   write = src_rdy1 & dst_rdy1 & eof1;
+   wire   read = src_rdy2 & dst_rdy2 & eof2;
+   wire   have_packet_int;
+   reg [15:0] counter;
+   wire [4:0] pkt_count;
+   assign debug = pkt_count;
+   
+   fifo_short #(.WIDTH(16)) frame_lengths
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(counter), .src_rdy_i(write), .dst_rdy_o(),
+      .dataout(length), .src_rdy_o(have_packet_int), .dst_rdy_i(read),
+      .occupied(pkt_count), .space());
+
+   always @(posedge clk)
+     if(reset | clear)
+       counter <= 1;   // Start at 1
+     else if(src_rdy1 & dst_rdy1)
+       if(eof1)
+	 counter <= 1;
+       else
+	 counter <= counter + 1;
+
+   always @(posedge clk)
+     if(reset | clear)
+       bus_error <= 0;
+     else if(dst_rdy2 & ~src_rdy2)
+       bus_error <= 1;
+     else if(read & ~have_packet_int)
+       bus_error <= 1;
+
+   reg 	      in_packet;
+   always @(posedge clk)
+     if(reset | clear)
+       have_packet <= 0;
+     else 
+       have_packet <= (have_packet_int & ~in_packet) | (pkt_count>1) ;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       in_packet <= 0;
+     else if(src_rdy2 & dst_rdy2)
+       if(eof2)
+	 in_packet <= 0;
+       else
+	 in_packet <= 1;
+   
+endmodule // fifo_watcher
diff --git a/fpga/usrp2/gpmc/gpmc_async.v b/fpga/usrp2/gpmc/gpmc_async.v
new file mode 100644
index 000000000..23bad56ae
--- /dev/null
+++ b/fpga/usrp2/gpmc/gpmc_async.v
@@ -0,0 +1,130 @@
+//////////////////////////////////////////////////////////////////////////////////
+
+module gpmc_async
+  #(parameter TXFIFOSIZE = 11, parameter RXFIFOSIZE = 11)
+   (// GPMC signals
+    input arst,
+    input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
+    input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
+    
+    // GPIOs for FIFO signalling
+    output rx_have_data, output tx_have_space, output reg bus_error, input bus_reset,
+    
+    // Wishbone signals
+    input wb_clk, input wb_rst,
+    output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
+    output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i,
+    
+    // FIFO interface
+    input fifo_clk, input fifo_rst, input clear_tx, input clear_rx,
+    output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i,
+    input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
+    
+    input [15:0] tx_frame_len, output [15:0] rx_frame_len,
+    
+    output [31:0] debug
+    );
+
+   wire 	  EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
+   wire [15:0] 	  EM_D_fifo;
+   wire [15:0] 	  EM_D_wb;
+   
+   assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb;
+   
+   wire 	  bus_error_tx, bus_error_rx;
+   
+   always @(posedge fifo_clk)
+     if(fifo_rst | clear_tx | clear_rx)
+       bus_error <= 0;
+     else
+       bus_error <= bus_error_tx | bus_error_rx;
+   
+   // CS4 is RAM_2PORT for DATA PATH (high-speed data)
+   //    Writes go into one RAM, reads come from the other
+   // CS6 is for CONTROL PATH (wishbone)
+
+   // ////////////////////////////////////////////
+   // TX Data Path
+
+   wire [17:0] 	  tx18_data, tx18b_data;
+   wire 	  tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy;
+   wire [15:0] 	  tx_fifo_space;
+   wire [35:0] 	  tx36_data;
+   wire 	  tx36_src_rdy, tx36_dst_rdy;
+   
+   gpmc_to_fifo_async gpmc_to_fifo_async
+     (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE),
+      .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), .clear(clear_tx),
+      .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy),
+      .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space),
+      .bus_error(bus_error_tx) );
+   
+   fifo_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
+      .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space),
+      .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied());
+
+   fifo19_to_fifo36 #(.LE(1)) f19_to_f36   // Little endian because ARM is LE
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
+      .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy),
+      .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy));
+   
+   fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx),
+      .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy),
+      .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i));
+
+   // ////////////////////////////////////////////
+   // RX Data Path
+   
+   wire [17:0] 	  rx18_data, rx18b_data;
+   wire 	  rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy;
+   wire [15:0] 	  rx_fifo_space;
+   wire [35:0] 	  rx36_data;
+   wire 	  rx36_src_rdy, rx36_dst_rdy;
+   wire 	  dummy;
+   
+   fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
+      .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o),
+      .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy));
+
+   fifo36_to_fifo19 #(.LE(1)) f36_to_f19   // Little endian because ARM is LE
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+      .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy),
+      .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) );
+
+   fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+      .datain(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space),
+      .dataout(rx18b_data), .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied());
+
+   fifo_to_gpmc_async fifo_to_gpmc_async
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+      .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy),
+      .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE),
+      .frame_len(rx_frame_len) );
+
+   wire [31:0] 	pkt_count;
+   
+   fifo_watcher fifo_watcher
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+      .src_rdy1(rx18_src_rdy), .dst_rdy1(rx18_dst_rdy), .sof1(rx18_data[16]), .eof1(rx18_data[17]),
+      .src_rdy2(rx18b_src_rdy), .dst_rdy2(rx18b_dst_rdy), .sof2(rx18b_data[16]), .eof2(rx18b_data[17]),
+      .have_packet(rx_have_data), .length(rx_frame_len), .bus_error(bus_error_rx),
+      .debug(pkt_count));
+
+   // ////////////////////////////////////////////
+   // Control path on CS6
+   
+   gpmc_wb gpmc_wb
+     (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE),
+      .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE),
+      .wb_clk(wb_clk), .wb_rst(wb_rst),
+      .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso),
+      .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o),
+      .wb_ack_i(wb_ack_i) );
+   
+      assign debug = pkt_count;
+   
+endmodule // gpmc_async
diff --git a/fpga/usrp2/gpmc/gpmc_sync.v b/fpga/usrp2/gpmc/gpmc_sync.v
new file mode 100644
index 000000000..61c54a793
--- /dev/null
+++ b/fpga/usrp2/gpmc/gpmc_sync.v
@@ -0,0 +1,108 @@
+//////////////////////////////////////////////////////////////////////////////////
+
+module gpmc_sync
+  (// GPMC signals
+   input arst,
+   input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
+   input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
+   
+   // GPIOs for FIFO signalling
+   output rx_have_data, output tx_have_space, output bus_error, input bus_reset,
+   
+   // Wishbone signals
+   input wb_clk, input wb_rst,
+   output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
+   output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i,
+
+   // FIFO interface
+   input fifo_clk, input fifo_rst,
+   output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i,
+   input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
+
+   output [31:0] debug
+   );
+
+   wire 	EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));
+   wire [15:0] 	EM_D_fifo;
+   wire [15:0] 	EM_D_wb;
+
+   assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb;
+
+   wire 	bus_error_tx, bus_error_rx;
+   assign bus_error = bus_error_tx | bus_error_rx;
+   
+   // CS4 is RAM_2PORT for DATA PATH (high-speed data)
+   //    Writes go into one RAM, reads come from the other
+   // CS6 is for CONTROL PATH (wishbone)
+
+   // ////////////////////////////////////////////
+   // TX Data Path
+
+   wire [17:0] 	tx18_data, tx18b_data;
+   wire 	tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy;
+   wire [15:0] 	tx_fifo_space, tx_frame_len;
+   
+   assign tx_frame_len = 10;
+   
+   gpmc_to_fifo_sync gpmc_to_fifo_sync
+     (.arst(arst),
+      .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE),
+      .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy),
+      .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space),
+      .bus_error(bus_error_tx) );
+   
+   fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) tx_fifo
+     (.wclk(EM_CLK), .datain(tx18_data), 
+      .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space),
+      .rclk(fifo_clk), .dataout(tx18b_data), 
+      .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied(), .arst(arst));
+
+   fifo19_to_fifo36 #(.LE(1)) f19_to_f36   // Little endian because ARM is LE
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy),
+      .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i));
+   
+   // ////////////////////////////////////////////
+   // RX Data Path
+
+   wire [17:0] 	rx18_data, rx18b_data;
+   wire 	rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy;
+   wire [15:0] 	rx_fifo_space, rx_frame_len;
+   wire 	dummy;
+   
+   fifo36_to_fifo19 #(.LE(1)) f36_to_f19   // Little endian because ARM is LE
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o),
+      .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) );
+
+   fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) rx_fifo
+     (.wclk(fifo_clk), .datain(rx18_data), 
+      .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space),
+      .rclk(EM_CLK), .dataout(rx18b_data), 
+      .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied(), .arst(arst));
+
+   fifo_to_gpmc_sync fifo_to_gpmc_sync
+     (.arst(arst),
+      .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy),
+      .EM_CLK(EM_CLK), .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE),
+      .fifo_ready(rx_have_data) );
+
+   fifo_watcher fifo_watcher
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
+      .src_rdy(rx18_src_rdy), .dst_rdy(rx18_dst_rdy), .sof(rx18_data[16]), .eof(rx18_data[17]),
+      .have_packet(), .length(), .next() );
+   
+   // ////////////////////////////////////////////
+   // Control path on CS6
+   
+   gpmc_wb gpmc_wb
+     (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE),
+      .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE),
+      .wb_clk(wb_clk), .wb_rst(wb_rst),
+      .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso),
+      .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o),
+      .wb_ack_i(wb_ack_i) );
+   
+      assign debug = 0;
+   
+endmodule // gpmc_sync
diff --git a/fpga/usrp2/gpmc/gpmc_to_fifo_async.v b/fpga/usrp2/gpmc/gpmc_to_fifo_async.v
new file mode 100644
index 000000000..55c0cef50
--- /dev/null
+++ b/fpga/usrp2/gpmc/gpmc_to_fifo_async.v
@@ -0,0 +1,68 @@
+
+module gpmc_to_fifo_async
+  (input [15:0] EM_D, input [1:0] EM_NBE, input EM_NCS, input EM_NWE,
+
+   input fifo_clk, input fifo_rst, input clear,
+   output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i,
+
+   input [15:0] frame_len, input [15:0] fifo_space, output reg fifo_ready,
+   output reg bus_error );
+
+   reg [15:0] counter;
+   // Synchronize the async control signals
+   reg [1:0] 	cs_del, we_del;
+   always @(posedge fifo_clk)
+     if(fifo_rst)
+       begin
+	  cs_del <= 2'b11;
+	  we_del <= 2'b11;
+       end
+     else
+       begin
+	  cs_del <= { cs_del[0], EM_NCS };
+	  we_del <= { we_del[0], EM_NWE };
+       end
+
+   wire do_write = (~cs_del[0] & (we_del == 2'b10));
+   wire first_write = (counter == 0);
+   wire last_write = ((counter+1) == frame_len);
+
+   always @(posedge fifo_clk)
+     if(do_write)
+       begin
+	  data_o[15:0] <= EM_D;
+	  data_o[16] <= first_write;
+	  data_o[17] <= last_write;
+	  //  no byte writes data_o[18] <= |EM_NBE;  // mark half full if either is not enabled  FIXME
+       end
+
+   always @(posedge fifo_clk)
+     if(fifo_rst | clear)
+       src_rdy_o <= 0;
+     else if(do_write)
+       src_rdy_o <= 1;
+     else
+       src_rdy_o <= 0;    // Assume it was taken
+
+   always @(posedge fifo_clk)
+     if(fifo_rst | clear)
+       counter <= 0;
+     else if(do_write)
+       if(last_write)
+	 counter <= 0;
+       else
+	 counter <= counter + 1;
+
+   always @(posedge fifo_clk)
+     if(fifo_rst | clear)
+       fifo_ready <= 0;
+     else
+       fifo_ready <= /* first_write & */ (fifo_space > 16'd1023);
+
+   always @(posedge fifo_clk)
+     if(fifo_rst | clear)
+       bus_error <= 0;
+     else if(src_rdy_o & ~dst_rdy_i)
+       bus_error <= 1;
+   
+endmodule // gpmc_to_fifo_async
diff --git a/fpga/usrp2/gpmc/gpmc_to_fifo_sync.v b/fpga/usrp2/gpmc/gpmc_to_fifo_sync.v
new file mode 100644
index 000000000..688de0e17
--- /dev/null
+++ b/fpga/usrp2/gpmc/gpmc_to_fifo_sync.v
@@ -0,0 +1,57 @@
+
+// Assumes a GPMC cycle with GPMC clock, as in the timing diagrams
+//   If a packet bigger or smaller than we are told is sent, behavior is undefined.
+//   If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error.
+//   If there is a bus error, we should be reset
+
+module gpmc_to_fifo_sync
+  (input arst,
+   input EM_CLK, input [15:0] EM_D, input [1:0] EM_NBE,
+   input EM_NCS, input EM_NWE,
+   output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i,
+   input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready, 
+   output reg bus_error);
+   
+   reg [10:0] 	counter;
+   wire 	first_write = (counter == 0);
+   wire 	last_write = ((counter+1) == frame_len);
+   wire 	do_write = ~EM_NCS & ~EM_NWE;
+   
+   always @(posedge EM_CLK or posedge arst)
+     if(arst)
+       data_o <= 0;
+     else if(do_write)
+       begin
+	  data_o[15:0] <= EM_D;
+	  data_o[16] <= first_write;
+	  data_o[17] <= last_write;
+	  //  no byte writes data_o[18] <= |EM_NBE;  // mark half full if either is not enabled  FIXME
+       end
+
+   always @(posedge EM_CLK or posedge arst)
+     if(arst)
+       src_rdy_o <= 0;
+     else if(do_write & ~bus_error)  // Don't put junk in if there is a bus error
+       src_rdy_o <= 1;
+     else
+       src_rdy_o <= 0;    // Assume it was taken, ignore dst_rdy_i
+
+   always @(posedge EM_CLK or posedge arst)
+     if(arst)
+       counter <= 0;
+     else if(do_write)
+       if(last_write)
+	 counter <= 0;
+       else
+	 counter <= counter + 1;
+
+   assign fifo_ready = first_write & (fifo_space > frame_len);
+   
+   always @(posedge EM_CLK or posedge arst)
+     if(arst)
+       bus_error <= 0;
+     else if(src_rdy_o & ~dst_rdy_i)
+       bus_error <= 1;
+   // must be reset to make the error go away
+
+endmodule // gpmc_to_fifo_sync
diff --git a/fpga/usrp2/gpmc/gpmc_wb.v b/fpga/usrp2/gpmc/gpmc_wb.v
new file mode 100644
index 000000000..db6fbc6e9
--- /dev/null
+++ b/fpga/usrp2/gpmc/gpmc_wb.v
@@ -0,0 +1,57 @@
+
+
+module gpmc_wb
+  (input EM_CLK, input [15:0] EM_D_in, output [15:0] EM_D_out, input [10:1] EM_A, input [1:0] EM_NBE,
+   input EM_NCS, input EM_NWE, input EM_NOE,
+
+   input wb_clk, input wb_rst,
+   output reg [10:0] wb_adr_o, output reg [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
+   output reg [1:0] wb_sel_o, output wb_cyc_o, output reg wb_stb_o, output reg wb_we_o, input wb_ack_i);
+   
+   // ////////////////////////////////////////////
+   // Control Path, Wishbone bus bridge (wb master)
+   reg [1:0] 	cs_del, we_del, oe_del;
+
+   // Synchronize the async control signals
+   always @(posedge wb_clk)
+     begin
+	cs_del <= { cs_del[0], EM_NCS };
+	we_del <= { we_del[0], EM_NWE };
+	oe_del <= { oe_del[0], EM_NOE };
+     end
+
+   always @(posedge wb_clk)
+     if(cs_del == 2'b10)  // Falling Edge
+       wb_adr_o <= { EM_A, 1'b0 };
+
+   always @(posedge wb_clk)
+     if(we_del == 2'b10)  // Falling Edge
+       begin
+	  wb_dat_mosi <= EM_D_in;
+	  wb_sel_o <= ~EM_NBE;
+       end
+
+   reg [15:0] EM_D_hold;
+   
+   always @(posedge wb_clk)
+     if(wb_ack_i)
+       EM_D_hold <= wb_dat_miso;
+
+   assign EM_D_out = wb_ack_i ? wb_dat_miso : EM_D_hold;
+   
+   assign wb_cyc_o = wb_stb_o;
+
+   always @(posedge wb_clk)
+     if(~cs_del[0] & (we_del == 2'b10) )
+       wb_we_o <= 1;
+     else if(wb_ack_i)  // Turn off we when done.  Could also use we_del[0], others...
+       wb_we_o <= 0;
+
+   // FIXME should this look at cs_del[1]?
+   always @(posedge wb_clk)
+     if(~cs_del[0] & ((we_del == 2'b10) | (oe_del == 2'b10)))
+       wb_stb_o <= 1;
+     else if(wb_ack_i)
+       wb_stb_o <= 0;
+   
+endmodule // gpmc_wb
diff --git a/fpga/usrp2/gpmc/make_timing_diag b/fpga/usrp2/gpmc/make_timing_diag
new file mode 100755
index 000000000..03166ad35
--- /dev/null
+++ b/fpga/usrp2/gpmc/make_timing_diag
@@ -0,0 +1,6 @@
+#!/bin/sh
+drawtiming -o single_data_write.gif single_data_write.txt
+drawtiming -o single_data_read.gif single_data_read.txt
+drawtiming -o burst_data_write.gif burst_data_write.txt
+#drawtiming -o burst_data_read.gif burst_data_read.txt
+
diff --git a/fpga/usrp2/gpmc/ram_to_fifo.v b/fpga/usrp2/gpmc/ram_to_fifo.v
new file mode 100644
index 000000000..8549dcc35
--- /dev/null
+++ b/fpga/usrp2/gpmc/ram_to_fifo.v
@@ -0,0 +1,46 @@
+
+
+module ram_to_fifo
+  (input clk, input reset,
+   input [10:0] read_length,  // From the dbsm (?)
+   output read_en, output reg [8:0] read_addr, input [31:0] read_data, input read_ready, output read_done,
+   output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
+
+   // read_length/2 = number of 32 bit lines, numbered 0 through read_length/2-1
+   wire [8:0] 	 last_line = (read_length[10:1]-1); 
+
+   reg 		 read_phase, sop;
+
+   assign read_en = (read_phase == 0) | dst_rdy_i;
+   assign src_rdy_o = (read_phase == 1);
+   
+   always @(posedge clk)
+     if(reset)
+       begin
+	  read_addr <= 0;
+	  read_phase <= 0;
+	  sop <= 1;
+       end
+     else
+       if(read_phase == 0)
+	 begin
+	    read_addr <= read_ready;
+	    read_phase <= read_ready;
+	 end
+       else if(dst_rdy_i)
+	 begin
+	    sop <= 0;
+	    if(read_addr == last_line)
+	      begin
+		 read_addr <= 0;
+		 read_phase <= 0;
+	      end
+	    else
+	      read_addr <= read_addr + 1;
+	 end
+   
+   assign read_done = (read_phase == 1) & (read_addr == last_line) & dst_rdy_i;
+   wire eop = (read_addr == last_line);
+   assign data_o = { 2'b00, eop, sop, read_data };
+   
+endmodule // ram_to_fifo
diff --git a/fpga/usrp2/gpmc/single_data_read.txt b/fpga/usrp2/gpmc/single_data_read.txt
new file mode 100644
index 000000000..1dc0e3a78
--- /dev/null
+++ b/fpga/usrp2/gpmc/single_data_read.txt
@@ -0,0 +1,12 @@
+# OMAP writes to FPGA
+# initialize the signals
+CLK=0,nWE=1,nCS=1,nOE=1,DATA=Z.
+CLK=1.
+CLK=0,nOE=0,nCS=0,DATA=RD_DATA.
+CLK=1.
+CLK=0.
+CLK=1.
+CLK=0,nOE=1,nCS=1,DATA=Z.
+CLK=1.
+
+
diff --git a/fpga/usrp2/gpmc/single_data_write.txt b/fpga/usrp2/gpmc/single_data_write.txt
new file mode 100644
index 000000000..287e3e2c1
--- /dev/null
+++ b/fpga/usrp2/gpmc/single_data_write.txt
@@ -0,0 +1,10 @@
+# OMAP writes to FPGA
+# initialize the signals
+CLK=0,nWE=1,nCS=1,nOE=1,DATA=Z.
+CLK=1.
+CLK=0,nWE=0,nCS=0,DATA=WR_DATA.
+CLK=1.
+CLK=0,nWE=1,nCS=1,DATA=Z.
+CLK=1.
+
+
diff --git a/fpga/usrp2/models/gpmc_model_async.v b/fpga/usrp2/models/gpmc_model_async.v
new file mode 100644
index 000000000..beeaee028
--- /dev/null
+++ b/fpga/usrp2/models/gpmc_model_async.v
@@ -0,0 +1,130 @@
+`timescale 1ps/1ps
+
+module gpmc_model_async
+  (output EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE,
+   output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, 
+   output reg EM_NWE, output reg EM_NOE );
+
+   assign EM_CLK = 0;
+   reg [15:0] EM_D_int;
+   assign EM_D = EM_D_int;
+   
+   initial
+     begin
+	EM_A <= 10'bz;
+	EM_NBE <= 2'b11;
+	EM_NWE <= 1;
+	EM_NOE <= 1;
+	EM_NCS4 <= 1;
+	EM_NCS6 <= 1;
+	EM_D_int <= 16'bz;
+ 	EM_WAIT0 <= 0;  // FIXME this is actually an input
+     end
+   
+   task GPMC_Write;
+      input ctrl;
+      input [10:0] addr;
+      input [15:0] data;
+      begin
+	 #23000;
+	 EM_A <= addr[10:1];
+	 EM_D_int <= data;
+	 #20100;
+	 if(ctrl)
+	   EM_NCS6 <= 0;
+	 else
+	   EM_NCS4 <= 0;
+	 #14000;
+	 EM_NWE <= 0;
+	 #77500;
+	 EM_NCS4 <= 1;
+	 EM_NCS6 <= 1;
+	 //#1.5;
+	 EM_NWE <= 1;
+	 #60000;
+	 EM_A <= 10'bz;
+	 EM_D_int <= 16'bz;
+      end
+   endtask // GPMC_Write
+
+   task GPMC_Read;
+      input ctrl;
+      input [10:0] addr;
+      begin
+	 #13000;
+	 EM_A <= addr[10:1];
+	 #3000;
+	 if(ctrl)
+	   EM_NCS6 <= 0;
+	 else
+	   EM_NCS4 <= 0;
+	 #14000;
+	 EM_NOE <= 0;
+	 #77500;
+	 EM_NCS4 <= 1;
+	 EM_NCS6 <= 1;
+	 //#1.5;
+	 $display("Data Read from GPMC: %X",EM_D);
+	 EM_NOE <= 1;
+	 #254000;
+	 EM_A <= 10'bz;
+      end
+   endtask // GPMC_Read
+   
+   initial
+     begin
+	#1000000;
+	GPMC_Write(1,36,16'hF00D);
+	#1000000;
+	GPMC_Read(1,36);
+	#1000000;
+	GPMC_Write(0,0,16'h1234);
+	GPMC_Write(0,0,16'h5678);
+	GPMC_Write(0,0,16'h9abc);
+	GPMC_Write(0,0,16'hF00D);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	#1000000;
+	GPMC_Write(0,0,16'h1234);
+	GPMC_Write(0,0,16'h5678);
+	GPMC_Write(0,0,16'h9abc);
+	GPMC_Write(0,0,16'hF00D);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'hDEAD);
+	GPMC_Write(0,0,16'h9876);
+	#1000000;
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	#1000000;
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	GPMC_Read(0,0);
+	#1000000;
+	GPMC_Read(0,0);
+	#100000000;
+	$finish;
+     end
+   
+endmodule // gpmc_model_async
diff --git a/fpga/usrp2/models/gpmc_model_sync.v b/fpga/usrp2/models/gpmc_model_sync.v
new file mode 100644
index 000000000..641720c15
--- /dev/null
+++ b/fpga/usrp2/models/gpmc_model_sync.v
@@ -0,0 +1,97 @@
+
+
+module gpmc_model_sync
+  (output reg EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE,
+   output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, 
+   output reg EM_NWE, output reg EM_NOE );
+
+   reg [15:0] EM_D_int;
+   assign EM_D = EM_D_int;
+
+   initial
+     begin
+	EM_CLK <= 0;
+	EM_A <= 10'bz;
+	EM_NBE <= 2'b11;
+	EM_NWE <= 1;
+	EM_NOE <= 1;
+	EM_NCS4 <= 1;
+	EM_NCS6 <= 1;
+	EM_D_int <= 16'bz;
+ 	EM_WAIT0 <= 0;  // FIXME this is actually an input
+     end
+   
+   task GPMC_Write;
+      input ctrl;
+      input [10:0] addr;
+      input [15:0] data;
+      begin
+	 EM_CLK <= 1;
+	 #10;
+	 EM_CLK <= 0;
+	 EM_NWE <= 0;
+	 if(ctrl)
+	   EM_NCS6 <= 0;
+	 else
+	   EM_NCS4 <= 0;
+	 EM_A <= addr[10:1];
+	 EM_D_int <= data;
+	 #10;
+	 EM_CLK <= 1;
+	 #10;
+	 EM_CLK <= 0;
+	 EM_NWE <= 1;
+	 EM_NCS4 <= 1;
+	 EM_NCS6 <= 1;
+	 EM_A <= 10'bz;
+	 EM_D_int <= 16'bz;
+	 #100;
+      end
+   endtask // GPMC_Write
+
+   task GPMC_Read;
+      input ctrl;
+      input [10:0] addr;
+      begin
+	 #1.3;
+	 EM_A <= addr[10:1];
+	 #3;
+	 if(ctrl)
+	   EM_NCS6 <= 0;
+	 else
+	   EM_NCS4 <= 0;
+	 #14;
+	 EM_NOE <= 0;
+	 #77.5;
+	 EM_NCS4 <= 1;
+	 EM_NCS6 <= 1;
+	 //#1.5;
+	 $display("Data Read from GPMC: %X",EM_D);
+	 EM_NOE <= 1;
+	 #254;
+	 EM_A <= 10'bz;
+      end
+   endtask // GPMC_Read
+   
+   initial
+     begin
+	#1000;
+	GPMC_Write(1,36,16'hF00D);
+	#1000;
+	GPMC_Read(1,36);
+	#1000;
+	GPMC_Write(0,36,16'h1234);
+	GPMC_Write(0,38,16'h5678);
+	GPMC_Write(0,40,16'h9abc);
+	GPMC_Write(0,11'h2F4,16'hF00D);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	GPMC_Write(0,11'h7FE,16'hDEAD);
+	#100000;
+	$finish;
+     end
+   
+endmodule // gpmc_model
diff --git a/fpga/usrp2/opencores/Makefile.srcs b/fpga/usrp2/opencores/Makefile.srcs
index 30360a17d..1ccecf337 100644
--- a/fpga/usrp2/opencores/Makefile.srcs
+++ b/fpga/usrp2/opencores/Makefile.srcs
@@ -23,6 +23,5 @@ i2c/rtl/verilog/timescale.v \
 spi/rtl/verilog/spi_clgen.v \
 spi/rtl/verilog/spi_defines.v \
 spi/rtl/verilog/spi_shift.v \
-spi/rtl/verilog/spi_top.v \
-spi/rtl/verilog/timescale.v \
+spi/rtl/verilog/spi_top16.v \
 ))
diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
index 7bc4f6e5e..2d9c34f40 100644
--- a/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
+++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
@@ -39,12 +39,9 @@
 //////////////////////////////////////////////////////////////////////
 
 `include "spi_defines.v"
-`include "timescale.v"
 
 module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge); 
 
-  parameter Tp = 1;
-  
   input                            clk_in;   // input clock (system clock)
   input                            rst;      // reset
   input                            enable;   // clock enable
@@ -68,40 +65,40 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge,
   assign cnt_one  = cnt == {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
   
   // Counter counts half period
-  always @(posedge clk_in or posedge rst)
+  always @(posedge clk_in)
   begin
     if(rst)
-      cnt <= #Tp {`SPI_DIVIDER_LEN{1'b1}};
+      cnt <= {`SPI_DIVIDER_LEN{1'b1}};
     else
       begin
         if(!enable || cnt_zero)
-          cnt <= #Tp divider;
+          cnt <= divider;
         else
-          cnt <= #Tp cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
+          cnt <= cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
       end
   end
   
   // clk_out is asserted every other half period
-  always @(posedge clk_in or posedge rst)
+  always @(posedge clk_in)
   begin
     if(rst)
-      clk_out <= #Tp 1'b0;
+      clk_out <= 1'b0;
     else
-      clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
+      clk_out <= (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
   end
    
   // Pos and neg edge signals
-  always @(posedge clk_in or posedge rst)
+  always @(posedge clk_in)
   begin
     if(rst)
       begin
-        pos_edge  <= #Tp 1'b0;
-        neg_edge  <= #Tp 1'b0;
+        pos_edge  <= 1'b0;
+        neg_edge  <= 1'b0;
       end
     else
       begin
-        pos_edge  <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
-        neg_edge  <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
+        pos_edge  <= (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
+        neg_edge  <= (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
       end
   end
 endmodule
diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v
index a6925918e..963a680a8 100644
--- a/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v
+++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v
@@ -43,8 +43,8 @@
 // low frequency of system clock this can be reduced.
 // Use SPI_DIVIDER_LEN for fine tuning theexact number.
 //
-//`define SPI_DIVIDER_LEN_8
-`define SPI_DIVIDER_LEN_16
+`define SPI_DIVIDER_LEN_8
+//`define SPI_DIVIDER_LEN_16
 //`define SPI_DIVIDER_LEN_24
 //`define SPI_DIVIDER_LEN_32
 
@@ -66,9 +66,9 @@
 // Use SPI_MAX_CHAR for fine tuning the exact number, when using
 // SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8.
 //
-`define SPI_MAX_CHAR_128
+//`define SPI_MAX_CHAR_128
 //`define SPI_MAX_CHAR_64
-//`define SPI_MAX_CHAR_32
+`define SPI_MAX_CHAR_32
 //`define SPI_MAX_CHAR_24
 //`define SPI_MAX_CHAR_16
 //`define SPI_MAX_CHAR_8
@@ -137,7 +137,7 @@
 `define SPI_TX_2                2
 `define SPI_TX_3                3
 `define SPI_CTRL                4
-`define SPI_DEVIDE              5
+`define SPI_DIVIDE              5
 `define SPI_SS                  6
 
 //
diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v
index b17ac8b1f..ac3bb3f48 100644
--- a/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v
+++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v
@@ -39,15 +39,12 @@
 //////////////////////////////////////////////////////////////////////
 
 `include "spi_defines.v"
-`include "timescale.v"
 
 module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
                   pos_edge, neg_edge, rx_negedge, tx_negedge,
                   tip, last, 
                   p_in, p_out, s_clk, s_in, s_out);
 
-  parameter Tp = 1;
-  
   input                          clk;          // system clock
   input                          rst;          // reset
   input                    [3:0] latch;        // latch signal for storing the data in shift register
@@ -89,149 +86,149 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
   assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
   
   // Character bit counter
-  always @(posedge clk or posedge rst)
+  always @(posedge clk)
   begin
     if(rst)
-      cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}};
+      cnt <= {`SPI_CHAR_LEN_BITS+1{1'b0}};
     else
       begin
         if(tip)
-          cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
+          cnt <= pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
         else
-          cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
+          cnt <= !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
       end
   end
   
   // Transfer in progress
-  always @(posedge clk or posedge rst)
+  always @(posedge clk)
   begin
     if(rst)
-      tip <= #Tp 1'b0;
+      tip <= 1'b0;
   else if(go && ~tip)
-    tip <= #Tp 1'b1;
+    tip <= 1'b1;
   else if(tip && last && pos_edge)
-    tip <= #Tp 1'b0;
+    tip <= 1'b0;
   end
   
   // Sending bits to the line
-  always @(posedge clk or posedge rst)
+  always @(posedge clk)
   begin
     if (rst)
-      s_out   <= #Tp 1'b0;
+      s_out   <= 1'b0;
     else
-      s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
+      s_out <= (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
   end
   
   // Receiving bits from the line
-  always @(posedge clk or posedge rst)
+  always @(posedge clk)
   begin
     if (rst)
-      data   <= #Tp {`SPI_MAX_CHAR{1'b0}};
+      data   <= {`SPI_MAX_CHAR{1'b0}};
 `ifdef SPI_MAX_CHAR_128
     else if (latch[0] && !tip)
       begin
         if (byte_sel[3])
-          data[31:24] <= #Tp p_in[31:24];
+          data[31:24] <= p_in[31:24];
         if (byte_sel[2])
-          data[23:16] <= #Tp p_in[23:16];
+          data[23:16] <= p_in[23:16];
         if (byte_sel[1])
-          data[15:8] <= #Tp p_in[15:8];
+          data[15:8] <= p_in[15:8];
         if (byte_sel[0])
-          data[7:0] <= #Tp p_in[7:0];
+          data[7:0] <= p_in[7:0];
       end
     else if (latch[1] && !tip)
       begin
         if (byte_sel[3])
-          data[63:56] <= #Tp p_in[31:24];
+          data[63:56] <= p_in[31:24];
         if (byte_sel[2])
-          data[55:48] <= #Tp p_in[23:16];
+          data[55:48] <= p_in[23:16];
         if (byte_sel[1])
-          data[47:40] <= #Tp p_in[15:8];
+          data[47:40] <= p_in[15:8];
         if (byte_sel[0])
-          data[39:32] <= #Tp p_in[7:0];
+          data[39:32] <= p_in[7:0];
       end
     else if (latch[2] && !tip)
       begin
         if (byte_sel[3])
-          data[95:88] <= #Tp p_in[31:24];
+          data[95:88] <= p_in[31:24];
         if (byte_sel[2])
-          data[87:80] <= #Tp p_in[23:16];
+          data[87:80] <= p_in[23:16];
         if (byte_sel[1])
-          data[79:72] <= #Tp p_in[15:8];
+          data[79:72] <= p_in[15:8];
         if (byte_sel[0])
-          data[71:64] <= #Tp p_in[7:0];
+          data[71:64] <= p_in[7:0];
       end
     else if (latch[3] && !tip)
       begin
         if (byte_sel[3])
-          data[127:120] <= #Tp p_in[31:24];
+          data[127:120] <= p_in[31:24];
         if (byte_sel[2])
-          data[119:112] <= #Tp p_in[23:16];
+          data[119:112] <= p_in[23:16];
         if (byte_sel[1])
-          data[111:104] <= #Tp p_in[15:8];
+          data[111:104] <= p_in[15:8];
         if (byte_sel[0])
-          data[103:96] <= #Tp p_in[7:0];
+          data[103:96] <= p_in[7:0];
       end
 `else
 `ifdef SPI_MAX_CHAR_64
     else if (latch[0] && !tip)
       begin
         if (byte_sel[3])
-          data[31:24] <= #Tp p_in[31:24];
+          data[31:24] <= p_in[31:24];
         if (byte_sel[2])
-          data[23:16] <= #Tp p_in[23:16];
+          data[23:16] <= p_in[23:16];
         if (byte_sel[1])
-          data[15:8] <= #Tp p_in[15:8];
+          data[15:8] <= p_in[15:8];
         if (byte_sel[0])
-          data[7:0] <= #Tp p_in[7:0];
+          data[7:0] <= p_in[7:0];
       end
     else if (latch[1] && !tip)
       begin
         if (byte_sel[3])
-          data[63:56] <= #Tp p_in[31:24];
+          data[63:56] <= p_in[31:24];
         if (byte_sel[2])
-          data[55:48] <= #Tp p_in[23:16];
+          data[55:48] <= p_in[23:16];
         if (byte_sel[1])
-          data[47:40] <= #Tp p_in[15:8];
+          data[47:40] <= p_in[15:8];
         if (byte_sel[0])
-          data[39:32] <= #Tp p_in[7:0];
+          data[39:32] <= p_in[7:0];
       end
 `else
     else if (latch[0] && !tip)
       begin
       `ifdef SPI_MAX_CHAR_8
         if (byte_sel[0])
-          data[`SPI_MAX_CHAR-1:0] <= #Tp p_in[`SPI_MAX_CHAR-1:0];
+          data[`SPI_MAX_CHAR-1:0] <= p_in[`SPI_MAX_CHAR-1:0];
       `endif
       `ifdef SPI_MAX_CHAR_16
         if (byte_sel[0])
-          data[7:0] <= #Tp p_in[7:0];
+          data[7:0] <= p_in[7:0];
         if (byte_sel[1])
-          data[`SPI_MAX_CHAR-1:8] <= #Tp p_in[`SPI_MAX_CHAR-1:8];
+          data[`SPI_MAX_CHAR-1:8] <= p_in[`SPI_MAX_CHAR-1:8];
       `endif
       `ifdef SPI_MAX_CHAR_24
         if (byte_sel[0])
-          data[7:0] <= #Tp p_in[7:0];
+          data[7:0] <= p_in[7:0];
         if (byte_sel[1])
-          data[15:8] <= #Tp p_in[15:8];
+          data[15:8] <= p_in[15:8];
         if (byte_sel[2])
-          data[`SPI_MAX_CHAR-1:16] <= #Tp p_in[`SPI_MAX_CHAR-1:16];
+          data[`SPI_MAX_CHAR-1:16] <= p_in[`SPI_MAX_CHAR-1:16];
       `endif
       `ifdef SPI_MAX_CHAR_32
         if (byte_sel[0])
-          data[7:0] <= #Tp p_in[7:0];
+          data[7:0] <= p_in[7:0];
         if (byte_sel[1])
-          data[15:8] <= #Tp p_in[15:8];
+          data[15:8] <= p_in[15:8];
         if (byte_sel[2])
-          data[23:16] <= #Tp p_in[23:16];
+          data[23:16] <= p_in[23:16];
         if (byte_sel[3])
-          data[`SPI_MAX_CHAR-1:24] <= #Tp p_in[`SPI_MAX_CHAR-1:24];
+          data[`SPI_MAX_CHAR-1:24] <= p_in[`SPI_MAX_CHAR-1:24];
       `endif
       end
 `endif
 `endif
     else
-      data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
+      data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
   end
   
 endmodule
diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v
index 09b2e50e1..8289449a9 100644
--- a/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v
+++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v
@@ -1,3 +1,6 @@
+
+// Modified 2010 by Matt Ettus to remove old verilog style
+
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 ////  spi_top.v                                                   ////
@@ -40,7 +43,6 @@
 
 
 `include "spi_defines.v"
-`include "timescale.v"
 
 module spi_top
 (
@@ -52,8 +54,6 @@ module spi_top
   ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i
 );
 
-  parameter Tp = 1;
-
   // Wishbone signals
   input                            wb_clk_i;         // master clock input
   input                            wb_rst_i;         // synchronous active high reset
@@ -101,7 +101,7 @@ module spi_top
   wire                             last_bit;         // marks last character bit
   
   // Address decoder
-  assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DEVIDE);
+  assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DIVIDE);
   assign spi_ctrl_sel    = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL);
   assign spi_tx_sel[0]   = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0);
   assign spi_tx_sel[1]   = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_1);
@@ -132,96 +132,96 @@ module spi_top
 `endif
 `endif
       `SPI_CTRL:    wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl};
-      `SPI_DEVIDE:  wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider};
+      `SPI_DIVIDE:  wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider};
       `SPI_SS:      wb_dat = {{32-`SPI_SS_NB{1'b0}}, ss};
       default:      wb_dat = 32'bx;
     endcase
   end
   
   // Wb data out
-  always @(posedge wb_clk_i or posedge wb_rst_i)
+  always @(posedge wb_clk_i)
   begin
     if (wb_rst_i)
-      wb_dat_o <= #Tp 32'b0;
+      wb_dat_o <= 32'b0;
     else
-      wb_dat_o <= #Tp wb_dat;
+      wb_dat_o <= wb_dat;
   end
   
   // Wb acknowledge
-  always @(posedge wb_clk_i or posedge wb_rst_i)
+  always @(posedge wb_clk_i)
   begin
     if (wb_rst_i)
-      wb_ack_o <= #Tp 1'b0;
+      wb_ack_o <= 1'b0;
     else
-      wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o;
+      wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o;
   end
   
   // Wb error
   assign wb_err_o = 1'b0;
   
   // Interrupt
-  always @(posedge wb_clk_i or posedge wb_rst_i)
+  always @(posedge wb_clk_i)
   begin
     if (wb_rst_i)
-      wb_int_o <= #Tp 1'b0;
+      wb_int_o <= 1'b0;
     else if (ie && tip && last_bit && pos_edge)
-      wb_int_o <= #Tp 1'b1;
+      wb_int_o <= 1'b1;
     else if (wb_ack_o)
-      wb_int_o <= #Tp 1'b0;
+      wb_int_o <= 1'b0;
   end
   
   // Divider register
-  always @(posedge wb_clk_i or posedge wb_rst_i)
+  always @(posedge wb_clk_i)
   begin
     if (wb_rst_i)
-        divider <= #Tp {`SPI_DIVIDER_LEN{1'b0}};
+        divider <= {`SPI_DIVIDER_LEN{1'b0}};
     else if (spi_divider_sel && wb_we_i && !tip)
       begin
       `ifdef SPI_DIVIDER_LEN_8
         if (wb_sel_i[0])
-          divider <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:0];
+          divider <= wb_dat_i[`SPI_DIVIDER_LEN-1:0];
       `endif
       `ifdef SPI_DIVIDER_LEN_16
         if (wb_sel_i[0])
-          divider[7:0] <= #Tp wb_dat_i[7:0];
+          divider[7:0] <= wb_dat_i[7:0];
         if (wb_sel_i[1])
-          divider[`SPI_DIVIDER_LEN-1:8] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:8];
+          divider[`SPI_DIVIDER_LEN-1:8] <= wb_dat_i[`SPI_DIVIDER_LEN-1:8];
       `endif
       `ifdef SPI_DIVIDER_LEN_24
         if (wb_sel_i[0])
-          divider[7:0] <= #Tp wb_dat_i[7:0];
+          divider[7:0] <= wb_dat_i[7:0];
         if (wb_sel_i[1])
-          divider[15:8] <= #Tp wb_dat_i[15:8];
+          divider[15:8] <= wb_dat_i[15:8];
         if (wb_sel_i[2])
-          divider[`SPI_DIVIDER_LEN-1:16] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:16];
+          divider[`SPI_DIVIDER_LEN-1:16] <= wb_dat_i[`SPI_DIVIDER_LEN-1:16];
       `endif
       `ifdef SPI_DIVIDER_LEN_32
         if (wb_sel_i[0])
-          divider[7:0] <= #Tp wb_dat_i[7:0];
+          divider[7:0] <= wb_dat_i[7:0];
         if (wb_sel_i[1])
-          divider[15:8] <= #Tp wb_dat_i[15:8];
+          divider[15:8] <= wb_dat_i[15:8];
         if (wb_sel_i[2])
-          divider[23:16] <= #Tp wb_dat_i[23:16];
+          divider[23:16] <= wb_dat_i[23:16];
         if (wb_sel_i[3])
-          divider[`SPI_DIVIDER_LEN-1:24] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:24];
+          divider[`SPI_DIVIDER_LEN-1:24] <= wb_dat_i[`SPI_DIVIDER_LEN-1:24];
       `endif
       end
   end
   
   // Ctrl register
-  always @(posedge wb_clk_i or posedge wb_rst_i)
+  always @(posedge wb_clk_i)
   begin
     if (wb_rst_i)
-      ctrl <= #Tp {`SPI_CTRL_BIT_NB{1'b0}};
+      ctrl <= {`SPI_CTRL_BIT_NB{1'b0}};
     else if(spi_ctrl_sel && wb_we_i && !tip)
       begin
         if (wb_sel_i[0])
-          ctrl[7:0] <= #Tp wb_dat_i[7:0] | {7'b0, ctrl[0]};
+          ctrl[7:0] <= wb_dat_i[7:0] | {7'b0, ctrl[0]};
         if (wb_sel_i[1])
-          ctrl[`SPI_CTRL_BIT_NB-1:8] <= #Tp wb_dat_i[`SPI_CTRL_BIT_NB-1:8];
+          ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8];
       end
     else if(tip && last_bit && pos_edge)
-      ctrl[`SPI_CTRL_GO] <= #Tp 1'b0;
+      ctrl[`SPI_CTRL_GO] <= 1'b0;
   end
   
   assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];
@@ -233,39 +233,39 @@ module spi_top
   assign ass        = ctrl[`SPI_CTRL_ASS];
   
   // Slave select register
-  always @(posedge wb_clk_i or posedge wb_rst_i)
+  always @(posedge wb_clk_i)
   begin
     if (wb_rst_i)
-      ss <= #Tp {`SPI_SS_NB{1'b0}};
+      ss <= {`SPI_SS_NB{1'b0}};
     else if(spi_ss_sel && wb_we_i && !tip)
       begin
       `ifdef SPI_SS_NB_8
         if (wb_sel_i[0])
-          ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0];
+          ss <= wb_dat_i[`SPI_SS_NB-1:0];
       `endif
       `ifdef SPI_SS_NB_16
         if (wb_sel_i[0])
-          ss[7:0] <= #Tp wb_dat_i[7:0];
+          ss[7:0] <= wb_dat_i[7:0];
         if (wb_sel_i[1])
-          ss[`SPI_SS_NB-1:8] <= #Tp wb_dat_i[`SPI_SS_NB-1:8];
+          ss[`SPI_SS_NB-1:8] <= wb_dat_i[`SPI_SS_NB-1:8];
       `endif
       `ifdef SPI_SS_NB_24
         if (wb_sel_i[0])
-          ss[7:0] <= #Tp wb_dat_i[7:0];
+          ss[7:0] <= wb_dat_i[7:0];
         if (wb_sel_i[1])
-          ss[15:8] <= #Tp wb_dat_i[15:8];
+          ss[15:8] <= wb_dat_i[15:8];
         if (wb_sel_i[2])
-          ss[`SPI_SS_NB-1:16] <= #Tp wb_dat_i[`SPI_SS_NB-1:16];
+          ss[`SPI_SS_NB-1:16] <= wb_dat_i[`SPI_SS_NB-1:16];
       `endif
       `ifdef SPI_SS_NB_32
         if (wb_sel_i[0])
-          ss[7:0] <= #Tp wb_dat_i[7:0];
+          ss[7:0] <= wb_dat_i[7:0];
         if (wb_sel_i[1])
-          ss[15:8] <= #Tp wb_dat_i[15:8];
+          ss[15:8] <= wb_dat_i[15:8];
         if (wb_sel_i[2])
-          ss[23:16] <= #Tp wb_dat_i[23:16];
+          ss[23:16] <= wb_dat_i[23:16];
         if (wb_sel_i[3])
-          ss[`SPI_SS_NB-1:24] <= #Tp wb_dat_i[`SPI_SS_NB-1:24];
+          ss[`SPI_SS_NB-1:24] <= wb_dat_i[`SPI_SS_NB-1:24];
       `endif
       end
   end
diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v
new file mode 100644
index 000000000..ee808a8ab
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_top16.v
@@ -0,0 +1,182 @@
+
+// Modified 2010 by Matt Ettus to remove old verilog style and
+// allow 16-bit operation
+
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  spi_top.v                                                   ////
+////                                                              ////
+////  This file is part of the SPI IP core project                ////
+////  http://www.opencores.org/projects/spi/                      ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Simon Srot (simons@opencores.org)                     ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+
+`include "spi_defines.v"
+
+module spi_top16
+  (input wb_clk_i, input wb_rst_i, 
+   input [4:0] wb_adr_i, 
+   input [15:0] wb_dat_i, 
+   output reg [15:0] wb_dat_o, 
+   input [1:0] wb_sel_i,
+   input wb_we_i, input wb_stb_i, input wb_cyc_i, 
+   output reg wb_ack_o, output wb_err_o, output reg wb_int_o,
+   
+   // SPI signals
+   output [15:0] ss_pad_o, output sclk_pad_o, output mosi_pad_o, input miso_pad_i);
+   
+   // Internal signals
+   reg [15:0] divider;          // Divider register
+   reg [`SPI_CTRL_BIT_NB-1:0] ctrl;             // Control and status register
+   reg [15:0] 		      ss;               // Slave select register
+   reg [31:0] 		      wb_dat;           // wb data out
+   wire [31:0] 		      rx;               // Rx register
+   wire 		      rx_negedge;       // miso is sampled on negative edge
+   wire 		      tx_negedge;       // mosi is driven on negative edge
+   wire [`SPI_CHAR_LEN_BITS-1:0] char_len;         // char len
+   wire 			 go;               // go
+   wire 			 lsb;              // lsb first on line
+   wire 			 ie;               // interrupt enable
+   wire 			 ass;              // automatic slave select
+   wire 			 spi_divider_sel;  // divider register select
+   wire 			 spi_ctrl_sel;     // ctrl register select
+   wire [3:0] 			 spi_tx_sel;       // tx_l register select
+   wire 			 spi_ss_sel;       // ss register select
+   wire 			 tip;              // transfer in progress
+   wire 			 pos_edge;         // recognize posedge of sclk
+   wire 			 neg_edge;         // recognize negedge of sclk
+   wire 			 last_bit;         // marks last character bit
+   
+   // Address decoder
+   assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_DIVIDE);
+   assign spi_ctrl_sel    = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_CTRL);
+   assign spi_tx_sel[0]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_0);
+   assign spi_tx_sel[1]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_1);
+   assign spi_tx_sel[2]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_2);
+   assign spi_tx_sel[3]   = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_3);
+   assign spi_ss_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_SS);
+   
+   always @(wb_adr_i or rx or ctrl or divider or ss)
+     case (wb_adr_i[4:2])   
+       `SPI_RX_0:    wb_dat = rx[31:0];
+       `SPI_CTRL:    wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl};
+       `SPI_DIVIDE:  wb_dat = {16'b0, divider};
+       `SPI_SS:      wb_dat = {16'b0, ss};
+       default : wb_dat = 32'd0;
+     endcase // case (wb_adr_i[4:2])
+   
+   always @(posedge wb_clk_i)
+     if (wb_rst_i)
+       wb_dat_o <= 32'b0;
+     else
+       wb_dat_o <= wb_adr_i[1] ? wb_dat[31:16] : wb_dat[15:0];
+   
+   always @(posedge wb_clk_i)
+     if (wb_rst_i)
+       wb_ack_o <= 1'b0;
+     else
+       wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o;
+   
+   assign wb_err_o = 1'b0;
+   
+   // Interrupt
+   always @(posedge wb_clk_i)
+     if (wb_rst_i)
+       wb_int_o <= 1'b0;
+     else if (ie && tip && last_bit && pos_edge)
+       wb_int_o <= 1'b1;
+     else if (wb_ack_o)
+       wb_int_o <= 1'b0;
+   
+   // Divider register
+   always @(posedge wb_clk_i)
+     if (wb_rst_i)
+       divider <= 16'b0;
+     else if (spi_divider_sel && wb_we_i && !tip && ~wb_adr_i[1])
+       divider <= wb_dat_i;
+   
+   // Ctrl register
+   always @(posedge wb_clk_i)
+     if (wb_rst_i)
+       ctrl <= {`SPI_CTRL_BIT_NB{1'b0}};
+     else if(spi_ctrl_sel && wb_we_i && !tip && ~wb_adr_i[1])
+       begin
+          if (wb_sel_i[0])
+            ctrl[7:0] <= wb_dat_i[7:0] | {7'b0, ctrl[0]};
+          if (wb_sel_i[1])
+            ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8];
+       end
+     else if(tip && last_bit && pos_edge)
+       ctrl[`SPI_CTRL_GO] <= 1'b0;
+   
+   assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];
+   assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE];
+   assign go         = ctrl[`SPI_CTRL_GO];
+   assign char_len   = ctrl[`SPI_CTRL_CHAR_LEN];
+   assign lsb        = ctrl[`SPI_CTRL_LSB];
+   assign ie         = ctrl[`SPI_CTRL_IE];
+   assign ass        = ctrl[`SPI_CTRL_ASS];
+   
+   // Slave select register
+   always @(posedge wb_clk_i)
+     if (wb_rst_i)
+       ss <= 16'b0;
+     else if(spi_ss_sel && wb_we_i && !tip & ~wb_adr_i[1])
+       begin
+          if (wb_sel_i[0])
+            ss[7:0] <= wb_dat_i[7:0];
+          if (wb_sel_i[1])
+            ss[15:8] <= wb_dat_i[15:8];
+       end
+   
+   assign ss_pad_o = ~((ss & {16{tip & ass}}) | (ss & {16{!ass}}));
+   
+   spi_clgen clgen (.clk_in(wb_clk_i), .rst(wb_rst_i), .go(go), .enable(tip), .last_clk(last_bit),
+                    .divider(divider[`SPI_DIVIDER_LEN-1:0]), .clk_out(sclk_pad_o), .pos_edge(pos_edge), 
+                    .neg_edge(neg_edge));
+
+   wire [3:0] new_sels = { (wb_adr_i[1] & wb_sel_i[1]), (wb_adr_i[1] & wb_sel_i[0]), 
+			   (~wb_adr_i[1] & wb_sel_i[1]), (~wb_adr_i[1] & wb_sel_i[0]) };
+   
+   
+   spi_shift shift (.clk(wb_clk_i), .rst(wb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
+                    .latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(new_sels), .lsb(lsb), 
+                    .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge), 
+                    .rx_negedge(rx_negedge), .tx_negedge(tx_negedge),
+                    .tip(tip), .last(last_bit), 
+                    .p_in({wb_dat_i,wb_dat_i}), .p_out(rx), 
+                    .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o));
+
+endmodule // spi_top16
diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/timescale.v b/fpga/usrp2/opencores/spi/rtl/verilog/timescale.v
deleted file mode 100644
index 60d4ecbd1..000000000
--- a/fpga/usrp2/opencores/spi/rtl/verilog/timescale.v
+++ /dev/null
@@ -1,2 +0,0 @@
-`timescale 1ns / 10ps
-
diff --git a/fpga/usrp2/top/.gitignore b/fpga/usrp2/top/.gitignore
index bf1b77066..0d90f1698 100644
--- a/fpga/usrp2/top/.gitignore
+++ b/fpga/usrp2/top/.gitignore
@@ -1 +1,2 @@
 /*.sav
+build*
diff --git a/fpga/usrp2/top/u1e/.gitignore b/fpga/usrp2/top/u1e/.gitignore
new file mode 100644
index 000000000..8d872713e
--- /dev/null
+++ b/fpga/usrp2/top/u1e/.gitignore
@@ -0,0 +1,6 @@
+*~
+build
+*.log
+*.cmd
+tb_u1e
+*.lxt
diff --git a/fpga/usrp2/top/u1e/Makefile b/fpga/usrp2/top/u1e/Makefile
new file mode 100644
index 000000000..3cb9fd8f3
--- /dev/null
+++ b/fpga/usrp2/top/u1e/Makefile
@@ -0,0 +1,101 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE = u1e
+BUILD_DIR = $(abspath build$(ISE))
+
+##################################################
+# Include other makefiles
+##################################################
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../extram/Makefile.srcs
+include ../../gpmc/Makefile.srcs
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd1800a \
+package cs484 \
+speed -4 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+u1e_core.v \
+u1e.v \
+u1e.ucf \
+timing.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(GPMC_SRCS)
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High 
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 \
+"Unused IOB Pins" "Pull Up"
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp2/top/u1e/README b/fpga/usrp2/top/u1e/README
new file mode 100644
index 000000000..14c7a4955
--- /dev/null
+++ b/fpga/usrp2/top/u1e/README
@@ -0,0 +1,4 @@
+
+make clean
+make sim
+./tb_u1e -lxt2
diff --git a/fpga/usrp2/top/u1e/cmdfile b/fpga/usrp2/top/u1e/cmdfile
new file mode 100644
index 000000000..291c723b8
--- /dev/null
+++ b/fpga/usrp2/top/u1e/cmdfile
@@ -0,0 +1,20 @@
+
+# My stuff
+-y .
+-y ../../control_lib
+-y ../../control_lib/newfifo
+-y ../../sdr_lib
+-y ../../timing
+-y ../../coregen
+-y ../../gpmc
+
+# Models
+-y ../../models
+-y /opt/Xilinx/10.1/ISE/verilog/src/unisims
+
+# Open Cores
+-y ../../opencores/spi/rtl/verilog
++incdir+../../opencores/spi/rtl/verilog
+-y ../../opencores/i2c/rtl/verilog
++incdir+../../opencores/i2c/rtl/verilog
+
diff --git a/fpga/usrp2/top/u1e/make.sim b/fpga/usrp2/top/u1e/make.sim
new file mode 100644
index 000000000..1c163884c
--- /dev/null
+++ b/fpga/usrp2/top/u1e/make.sim
@@ -0,0 +1,7 @@
+all: sim
+
+sim:	
+	iverilog -Wimplicit -Wportbind -c cmdfile tb_u1e.v -o tb_u1e
+
+clean:
+	rm -f tb_u1e *.vcd *.lxt a.out
diff --git a/fpga/usrp2/top/u1e/tb_u1e.v b/fpga/usrp2/top/u1e/tb_u1e.v
new file mode 100644
index 000000000..5fc8134fb
--- /dev/null
+++ b/fpga/usrp2/top/u1e/tb_u1e.v
@@ -0,0 +1,41 @@
+`timescale 1ps / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module tb_u1e();
+   
+   wire [2:0] debug_led;
+   wire [31:0] debug;
+   wire [1:0] debug_clk;
+
+   xlnx_glbl glbl (.GSR(),.GTS());
+
+   initial begin
+      $dumpfile("tb_u1e.lxt");
+      $dumpvars(0,tb_u1e);
+   end
+    
+   // GPMC
+   wire       EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE;
+   wire [15:0] EM_D;
+   wire [10:1] EM_A;
+   wire [1:0]  EM_NBE;
+   
+   reg  clk_fpga = 0, rst_fpga = 1;
+   always #15625 clk_fpga = ~clk_fpga;
+
+   initial #200000
+     @(posedge clk_fpga)
+       rst_fpga <= 0;
+   
+   u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(rst_fpga), 
+		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+		     .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
+		     .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
+
+   gpmc_model_async gpmc_model_async
+     (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+      .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
+      .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
+   
+endmodule // tb_u1e
diff --git a/fpga/usrp2/top/u1e/timing.ucf b/fpga/usrp2/top/u1e/timing.ucf
new file mode 100644
index 000000000..8df28c9d3
--- /dev/null
+++ b/fpga/usrp2/top/u1e/timing.ucf
@@ -0,0 +1,13 @@
+
+NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P";
+TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %;
+
+
+
+
+#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;
+#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP;
+#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+
+#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
diff --git a/fpga/usrp2/top/u1e/u1e.ucf b/fpga/usrp2/top/u1e/u1e.ucf
new file mode 100644
index 000000000..0c487a601
--- /dev/null
+++ b/fpga/usrp2/top/u1e/u1e.ucf
@@ -0,0 +1,259 @@
+
+NET "CLK_FPGA_P"  LOC = "Y11"  ;
+NET "CLK_FPGA_N"  LOC = "Y10"  ;
+
+## GPMC
+NET "EM_D<15>"  LOC = "D13"  ;
+NET "EM_D<14>"  LOC = "D15"  ;
+NET "EM_D<13>"  LOC = "C16"  ;
+NET "EM_D<12>"  LOC = "B20"  ;
+NET "EM_D<11>"  LOC = "A19"  ;
+NET "EM_D<10>"  LOC = "A17"  ;
+NET "EM_D<9>"  LOC = "E15"  ;
+NET "EM_D<8>"  LOC = "F15"  ;
+NET "EM_D<7>"  LOC = "E16"  ;
+NET "EM_D<6>"  LOC = "F16"  ;
+NET "EM_D<5>"  LOC = "B17"  ;
+NET "EM_D<4>"  LOC = "C17"  ;
+NET "EM_D<3>"  LOC = "B19"  ;
+NET "EM_D<2>"  LOC = "D19"  ;
+NET "EM_D<1>"  LOC = "C19"  ;
+NET "EM_D<0>"  LOC = "A20"  ;
+
+NET "EM_A<10>"  LOC = "C14"  ;
+NET "EM_A<9>"  LOC = "C10"  ;
+NET "EM_A<8>"  LOC = "C5"  ;
+NET "EM_A<7>"  LOC = "A18"  ;
+NET "EM_A<6>"  LOC = "A15"  ;
+NET "EM_A<5>"  LOC = "A12"  ;
+NET "EM_A<4>"  LOC = "A10"  ;
+NET "EM_A<3>"  LOC = "E7"  ;
+NET "EM_A<2>"  LOC = "A7"  ;
+NET "EM_A<1>"  LOC = "C15"  ;
+
+NET "EM_NCS6"  LOC = "E17"  ;
+NET "EM_NCS5"  LOC = "E10"  ;
+NET "EM_NCS4"  LOC = "E6"  ;
+#NET "EM_NCS1"  LOC = "D18"  ;
+#NET "EM_NCS0"  LOC = "D17"  ;
+
+NET "EM_CLK"  LOC = "F11"  ;
+NET "EM_WAIT0"  LOC = "F14"  ;
+NET "EM_NBE<1>"  LOC = "D14"  ;
+NET "EM_NBE<0>"  LOC = "A13"  ;
+NET "EM_NWE"  LOC = "B13"  ;
+NET "EM_NOE"  LOC = "A14"  ;
+#NET "EM_NADV_ALE"  LOC = "B15"  ;
+#NET "EM_NWP"  LOC = "F13"  ;
+
+## Overo GPIO
+NET "overo_gpio0"  LOC = "F9"  ;  # MISC GPIO for debug
+NET "overo_gpio14"  LOC = "C4"  ;  # MISC GPIO for debug
+NET "overo_gpio21"  LOC = "D5"  ;  # MISC GPIO for debug
+NET "overo_gpio22"  LOC = "A3"  ;  # MISC GPIO for debug
+NET "overo_gpio23"  LOC = "B3"  ;  # MISC GPIO for debug
+NET "overo_gpio64"  LOC = "A4"  ;  # MISC GPIO for debug
+NET "overo_gpio65"  LOC = "F8"  ;  # MISC GPIO for debug
+
+NET "overo_gpio127"  LOC = "C8"  ;  # Changed name to gpio10
+NET "overo_gpio128"  LOC = "G8"  ;  # Changed name to gpio186
+
+NET "overo_gpio144"  LOC = "A5"  ;  # tx_have_space
+NET "overo_gpio145"  LOC = "C7"  ;  # tx_underrun
+NET "overo_gpio146"  LOC = "A6"  ;  # rx_have_data
+NET "overo_gpio147"  LOC = "B6"  ;  # rx_overrun
+NET "overo_gpio163"  LOC = "D7"  ;  # MISC GPIO for debug
+NET "overo_gpio170"  LOC = "E8"  ;  # MISC GPIO for debug
+NET "overo_gpio176"  LOC = "B4"  ;  # MISC GPIO for debug
+
+## Overo UART
+#NET "overo_txd1"  LOC = "C6"  ;
+#NET "overo_rxd1"  LOC = "D6"  ;
+
+## FTDI UART to USB converter
+NET "FPGA_TXD"  LOC = "G19"  ;
+NET "FPGA_RXD"  LOC = "F20"  ;
+
+#NET "SYSEN"  LOC = "C11"  ;
+
+## I2C
+NET "db_scl"  LOC = "F19"  ;
+NET "db_sda"  LOC = "F18"  ;
+
+## SPI
+### DBoard SPI
+NET "db_sclk_rx"  LOC = "D21"  ;
+NET "db_miso_rx"  LOC = "D22"  ;
+NET "db_mosi_rx"  LOC = "D20"  ;
+NET "db_sen_rx"  LOC = "E19"  ;
+NET "db_sclk_tx"  LOC = "F21"  ;
+NET "db_miso_tx"  LOC = "E20"  ;
+NET "db_mosi_tx"  LOC = "G17"  ;
+NET "db_sen_tx"  LOC = "G18"  ;
+
+### AD9862 SPI and aux SPI Interfaces
+#NET "aux_sdi_codec"  LOC = "G3"  ;
+#NET "aux_sdo_codec"  LOC = "F3"  ;
+#NET "aux_sclk_codec"  LOC = "C1"  ;
+NET "sen_codec"  LOC = "F5"  |IOSTANDARD = LVCMOS33;
+NET "mosi_codec"  LOC = "F4"  |IOSTANDARD = LVCMOS33;
+NET "miso_codec"  LOC = "H4"  ;
+NET "sclk_codec"  LOC = "H3"  |IOSTANDARD = LVCMOS33;
+
+### Clock Gen SPI
+NET "cgen_miso"  LOC = "F22"  ;
+NET "cgen_mosi"  LOC = "E22"  ;
+NET "cgen_sclk"  LOC = "J19"  ;
+NET "cgen_sen_b"  LOC = "H20"  ;
+
+## Clock gen control
+NET "cgen_st_status"  LOC = "P20"  ;
+NET "cgen_st_ld"  LOC = "R17"  ;
+NET "cgen_st_refmon"  LOC = "P17"  ;
+NET "cgen_sync_b"  LOC = "U18"  ;
+NET "cgen_ref_sel"  LOC = "U19"  ;
+
+## Debug pins
+NET "debug_led<3>"  LOC = "Y15"  ;
+NET "debug_led<2>"  LOC = "K16"  ;
+NET "debug_led<1>"  LOC = "J17"  ;
+NET "debug_led<0>"  LOC = "H22"  ;
+NET "debug<0>"  LOC = "G22"  ;
+NET "debug<1>"  LOC = "H17"  ;
+NET "debug<2>"  LOC = "H18"  ;
+NET "debug<3>"  LOC = "K20"  ;
+NET "debug<4>"  LOC = "J20"  ;
+NET "debug<5>"  LOC = "K19"  ;
+NET "debug<6>"  LOC = "K18"  ;
+NET "debug<7>"  LOC = "L22"  ;
+NET "debug<8>"  LOC = "K22"  ;
+NET "debug<9>"  LOC = "N22"  ;
+NET "debug<10>"  LOC = "M22"  ;
+NET "debug<11>"  LOC = "N20"  ;
+NET "debug<12>"  LOC = "N19"  ;
+NET "debug<13>"  LOC = "R22"  ;
+NET "debug<14>"  LOC = "P22"  ;
+NET "debug<15>"  LOC = "N17"  ;
+NET "debug<16>"  LOC = "P16"  ;
+NET "debug<17>"  LOC = "U22"  ;
+NET "debug<18>"  LOC = "P19"  ;
+NET "debug<19>"  LOC = "R18"  ;
+NET "debug<20>"  LOC = "U20"  ;
+NET "debug<21>"  LOC = "T20"  ;
+NET "debug<22>"  LOC = "R19"  ;
+NET "debug<23>"  LOC = "R20"  ;
+NET "debug<24>"  LOC = "W22"  ;
+NET "debug<25>"  LOC = "Y22"  ;
+NET "debug<26>"  LOC = "T18"  ;
+NET "debug<27>"  LOC = "T17"  ;
+NET "debug<28>"  LOC = "W19"  ;
+NET "debug<29>"  LOC = "V20"  ;
+NET "debug<30>"  LOC = "Y21"  ;
+NET "debug<31>"  LOC = "AA22"  ;
+NET "debug_clk<0>"  LOC = "N18"  ;
+NET "debug_clk<1>"  LOC = "M17"  ;
+
+NET "debug_pb"  LOC = "C22"  ;
+
+#NET "reset_codec"  LOC = "C2"  ;
+
+NET "RXSYNC"  LOC = "F2"  ;
+NET "DB<11>"  LOC = "G6"  ;
+NET "DB<10>"  LOC = "G5"  ;
+NET "DB<9>"  LOC = "E4"  ;
+NET "DB<8>"  LOC = "E3"  ;
+NET "DB<7>"  LOC = "H6"  ;
+NET "DB<6>"  LOC = "H5"  ;
+NET "DB<5>"  LOC = "H1"  ;
+NET "DB<4>"  LOC = "G1"  ;
+NET "DB<3>"  LOC = "K5"  ;
+NET "DB<2>"  LOC = "K4"  ;
+NET "DB<1>"  LOC = "H2"  ;
+NET "DB<0>"  LOC = "L5"  ;
+
+NET "DA<11>"  LOC = "K6"  ;
+NET "DA<10>"  LOC = "K3"  ;
+NET "DA<9>"  LOC = "K2"  ;
+NET "DA<8>"  LOC = "N1"  ;
+NET "DA<7>"  LOC = "N5"  ;
+NET "DA<6>"  LOC = "N6"  ;
+NET "DA<5>"  LOC = "P2"  ;
+NET "DA<4>"  LOC = "P1"  ;
+NET "DA<3>"  LOC = "R6"  ;
+NET "DA<2>"  LOC = "P6"  ;
+NET "DA<1>"  LOC = "R1"  ;
+NET "DA<0>"  LOC = "R2"  ;
+
+NET "TX<13>"  LOC = "T6"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<12>"  LOC = "U1"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<11>"  LOC = "T1"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<10>"  LOC = "R5"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<9>"  LOC = "V1"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<8>"  LOC = "U2"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<7>"  LOC = "T4"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<6>"  LOC = "R3"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<5>"  LOC = "W1"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<4>"  LOC = "Y1"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<3>"  LOC = "V3"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<2>"  LOC = "V4"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<1>"  LOC = "W2"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TX<0>"  LOC = "W3"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TXSYNC"  LOC = "U5"   |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+NET "TXBLANK"  LOC = "U4"  |IOSTANDARD = LVCMOS33  |DRIVE = 12  |SLEW = FAST ;
+
+NET "PPS_IN"  LOC = "M5"  ;
+
+NET "io_tx<0>"  LOC = "AB20"  ;
+NET "io_tx<1>"  LOC = "Y17"  ;
+NET "io_tx<2>"  LOC = "Y16"  ;
+NET "io_tx<3>"  LOC = "U16"  ;
+NET "io_tx<4>"  LOC = "V16"  ;
+NET "io_tx<5>"  LOC = "AB19"  ;
+NET "io_tx<6>"  LOC = "AA19"  ;
+NET "io_tx<7>"  LOC = "U14"  ;
+NET "io_tx<8>"  LOC = "U15"  ;
+NET "io_tx<9>"  LOC = "AB17"  ;
+NET "io_tx<10>"  LOC = "AB18"  ;
+NET "io_tx<11>"  LOC = "Y13"  ;
+NET "io_tx<12>"  LOC = "W14"  ;
+NET "io_tx<13>"  LOC = "U13"  ;
+NET "io_tx<14>"  LOC = "AA15"  ;
+NET "io_tx<15>"  LOC = "AB14"  ;
+
+NET "io_rx<0>"  LOC = "Y8"  ;
+NET "io_rx<1>"  LOC = "Y9"  ;
+NET "io_rx<2>"  LOC = "V7"  ;
+NET "io_rx<3>"  LOC = "U8"  ;
+NET "io_rx<4>"  LOC = "V10"  ;
+NET "io_rx<5>"  LOC = "U9"  ;
+NET "io_rx<6>"  LOC = "AB7"  ;
+NET "io_rx<7>"  LOC = "AA8"  ;
+NET "io_rx<8>"  LOC = "W8"  ;
+NET "io_rx<9>"  LOC = "V8"  ;
+NET "io_rx<10>"  LOC = "AB5"  ;
+NET "io_rx<11>"  LOC = "AB6"  ;
+NET "io_rx<12>"  LOC = "AB4"  ;
+NET "io_rx<13>"  LOC = "AA4"  ;
+NET "io_rx<14>"  LOC = "W5"  ;
+NET "io_rx<15>"  LOC = "Y4"  ;
+
+#NET "CLKOUT2_CODEC"  LOC = "U12"  ;
+#NET "CLKOUT1_CODEC"  LOC = "V12"  ;
+
+## FPGA Config Pins
+#NET "fpga_cfg_prog_b"  LOC = "A2"  ;
+#NET "fpga_cfg_done"  LOC = "AB21"  ;
+#NET "fpga_cfg_din"  LOC = "W17"  ;
+#NET "fpga_cfg_cclk"  LOC = "V17"  ;
+#NET "fpga_cfg_init_b"  LOC = "W15"  ;
+
+## Unused
+#NET "unnamed_net53"  LOC = "B1"  ;  # TMS
+#NET "unnamed_net52"  LOC = "B22"  ; # TDO
+#NET "unnamed_net51"  LOC = "D2"  ;  # TDI
+#NET "unnamed_net50"  LOC = "A21"  ; # TCK
+#NET "unnamed_net59"  LOC = "F7"  ;  # PUDC_B
+#NET "unnamed_net58"  LOC = "V6"  ;  # M2
+#NET "unnamed_net57"  LOC = "AA3"  ; # M1
+#NET "unnamed_net56"  LOC = "AB3"  ; # M0
+#NET "GND"  LOC = "V19"  ;  # Suspend, unused
diff --git a/fpga/usrp2/top/u1e/u1e.v b/fpga/usrp2/top/u1e/u1e.v
new file mode 100644
index 000000000..445b14a03
--- /dev/null
+++ b/fpga/usrp2/top/u1e/u1e.v
@@ -0,0 +1,141 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module u1e
+  (input CLK_FPGA_P, input CLK_FPGA_N,  // Diff
+   output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+   input debug_pb, output FPGA_TXD, input FPGA_RXD,
+
+   // GPMC
+   input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
+   input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6,
+   input EM_NWE, input EM_NOE,
+
+   inout db_sda, inout db_scl, // I2C
+
+   output db_sclk_tx, output db_sen_tx, output db_mosi_tx, input db_miso_tx,   // DB TX SPI
+   output db_sclk_rx, output db_sen_rx, output db_mosi_rx, input db_miso_rx,   // DB TX SPI
+   output sclk_codec, output sen_codec, output mosi_codec, input miso_codec,   // AD9862 main SPI
+   output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso,     // Clock gen SPI
+
+   input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel,
+   
+   output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147,  // Fifo controls
+   input overo_gpio0, input overo_gpio14, input overo_gpio21, input overo_gpio22,  // Misc GPIO
+   input overo_gpio23, input overo_gpio64, input overo_gpio65, input overo_gpio127, // Misc GPIO
+   input overo_gpio128, input overo_gpio163, input overo_gpio170, input overo_gpio176, // Misc GPIO
+   
+   inout [15:0] io_tx, inout [15:0] io_rx,
+
+   output [13:0] TX, output TXSYNC, output TXBLANK,
+   input [11:0] DA, input [11:0] DB, input RXSYNC,
+  
+   input PPS_IN
+   );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Clocking
+   wire  clk_fpga, clk_fpga_in;
+   
+   IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) 
+   clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
+
+   wire  clk_2x, dcm_rst, dcm_locked, clk_fb;
+   DCM #(.CLK_FEEDBACK ( "1X" ),
+	 .CLKDV_DIVIDE ( 2 ),
+	 .CLKFX_DIVIDE ( 2 ),
+	 .CLKFX_MULTIPLY ( 2 ),
+	 .CLKIN_DIVIDE_BY_2 ( "FALSE" ),
+	 .CLKIN_PERIOD ( 15.625 ),
+	 .CLKOUT_PHASE_SHIFT ( "NONE" ),
+	 .DESKEW_ADJUST ( "SYSTEM_SYNCHRONOUS" ),
+	 .DFS_FREQUENCY_MODE ( "LOW" ),
+	 .DLL_FREQUENCY_MODE ( "LOW" ),
+	 .DUTY_CYCLE_CORRECTION ( "TRUE" ),
+	 .FACTORY_JF ( 16'h8080 ),
+	 .PHASE_SHIFT ( 0 ),
+	 .STARTUP_WAIT ( "FALSE" ))
+   clk_doubler (.CLKFB(clk_fb), .CLKIN(clk_fpga_in), .RST(dcm_rst), 
+                .DSSEN(0), .PSCLK(0), .PSEN(0), .PSINCDEC(0), .PSDONE(), 
+		.CLKDV(), .CLKFX(), .CLKFX180(), 
+                .CLK2X(), .CLK2X180(), 
+                .CLK0(clk_fb), .CLK90(clk_fpga), .CLK180(), .CLK270(), 
+                .LOCKED(dcm_locked), .STATUS());
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // SPI
+   wire  mosi, sclk, miso;
+   assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0;
+   assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0;
+   assign { sclk_codec, mosi_codec } = ~sen_codec ? {sclk,mosi} : 2'b0;
+   assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0;
+   assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) |
+		 (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso);
+
+   // /////////////////////////////////////////////////////////////////////////
+   // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL
+
+   assign TXBLANK = 0;
+   wire [13:0] tx_i, tx_q;
+
+   reg[13:0] delay_q;
+   always @(posedge clk_fpga)
+     delay_q <= tx_q;
+   
+   genvar i;
+   generate
+      for(i=0;i<14;i=i+1)
+	begin : gen_dacout
+	   ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" 
+		   .INIT(1'b0),            // Sets initial state of the Q output to 1'b0 or 1'b1
+		   .SRTYPE("SYNC"))        // Specifies "SYNC" or "ASYNC" set/reset
+	   ODDR2_inst (.Q(TX[i]),      // 1-bit DDR output data
+		       .C0(clk_fpga),  // 1-bit clock input
+		       .C1(~clk_fpga), // 1-bit clock input
+		       .CE(1'b1),      // 1-bit clock enable input
+		       .D0(tx_i[i]),   // 1-bit data input (associated with C0)
+		       .D1(delay_q[i]),   // 1-bit data input (associated with C1)
+		       .R(1'b0),       // 1-bit reset input
+		       .S(1'b0));      // 1-bit set input
+	end // block: gen_dacout
+      endgenerate
+   ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" 
+	   .INIT(1'b0),            // Sets initial state of the Q output to 1'b0 or 1'b1
+	   .SRTYPE("SYNC"))        // Specifies "SYNC" or "ASYNC" set/reset
+   ODDR2_txsnc (.Q(TXSYNC),      // 1-bit DDR output data
+		.C0(clk_fpga),  // 1-bit clock input
+		.C1(~clk_fpga), // 1-bit clock input
+		.CE(1'b1),      // 1-bit clock enable input
+		.D0(1'b0),   // 1-bit data input (associated with C0)
+		.D1(1'b1),   // 1-bit data input (associated with C1)
+		.R(1'b0),       // 1-bit reset input
+		.S(1'b0));      // 1-bit set input
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Main U1E Core
+   u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb),
+		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
+		     .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD),
+		     .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS5(EM_NCS5), 
+		     .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE),
+		     .db_sda(db_sda), .db_scl(db_scl),
+		     .sclk(sclk), .sen({cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso),
+		     .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), 
+		     .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel),
+		     .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145),
+		     .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147),
+		     .io_tx(io_tx), .io_rx(io_rx),
+		     .tx_i(tx_i), .tx_q(tx_q), 
+		     .rx_i(DA), .rx_q(DB),
+		     .misc_gpio( {{overo_gpio128,overo_gpio163,overo_gpio170,overo_gpio176},
+				  {overo_gpio0,overo_gpio14,overo_gpio21,overo_gpio22},
+				  {overo_gpio23,overo_gpio64,overo_gpio65,overo_gpio127}}),
+		     .pps_in(PPS_IN) );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Local Debug
+   // assign debug_clk = {clk_fpga, clk_2x };
+   // assign debug = { TXSYNC, TXBLANK, TX };
+   
+endmodule // u1e
diff --git a/fpga/usrp2/top/u1e/u1e_core.v b/fpga/usrp2/top/u1e/u1e_core.v
new file mode 100644
index 000000000..619e44b8a
--- /dev/null
+++ b/fpga/usrp2/top/u1e/u1e_core.v
@@ -0,0 +1,459 @@
+
+
+//`define LOOPBACK 1
+//`define TIMED 1
+`define DSP 1
+
+module u1e_core
+  (input clk_fpga, input rst_fpga,
+   output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+   output debug_txd, input debug_rxd,
+   
+   // GPMC
+   input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
+   input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6,
+   input EM_NWE, input EM_NOE,
+   
+   inout db_sda, inout db_scl,
+   output sclk, output [7:0] sen, output mosi, input miso,
+
+   input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel,   
+   output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun,
+   inout [15:0] io_tx, inout [15:0] io_rx, 
+   output [13:0] tx_i, output [13:0] tx_q, 
+   input [11:0] rx_i, input [11:0] rx_q, 
+   
+   input [11:0] misc_gpio, input pps_in
+   );
+
+   localparam TXFIFOSIZE = 13;
+   localparam RXFIFOSIZE = 13;
+
+   localparam SR_RX_DSP = 0;     // 5 regs
+   localparam SR_CLEAR_FIFO = 6; // 1 reg
+   localparam SR_RX_CTRL = 8;    // 9 regs
+   localparam SR_TX_DSP = 17;    // 5 regs
+   localparam SR_TX_CTRL = 24;   // 2 regs
+   localparam SR_TIME64 = 28;    // 4 regs
+
+   wire 	COMPAT_NUM = 8'd2;
+   
+   wire 	wb_clk = clk_fpga;
+   wire 	wb_rst = rst_fpga;
+   
+   wire 	pps_int;
+   wire [63:0] 	vita_time;
+   reg [15:0] 	reg_leds, reg_cgen_ctrl, reg_test, xfer_rate;
+   
+   wire [7:0] 	set_addr;
+   wire [31:0] 	set_data;
+   wire 	set_stb;
+
+   wire [31:0] 	debug_vt;
+
+   // /////////////////////////////////////////////////////////////////////////////////////
+   // GPMC Slave to Wishbone Master
+   localparam dw = 16;
+   localparam aw = 11;
+   localparam sw = 2;
+   
+   wire [dw-1:0] m0_dat_mosi, m0_dat_miso;
+   wire [aw-1:0] m0_adr;
+   wire [sw-1:0] m0_sel;
+   wire 	 m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty;
+
+   wire [31:0] 	 debug_gpmc;
+
+   wire [35:0] 	 tx_data, rx_data, tx_err_data;
+   wire 	 tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, 
+		 tx_err_src_rdy, tx_err_dst_rdy;
+   reg [15:0] 	 tx_frame_len;
+   wire [15:0] 	 rx_frame_len;
+   wire [7:0] 	 rate;
+
+   wire 	 bus_error;
+
+   wire 	 clear_rx_int, clear_tx_int, clear_tx, clear_rx, do_clear;
+   
+   setting_reg #(.my_addr(SR_CLEAR_FIFO), .width(2)) sr_clear
+     (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({clear_tx_int,clear_rx_int}),.changed(do_clear));
+   assign clear_tx = clear_tx_int & do_clear;
+   assign clear_rx = clear_rx_int & do_clear;
+   
+   gpmc_async #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE))
+   gpmc (.arst(wb_rst),
+	 .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+	 .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), 
+	 .EM_NOE(EM_NOE),
+	 
+	 .rx_have_data(rx_have_data), .tx_have_space(tx_have_space),
+	 .bus_error(bus_error), .bus_reset(0),
+	 
+	 .wb_clk(wb_clk), .wb_rst(wb_rst),
+	 .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso),
+	 .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we),
+	 .wb_ack_i(m0_ack),
+	 
+	 .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx),
+	 .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy),
+	 .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
+	 
+	 .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len),
+	 .debug(debug_gpmc));
+
+   wire 	 rx_sof = rx_data[32];
+   wire 	 rx_eof = rx_data[33];
+   wire 	 rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int;
+   
+`ifdef LOOPBACK
+   wire [7:0] 	 WHOAMI = 1;
+   
+   fifo_cascade #(.WIDTH(36), .SIZE(12)) loopback_fifo
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx | clear_rx),
+      .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
+      .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
+
+   assign tx_underrun = 0;
+   assign rx_overrun = 0;
+
+   wire 	 run_tx, run_rx, strobe_tx, strobe_rx;
+`endif // LOOPBACK
+
+`ifdef TIMED
+   wire [7:0] 	 WHOAMI = 2;
+   
+   // TX side
+   wire 	 tx_enable;
+   
+   fifo_pacer tx_pacer
+     (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(tx_enable),
+      .src1_rdy_i(tx_src_rdy), .dst1_rdy_o(tx_dst_rdy),
+      .src2_rdy_o(tx_src_rdy_int), .dst2_rdy_i(tx_dst_rdy_int),
+      .underrun(tx_underrun), .overrun());
+   
+   packet_verifier32 pktver32
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx),
+      .data_i(tx_data), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int),
+      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+   // RX side
+   wire 	 rx_enable;
+
+   packet_generator32 pktgen32
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
+      .data_o(rx_data), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int));
+
+   fifo_pacer rx_pacer
+     (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(rx_enable),
+      .src1_rdy_i(rx_src_rdy_int), .dst1_rdy_o(rx_dst_rdy_int),
+      .src2_rdy_o(rx_src_rdy), .dst2_rdy_i(rx_dst_rdy),
+      .underrun(), .overrun(rx_overrun));
+   
+`endif //  `ifdef TIMED
+
+`ifdef DSP
+   wire [7:0] 	 WHOAMI = 0;
+   
+   wire [31:0] 	 debug_rx_dsp, vrc_debug, vrf_debug;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // DSP RX
+   wire [31:0] 	 sample_rx, sample_tx;
+   wire 	 strobe_rx, strobe_tx;
+   wire 	 rx1_dst_rdy, rx1_src_rdy;
+   wire [99:0] 	 rx1_data;
+   wire 	 run_rx;
+   wire [35:0] 	 vita_rx_data;
+   wire 	 vita_rx_src_rdy, vita_rx_dst_rdy;
+      
+   dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx
+     (.clk(wb_clk),.rst(wb_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_a({rx_i,2'b0}),.adc_ovf_a(0),.adc_b({rx_q,2'b0}),.adc_ovf_b(0),
+      .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
+      .debug(debug_rx_dsp) );
+
+   vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .vita_time(vita_time), .overrun(rx_overrun),
+      .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
+      .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy),
+      .debug_rx(vrc_debug));
+
+   vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy),
+      .data_o(vita_rx_data), .dst_rdy_i(vita_rx_dst_rdy), .src_rdy_o(vita_rx_src_rdy),
+      .fifo_occupied(), .fifo_full(), .fifo_empty(),
+      .debug_rx(vrf_debug) );
+   
+   fifo36_mux #(.prio(0)) mux_err_stream
+     (.clk(wb_clk), .reset(wb_rst), .clear(0),
+      .data0_i(vita_rx_data), .src0_rdy_i(vita_rx_src_rdy), .dst0_rdy_o(vita_rx_dst_rdy),
+      .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy),
+      .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
+   
+   // ///////////////////////////////////////////////////////////////////////////////////
+   // DSP TX
+
+   wire [15:0] 	 tx_i_int, tx_q_int;
+   wire 	 run_tx;
+   
+   vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), 
+		   .REPORT_ERROR(1), .PROT_ENG_FLAGS(0)) 
+   vita_tx_chain
+     (.clk(wb_clk), .reset(wb_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .vita_time(vita_time),
+      .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
+      .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
+      .dac_a(tx_i_int),.dac_b(tx_q_int),
+      .underrun(underrun), .run(run_tx),
+      .debug(debug_vt));
+   
+   assign tx_i = tx_i_int[15:2];
+   assign tx_q = tx_q_int[15:2];
+   
+`else // !`ifdef DSP
+   // Dummy DSP signal generator for test purposes
+   wire [23:0] 	 tx_i_int, tx_q_int;
+   wire [23:0] 	 freq = {reg_test,8'd0};
+   reg [23:0] 	 phase;
+   
+   always @(posedge wb_clk)
+     phase <= phase + freq;
+   
+   cordic_z24 #(.bitwidth(24)) tx_cordic
+     (.clock(wb_clk), .reset(wb_rst), .enable(1),
+      .xi(24'd2500000), .yi(24'd0), .zi(phase), .xo(tx_i_int), .yo(tx_q_int), .zo());
+
+   assign tx_i = tx_i_int[23:10];
+   assign tx_q = tx_q_int[23:10];
+`endif // !`ifdef DSP
+      
+   // /////////////////////////////////////////////////////////////////////////////////////
+   // Wishbone Intercon, single master
+   wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso,
+		 s4_dat_mosi, s5_dat_mosi, s4_dat_miso, s5_dat_miso, s6_dat_mosi, s7_dat_mosi, s6_dat_miso, s7_dat_miso,
+		 s8_dat_mosi, s9_dat_mosi, s8_dat_miso, s9_dat_miso, sa_dat_mosi, sb_dat_mosi, sa_dat_miso, sb_dat_miso,
+		 sc_dat_mosi, sd_dat_mosi, sc_dat_miso, sd_dat_miso, se_dat_mosi, sf_dat_mosi, se_dat_miso, sf_dat_miso;
+   wire [aw-1:0] s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr;
+   wire [aw-1:0] s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr;
+   wire [sw-1:0] s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel;
+   wire [sw-1:0] s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel;
+   wire 	 s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack;
+   wire 	 s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack;
+   wire 	 s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb;
+   wire 	 s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb;
+   wire 	 s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc;
+   wire 	 s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc;
+   wire 	 s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we;
+   wire 	 s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we, sf_we;
+   
+   wb_1master #(.dw(dw), .aw(aw), .sw(sw), .decode_w(4),
+		.s0_addr(4'h0), .s0_mask(4'hF), .s1_addr(4'h1), .s1_mask(4'hF),
+		.s2_addr(4'h2), .s2_mask(4'hF),	.s3_addr(4'h3), .s3_mask(4'hF),
+		.s4_addr(4'h4), .s4_mask(4'hF),	.s5_addr(4'h5), .s5_mask(4'hF),
+		.s6_addr(4'h6), .s6_mask(4'hF),	.s7_addr(4'h7), .s7_mask(4'hF),
+		.s8_addr(4'h8), .s8_mask(4'hF),	.s9_addr(4'h9), .s9_mask(4'hF),
+		.sa_addr(4'ha), .sa_mask(4'hF),	.sb_addr(4'hb), .sb_mask(4'hF),
+		.sc_addr(4'hc), .sc_mask(4'hF),	.sd_addr(4'hd), .sd_mask(4'hF),
+		.se_addr(4'he), .se_mask(4'hF),	.sf_addr(4'hf), .sf_mask(4'hF))
+   wb_1master
+     (.clk_i(wb_clk),.rst_i(wb_rst),       
+      .m0_dat_o(m0_dat_miso),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_mosi),
+      .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
+      .s0_dat_o(s0_dat_mosi),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
+      .s0_dat_i(s0_dat_miso),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0),
+      .s1_dat_o(s1_dat_mosi),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
+      .s1_dat_i(s1_dat_miso),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0),
+      .s2_dat_o(s2_dat_mosi),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
+      .s2_dat_i(s2_dat_miso),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0),
+      .s3_dat_o(s3_dat_mosi),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
+      .s3_dat_i(s3_dat_miso),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0),
+      .s4_dat_o(s4_dat_mosi),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
+      .s4_dat_i(s4_dat_miso),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0),
+      .s5_dat_o(s5_dat_mosi),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
+      .s5_dat_i(s5_dat_miso),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0),
+      .s6_dat_o(s6_dat_mosi),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
+      .s6_dat_i(s6_dat_miso),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0),
+      .s7_dat_o(s7_dat_mosi),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
+      .s7_dat_i(s7_dat_miso),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0),
+      .s8_dat_o(s8_dat_mosi),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb),
+      .s8_dat_i(s8_dat_miso),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0),
+      .s9_dat_o(s9_dat_mosi),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
+      .s9_dat_i(s9_dat_miso),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0),
+      .sa_dat_o(sa_dat_mosi),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb),
+      .sa_dat_i(sa_dat_miso),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0),
+      .sb_dat_o(sb_dat_mosi),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb),
+      .sb_dat_i(sb_dat_miso),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0),
+      .sc_dat_o(sc_dat_mosi),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb),
+      .sc_dat_i(sc_dat_miso),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0),
+      .sd_dat_o(sd_dat_mosi),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb),
+      .sd_dat_i(sd_dat_miso),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0),
+      .se_dat_o(se_dat_mosi),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb),
+      .se_dat_i(se_dat_miso),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0),
+      .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb),
+      .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) );
+
+   assign s7_ack = 0;
+   assign s8_ack = 0;   assign s9_ack = 0;   assign sa_ack = 0;   assign sb_ack = 0;
+   assign sc_ack = 0;   assign sd_ack = 0;   assign se_ack = 0;   assign sf_ack = 0;
+
+   // /////////////////////////////////////////////////////////////////////////////////////
+   // Slave 0, Misc LEDs, Switches, controls
+   
+   localparam REG_LEDS = 7'd0;         // out
+   localparam REG_SWITCHES = 7'd2;     // in
+   localparam REG_CGEN_CTRL = 7'd4;    // out
+   localparam REG_CGEN_ST = 7'd6;      // in
+   localparam REG_TEST = 7'd8;         // out
+   localparam REG_RX_FRAMELEN = 7'd10; // in
+   localparam REG_TX_FRAMELEN = 7'd12; // out
+   localparam REG_XFER_RATE = 7'd14;   // out
+   localparam REG_COMPAT = 7'd16;      // in
+   
+   always @(posedge wb_clk)
+     if(wb_rst)
+       begin
+	  reg_leds <= 0;
+	  reg_cgen_ctrl <= 2'b11;
+	  reg_test <= 0;
+	  tx_frame_len <= 0;
+	  xfer_rate <= 0;
+       end
+     else
+       if(s0_cyc & s0_stb & s0_we) 
+	 case(s0_adr[6:0])
+	   REG_LEDS :
+	     reg_leds <= s0_dat_mosi;
+	   REG_CGEN_CTRL :
+	     reg_cgen_ctrl <= s0_dat_mosi;
+	   REG_TEST :
+	     reg_test <= s0_dat_mosi;
+	   REG_TX_FRAMELEN :
+	     tx_frame_len <= s0_dat_mosi;
+	   REG_XFER_RATE :
+	     xfer_rate <= s0_dat_mosi;
+	 endcase // case (s0_adr[6:0])
+
+   assign tx_enable = xfer_rate[15];
+   assign rx_enable = xfer_rate[14];
+   assign rate = xfer_rate[7:0];
+   
+   assign { debug_led[3:0] } = {run_rx,run_tx,reg_leds[1:0]};
+   assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl;
+   
+   assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : 
+			(s0_adr[6:0] == REG_SWITCHES) ? { 16'd0 } :
+			(s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl :
+			(s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} :
+			(s0_adr[6:0] == REG_TEST) ? reg_test :
+			(s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len :
+			(s0_adr[6:0] == REG_COMPAT) ? { WHOAMI, COMPAT_NUM } :
+			16'hBEEF;
+   
+   assign s0_ack = s0_stb & s0_cyc;
+
+   // /////////////////////////////////////////////////////////////////////////////////////
+   // Slave 1, UART
+   //    depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock
+   
+   simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart 
+     (.clk_i(wb_clk),.rst_i(wb_rst),
+      .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack),
+      .adr_i(s1_adr[3:1]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso),
+      .rx_int_o(),.tx_int_o(),
+      .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o());
+
+   // /////////////////////////////////////////////////////////////////////////////////////
+   // Slave 2, SPI
+
+   spi_top16 shared_spi
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_mosi),
+      .wb_dat_o(s2_dat_miso),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
+      .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(),
+      .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) );
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Slave 3, I2C
+
+   wire 	scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o;
+   i2c_master_top #(.ARST_LVL(1)) i2c 
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), 
+      .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]),
+      .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
+      .wb_ack_o(s3_ack),.wb_inta_o(),
+      .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
+      .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
+
+   assign 	 s3_dat_miso[15:8] = 8'd0;
+
+   // I2C -- Don't use external transistors for open drain, the FPGA implements this
+   IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o));
+   IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+   // /////////////////////////////////////////////////////////////////////////
+   // GPIOs -- Slave #4
+
+   wire [31:0] 	atr_lines;
+   wire [31:0] 	debug_gpio_0, debug_gpio_1;
+   
+   nsgpio16LE 
+     nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst),
+		.cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
+		.dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack),
+		.atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
+		.gpio( {io_tx,io_rx} ) );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Settings Bus -- Slave #5
+
+   // only have 32 regs, 32 bits each with current setup...
+   settings_bus_16LE #(.AWIDTH(11),.RWIDTH(11-4-2)) settings_bus_16LE
+     (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s5_adr),.wb_dat_i(s5_dat_mosi),
+      .wb_stb_i(s5_stb),.wb_we_i(s5_we),.wb_ack_o(s5_ack),
+      .strobe(set_stb),.addr(set_addr),.data(set_data) );
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // ATR Controller -- Slave #6
+
+   atr_controller16 atr_controller16
+     (.clk_i(wb_clk), .rst_i(wb_rst),
+      .adr_i(s6_adr), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso),
+      .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack),
+      .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines));
+
+
+   // /////////////////////////////////////////////////////////////////////////
+   // VITA Timing
+
+   time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit
+     (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int));
+   
+   // /////////////////////////////////////////////////////////////////////////////////////
+   // Debug circuitry
+
+   assign debug_clk = { EM_CLK, clk_fpga };
+
+   assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun },
+		    { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int },
+		    { EM_D } };
+
+   assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]}, 
+			   {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} };
+
+   assign debug_gpio_1 = debug_vt;
+   
+/*   
+   assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy},
+			   {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy},
+			   {rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0},
+			   {2'b0, bus_error, debug_gpmc[4:0] },
+			   {misc_gpio[7:0]} };
+  */ 
+endmodule // u1e_core
diff --git a/fpga/usrp2/top/u1e_ethdebug/.gitignore b/fpga/usrp2/top/u1e_ethdebug/.gitignore
new file mode 100644
index 000000000..8d872713e
--- /dev/null
+++ b/fpga/usrp2/top/u1e_ethdebug/.gitignore
@@ -0,0 +1,6 @@
+*~
+build
+*.log
+*.cmd
+tb_u1e
+*.lxt
diff --git a/fpga/usrp2/top/u1e_ethdebug/Makefile b/fpga/usrp2/top/u1e_ethdebug/Makefile
new file mode 100644
index 000000000..751b52970
--- /dev/null
+++ b/fpga/usrp2/top/u1e_ethdebug/Makefile
@@ -0,0 +1,83 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE = u1e
+BUILD_DIR = $(abspath build$(ISE))
+
+##################################################
+# Include other makefiles
+##################################################
+
+include ../Makefile.common
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd1800a \
+package cs484 \
+speed -4 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+u1e.v \
+u1e.ucf
+
+SOURCES = $(abspath $(TOP_SRCS))
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High 
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 \
+"Unused IOB Pins" "Pull Up"
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp2/top/u1e_ethdebug/u1e.ucf b/fpga/usrp2/top/u1e_ethdebug/u1e.ucf
new file mode 100644
index 000000000..d6a2ea4ed
--- /dev/null
+++ b/fpga/usrp2/top/u1e_ethdebug/u1e.ucf
@@ -0,0 +1,88 @@
+
+## GPMC
+NET "EM_D<15>"  LOC = "D13"  ;
+NET "EM_D<14>"  LOC = "D15"  ;
+NET "EM_D<13>"  LOC = "C16"  ;
+NET "EM_D<12>"  LOC = "B20"  ;
+NET "EM_D<11>"  LOC = "A19"  ;
+NET "EM_D<10>"  LOC = "A17"  ;
+NET "EM_D<9>"  LOC = "E15"  ;
+NET "EM_D<8>"  LOC = "F15"  ;
+NET "EM_D<7>"  LOC = "E16"  ;
+NET "EM_D<6>"  LOC = "F16"  ;
+NET "EM_D<5>"  LOC = "B17"  ;
+NET "EM_D<4>"  LOC = "C17"  ;
+NET "EM_D<3>"  LOC = "B19"  ;
+NET "EM_D<2>"  LOC = "D19"  ;
+NET "EM_D<1>"  LOC = "C19"  ;
+NET "EM_D<0>"  LOC = "A20"  ;
+
+NET "EM_A<10>"  LOC = "C14"  ;
+NET "EM_A<9>"  LOC = "C10"  ;
+NET "EM_A<8>"  LOC = "C5"  ;
+NET "EM_A<7>"  LOC = "A18"  ;
+NET "EM_A<6>"  LOC = "A15"  ;
+NET "EM_A<5>"  LOC = "A12"  ;
+NET "EM_A<4>"  LOC = "A10"  ;
+NET "EM_A<3>"  LOC = "E7"  ;
+NET "EM_A<2>"  LOC = "A7"  ;
+NET "EM_A<1>"  LOC = "C15"  ;
+
+NET "EM_NCS6"  LOC = "E17"  ;
+NET "EM_NCS5"  LOC = "E10"  ;
+NET "EM_NCS4"  LOC = "E6"  ;
+#NET "EM_NCS1"  LOC = "D18"  ;
+#NET "EM_NCS0"  LOC = "D17"  ;
+
+NET "EM_CLK"  LOC = "F11"  ;
+NET "EM_WAIT0"  LOC = "F14"  ;
+#NET "EM_NBE<1>"  LOC = "D14"  ;
+#NET "EM_NBE<0>"  LOC = "A13"  ;
+NET "EM_NWE"  LOC = "B13"  ;
+NET "EM_NOE"  LOC = "A14"  ;
+NET "EM_NADV_ALE"  LOC = "B15"  ;
+#NET "EM_NWP"  LOC = "F13"  ;
+NET "overo_gpio64"  LOC = "A4"  ;  # nRESET
+NET "overo_gpio176"  LOC = "B4"  ;  # IRQ
+
+## Debug pins
+NET "debug_led<3>"  LOC = "Y15"  ;
+NET "debug_led<2>"  LOC = "K16"  ;
+NET "debug_led<1>"  LOC = "J17"  ;
+NET "debug_led<0>"  LOC = "H22"  ;
+NET "debug<0>"  LOC = "G22"  ;
+NET "debug<1>"  LOC = "H17"  ;
+NET "debug<2>"  LOC = "H18"  ;
+NET "debug<3>"  LOC = "K20"  ;
+NET "debug<4>"  LOC = "J20"  ;
+NET "debug<5>"  LOC = "K19"  ;
+NET "debug<6>"  LOC = "K18"  ;
+NET "debug<7>"  LOC = "L22"  ;
+NET "debug<8>"  LOC = "K22"  ;
+NET "debug<9>"  LOC = "N22"  ;
+NET "debug<10>"  LOC = "M22"  ;
+NET "debug<11>"  LOC = "N20"  ;
+NET "debug<12>"  LOC = "N19"  ;
+NET "debug<13>"  LOC = "R22"  ;
+NET "debug<14>"  LOC = "P22"  ;
+NET "debug<15>"  LOC = "N17"  ;
+NET "debug<16>"  LOC = "P16"  ;
+NET "debug<17>"  LOC = "U22"  ;
+NET "debug<18>"  LOC = "P19"  ;
+NET "debug<19>"  LOC = "R18"  ;
+NET "debug<20>"  LOC = "U20"  ;
+NET "debug<21>"  LOC = "T20"  ;
+NET "debug<22>"  LOC = "R19"  ;
+NET "debug<23>"  LOC = "R20"  ;
+NET "debug<24>"  LOC = "W22"  ;
+NET "debug<25>"  LOC = "Y22"  ;
+NET "debug<26>"  LOC = "T18"  ;
+NET "debug<27>"  LOC = "T17"  ;
+NET "debug<28>"  LOC = "W19"  ;
+NET "debug<29>"  LOC = "V20"  ;
+NET "debug<30>"  LOC = "Y21"  ;
+NET "debug<31>"  LOC = "AA22"  ;
+NET "debug_clk<0>"  LOC = "N18"  ;
+NET "debug_clk<1>"  LOC = "M17"  ;
+
+NET "debug_pb"  LOC = "C22"  ;
diff --git a/fpga/usrp2/top/u1e_ethdebug/u1e.v b/fpga/usrp2/top/u1e_ethdebug/u1e.v
new file mode 100644
index 000000000..2a543a313
--- /dev/null
+++ b/fpga/usrp2/top/u1e_ethdebug/u1e.v
@@ -0,0 +1,28 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+//`define DCM 1
+
+module u1e
+  (output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
+   input debug_pb,
+
+   // GPMC
+   input EM_CLK, input [15:0] EM_D, input [10:1] EM_A,
+   input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, input EM_NWE, input EM_NOE,
+   input EM_NADV_ALE,
+
+   input overo_gpio64, input overo_gpio176
+   );
+
+   assign debug_clk = {EM_CLK, EM_NADV_ALE};
+
+   assign debug_led = {1'b0, EM_A[9], EM_A[8], debug_pb};
+
+   assign debug = { {overo_gpio64, overo_gpio176, EM_WAIT0, EM_NCS4, EM_NCS5, EM_NCS6, EM_NWE, EM_NOE },
+		    { EM_A[10], EM_A[7:1] },
+		    { EM_D[15:8] },
+		    { EM_D[7:0] } };
+   
+
+endmodule // u1e
diff --git a/fpga/usrp2/top/u1e_passthru/.gitignore b/fpga/usrp2/top/u1e_passthru/.gitignore
new file mode 100644
index 000000000..1b2211df0
--- /dev/null
+++ b/fpga/usrp2/top/u1e_passthru/.gitignore
@@ -0,0 +1 @@
+build*
diff --git a/fpga/usrp2/top/u1e_passthru/Makefile b/fpga/usrp2/top/u1e_passthru/Makefile
new file mode 100644
index 000000000..d1950629b
--- /dev/null
+++ b/fpga/usrp2/top/u1e_passthru/Makefile
@@ -0,0 +1,99 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE = passthru
+BUILD_DIR = $(abspath build$(ISE))
+
+##################################################
+# Include other makefiles
+##################################################
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../extram/Makefile.srcs
+include ../../gpmc/Makefile.srcs
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd1800a \
+package cs484 \
+speed -4 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+passthru.v \
+passthru.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(GPMC_SRCS)
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High 
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 \
+"Unused IOB Pins" "Pull Up"
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp2/top/u1e_passthru/passthru.ucf b/fpga/usrp2/top/u1e_passthru/passthru.ucf
new file mode 100644
index 000000000..64e6f0440
--- /dev/null
+++ b/fpga/usrp2/top/u1e_passthru/passthru.ucf
@@ -0,0 +1,6 @@
+NET "overo_gpio145"  LOC = "C7"  ;
+NET "cgen_mosi"  LOC = "E22"  ;
+NET "cgen_sclk"  LOC = "J19"  ;
+NET "cgen_sen_b"  LOC = "H20"  ;
+NET "fpga_cfg_din"  LOC = "W17"  ;
+NET "fpga_cfg_cclk"  LOC = "V17"  ;
diff --git a/fpga/usrp2/top/u1e_passthru/passthru.v b/fpga/usrp2/top/u1e_passthru/passthru.v
new file mode 100644
index 000000000..12e4db017
--- /dev/null
+++ b/fpga/usrp2/top/u1e_passthru/passthru.v
@@ -0,0 +1,18 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module passthru
+  (input overo_gpio145,
+   output cgen_sclk,
+   output cgen_sen_b,
+   output cgen_mosi,
+   input fpga_cfg_din,
+   input fpga_cfg_cclk
+   );
+   
+   assign cgen_sclk = fpga_cfg_cclk;
+   assign cgen_sen_b = overo_gpio145;
+   assign cgen_mosi = fpga_cfg_din;
+   
+   
+endmodule // passthru
diff --git a/host/CMakeLists.txt b/host/CMakeLists.txt
index a60eed0a5..e5ce78782 100644
--- a/host/CMakeLists.txt
+++ b/host/CMakeLists.txt
@@ -16,7 +16,7 @@
 #
 
 CMAKE_MINIMUM_REQUIRED(VERSION 2.6)
-PROJECT(UHD CXX)
+PROJECT(UHD CXX C)
 ENABLE_TESTING()
 
 ########################################################################
@@ -64,7 +64,7 @@ IF(CMAKE_COMPILER_IS_GNUCXX)
     #causes trouble when compiling libusb1.0 on macintosh
     #comment out until mac ports libusb gets its act together
     #ADD_DEFINITIONS(-pedantic)
-    ADD_DEFINITIONS(-ansi)
+    #ADD_DEFINITIONS(-ansi)
     #only export symbols that are declared to be part of the uhd api:
     UHD_ADD_OPTIONAL_CXX_COMPILER_FLAG(-fvisibility=hidden HAVE_VISIBILITY_HIDDEN)
 ENDIF(CMAKE_COMPILER_IS_GNUCXX)
diff --git a/host/apps/omap_debug/.gitignore b/host/apps/omap_debug/.gitignore
new file mode 100644
index 000000000..008a23138
--- /dev/null
+++ b/host/apps/omap_debug/.gitignore
@@ -0,0 +1,20 @@
+.gitignore
+clkgen-config
+fpga-downloader
+usrp-e-button
+usrp-e-crc-rw
+usrp-e-ctl
+usrp-e-debug-pins
+usrp-e-fpga-rw
+usrp-e-gpio
+usrp-e-i2c
+usrp-e-lb-test
+usrp-e-led
+usrp-e-loopback
+usrp-e-random-loopback
+usrp-e-rw
+usrp-e-spi
+usrp-e-timed
+usrp-e-uart
+usrp-e-uart-rx
+usrp-e-mm-loopback
diff --git a/host/apps/omap_debug/Makefile b/host/apps/omap_debug/Makefile
new file mode 100644
index 000000000..46d4714a8
--- /dev/null
+++ b/host/apps/omap_debug/Makefile
@@ -0,0 +1,61 @@
+CFLAGS=-Wall -I../../lib/usrp/usrp_e/ -march=armv7-a -mtune=cortex-a8 -mfpu=neon -O3
+CXXFLAGS=-Wall -I../../lib/usrp/usrp_e/ -march=armv7-a -mtune=cortex-a8 -mfpu=neon -O3
+
+all : usrp-e-spi usrp-e-i2c usrp-e-loopback usrp-e-mm-loopback usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio usrp-e-debug-pins usrp-e-random-loopback usrp-e-timed usrp-e-lb-test usrp-e-crc-rw clkgen-config
+
+usrp-e-spi : usrp-e-spi.c
+
+usrp-e-i2c : usrp-e-i2c.c
+
+usrp-e-loopback : usrp-e-loopback.c
+	gcc -o $@ $< -lpthread ${CFLAGS}
+
+usrp-e-mm-loopback : usrp-e-mm-loopback.c
+	gcc -o $@ $< -lpthread ${CFLAGS}
+
+usrp-e-timed : usrp-e-timed.c
+	gcc -o $@ $< -lpthread ${CFLAGS}
+
+usrp-e-random-loopback : usrp-e-random-loopback.c
+	gcc -o $@ $< -lpthread ${CFLAGS}
+
+usrp-e-crc-rw : usrp-e-crc-rw.c
+	gcc -o $@ $< -lpthread ${CFLAGS}
+
+usrp-e-uart : usrp-e-uart.c
+
+usrp-e-uart-rx : usrp-e-uart-rx.c
+
+usrp-e-led : usrp-e-led.c
+
+usrp-e-ctl : usrp-e-ctl.c
+
+usrp-e-button : usrp-e-button.c
+
+fpga-downloader : fpga-downloader.cc
+
+clkgen-config : clkgen-config.cc
+
+usrp-e-gpio : usrp-e-gpio.c
+
+usrp-e-lb-test : usrp-e-lb-test.c
+
+usrp-e-debug-pins : usrp-e-debug-pins.c
+clean :
+	rm -f usrp-e-spi
+	rm -f usrp-e-i2c
+	rm -f usrp-e-loopback
+	rm -f usrp-e-mm-loopback
+	rm -f usrp-e-timed
+	rm -f usrp-e-rw-random
+	rm -f usrp-e-uart
+	rm -f usrp-e-uart-rx
+	rm -f usrp-e-led
+	rm -f usrp-e-ctl
+	rm -f usrp-e-button
+	rm -f fpga-downloader
+	rm -f usrp-e-gpio
+	rm -f usrp-e-debug-pins
+	rm -f usrp-e-lb-test
+	rm -f usrp-e-crc-rw
+	rm -f clkgen-config
diff --git a/host/apps/omap_debug/README b/host/apps/omap_debug/README
new file mode 100644
index 000000000..bbe0c2cc4
--- /dev/null
+++ b/host/apps/omap_debug/README
@@ -0,0 +1 @@
+OMAP development tools go here
diff --git a/host/apps/omap_debug/clkgen-config.cc b/host/apps/omap_debug/clkgen-config.cc
new file mode 100644
index 000000000..e8279b4ae
--- /dev/null
+++ b/host/apps/omap_debug/clkgen-config.cc
@@ -0,0 +1,296 @@
+/* -*- c++ -*- */
+/*
+ * Copyright 2003,2004,2008,2009 Free Software Foundation, Inc.
+ *
+ * This file is part of UHD
+ *
+ * GNU Radio is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3, or (at your option)
+ * any later version.
+ *
+ * GNU Radio is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with GNU Radio; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+*/
+
+#include <iostream>
+#include <sstream>
+#include <fstream>
+#include <string>
+#include <cstdlib>
+
+#include <fcntl.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/ioctl.h>
+
+#include <linux/spi/spidev.h>
+
+
+// Programming data for clock gen chip
+static const unsigned int config_data[] = {
+	0x000024,
+	0x023201,
+	0x000081,
+	0x000400,
+	0x00104c,
+	0x001101,
+	0x001200,
+	0x001300,
+	0x001414,
+	0x001500,
+	0x001604,
+	0x001704,
+	0x001807,
+	0x001900,
+	//0x001a00,//for debug
+	0x001a32,
+	0x001b12,
+	0x001c44,
+	0x001d00,
+	0x001e00,
+	0x00f062,
+	0x00f162,
+	0x00f262,
+	0x00f362,
+	0x00f462,
+	0x00f562,
+	0x00f662,
+	0x00f762,
+	0x00f862,
+	0x00f962,
+	0x00fa62,
+	0x00fb62,
+	0x00fc00,
+	0x00fd00,
+	0x019021,
+	0x019100,
+	0x019200,
+	0x019333,
+	0x019400,
+	0x019500,
+	0x019611,
+	0x019700,
+	0x019800,
+	0x019900,
+	0x019a00,
+	0x019b00,
+	0x01e003,
+	0x01e102,
+	0x023000,
+	0x023201,
+	0x0b0201,
+	0x0b0300,
+	0x001fff,
+	0x0a0000,
+	0x0a0100,
+	0x0a0200,
+	0x0a0302,
+	0x0a0400,
+	0x0a0504,
+	0x0a060e,
+	0x0a0700,
+	0x0a0810,
+	0x0a090e,
+	0x0a0a00,
+	0x0a0bf0,
+	0x0a0c0b,
+	0x0a0d01,
+	0x0a0e90,
+	0x0a0f01,
+	0x0a1001,
+	0x0a11e0,
+	0x0a1201,
+	0x0a1302,
+	0x0a1430,
+	0x0a1580,
+	0x0a16ff,
+	0x023201,
+	0x0b0301,
+	0x023201,
+};
+
+
+const unsigned int CLKGEN_SELECT = 145;
+
+
+enum gpio_direction {IN, OUT};
+
+class gpio {
+	public:
+
+	gpio(unsigned int gpio_num, gpio_direction pin_direction, bool close_action);
+	~gpio();
+
+	bool get_value();
+	void set_value(bool state);
+
+	private:
+
+	unsigned int gpio_num;
+
+	std::stringstream base_path;
+	std::fstream value_file;
+	std::fstream direction_file;
+	bool close_action; // True set to input and release, false do nothing
+};
+
+class spidev {
+	public:
+
+	spidev(std::string dev_name);
+	~spidev();
+
+	void send(char *wbuf, char *rbuf, unsigned int nbytes);
+
+	private:
+
+	int fd;
+
+};
+
+gpio::gpio(unsigned int _gpio_num, gpio_direction pin_direction, bool close_action)
+{
+	std::fstream export_file;
+
+	gpio_num = _gpio_num;
+
+	export_file.open("/sys/class/gpio/export", std::ios::out);
+	if (!export_file.is_open())  ///\todo Poor error handling
+		std::cout << "Failed to open gpio export file." << std::endl;
+
+	export_file << gpio_num << std::endl;
+
+	base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush;
+
+	std::string direction_file_name;
+
+	direction_file_name = base_path.str() + "/direction";
+
+	direction_file.open(direction_file_name.c_str()); 
+	if (!direction_file.is_open())
+		std::cout << "Failed to open direction file." << std::endl;
+	if (pin_direction == OUT)
+		direction_file << "out" << std::endl;
+	else
+		direction_file << "in" << std::endl;
+
+	std::string value_file_name;
+
+	value_file_name = base_path.str() + "/value";
+
+	value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out);
+	if (!value_file.is_open())
+		std::cout << "Failed to open value file." << std::endl;
+}
+
+bool gpio::get_value()
+{
+
+	std::string val;
+
+	std::getline(value_file, val);
+	value_file.seekg(0);
+
+	if (val == "0")
+		return false;
+	else if (val == "1")
+		return true;
+	else
+		std::cout << "Data read from value file|" << val << "|" << std::endl;
+
+	return false;
+}
+
+void gpio::set_value(bool state)
+{
+
+	if (state)
+		value_file << "1" << std::endl;
+	else
+		value_file << "0" << std::endl;
+}
+
+gpio::~gpio()
+{
+	if (close_action) {
+		std::fstream unexport_file;
+
+		direction_file << "in" << std::endl;
+
+		unexport_file.open("/sys/class/gpio/unexport", std::ios::out);
+		if (!unexport_file.is_open())  ///\todo Poor error handling
+			std::cout << "Failed to open gpio export file." << std::endl;
+
+		unexport_file << gpio_num << std::endl;
+		
+	 }
+
+}
+
+spidev::spidev(std::string fname)
+{
+	int ret;
+	int mode = 0;
+	int speed = 12000;
+	int bits = 24;
+
+	fd = open(fname.c_str(), O_RDWR);
+
+	ret = ioctl(fd, SPI_IOC_WR_MODE, &mode);
+	ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed);
+	ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits);
+}
+	
+
+spidev::~spidev()
+{
+	close(fd);
+}
+
+void spidev::send(char *buf, char *rbuf, unsigned int nbytes)
+{
+	int ret;
+
+	struct spi_ioc_transfer tr;
+	tr.tx_buf = (unsigned long) buf;
+	tr.rx_buf = (unsigned long) rbuf;
+	tr.len = nbytes;
+	tr.delay_usecs = 0;
+	tr.speed_hz = 12000000;
+	tr.bits_per_word = 24;
+
+	ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);	
+
+}
+
+static void send_config_to_clkgen(gpio &chip_select, const unsigned int data[], unsigned int data_size)
+{
+	spidev spi("/dev/spidev1.0");
+	unsigned int rbuf;
+
+	for (unsigned int i = 0; i < data_size; i++) {
+
+		std::cout << "sending " << std::hex << data[i] << std::endl;
+		chip_select.set_value(0);
+		spi.send((char *)&data[i], (char *)&rbuf, 4);
+		chip_select.set_value(1);
+
+	};
+}
+
+int main(int argc, char *argv[])
+{
+
+	gpio clkgen_select(CLKGEN_SELECT, OUT, true);
+
+	send_config_to_clkgen(clkgen_select, config_data, sizeof(config_data)/sizeof(unsigned int));
+}
+
diff --git a/host/apps/omap_debug/fetch-bin.sh b/host/apps/omap_debug/fetch-bin.sh
new file mode 100755
index 000000000..019ddaaf2
--- /dev/null
+++ b/host/apps/omap_debug/fetch-bin.sh
@@ -0,0 +1,6 @@
+if [ $GHQ ]; then
+	scp $GHQ_USER@astro:/workspace/usrp1-e-dev/u1e.bin /home/root
+else
+	scp -P 8822 balister@192.168.1.10:src/git/fpgapriv/usrp2/top/u1e/build/u1e.bin /home/root
+fi
+sync
diff --git a/host/apps/omap_debug/fetch-kernel.sh b/host/apps/omap_debug/fetch-kernel.sh
new file mode 100755
index 000000000..ce420f3d2
--- /dev/null
+++ b/host/apps/omap_debug/fetch-kernel.sh
@@ -0,0 +1,7 @@
+if [ $GHQ ]; then
+	scp $GHQ_USER@astro:/workspace/usrp1-e-dev/kernel_usrp/arch/arm/boot/uImage /media/mmcblk0p1/uImage
+else
+	scp balister@192.168.1.10:src/git/kernel_usrp/arch/arm/boot/uImage /media/mmcblk0p1/uImage
+fi
+sync
+
diff --git a/host/apps/omap_debug/fetch-module.sh b/host/apps/omap_debug/fetch-module.sh
new file mode 100755
index 000000000..ec28989bd
--- /dev/null
+++ b/host/apps/omap_debug/fetch-module.sh
@@ -0,0 +1,6 @@
+if [ $GHQ ]; then
+	scp $GHQ_USER@astro:/workspace/usrp1-e-dev/kernel_usrp/drivers/misc/usrp_e.ko /lib/modules/2.6.33/kernel/drivers/misc
+else
+	scp balister@192.168.1.10:src/git/kernel_usrp/drivers/misc/usrp_e.ko /lib/modules/2.6.33/kernel/drivers/misc
+fi
+sync
diff --git a/host/apps/omap_debug/fetch-u-boot.sh b/host/apps/omap_debug/fetch-u-boot.sh
new file mode 100755
index 000000000..5309364b8
--- /dev/null
+++ b/host/apps/omap_debug/fetch-u-boot.sh
@@ -0,0 +1,7 @@
+if [ $GHQ ]; then
+	scp $GHQ_USER@astro:/workspace/usrp1-e-dev/u-boot-overo/u-boot.bin /media/mmcblk0p1/
+else
+	scp balister@192.168.1.167:src/git/u-boot/u-boot.bin /media/mmcblk0p1/ 
+fi
+sync
+
diff --git a/host/apps/omap_debug/fpga-downloader.cc b/host/apps/omap_debug/fpga-downloader.cc
new file mode 100644
index 000000000..4e475b5c1
--- /dev/null
+++ b/host/apps/omap_debug/fpga-downloader.cc
@@ -0,0 +1,253 @@
+/* -*- c++ -*- */
+/*
+ * Copyright 2003,2004,2008,2009 Free Software Foundation, Inc.
+ *
+ * This file is part of GNU Radio
+ *
+ * GNU Radio is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3, or (at your option)
+ * any later version.
+ *
+ * GNU Radio is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with GNU Radio; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+*/
+
+#include <iostream>
+#include <sstream>
+#include <fstream>
+#include <string>
+#include <cstdlib>
+
+#include <fcntl.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/ioctl.h>
+
+#include <linux/spi/spidev.h>
+
+/*
+ * Configuration connections
+ *
+ * CCK    - MCSPI1_CLK
+ * DIN    - MCSPI1_MOSI
+ * PROG_B - GPIO_175     - output (change mux)
+ * DONE   - GPIO_173     - input  (change mux)
+ * INIT_B - GPIO_114     - input  (change mux)
+ *
+*/
+
+const unsigned int PROG_B = 175;
+const unsigned int DONE   = 173;
+const unsigned int INIT_B = 114;
+
+static std::string bit_file = "safe_u1e.bin";
+
+const int BUF_SIZE = 4096;
+
+enum gpio_direction {IN, OUT};
+
+class gpio {
+	public:
+
+	gpio(unsigned int gpio_num, gpio_direction pin_direction);
+
+	bool get_value();
+	void set_value(bool state);
+
+	private:
+
+	std::stringstream base_path;
+	std::fstream value_file;	
+};
+
+class spidev {
+	public:
+
+	spidev(std::string dev_name);
+	~spidev();
+
+	void send(char *wbuf, char *rbuf, unsigned int nbytes);
+
+	private:
+
+	int fd;
+
+};
+
+gpio::gpio(unsigned int gpio_num, gpio_direction pin_direction)
+{
+	std::fstream export_file;
+
+	export_file.open("/sys/class/gpio/export", std::ios::out);
+	if (!export_file.is_open())  ///\todo Poor error handling
+		std::cout << "Failed to open gpio export file." << std::endl;
+
+	export_file << gpio_num << std::endl;
+
+	base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush;
+
+	std::fstream direction_file;
+	std::string direction_file_name;
+
+	if (gpio_num != 114) {
+		direction_file_name = base_path.str() + "/direction";
+
+		direction_file.open(direction_file_name.c_str()); 
+		if (!direction_file.is_open())
+			std::cout << "Failed to open direction file." << std::endl;
+		if (pin_direction == OUT)
+			direction_file << "out" << std::endl;
+		else
+			direction_file << "in" << std::endl;
+	}
+
+	std::string value_file_name;
+
+	value_file_name = base_path.str() + "/value";
+
+	value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out);
+	if (!value_file.is_open())
+		std::cout << "Failed to open value file." << std::endl;
+}
+
+bool gpio::get_value()
+{
+
+	std::string val;
+
+	std::getline(value_file, val);
+	value_file.seekg(0);
+
+	if (val == "0")
+		return false;
+	else if (val == "1")
+		return true;
+	else
+		std::cout << "Data read from value file|" << val << "|" << std::endl;
+
+	return false;
+}
+
+void gpio::set_value(bool state)
+{
+
+	if (state)
+		value_file << "1" << std::endl;
+	else
+		value_file << "0" << std::endl;
+}
+
+static void prepare_fpga_for_configuration(gpio &prog, gpio &init)
+{
+
+	prog.set_value(true);
+	prog.set_value(false);
+	prog.set_value(true);
+
+#if 0
+	bool ready_to_program(false);
+	unsigned int count(0);
+	do {
+		ready_to_program = init.get_value();
+		count++;
+
+		sleep(1);
+	} while (count < 10 && !ready_to_program);
+
+	if (count == 10) {
+		std::cout << "FPGA not ready for programming." << std::endl;
+		exit(-1);
+	}
+#endif
+}
+
+spidev::spidev(std::string fname)
+{
+	int ret;
+	int mode = 0;
+	int speed = 12000000;
+	int bits = 8;
+
+	fd = open(fname.c_str(), O_RDWR);
+
+	ret = ioctl(fd, SPI_IOC_WR_MODE, &mode);
+	ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed);
+	ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits);
+}
+	
+
+spidev::~spidev()
+{
+	close(fd);
+}
+
+void spidev::send(char *buf, char *rbuf, unsigned int nbytes)
+{
+	int ret;
+
+	struct spi_ioc_transfer tr;
+	tr.tx_buf = (unsigned long) buf;
+	tr.rx_buf = (unsigned long) rbuf;
+	tr.len = nbytes;
+	tr.delay_usecs = 0;
+	tr.speed_hz = 48000000;
+	tr.bits_per_word = 8;
+
+	ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);	
+
+}
+
+static void send_file_to_fpga(std::string &file_name, gpio &error, gpio &done)
+{
+	std::ifstream bitstream;
+
+	std::cout << "File name - " << file_name.c_str() << std::endl;
+
+	bitstream.open(file_name.c_str(), std::ios::binary);
+	if (!bitstream.is_open())
+		std::cout << "File " << file_name << " not opened succesfully." << std::endl;
+
+	spidev spi("/dev/spidev1.0");
+	char buf[BUF_SIZE];
+	char rbuf[BUF_SIZE];
+
+	do {
+		bitstream.read(buf, BUF_SIZE);
+		spi.send(buf, rbuf, bitstream.gcount());
+
+		if (error.get_value())
+			std::cout << "INIT_B went high, error occured." << std::endl;
+
+		if (!done.get_value())
+			std::cout << "Configuration complete." << std::endl;
+
+	} while (bitstream.gcount() == BUF_SIZE);
+}
+
+int main(int argc, char *argv[])
+{
+
+	gpio gpio_prog_b(PROG_B, OUT);
+	gpio gpio_init_b(INIT_B, IN);
+	gpio gpio_done  (DONE,   IN);
+
+	if (argc == 2)
+		bit_file = argv[1];
+
+	std::cout << "FPGA config file: " << bit_file << std::endl;
+
+	prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b);
+
+	std::cout << "Done = " << gpio_done.get_value() << std::endl;
+
+	send_file_to_fpga(bit_file, gpio_init_b, gpio_done);
+}
+
diff --git a/host/apps/omap_debug/read_board_id.sh b/host/apps/omap_debug/read_board_id.sh
new file mode 100755
index 000000000..96081f219
--- /dev/null
+++ b/host/apps/omap_debug/read_board_id.sh
@@ -0,0 +1,10 @@
+#!/bin/sh
+
+i2cget -y 3 0x51 0x00 b
+i2cget -y 3 0x51 0x01 b
+i2cget -y 3 0x51 0x02 b
+i2cget -y 3 0x51 0x03 b
+i2cget -y 3 0x51 0x04 b
+i2cget -y 3 0x51 0x05 b
+
+
diff --git a/host/apps/omap_debug/reload-fpga.sh b/host/apps/omap_debug/reload-fpga.sh
new file mode 100755
index 000000000..2754718a4
--- /dev/null
+++ b/host/apps/omap_debug/reload-fpga.sh
@@ -0,0 +1,7 @@
+#!/bin/sh
+
+rmmod usrp_e
+fpga-downloader /home/root/u1e.bin
+modprobe usrp_e
+usrp-e-debug-pins 1
+
diff --git a/host/apps/omap_debug/set_debug_pins.py b/host/apps/omap_debug/set_debug_pins.py
new file mode 100755
index 000000000..0f9ecd7b9
--- /dev/null
+++ b/host/apps/omap_debug/set_debug_pins.py
@@ -0,0 +1,35 @@
+#!/usr/bin/python
+
+import os
+
+# Memory Map
+misc_base = 0
+uart_base = 1
+spi_base = 2
+i2c_base = 3
+gpio_base = 4 * 128
+settings_base = 5
+
+# GPIO offset
+gpio_pins = 0
+gpio_ddr = 4
+gpio_ctrl_lo = 8
+gpio_ctrl_hi = 12
+
+def set_reg(reg, val):
+    os.system("./usrp1-e-ctl w %d 1 %d" % (reg,val))
+
+def get_reg(reg):
+    fin,fout = os.popen4("./usrp1-e-ctl r %d 1" % (reg,))
+    print fout.read()
+
+# Set DDRs to output
+set_reg(gpio_base+gpio_ddr, 0xFFFF)
+set_reg(gpio_base+gpio_ddr+2, 0xFFFF)
+
+# Set CTRL to Debug #0 ( A is for debug 0, F is for debug 1 )
+set_reg(gpio_base+gpio_ctrl_lo, 0xAAAA)
+set_reg(gpio_base+gpio_ctrl_lo+2, 0xAAAA)
+set_reg(gpio_base+gpio_ctrl_hi, 0xAAAA)
+set_reg(gpio_base+gpio_ctrl_hi+2, 0xAAAA)
+
diff --git a/host/apps/omap_debug/setup-board-id-eeprom.sh b/host/apps/omap_debug/setup-board-id-eeprom.sh
new file mode 100755
index 000000000..4dba1cce5
--- /dev/null
+++ b/host/apps/omap_debug/setup-board-id-eeprom.sh
@@ -0,0 +1,17 @@
+#!/bin/sh
+
+i2cset -y 3 0x51 0x00 0x00
+i2cset -y 3 0x51 0x01 0x03
+i2cset -y 3 0x51 0x02 0x00
+i2cset -y 3 0x51 0x03 0x01
+i2cset -y 3 0x51 0x04 0x01
+i2cset -y 3 0x51 0x05 0x00
+i2cset -y 3 0x51 0x06 0x00
+
+i2cget -y 3 0x51 0 b  
+i2cget -y 3 0x51 1 b  
+i2cget -y 3 0x51 2 b  
+i2cget -y 3 0x51 3 b  
+i2cget -y 3 0x51 4 b  
+i2cget -y 3 0x51 5 b  
+i2cget -y 3 0x51 6 b  
diff --git a/host/apps/omap_debug/test.c b/host/apps/omap_debug/test.c
new file mode 100644
index 000000000..36f4d700a
--- /dev/null
+++ b/host/apps/omap_debug/test.c
@@ -0,0 +1,34 @@
+#include <stdio.h>
+
+void
+main()
+{
+  int x;
+  char *y;
+  long long z;
+
+  x = 0x01020304;
+  z = 0x0102030405060708LL;
+
+  printf("%x\n",x);
+  y = (char *)&x;
+  printf("%x\n",y[0]);
+  printf("%x\n",y[1]);
+  printf("%x\n",y[2]);
+  printf("%x\n",y[3]);
+
+  printf("Printing z ...\n");
+  printf("%llx\n",z);
+  printf("Printing z done\n");
+
+  y = (char *)&z;
+  printf("%x\n",y[0]);
+  printf("%x\n",y[1]);
+  printf("%x\n",y[2]);
+  printf("%x\n",y[3]);
+  printf("%x\n",y[4]);
+  printf("%x\n",y[5]);
+  printf("%x\n",y[6]);
+  printf("%x\n",y[7]);
+}
+
diff --git a/host/apps/omap_debug/u1e-read-stream.c b/host/apps/omap_debug/u1e-read-stream.c
new file mode 100644
index 000000000..4e4c21d9e
--- /dev/null
+++ b/host/apps/omap_debug/u1e-read-stream.c
@@ -0,0 +1,21 @@
+#include <stdio.h>
+#include <sys/types.h>
+#include <fcntl.h>
+
+int main(int rgc, char *argv[])
+{
+	int fp, cnt, n;
+	short buf[1024];
+
+	n = 0;
+
+	fp = open("/dev/usrp1_e0", O_RDONLY);
+	printf("fp = %d\n", fp);
+
+	do {
+		cnt = read(fp, buf, 2048);
+		n++;
+//		printf("Bytes read - %d\n", cnt);
+	} while(n < 10*512);
+	printf("Data - %hX\n", buf[0]);
+}
diff --git a/host/apps/omap_debug/usrp-e-button.c b/host/apps/omap_debug/usrp-e-button.c
new file mode 100644
index 000000000..f13291491
--- /dev/null
+++ b/host/apps/omap_debug/usrp-e-button.c
@@ -0,0 +1,56 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/types.h>
+#include <fcntl.h>
+#include <string.h>
+#include <sys/ioctl.h>
+#include <unistd.h>
+
+#include "usrp_e.h"
+#include "usrp_e_regs.hpp"
+
+// Usage: usrp_e_uart <string>
+
+#define PB1 (1<<8)
+#define PB2 (1<<9)
+#define PB3 (1<<10)
+#define P1 (0)
+#define P2 (0xFF)
+#define P3 (0xAA)
+#define P4 (0x55)
+
+int main(int argc, char *argv[])
+{
+	int fp, ret;
+	struct usrp_e_ctl16 d;
+	int pb1=0, pb2=0, pb3=0, p1=0, p2=0, p3=0, p4=0;
+
+	fp = open("/dev/usrp_e0", O_RDWR);
+	printf("fp = %d\n", fp);
+
+	d.offset = UE_REG_MISC_SW;
+	d.count = 1;
+
+	do {
+		ret = ioctl(fp, USRP_E_READ_CTL16, &d);
+		if (d.buf[0] & PB1) {
+			pb1 = 1;
+			printf("Pushbutton 1 hit\n");
+		}
+
+		if (d.buf[0] & PB2) {
+			pb2 = 1;
+			printf("Pushbutton 2 hit\n");
+		}
+
+		if (d.buf[0] & PB3) {
+			pb3 = 1;
+			printf("Pushbutton 3 hit\n");
+		}
+
+		sleep(1);
+
+	} while (!(pb1 && pb2 && pb3));
+
+	return 0;
+}
diff --git a/host/apps/omap_debug/usrp-e-crc-rw.c b/host/apps/omap_debug/usrp-e-crc-rw.c
new file mode 100644
index 000000000..c3ae45cc1
--- /dev/null
+++ b/host/apps/omap_debug/usrp-e-crc-rw.c
@@ -0,0 +1,274 @@
+#include <stdio.h>
+#include <sys/types.h>
+#include <sys/time.h>
+#include <sys/ioctl.h>
+#include <string.h>
+#include <fcntl.h>
+#include <pthread.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <stddef.h>
+#include "usrp_e.h"
+
+// max length #define PKT_DATA_LENGTH 1016
+static int packet_data_length;
+
+static int fp;
+static u_int32_t crc_tab[256];
+
+// CRC code from http://www.koders.com/c/fid699AFE0A656F0022C9D6B9D1743E697B69CE5815.aspx
+// GPLv2
+
+static u_int32_t chksum_crc32_gentab(void)
+{
+	unsigned long crc, poly;
+	unsigned long i, j;
+
+	poly = 0xEDB88320L;
+
+	for (i = 0; i < 256; i++) {
+		crc = i;
+		for (j = 8; j > 0; j--) {
+			if (crc & 1) {
+				crc = (crc >> 1) ^ poly;
+			} else {
+				crc >>= 1;
+			}
+		}
+		crc_tab[i] = crc;
+	}
+
+	return 0;
+}
+
+static void *read_thread(void *threadid)
+{
+	int cnt;
+	struct usrp_transfer_frame *rx_data;
+	int rx_pkt_cnt;
+	int i;
+	unsigned long crc;
+	unsigned int rx_crc;
+	unsigned long bytes_transfered, elapsed_seconds;
+	struct timeval start_time, finish_time;
+
+	__u8 *p;
+	__u32 *pi;
+
+	printf("Greetings from the reading thread!\n");
+
+	// IMPORTANT: must assume max length packet from fpga
+	rx_data = malloc(2048);
+
+	rx_pkt_cnt = 0;
+
+	bytes_transfered = 0;
+	gettimeofday(&start_time, NULL);
+
+	while (1) {
+		
+		cnt = read(fp, rx_data, 2048);
+		if (cnt < 0)
+			printf("Error returned from read: %d\n", cnt);
+
+		rx_pkt_cnt++;
+
+#if 0
+		if (rx_pkt_cnt  == 512) {
+			printf(".");
+			fflush(stdout);
+			rx_pkt_cnt = 0;
+		}
+#endif
+
+		if (rx_data->status & RB_OVERRUN)
+			printf("O");
+
+		printf("rx_data->len = %d\n", rx_data->len);
+
+	
+		crc = 0xFFFFFFFF;
+		for (i = 0; i < rx_data->len - 4; i+=2) {
+			crc = ((crc >> 8) & 0x00FFFFFF) ^
+				crc_tab[(crc ^ rx_data->buf[i+1]) & 0xFF];
+printf("idx = %d, data = %X, crc = %X\n", i, rx_data->buf[i+1],crc);
+			crc = ((crc >> 8) & 0x00FFFFFF) ^
+				crc_tab[(crc ^ rx_data->buf[i]) & 0xFF];
+printf("idx = %d, data = %X, crc = %X\n", i, rx_data->buf[i],crc);
+		}
+
+		p = &rx_data->buf[rx_data->len - 4];
+		pi = (__u32 *) p;
+		rx_crc = *pi;
+
+#if 1
+		printf("rx_data->len = %d\n", rx_data->len);
+		printf("rx_data->status = %d\n", rx_data->status);
+		for (i = 0; i < rx_data->len; i++)
+			printf("idx = %d, data = %X\n", i, rx_data->buf[i]);
+		printf("calc crc = %lX, rx crc = %X\n", crc, rx_crc); 
+		fflush(stdout);
+		break;
+#endif
+
+		if (rx_crc != (crc & 0xFFFFFFFF)) {
+			printf("CRC Error, calc crc: %X, rx_crc: %X\n",
+				(crc & 0xFFFFFFFF), rx_crc);
+		}
+
+		bytes_transfered += rx_data->len;
+
+		if (bytes_transfered > (100 * 1000000)) {
+			gettimeofday(&finish_time, NULL);
+			elapsed_seconds = finish_time.tv_sec - start_time.tv_sec;
+
+			printf("Bytes transfered = %ld, elapsed seconds = %ld\n", bytes_transfered, elapsed_seconds);
+			printf("RX data transfer rate = %f K Samples/second\n",
+				(float) bytes_transfered / (float) elapsed_seconds / 250);
+
+
+			start_time = finish_time;
+			bytes_transfered = 0;
+		}
+	}	
+}
+	
+static void *write_thread(void *threadid)
+{
+	int seq_number, i, cnt, tx_pkt_cnt;
+	int tx_len;
+	unsigned long crc;
+	struct usrp_transfer_frame *tx_data;
+	unsigned long bytes_transfered, elapsed_seconds;
+	struct timeval start_time, finish_time;
+
+	printf("Greetings from the write thread!\n");
+
+	tx_pkt_cnt = 0;
+	tx_data = malloc(2048);
+
+	bytes_transfered = 0;
+	gettimeofday(&start_time, NULL);
+
+	while (1) {
+
+		tx_pkt_cnt++;
+
+#if 0
+		if (tx_pkt_cnt  == 512) {
+			printf(".");
+			fflush(stdout);
+		}
+		if (tx_pkt_cnt  == 1024) {
+			printf("'");
+			fflush(stdout);
+		}
+		if (tx_pkt_cnt  == 1536) {
+			printf(":");
+			fflush(stdout);
+			tx_pkt_cnt = 0;
+		}
+#endif
+
+		tx_len = 2048 - sizeof(struct usrp_transfer_frame) - sizeof(int);
+		tx_data->len = tx_len + sizeof(int);
+
+		crc = 0xFFFFFFFF;
+		for (i = 0; i < tx_len; i++) {
+			tx_data->buf[i] = i & 0xFF;
+
+			crc = ((crc >> 8) & 0x00FFFFFF) ^
+				crc_tab[(crc ^ tx_data->buf[i]) & 0xFF];
+
+		}
+		*((int *) &tx_data[tx_len]) = crc;
+
+		cnt = write(fp, tx_data, 2048);
+		if (cnt < 0)
+			printf("Error returned from write: %d\n", cnt);
+
+
+		bytes_transfered += tx_data->len;
+
+		if (bytes_transfered > (100 * 1000000)) {
+			gettimeofday(&finish_time, NULL);
+			elapsed_seconds = finish_time.tv_sec - start_time.tv_sec;
+
+			printf("Bytes transfered = %d, elapsed seconds = %d\n", bytes_transfered, elapsed_seconds);
+			printf("TX data transfer rate = %f K Samples/second\n",
+				(float) bytes_transfered / (float) elapsed_seconds / 250);
+
+
+			start_time = finish_time;
+			bytes_transfered = 0;
+		}
+
+//		sleep(1);
+	}
+}
+
+
+int main(int argc, char *argv[])
+{
+	pthread_t tx, rx;
+	long int t;
+	int fpga_config_flag ,decimation;
+	struct usrp_e_ctl16 d;
+	struct sched_param s = {
+		.sched_priority = 1
+	};
+
+	if (argc < 4) {
+		printf("%s t|w|rw decimation data_size\n", argv[0]);
+		return -1;
+	}
+
+	chksum_crc32_gentab();
+
+	decimation = atoi(argv[2]);
+	packet_data_length = atoi(argv[3]);
+
+	fp = open("/dev/usrp_e0", O_RDWR);
+	printf("fp = %d\n", fp);
+
+	fpga_config_flag = 0;
+	if (strcmp(argv[1], "w") == 0)
+		fpga_config_flag |= (1 << 15);
+	else if (strcmp(argv[1], "r") == 0)
+		fpga_config_flag |= (1 << 14);
+	else if (strcmp(argv[1], "rw") == 0)
+		fpga_config_flag |= ((1 << 15) | (1 << 14));
+
+	fpga_config_flag |= decimation;
+
+	d.offset = 14;
+	d.count = 1;
+	d.buf[0] = fpga_config_flag;
+	ioctl(fp, USRP_E_WRITE_CTL16, &d);
+
+	sleep(1); // in case the kernel threads need time to start. FIXME if so
+
+	sched_setscheduler(0, SCHED_RR, &s);
+
+	if (fpga_config_flag & (1 << 14)) {
+		if (pthread_create(&rx, NULL, read_thread, (void *) t)) {
+			printf("Failed to create rx thread\n");
+			exit(-1);
+		}
+	}
+
+	sleep(1);
+
+	if (fpga_config_flag & (1 << 15)) {
+		if (pthread_create(&tx, NULL, write_thread, (void *) t)) {
+			printf("Failed to create tx thread\n");
+			exit(-1);
+		}
+	}
+
+	sleep(10000);
+
+	printf("Done sleeping\n");
+
+	return 0;
+}
diff --git a/host/apps/omap_debug/usrp-e-ctl.c b/host/apps/omap_debug/usrp-e-ctl.c
new file mode 100644
index 000000000..69c48ee6f
--- /dev/null
+++ b/host/apps/omap_debug/usrp-e-ctl.c
@@ -0,0 +1,48 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/types.h>
+#include <fcntl.h>
+#include <sys/ioctl.h>
+
+#include "usrp_e.h"
+
+// Usage: usrp_e_ctl w|r offset number_of_values val1 val2 ....
+
+int main(int argc, char *argv[])
+{
+	int fp, i, cnt, ret;
+	struct usrp_e_ctl16 ctl_data;
+
+	if (argc < 4) {
+		printf("Usage: usrp_e_ctl w|r offset number_of_values val1 val2 ....\n");
+		exit(-1);
+	}
+
+	cnt = atoi(argv[3]);
+
+	ctl_data.offset = atoi(argv[2]);
+	ctl_data.count  = cnt;
+
+	fp = open("/dev/usrp_e0", O_RDWR);
+	printf("fp = %d\n", fp);
+
+	if (*argv[1] == 'w') {
+		for (i=0; i<cnt; i++)
+			ctl_data.buf[i] = atoi(argv[4+i]);
+
+		ret = ioctl(fp, USRP_E_WRITE_CTL16, &ctl_data);
+		printf("Return value from write ioctl = %d\n", ret);
+	}
+
+	if (*argv[1] == 'r') {
+		ret = ioctl(fp, USRP_E_READ_CTL16, &ctl_data);
+		printf("Return value from write ioctl = %d\n", ret);
+
+		for (i=0; i<ctl_data.count; i++) {
+			if (!(i%8))
+				printf("\nData at %4d :", i);
+			printf(" %5d", ctl_data.buf[i]);
+		}
+		printf("\n");
+	}
+}
diff --git a/host/apps/omap_debug/usrp-e-debug-pins.c b/host/apps/omap_debug/usrp-e-debug-pins.c
new file mode 100644
index 000000000..d18bbf990
--- /dev/null
+++ b/host/apps/omap_debug/usrp-e-debug-pins.c
@@ -0,0 +1,77 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include <fcntl.h>
+#include <string.h>
+#include <sys/ioctl.h>
+
+#include "usrp_e.h"
+#include "usrp_e_regs.hpp"
+
+// Usage: usrp_e_gpio <string>
+
+static int fp;
+
+static int read_reg(__u16 reg)
+{
+	int ret;
+	struct usrp_e_ctl16 d;
+
+	d.offset = reg;
+	d.count = 1;
+	ret = ioctl(fp, USRP_E_READ_CTL16, &d);
+	return d.buf[0];
+}
+
+static void write_reg(__u16 reg, __u16 val)
+{
+	int ret;
+	struct usrp_e_ctl16 d;
+
+	d.offset = reg;
+	d.count = 1;
+	d.buf[0] = val;
+	ret = ioctl(fp, USRP_E_WRITE_CTL16, &d);
+}
+
+int main(int argc, char *argv[])
+{
+	int test;
+
+	test = 0;
+	if (argc < 2) {
+		printf("%s 0|1|off\n", argv[0]);
+	}
+
+        fp = open("/dev/usrp_e0", O_RDWR);
+        printf("fp = %d\n", fp);
+	if (fp < 0) {
+		perror("Open failed");
+		return -1;
+	}
+
+	if (strcmp(argv[1], "0") == 0) {
+		printf("Selected 0 based on %s\n", argv[1]);
+		write_reg(UE_REG_GPIO_TX_DDR, 0xFFFF);
+		write_reg(UE_REG_GPIO_RX_DDR, 0xFFFF);
+		write_reg(UE_REG_GPIO_TX_SEL, 0x0);
+		write_reg(UE_REG_GPIO_RX_SEL, 0x0);
+		write_reg(UE_REG_GPIO_TX_DBG, 0xFFFF);
+		write_reg(UE_REG_GPIO_RX_DBG, 0xFFFF);
+	} else if (strcmp(argv[1], "1") == 0) {
+		printf("Selected 1 based on %s\n", argv[1]);
+		write_reg(UE_REG_GPIO_TX_DDR, 0xFFFF);
+		write_reg(UE_REG_GPIO_RX_DDR, 0xFFFF);
+		write_reg(UE_REG_GPIO_TX_SEL, 0xFFFF);
+		write_reg(UE_REG_GPIO_RX_SEL, 0xFFFF);
+		write_reg(UE_REG_GPIO_TX_DBG, 0xFFFF);
+		write_reg(UE_REG_GPIO_RX_DBG, 0xFFFF);
+	} else {
+		printf("Selected off based on %s\n", argv[1]);
+		write_reg(UE_REG_GPIO_TX_DDR, 0x0);
+		write_reg(UE_REG_GPIO_RX_DDR, 0x0);
+	}
+
+	return 0;
+}
diff --git a/host/apps/omap_debug/usrp-e-gpio.c b/host/apps/omap_debug/usrp-e-gpio.c
new file mode 100644
index 000000000..adef877d3
--- /dev/null
+++ b/host/apps/omap_debug/usrp-e-gpio.c
@@ -0,0 +1,83 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include <fcntl.h>
+#include <string.h>
+#include <sys/ioctl.h>
+
+#include "usrp_e.h"
+#include "usrp_e_regs.hpp"
+
+// Usage: usrp_e_gpio <string>
+
+static int fp;
+
+static int read_reg(__u16 reg)
+{
+	int ret;
+	struct usrp_e_ctl16 d;
+
+	d.offset = reg;
+	d.count = 1;
+	ret = ioctl(fp, USRP_E_READ_CTL16, &d);
+	return d.buf[0];
+}
+
+static void write_reg(__u16 reg, __u16 val)
+{
+	int ret;
+	struct usrp_e_ctl16 d;
+
+	d.offset = reg;
+	d.count = 1;
+	d.buf[0] = val;
+	ret = ioctl(fp, USRP_E_WRITE_CTL16, &d);
+}
+
+int main(int argc, char *argv[])
+{
+	int i, test, data_in;
+
+	test = 0;
+	if (argc > 1)
+		test = 1;
+
+	fp = open("/dev/usrp_e0", O_RDWR);
+	printf("fp = %d\n", fp);
+
+	write_reg(UE_REG_GPIO_TX_DDR, 0x0);
+	write_reg(UE_REG_GPIO_RX_DDR, 0xFFFF);
+
+	for (i=0; i < 16; i++) {
+		write_reg(UE_REG_GPIO_RX_IO, 1 << i);
+		sleep(1);
+		if (test) {
+			data_in = read_reg(UE_REG_GPIO_TX_IO);
+			if (data_in != (1 << i))
+				printf("Read failed, wrote: %X read: %X\n", \
+					1 << i, data_in);
+		}
+	}
+
+	write_reg(UE_REG_GPIO_RX_DDR, 0x0);
+	write_reg(UE_REG_GPIO_TX_DDR, 0xFFFF);
+
+	sleep(1);
+
+	for (i=0; i < 16; i++) {
+		write_reg(UE_REG_GPIO_TX_IO, 1 << i);
+		sleep(1);
+		if (test) {
+			data_in = read_reg(UE_REG_GPIO_RX_IO);
+			if (data_in != (1 << i))
+				printf("Read failed, wrote: %X read: %X\n", \
+					1 << i, data_in);
+		}
+	}
+
+	write_reg(UE_REG_GPIO_RX_DDR, 0x0);
+	write_reg(UE_REG_GPIO_TX_DDR, 0x0);
+
+	return 0;
+}
diff --git a/host/apps/omap_debug/usrp-e-i2c.c b/host/apps/omap_debug/usrp-e-i2c.c
new file mode 100644
index 000000000..da8709ae1
--- /dev/null
+++ b/host/apps/omap_debug/usrp-e-i2c.c
@@ -0,0 +1,87 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include <fcntl.h>
+#include <sys/ioctl.h>
+
+#include "usrp_e.h"
+
+// Usage: usrp_e_i2c w address data0 data1 data 2 ....
+// Usage: usrp_e_i2c r address count
+
+int main(int argc, char *argv[])
+{
+	int fp, ret, i, tmp;
+	struct usrp_e_i2c *i2c_msg;
+	int direction, address, count;
+
+	if (argc < 3) {
+		printf("Usage: usrp-e-i2c w address data0 data1 data2 ...\n");
+		printf("Usage: usrp-e-i2c r address count\n");
+		printf("All addresses and data in hex.\n");
+		exit(-1);
+	}
+
+	if (strcmp(argv[1], "r") == 0) {
+		direction = 0;
+	} else if (strcmp(argv[1], "w") == 0) {
+		direction = 1;
+	} else {
+		return -1;
+	}
+
+	sscanf(argv[2], "%X", &address);
+	printf("Address = %X\n", address);
+
+	fp = open("/dev/usrp_e0", O_RDWR);
+	printf("fp = %d\n", fp);
+	if (fp < 0) {
+		perror("Open failed");
+		return -1;
+	}
+
+//	sleep(1);
+
+	if (direction) {
+		count = argc - 3;
+	} else {
+		sscanf(argv[3], "%X", &count);
+	}
+	printf("Count = %X\n", count);
+
+	i2c_msg = malloc(sizeof(i2c_msg) + count * sizeof(char));
+
+	i2c_msg->addr = address;
+	i2c_msg->len = count;
+
+	for (i = 0; i < count; i++) {
+		i2c_msg->data[i] = i;
+	}
+
+	if (direction) {
+		// Write
+
+		for (i=0; i<count; i++) {
+			sscanf(argv[3+i], "%X", &tmp);
+			i2c_msg->data[i] = tmp;
+		}
+
+		ret = ioctl(fp, USRP_E_I2C_WRITE, i2c_msg);
+		printf("Return value from i2c_write ioctl: %d\n", ret);
+	} else {
+		// Read
+
+		ret = ioctl(fp, USRP_E_I2C_READ, i2c_msg);
+		printf("Return value from i2c_read ioctl: %d\n", ret);
+
+		printf("Ioctl: %d Data read :", ret);
+		for (i=0; i<count; i++) {
+			printf(" %X", i2c_msg->data[i]);
+		}
+		printf("\n");
+			
+	}
+	return 0;
+}
diff --git a/host/apps/omap_debug/usrp-e-lb-test.c b/host/apps/omap_debug/usrp-e-lb-test.c
new file mode 100644
index 000000000..68848064e
--- /dev/null
+++ b/host/apps/omap_debug/usrp-e-lb-test.c
@@ -0,0 +1,58 @@
+#include <stdio.h>
+#include <sys/types.h>
+#include <fcntl.h>
+#include <pthread.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <stddef.h>
+#include "usrp_e.h"
+
+// max length #define PKT_DATA_LENGTH 1016
+
+int main(int argc, char *argv[])
+{
+	struct usrp_transfer_frame *tx_data, *rx_data;
+	int i, fp, packet_data_length, cnt;
+	struct usrp_e_ctl16 d;
+
+	if (argc < 2) {
+		printf("%s data_size (in bytes < 2040)\n", argv[0]);
+		return -1;
+	}
+
+	packet_data_length = atoi(argv[1]);
+
+	fp = open("/dev/usrp_e0", O_RDWR);
+
+	d.offset = 14;
+	d.count = 1;
+	d.buf[0] = (1 << 13);
+	ioctl(fp, USRP_E_WRITE_CTL16, &d);
+
+	tx_data = malloc(2048);
+	rx_data = malloc(2048);
+
+	tx_data->status = 0;
+	tx_data->len = sizeof(struct usrp_transfer_frame) + packet_data_length;
+
+	while (1) {
+
+		for (i = 0; i < packet_data_length; i++) {
+			tx_data->buf[i] = random() >> 24;
+
+		}
+
+		cnt = write(fp, tx_data, 2048);
+		cnt = read(fp, rx_data, 2048);
+
+		if (tx_data->len != rx_data->len)
+			printf("Bad frame length sent %d, read %d\n", tx_data->len, rx_data->len);
+
+		for (i = 0; i < packet_data_length; i++) {
+			if (tx_data->buf[i] != rx_data->buf[i])
+				printf("Bad data at %d, sent %d, received %d\n", i, tx_data->buf[i], rx_data->buf[i]);
+		}
+		printf("---------------------------------------------------\n");
+		sleep(1);
+	}
+}
diff --git a/host/apps/omap_debug/usrp-e-led.c b/host/apps/omap_debug/usrp-e-led.c
new file mode 100644
index 000000000..d1b6c8996
--- /dev/null
+++ b/host/apps/omap_debug/usrp-e-led.c
@@ -0,0 +1,35 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/types.h>
+#include <fcntl.h>
+#include <string.h>
+#include <sys/ioctl.h>
+#include <unistd.h>
+
+#include "usrp_e.h"
+#include "usrp_e_regs.hpp"
+
+// Usage: usrp_e_uart <string>
+
+
+int main(int argc, char *argv[])
+{
+	int fp, i, ret;
+	struct usrp_e_ctl16 d;
+
+	fp = open("/dev/usrp_e0", O_RDWR);
+	printf("fp = %d\n", fp);
+
+	d.offset = UE_REG_MISC_BASE;
+	d.count = 1;
+
+	while (1) {
+		for (i=0; i<8; i++) {
+			d.buf[0] = i;
+			ret = ioctl(fp, USRP_E_WRITE_CTL16, &d);
+			sleep(1);
+		}
+	}
+
+	return 0;
+}
diff --git a/host/apps/omap_debug/usrp-e-loopback.c b/host/apps/omap_debug/usrp-e-loopback.c
new file mode 100644
index 000000000..d11cf7d09
--- /dev/null
+++ b/host/apps/omap_debug/usrp-e-loopback.c
@@ -0,0 +1,194 @@
+#include <stdio.h>
+#include <sys/types.h>
+#include <fcntl.h>
+#include <pthread.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <stddef.h>
+#include <sys/mman.h>
+#include "usrp_e.h"
+
+// max length #define PKT_DATA_LENGTH 1016
+static int packet_data_length;
+static int error;
+
+struct pkt {
+	int len;
+	int checksum;
+	int seq_num;
+	short data[];
+};
+
+static int fp;
+
+static int calc_checksum(struct pkt *p)
+{
+	int i, sum;
+
+	i = 0;
+	sum = 0;
+
+	for (i=0; i < p->len; i++)
+		sum += p->data[i];
+
+	sum += p->seq_num;
+	sum += p->len;
+
+	return sum;
+}
+
+static void *read_thread(void *threadid)
+{
+	char *rx_data;
+	int cnt, prev_seq_num, pkt_count, seq_num_failure;
+	struct pkt *p;
+	unsigned long bytes_transfered, elapsed_seconds;
+	struct timeval start_time, finish_time;
+
+	printf("Greetings from the reading thread!\n");
+
+	bytes_transfered = 0;
+	gettimeofday(&start_time, NULL);
+
+	// IMPORTANT: must assume max length packet from fpga
+	rx_data = malloc(2048);
+	p = (struct pkt *) ((void *)rx_data);
+
+	prev_seq_num = 0;
+	pkt_count = 0;
+	seq_num_failure = 0;
+
+	while (1) {
+
+		cnt = read(fp, rx_data, 2048);
+		if (cnt < 0)
+			printf("Error returned from read: %d, sequence number = %d\n", cnt, p->seq_num);
+
+//		printf("p->seq_num = %d\n", p->seq_num);
+
+
+		pkt_count++;
+
+		if (p->seq_num != prev_seq_num + 1) {
+			printf("Sequence number fail, current = %d, previous = %d, pkt_count = %d\n",
+				p->seq_num, prev_seq_num, pkt_count);
+
+			seq_num_failure ++;
+			if (seq_num_failure > 2)
+				error = 1;
+		}
+
+		prev_seq_num = p->seq_num;
+
+		if (calc_checksum(p) != p->checksum) {
+			printf("Checksum fail packet = %X, expected = %X, pkt_count = %d\n",
+				calc_checksum(p), p->checksum, pkt_count);
+			error = 1;
+		}
+
+		bytes_transfered += cnt;
+
+		if (bytes_transfered > (100 * 1000000)) {
+			gettimeofday(&finish_time, NULL);
+			elapsed_seconds = finish_time.tv_sec - start_time.tv_sec;
+
+			printf("RX data transfer rate = %f K Samples/second\n",
+				(float) bytes_transfered / (float) elapsed_seconds / 4000);
+
+
+			start_time = finish_time;
+			bytes_transfered = 0;
+		}
+
+
+//		printf(".");
+//		fflush(stdout);
+//		printf("\n");
+	}
+
+}
+
+static void *write_thread(void *threadid)
+{
+	int seq_number, i, cnt;
+	void *tx_data;
+	struct pkt *p;
+
+	printf("Greetings from the write thread!\n");
+
+	tx_data = malloc(2048);
+	p = (struct pkt *) ((void *)tx_data);
+
+	for (i=0; i < packet_data_length; i++)
+//		p->data[i] = random() >> 16;
+		p->data[i] = i;
+
+	seq_number = 1;
+
+	while (1) {
+		p->seq_num = seq_number++;
+
+		if (packet_data_length > 0)
+			p->len = packet_data_length;
+		else
+			p->len = (random() & 0x1ff) + (1004 - 512);
+
+		p->checksum = calc_checksum(p);
+
+		cnt = write(fp, tx_data, p->len * 2 + 12);
+		if (cnt < 0)
+			printf("Error returned from write: %d\n", cnt);
+//		sleep(1);
+	}
+}
+
+
+int main(int argc, char *argv[])
+{
+	pthread_t tx, rx;
+	long int t;
+	struct sched_param s = {
+		.sched_priority = 1
+	};
+	void *rb;
+	struct usrp_transfer_frame *tx_rb, *rx_rb;
+
+	if (argc < 2) {
+		printf("%s data_size\n", argv[0]);
+		return -1;
+	}
+
+	packet_data_length = atoi(argv[1]);
+
+	fp = open("/dev/usrp_e0", O_RDWR);
+	printf("fp = %d\n", fp);
+
+	rb = mmap(0, 202 * 4096, PROT_READ|PROT_WRITE, MAP_SHARED, fp, 0);
+	if (!rb) {
+		printf("mmap failed\n");
+		exit;
+	}
+
+
+	sched_setscheduler(0, SCHED_RR, &s);
+	error = 0;
+
+#if 1
+	if (pthread_create(&rx, NULL, read_thread, (void *) t)) {
+		printf("Failed to create rx thread\n");
+		exit(-1);
+	}
+
+	sleep(1);
+#endif
+
+	if (pthread_create(&tx, NULL, write_thread, (void *) t)) {
+		printf("Failed to create tx thread\n");
+		exit(-1);
+	}
+
+//	while (!error)
+		sleep(1000000000);
+
+	printf("Done sleeping\n");
+}
diff --git a/host/apps/omap_debug/usrp-e-mm-loopback.c b/host/apps/omap_debug/usrp-e-mm-loopback.c
new file mode 100644
index 000000000..f5fc83c87
--- /dev/null
+++ b/host/apps/omap_debug/usrp-e-mm-loopback.c
@@ -0,0 +1,258 @@
+#include <stdio.h>
+#include <sys/types.h>
+#include <sys/ioctl.h>
+#include <fcntl.h>
+#include <pthread.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <stddef.h>
+#include <sys/mman.h>
+#include <poll.h>
+#include "usrp_e.h"
+
+// max length #define PKT_DATA_LENGTH 1016
+static int packet_data_length;
+static int error;
+
+struct pkt {
+	int len;
+	int checksum;
+	int seq_num;
+	short data[1024-6];
+};
+
+struct ring_buffer_info (*rxi)[];
+struct ring_buffer_info (*txi)[];
+struct pkt (*rx_buf)[200];
+struct pkt (*tx_buf)[200];
+
+static int fp;
+static struct usrp_e_ring_buffer_size_t rb_size;
+
+static int calc_checksum(struct pkt *p)
+{
+	int i, sum;
+
+	i = 0;
+	sum = 0;
+
+	for (i=0; i < p->len; i++)
+		sum += p->data[i];
+
+	sum += p->seq_num;
+	sum += p->len;
+
+	return sum;
+}
+
+static void *read_thread(void *threadid)
+{
+	int cnt, prev_seq_num, pkt_count, seq_num_failure;
+	struct pkt *p;
+	unsigned long bytes_transfered, elapsed_seconds;
+	struct timeval start_time, finish_time;
+	int rb_read;
+
+	printf("Greetings from the reading thread!\n");
+	printf("sizeof pkt = %d\n", sizeof(struct pkt));
+
+	rb_read = 0;
+
+	bytes_transfered = 0;
+	gettimeofday(&start_time, NULL);
+
+	prev_seq_num = 0;
+	pkt_count = 0;
+	seq_num_failure = 0;
+
+	while (1) {
+
+		if (!((*rxi)[rb_read].flags & RB_USER)) {
+//			printf("Waiting for data\n");
+			struct pollfd pfd;
+			pfd.fd = fp;
+			pfd.events = POLLIN;
+			ssize_t ret = poll(&pfd, 1, -1);
+		}
+
+//		printf("pkt received, rb_read = %d\n", rb_read);
+
+		cnt = (*rxi)[rb_read].len;
+		p = &(*rx_buf)[rb_read];
+
+//		cnt = read(fp, rx_data, 2048);
+//		if (cnt < 0)
+//			printf("Error returned from read: %d, sequence number = %d\n", cnt, p->seq_num);
+
+//		printf("p = %X, p->seq_num = %d p->len = %d\n", p, p->seq_num, p->len);
+
+
+		pkt_count++;
+
+		if (p->seq_num != prev_seq_num + 1) {
+			printf("Sequence number fail, current = %d, previous = %d, pkt_count = %d\n",
+				p->seq_num, prev_seq_num, pkt_count);
+			printf("pkt received, rb_read = %d\n", rb_read);
+			printf("p = %X, p->seq_num = %d p->len = %d\n", p, p->seq_num, p->len);
+
+			seq_num_failure ++;
+			if (seq_num_failure > 2)
+				error = 1;
+		}
+
+		prev_seq_num = p->seq_num;
+
+		if (calc_checksum(p) != p->checksum) {
+			printf("Checksum fail packet = %X, expected = %X, pkt_count = %d\n",
+				calc_checksum(p), p->checksum, pkt_count);
+			error = 1;
+		}
+
+		(*rxi)[rb_read].flags = RB_KERNEL;
+
+		rb_read++;
+		if (rb_read == rb_size.num_rx_frames)
+			rb_read = 0;
+
+		bytes_transfered += cnt;
+
+		if (bytes_transfered > (100 * 1000000)) {
+			gettimeofday(&finish_time, NULL);
+			elapsed_seconds = finish_time.tv_sec - start_time.tv_sec;
+
+			printf("RX data transfer rate = %f K Samples/second\n",
+				(float) bytes_transfered / (float) elapsed_seconds / 4000);
+
+
+			start_time = finish_time;
+			bytes_transfered = 0;
+		}
+
+
+//		printf(".");
+//		fflush(stdout);
+//		printf("\n");
+	}
+
+}
+
+static void *write_thread(void *threadid)
+{
+	int seq_number, i, cnt, rb_write;
+	void *tx_data;
+	struct pkt *p;
+
+	printf("Greetings from the write thread!\n");
+
+	tx_data = malloc(2048);
+	p = (struct pkt *) ((void *)tx_data);
+
+	for (i=0; i < packet_data_length; i++)
+//		p->data[i] = random() >> 16;
+		p->data[i] = i;
+
+	seq_number = 1;
+	rb_write = 0;
+
+	while (1) {
+		p->seq_num = seq_number++;
+
+		if (packet_data_length > 0)
+			p->len = packet_data_length;
+		else
+			p->len = (random() & 0x1ff) + (1004 - 512);
+
+		p->checksum = calc_checksum(p);
+
+		if (!((*txi)[rb_write].flags & RB_KERNEL)) {
+//			printf("Waiting for space\n");
+			struct pollfd pfd;
+			pfd.fd = fp;
+			pfd.events = POLLOUT;
+			ssize_t ret = poll(&pfd, 1, -1);
+		}
+
+		memcpy(&(*tx_buf)[rb_write], tx_data, p->len * 2 + 12);
+
+		(*txi)[rb_write].len = p->len * 2 + 12;
+		(*txi)[rb_write].flags = RB_USER;
+
+		rb_write++;
+		if (rb_write == rb_size.num_tx_frames)
+			rb_write = 0;
+
+		cnt = write(fp, NULL, 0);
+//		if (cnt < 0)
+//			printf("Error returned from write: %d\n", cnt);
+//		sleep(1);
+	}
+}
+
+
+int main(int argc, char *argv[])
+{
+	pthread_t tx, rx;
+	long int t;
+	struct sched_param s = {
+		.sched_priority = 1
+	};
+	int ret, map_size, page_size;
+	void *rb;
+
+	if (argc < 2) {
+		printf("%s data_size\n", argv[0]);
+		return -1;
+	}
+
+	packet_data_length = atoi(argv[1]);
+
+	fp = open("/dev/usrp_e0", O_RDWR);
+	printf("fp = %d\n", fp);
+
+	page_size = getpagesize();
+
+	ret = ioctl(fp, USRP_E_GET_RB_INFO, &rb_size);
+
+	map_size = (rb_size.num_pages_rx_flags + rb_size.num_pages_tx_flags) * page_size +
+		(rb_size.num_rx_frames + rb_size.num_tx_frames) * (page_size >> 1);
+
+	rb = mmap(0, map_size, PROT_READ|PROT_WRITE, MAP_SHARED, fp, 0);
+	if (rb == MAP_FAILED) {
+		perror("mmap failed");
+		return -1;
+	}
+
+	printf("rb = %X\n", rb);
+
+	rxi = rb;
+	rx_buf = rb + (rb_size.num_pages_rx_flags * page_size);
+	txi = rb +  (rb_size.num_pages_rx_flags * page_size) +
+		(rb_size.num_rx_frames * page_size >> 1);
+	tx_buf = rb +  (rb_size.num_pages_rx_flags * page_size) +
+		(rb_size.num_rx_frames * page_size >> 1) +
+		(rb_size.num_pages_tx_flags * page_size);
+
+	printf("rxi = %X, rx_buf = %X, txi = %X, tx_buf = %X\n", rxi, rx_buf, txi, tx_buf);
+
+	sched_setscheduler(0, SCHED_RR, &s);
+	error = 0;
+
+#if 1
+	if (pthread_create(&rx, NULL, read_thread, (void *) t)) {
+		printf("Failed to create rx thread\n");
+		exit(-1);
+	}
+
+	sleep(1);
+#endif
+
+	if (pthread_create(&tx, NULL, write_thread, (void *) t)) {
+		printf("Failed to create tx thread\n");
+		exit(-1);
+	}
+
+//	while (!error)
+		sleep(1000000000);
+
+	printf("Done sleeping\n");
+}
diff --git a/host/apps/omap_debug/usrp-e-ram.c b/host/apps/omap_debug/usrp-e-ram.c
new file mode 100644
index 000000000..d548f7ccd
--- /dev/null
+++ b/host/apps/omap_debug/usrp-e-ram.c
@@ -0,0 +1,25 @@
+#include <stdio.h>
+#include <sys/types.h>
+#include <fcntl.h>
+
+int main(int rgc, char *argv[])
+{
+	int fp, i, cnt;
+	unsigned short buf[1024];
+	unsigned short buf_rb[1024];
+
+	fp = open("/dev/usrp1_e0", O_RDWR);
+	printf("fp = %d\n", fp);
+
+	for (i=0; i<1024; i++)
+		buf[i] = i*256; 
+	write(fp, buf, 2048);
+	read(fp, buf_rb, 2048);
+
+	printf("Read back %hX %hX\n", buf_rb[0], buf_rb[1]);
+
+	for (i=0; i<1024; i++) {
+		if (buf[i] != buf_rb[i])
+			printf("Read - %hX, expected - %hX\n", buf_rb[i], buf[i]);
+	}
+}
diff --git a/host/apps/omap_debug/usrp-e-random-loopback.c b/host/apps/omap_debug/usrp-e-random-loopback.c
new file mode 100644
index 000000000..5960b8fbd
--- /dev/null
+++ b/host/apps/omap_debug/usrp-e-random-loopback.c
@@ -0,0 +1,149 @@
+#include <stdio.h>
+#include <sys/types.h>
+#include <fcntl.h>
+#include <pthread.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <stddef.h>
+#include "usrp_e.h"
+
+// max length #define PKT_DATA_LENGTH 1014
+static int packet_data_length;
+
+struct pkt {
+	int checksum;
+	int seq_num;
+	int len;
+	short data[];
+};
+
+static int fp;
+
+static int calc_checksum(struct pkt *p)
+{
+	int i, sum;
+
+	i = 0;
+	sum = 0;
+
+	for (i=0; i < p->len; i++)
+		sum += p->data[i];
+
+	sum += p->seq_num;
+
+	return sum;
+}
+
+int randN(int n)
+{
+	long tmp;
+
+	tmp = rand()  % n;
+
+	return tmp;
+}
+
+static void *read_thread(void *threadid)
+{
+	int cnt, prev_seq_num;
+	struct usrp_transfer_frame *rx_data;
+	struct pkt *p;
+
+	printf("Greetings from the reading thread!\n");
+
+	// IMPORTANT: must assume max length packet from fpga
+	rx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (1014 * 2));
+	rx_data = malloc(2048);
+	p = (struct pkt *) ((void *)rx_data + offsetof(struct usrp_transfer_frame, buf));
+	//p = &(rx_data->buf[0]);
+	printf("Address of rx_data = %p, p = %p\n", rx_data, p);
+	printf("offsetof = %d\n", offsetof(struct usrp_transfer_frame, buf));
+	printf("sizeof rx data = %d\n", sizeof(struct usrp_transfer_frame) + sizeof(struct pkt));
+
+	prev_seq_num = 0;
+
+	while (1) {
+
+		cnt = read(fp, rx_data, 2048);
+//		printf("Packet received, status = %X, len = %d\n", rx_data->status, rx_data->len);
+//		printf("p->seq_num = %d\n", p->seq_num);
+
+		if (p->seq_num != prev_seq_num + 1)
+			printf("Sequence number fail, current = %d, previous = %d\n",
+				p->seq_num, prev_seq_num);
+		prev_seq_num = p->seq_num;
+
+		if (calc_checksum(p) != p->checksum)
+			printf("Checksum fail packet = %d, expected = %d\n",
+				calc_checksum(p), p->checksum);
+		printf(".");
+		fflush(stdout);
+//		printf("\n");
+	}
+
+}
+
+static void *write_thread(void *threadid)
+{
+	int seq_number, i, cnt, pkt_cnt;
+	struct usrp_transfer_frame *tx_data;
+	struct pkt *p;
+
+	printf("Greetings from the write thread!\n");
+
+	// Allocate max length buffer for frame
+	tx_data = malloc(2048);
+	p = (struct pkt *) ((void *)tx_data + offsetof(struct usrp_transfer_frame, buf));
+	printf("Address of tx_data = %p, p = %p\n", tx_data, p);
+
+	printf("sizeof rp_transfer_frame = %d, sizeof pkt = %d\n", sizeof(struct usrp_transfer_frame), sizeof(struct pkt));
+
+	for (i=0; i < 1014; i++)
+//		p->data[i] = random() >> 16;
+		p->data[i] = i;
+
+	tx_data->status = 0xdeadbeef;
+	tx_data->len = 8 + packet_data_length * 2;
+
+	printf("tx_data->len = %d\n", tx_data->len);
+
+	seq_number = 1;
+
+	while (1) {
+		pkt_cnt = randN(16);
+		for (i = 0; i < pkt_cnt; i++) {
+			p->seq_num = seq_number++;
+			p->len = randN(1013) + 1;
+			p->checksum = calc_checksum(p);
+			tx_data->len = 12 + p->len * 2;
+			cnt = write(fp, tx_data, tx_data->len + 8);
+		}
+		sleep(random() >> 31);
+	}
+}
+
+
+int main(int argc, char *argv[])
+{
+	pthread_t tx, rx;
+	long int t;
+
+	fp = open("/dev/usrp_e0", O_RDWR);
+	printf("fp = %d\n", fp);
+
+	if (pthread_create(&rx, NULL, read_thread, (void *) t)) {
+		printf("Failed to create rx thread\n");
+		exit(-1);
+	}
+
+	sleep(1);
+
+	if (pthread_create(&tx, NULL, write_thread, (void *) t)) {
+		printf("Failed to create tx thread\n");
+		exit(-1);
+	}
+
+	sleep(1000000000);
+
+	printf("Done sleeping\n");
+}
diff --git a/host/apps/omap_debug/usrp-e-read.c b/host/apps/omap_debug/usrp-e-read.c
new file mode 100644
index 000000000..c28f018d5
--- /dev/null
+++ b/host/apps/omap_debug/usrp-e-read.c
@@ -0,0 +1,18 @@
+#include <stdio.h>
+#include <sys/types.h>
+#include <fcntl.h>
+
+int main(int rgc, char *argv[])
+{
+	int fp, cnt;
+	short buf[1024];
+
+	fp = open("/dev/usrp1_e0", O_RDONLY);
+	printf("fp = %d\n", fp);
+
+	do {
+	cnt = read(fp, buf, 2048);
+//	printf("Bytes read - %d\n", cnt);
+	} while(1);
+	printf("Data - %hX\n", buf[0]);
+}
diff --git a/host/apps/omap_debug/usrp-e-spi.c b/host/apps/omap_debug/usrp-e-spi.c
new file mode 100644
index 000000000..c353c409b
--- /dev/null
+++ b/host/apps/omap_debug/usrp-e-spi.c
@@ -0,0 +1,54 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include <fcntl.h>
+#include <sys/ioctl.h>
+
+#include "usrp_e.h"
+
+// Usage: usrp_e_spi w|rb slave data
+
+int main(int argc, char *argv[])
+{
+	int fp, slave, length, ret;
+	unsigned int data;
+	struct usrp_e_spi spi_dat;
+
+	if (argc < 5) {
+		printf("Usage: usrp_e_spi w|rb slave transfer_length data\n");
+		exit(-1);
+	}
+
+	slave = atoi(argv[2]);
+	length = atoi(argv[3]);
+	data = atoll(argv[4]);
+
+	printf("Data = %X\n", data);
+
+	fp = open("/dev/usrp_e0", O_RDWR);
+	printf("fp = %d\n", fp);
+	if (fp < 0) {
+		perror("Open failed");
+		return -1;
+	}
+
+//	sleep(1);
+
+
+	spi_dat.slave = slave;
+	spi_dat.data = data;
+	spi_dat.length = length;
+	spi_dat.flags = UE_SPI_PUSH_FALL | UE_SPI_LATCH_RISE;
+
+	if (*argv[1] == 'r') {
+		spi_dat.readback = 1;
+		ret = ioctl(fp, USRP_E_SPI, &spi_dat);
+		printf("Ioctl returns: %d, Data returned = %d\n", ret, spi_dat.data);
+	} else {
+		spi_dat.readback = 0;
+		ioctl(fp, USRP_E_SPI, &spi_dat);
+	}
+
+	return 0;
+}
diff --git a/host/apps/omap_debug/usrp-e-timed.c b/host/apps/omap_debug/usrp-e-timed.c
new file mode 100644
index 000000000..3cb33ce2d
--- /dev/null
+++ b/host/apps/omap_debug/usrp-e-timed.c
@@ -0,0 +1,233 @@
+#include <stdio.h>
+#include <sys/types.h>
+#include <fcntl.h>
+#include <pthread.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <stddef.h>
+#include "usrp_e.h"
+
+// max length #define PKT_DATA_LENGTH 1016
+static int packet_data_length;
+
+struct pkt {
+	int checksum;
+	int seq_num;
+	short data[];
+};
+
+static int fp;
+
+static int calc_checksum(struct pkt *p)
+{
+	int i, sum;
+
+	i = 0;
+	sum = 0;
+
+	for (i=0; i < packet_data_length; i++)
+		sum += p->data[i];
+
+	sum += p->seq_num;
+
+	return sum;
+}
+
+static void *read_thread(void *threadid)
+{
+	int cnt, prev_seq_num;
+	struct usrp_transfer_frame *rx_data;
+	struct pkt *p;
+	int rx_pkt_cnt;
+	int i;
+	unsigned long bytes_transfered, elapsed_seconds;
+	struct timeval start_time, finish_time;
+
+	printf("Greetings from the reading thread!\n");
+
+	bytes_transfered = 0;
+	gettimeofday(&start_time, NULL);
+
+	// IMPORTANT: must assume max length packet from fpga
+	rx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (1016 * 2));
+	p = (struct pkt *) ((void *)rx_data + offsetof(struct usrp_transfer_frame, buf));
+	//p = &(rx_data->buf[0]);
+	printf("Address of rx_data = %p, p = %p\n", rx_data, p);
+	printf("offsetof = %d\n", offsetof(struct usrp_transfer_frame, buf));
+	printf("sizeof rx data = %d\n", sizeof(struct usrp_transfer_frame) + sizeof(struct pkt));
+
+	prev_seq_num = 0;
+
+	rx_pkt_cnt = 0;
+
+	while (1) {
+
+		cnt = read(fp, rx_data, 2048);
+		if (cnt < 0)
+			printf("Error returned from read: %d\n", cnt);
+		rx_pkt_cnt++;
+
+#if 0
+		if (rx_pkt_cnt  == 512) {
+			printf(".");
+			fflush(stdout);
+			rx_pkt_cnt = 0;
+		}
+#endif
+
+		if (rx_data->status & RB_OVERRUN)
+			printf("O");
+
+		bytes_transfered += rx_data->len;
+
+		if (bytes_transfered > (100 * 1000000)) {
+			gettimeofday(&finish_time, NULL);
+			elapsed_seconds = finish_time.tv_sec - start_time.tv_sec;
+
+			printf("RX data transfer rate = %f K Samples/second\n",
+				(float) bytes_transfered / (float) elapsed_seconds / 4000);
+
+
+			start_time = finish_time;
+			bytes_transfered = 0;
+                }
+	}
+
+}
+
+static void *write_thread(void *threadid)
+{
+	int seq_number, i, cnt, tx_pkt_cnt;
+	struct usrp_transfer_frame *tx_data;
+	struct pkt *p;
+	unsigned long bytes_transfered, elapsed_seconds;
+	struct timeval start_time, finish_time;
+
+	printf("Greetings from the write thread!\n");
+
+	bytes_transfered = 0;
+	gettimeofday(&start_time, NULL);
+
+	tx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (packet_data_length * 2));
+	p = (struct pkt *) ((void *)tx_data + offsetof(struct usrp_transfer_frame, buf));
+	printf("Address of tx_data = %p, p = %p\n", tx_data, p);
+
+	printf("sizeof rp_transfer_frame = %d, sizeof pkt = %d\n", sizeof(struct usrp_transfer_frame), sizeof(struct pkt));
+
+	for (i=0; i < packet_data_length; i++)
+//		p->data[i] = random() >> 16;
+		p->data[i] = i;
+
+	tx_data->status = 0;
+	tx_data->len = 8 + packet_data_length * 2;
+
+	printf("tx_data->len = %d\n", tx_data->len);
+
+	seq_number = 1;
+	tx_pkt_cnt = 0;
+
+	while (1) {
+
+		tx_pkt_cnt++;
+
+#if 0
+		if (tx_pkt_cnt  == 512) {
+			printf(".");
+			fflush(stdout);
+		}
+		if (tx_pkt_cnt  == 1024) {
+			printf("'");
+			fflush(stdout);
+		}
+		if (tx_pkt_cnt  == 1536) {
+			printf(":");
+			fflush(stdout);
+			tx_pkt_cnt = 0;
+		}
+#endif
+
+//		printf("tx status = %X, len = %d\n", tx_data->status, tx_data->len);
+		p->seq_num = seq_number++;
+		p->checksum = calc_checksum(p);
+		cnt = write(fp, tx_data, 2048);
+		if (cnt < 0)
+			printf("Error returned from write: %d\n", cnt);
+
+		bytes_transfered += tx_data->len;
+
+		if (bytes_transfered > (100 * 1000000)) {
+			gettimeofday(&finish_time, NULL);
+			elapsed_seconds = finish_time.tv_sec - start_time.tv_sec;
+
+			printf("TX data transfer rate = %f K Samples/second\n",
+				(float) bytes_transfered / (float) elapsed_seconds / 4000);
+
+
+			start_time = finish_time;
+			bytes_transfered = 0;
+                }
+//		sleep(1);
+	}
+}
+
+
+int main(int argc, char *argv[])
+{
+	pthread_t tx, rx;
+	long int t;
+	int fpga_config_flag ,decimation;
+	struct usrp_e_ctl16 d;
+	struct sched_param s = {
+		.sched_priority = 1
+	};
+
+	if (argc < 4) {
+		printf("%s r|w|rw decimation data_size\n", argv[0]);
+		return -1;
+	}
+
+	decimation = atoi(argv[2]);
+	packet_data_length = atoi(argv[3]);
+
+	fp = open("/dev/usrp_e0", O_RDWR);
+	printf("fp = %d\n", fp);
+
+	fpga_config_flag = 0;
+	if (strcmp(argv[1], "w") == 0)
+		fpga_config_flag |= (1 << 15);
+	else if (strcmp(argv[1], "r") == 0)
+		fpga_config_flag |= (1 << 14);
+	else if (strcmp(argv[1], "rw") == 0)
+		fpga_config_flag |= ((1 << 15) | (1 << 14));
+
+	fpga_config_flag |= decimation;
+
+	d.offset = 14;
+	d.count = 1;
+	d.buf[0] = fpga_config_flag;
+	ioctl(fp, USRP_E_WRITE_CTL16, &d);
+
+	sleep(1); // in case the kernel threads need time to start. FIXME if so
+
+	sched_setscheduler(0, SCHED_RR, &s);
+
+	if (fpga_config_flag & (1 << 14)) {
+		if (pthread_create(&rx, NULL, read_thread, (void *) t)) {
+			printf("Failed to create rx thread\n");
+			exit(-1);
+		}
+	}
+
+	sleep(1);
+
+	if (fpga_config_flag & (1 << 15)) {
+		if (pthread_create(&tx, NULL, write_thread, (void *) t)) {
+			printf("Failed to create tx thread\n");
+			exit(-1);
+		}
+	}
+
+	sleep(10000);
+
+	printf("Done sleeping\n");
+}
diff --git a/host/apps/omap_debug/usrp-e-uart-rx.c b/host/apps/omap_debug/usrp-e-uart-rx.c
new file mode 100644
index 000000000..24b417980
--- /dev/null
+++ b/host/apps/omap_debug/usrp-e-uart-rx.c
@@ -0,0 +1,53 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/types.h>
+#include <fcntl.h>
+#include <string.h>
+#include <sys/ioctl.h>
+
+#include "usrp_e.h"
+#include "usrp_e_regs.hpp"
+
+// Usage: usrp_e_uart <string>
+
+
+int main(int argc, char *argv[])
+{
+	int fp, ret;
+	struct usrp_e_ctl16 d;
+	__u16 clkdiv;
+
+	if (argc == 0) {
+		printf("Usage: usrp-e-uart-rx <opt clkdiv>\n");
+		printf("clkdiv = 278 is 230.4k \n");
+		printf("clkdiv = 556 is 115.2k \n");
+		exit(-1);
+	}
+
+	fp = open("/dev/usrp_e0", O_RDWR);
+	printf("fp = %d\n", fp);
+
+	if (argc == 2) {
+		clkdiv = atoi(argv[1]);
+		d.offset = UE_REG_UART_CLKDIV;
+		d.count = 1;
+		d.buf[0] = clkdiv;
+		ret = ioctl(fp, USRP_E_WRITE_CTL16, &d);
+	}
+
+	while(1) {
+		d.offset = UE_REG_UART_RXLEVEL;
+		d.count = 1;
+		ret = ioctl(fp, USRP_E_READ_CTL16, &d);
+
+		if (d.buf[0] > 0) {
+			d.offset = UE_REG_UART_RXCHAR;
+			d.count = 1;
+			ret = ioctl(fp, USRP_E_READ_CTL16, &d);
+			printf("%c", d.buf[0]);
+			fflush(stdout);
+		}
+	}
+
+	return 0;
+}
diff --git a/host/apps/omap_debug/usrp-e-uart.c b/host/apps/omap_debug/usrp-e-uart.c
new file mode 100644
index 000000000..2956c407f
--- /dev/null
+++ b/host/apps/omap_debug/usrp-e-uart.c
@@ -0,0 +1,48 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/types.h>
+#include <fcntl.h>
+#include <string.h>
+#include <sys/ioctl.h>
+
+#include "usrp_e.h"
+#include "usrp_e_regs.hpp"
+
+// Usage: usrp_e_uart <string>
+
+
+int main(int argc, char *argv[])
+{
+	int fp, i, ret;
+	struct usrp_e_ctl16 d;
+	char *str = argv[1];
+	__u16 clkdiv;
+
+	if (argc < 2) {
+		printf("Usage: usrp_e_uart <string> <opt clkdiv>\n");
+		printf("clkdiv = 278 is 230.4k \n");
+		printf("clkdiv = 556 is 115.2k \n");
+		exit(-1);
+	}
+
+	fp = open("/dev/usrp_e0", O_RDWR);
+	printf("fp = %d\n", fp);
+
+	if (argc == 3) {
+		clkdiv = atoi(argv[2]);
+		d.offset = UE_REG_UART_CLKDIV;
+		d.count = 1;
+		d.buf[0] = clkdiv;
+		ret = ioctl(fp, USRP_E_WRITE_CTL16, &d);
+	}
+
+	for (i=0; i<strlen(str); i++) {
+		d.offset = UE_REG_UART_TXCHAR;
+		d.count = 1;
+		d.buf[0] = str[i];
+		ret = ioctl(fp, USRP_E_WRITE_CTL16, &d);
+		printf("Wrote %X, to %X, ret = %d\n", d.buf[0], d.offset, ret);
+	}
+
+	return 0;
+}
diff --git a/host/apps/omap_debug/usrp-e-write.c b/host/apps/omap_debug/usrp-e-write.c
new file mode 100644
index 000000000..903c0071f
--- /dev/null
+++ b/host/apps/omap_debug/usrp-e-write.c
@@ -0,0 +1,21 @@
+#include <stdio.h>
+#include <sys/types.h>
+#include <fcntl.h>
+
+int main(int rgc, char *argv[])
+{
+	int fp, i, cnt;
+	short buf[1024];
+
+	fp = open("/dev/usrp1_e0", O_WRONLY);
+	printf("fp = %d\n", fp);
+
+	for (i=0; i<1024; i++) {
+		buf[i] = i;
+	}
+
+//	do {
+		cnt = write(fp, buf, 2048);
+		printf("Bytes written - %d\n", cnt);
+//	} while (1);
+}
diff --git a/host/apps/omap_debug/usrp_e.h b/host/apps/omap_debug/usrp_e.h
new file mode 100644
index 000000000..f96706c4a
--- /dev/null
+++ b/host/apps/omap_debug/usrp_e.h
@@ -0,0 +1,90 @@
+
+/*
+ *  Copyright (C) 2010 Ettus Research, LLC
+ *
+ *  Written by Philip Balister <philip@opensdr.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ */
+
+#ifndef __USRP_E_H
+#define __USRP_E_H
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+struct usrp_e_ctl16 {
+	__u32 offset;
+	__u32 count;
+	__u16 buf[20];
+};
+
+struct usrp_e_ctl32 {
+	__u32 offset;
+	__u32 count;
+	__u32 buf[10];
+};
+
+/* SPI interface */
+
+#define UE_SPI_TXONLY	0
+#define UE_SPI_TXRX	1
+
+/* Defines for spi ctrl register */
+#define UE_SPI_CTRL_TXNEG	(BIT(10))
+#define UE_SPI_CTRL_RXNEG	(BIT(9))
+
+#define UE_SPI_PUSH_RISE	0
+#define UE_SPI_PUSH_FALL	UE_SPI_CTRL_TXNEG
+#define UE_SPI_LATCH_RISE	0
+#define UE_SPI_LATCH_FALL	UE_SPI_CTRL_RXNEG
+#define USRP_E_GET_COMPAT_NUMBER _IO(USRP_E_IOC_MAGIC, 0x28)
+
+#define USRP_E_COMPAT_NUMBER 1
+
+struct usrp_e_spi {
+	__u8 readback;
+	__u32 slave;
+	__u32 data;
+	__u32 length;
+	__u32 flags;
+};
+
+struct usrp_e_i2c {
+	__u8 addr;
+	__u32 len;
+	__u8 data[];
+};
+
+#define USRP_E_IOC_MAGIC	'u'
+#define USRP_E_WRITE_CTL16	_IOW(USRP_E_IOC_MAGIC, 0x20, struct usrp_e_ctl16)
+#define USRP_E_READ_CTL16	_IOWR(USRP_E_IOC_MAGIC, 0x21, struct usrp_e_ctl16)
+#define USRP_E_WRITE_CTL32	_IOW(USRP_E_IOC_MAGIC, 0x22, struct usrp_e_ctl32)
+#define USRP_E_READ_CTL32	_IOWR(USRP_E_IOC_MAGIC, 0x23, struct usrp_e_ctl32)
+#define USRP_E_SPI		_IOWR(USRP_E_IOC_MAGIC, 0x24, struct usrp_e_spi)
+#define USRP_E_I2C_READ		_IOWR(USRP_E_IOC_MAGIC, 0x25, struct usrp_e_i2c)
+#define USRP_E_I2C_WRITE	_IOW(USRP_E_IOC_MAGIC, 0x26, struct usrp_e_i2c)
+#define USRP_E_GET_RB_INFO      _IOR(USRP_E_IOC_MAGIC, 0x27, struct usrp_e_ring_buffer_size_t)
+
+/* Flag defines */
+#define RB_USER (1<<0)
+#define RB_KERNEL (1<<1)
+#define RB_OVERRUN (1<<2)
+#define RB_DMA_ACTIVE (1<<3)
+
+struct ring_buffer_info {
+	int flags;
+	int len;
+};
+
+struct usrp_e_ring_buffer_size_t {
+	int num_pages_rx_flags;
+	int num_rx_frames;
+	int num_pages_tx_flags;
+	int num_tx_frames;
+};
+
+#endif
diff --git a/host/apps/omap_debug/write-eeprom.sh b/host/apps/omap_debug/write-eeprom.sh
new file mode 100755
index 000000000..301b06f07
--- /dev/null
+++ b/host/apps/omap_debug/write-eeprom.sh
@@ -0,0 +1,92 @@
+#!/bin/bash
+
+if [ $# -ne 3 ] && [ $# -ne 5 ];
+then
+	echo "Usage:"
+	echo ""
+	echo "writeprom.sh deviceid rev fab_rev [envvar envsetting]"
+	echo	
+	echo " deviceid   - expansion board device number from table:"
+	echo 
+	echo "   Summit     0x01"
+	echo "   Tobi       0x02"
+	echo "   Tobi Duo   0x03"
+	echo "   Palo35     0x04"
+	echo "   Palo43     0x05"
+	echo "   Chestnut43 0x06"
+	echo "   Pinto      0x07"
+	echo
+	echo " rev          - board revision (e.g. 0x00)"
+	echo " fab_rev      - revision marking from pcb (e.g. R2411)"
+	echo " envvar       - optional u-boot env variable name"
+	echo "                (e.g. dvimode)"
+	echo " envsetting   - optional u-boot env variable setting"
+	echo "                (e.g. 1024x768MR-16@60)"
+	exit 1
+fi
+
+fabrevision=$3
+if [ ${#fabrevision} -ge 8 ]; then
+	echo "Error: fab revision string must less than 8 characters"
+	exit 1
+fi
+
+envvar=$4
+if [ ${#envar} -ge 16 ]; then
+	echo "Error: environment variable name string must less than 16 characters"
+	exit 1
+fi
+
+envsetting=$5
+if [ ${#ensetting} -ge 64 ]; then
+	echo "Error: environment setting string must less than 64 characters"
+	exit 1
+fi
+
+bus=3
+device=0x51
+vendorid=0x03
+
+i2cset -y $bus $device 0x00 0x00
+i2cset -y $bus $device 0x01 $vendorid
+i2cset -y $bus $device 0x02 0x00
+i2cset -y $bus $device 0x03 $1
+i2cset -y $bus $device 0x04 $2
+i2cset -y $bus $device 0x05 00
+
+let i=6
+hexdumpargs="'${#fabrevision}/1 \"0x%02x \"'"
+command="echo -n \"$fabrevision\" | hexdump -e $hexdumpargs"
+hex=$(eval $command)
+for character in $hex; do
+	i2cset -y $bus $device $i $character
+	let i=$i+1
+done
+i2cset -y $bus $device $i 0x00
+
+if [ $# -eq 5 ]
+then
+	i2cset -y $bus $device 0x05 0x01
+
+	let i=14
+	hexdumpargs="'${#envvar}/1 \"0x%02x \"'"
+	command="echo -n \"$envvar\" | hexdump -e $hexdumpargs"
+	hex=$(eval $command)
+	for character in $hex; do
+		i2cset -y $bus $device $i $character
+		let i=$i+1
+	done
+ 	i2cset -y $bus $device $i 0x00
+
+	let i=30
+	hexdumpargs="'${#envsetting}/1 \"0x%02x \"'"
+	command="echo -n \"$envsetting\" | hexdump -e $hexdumpargs"
+	hex=$(eval $command)
+	for character in $hex; do
+		i2cset -y $bus $device $i $character
+		let i=$i+1
+	done	 
+	i2cset -y $bus $device $i 0x00
+fi
+
+
diff --git a/host/apps/omap_debug/write_board_id.sh b/host/apps/omap_debug/write_board_id.sh
new file mode 100755
index 000000000..067269c64
--- /dev/null
+++ b/host/apps/omap_debug/write_board_id.sh
@@ -0,0 +1,10 @@
+#!/bin/sh
+
+i2cset -y 3 0x51 0x00 0x00
+i2cset -y 3 0x51 0x01 0x03
+i2cset -y 3 0x51 0x02 0x00
+i2cset -y 3 0x51 0x03 0x01
+i2cset -y 3 0x51 0x04 0x00
+i2cset -y 3 0x51 0x05 0x00
+
+
diff --git a/host/examples/ascii_art_dft.hpp b/host/examples/ascii_art_dft.hpp
index 92fb77596..ee2267c2d 100644
--- a/host/examples/ascii_art_dft.hpp
+++ b/host/examples/ascii_art_dft.hpp
@@ -28,7 +28,7 @@ namespace acsii_art_dft{
     );
 
     /*!
-     * Convert a DFT to a printable ascii plot.
+     * Convert a DFT to a piroundable ascii plot.
      * \param dft the log power dft bins
      * \param width the frame width in characters
      * \param height the frame height in characters
diff --git a/host/examples/tx_from_file.cpp b/host/examples/tx_from_file.cpp
new file mode 100644
index 000000000..9611cf47c
--- /dev/null
+++ b/host/examples/tx_from_file.cpp
@@ -0,0 +1,125 @@
+//
+// Copyright 2010 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include <uhd/utils/thread_priority.hpp>
+#include <uhd/utils/safe_main.hpp>
+#include <uhd/usrp/simple_usrp.hpp>
+#include <boost/program_options.hpp>
+#include <boost/format.hpp>
+#include <iostream>
+#include <complex>
+#include <fstream>
+
+namespace po = boost::program_options;
+
+int UHD_SAFE_MAIN(int argc, char *argv[]){
+    uhd::set_thread_priority_safe();
+
+    //variables to be set by po
+    std::string args;
+    time_t seconds_in_future;
+    size_t total_num_samps;
+    size_t samps_per_packet;
+    double tx_rate, freq;
+    float ampl;
+    float tx_gain;
+
+    //setup the program options
+    po::options_description desc("Allowed options");
+    desc.add_options()
+        ("help", "help message")
+        ("args", po::value<std::string>(&args)->default_value(""), "simple uhd device address args")
+        ("secs", po::value<time_t>(&seconds_in_future)->default_value(3), "number of seconds in the future to transmit")
+        ("nsamps", po::value<size_t>(&total_num_samps)->default_value(1000), "total number of samples to transmit")
+        ("txrate", po::value<double>(&tx_rate)->default_value(100e6/16), "rate of outgoing samples")
+        ("freq", po::value<double>(&freq)->default_value(0), "rf center frequency in Hz")
+        ("ampl", po::value<float>(&ampl)->default_value(float(0.3)), "amplitude of each sample")
+        ("gain", po::value<float>(&tx_gain)->default_value(float(0)), "amplitude of each sample")
+        ("dilv", "specify to disable inner-loop verbose")
+    ;
+    po::variables_map vm;
+    po::store(po::parse_command_line(argc, argv, desc), vm);
+    po::notify(vm);
+
+    //print the help message
+    if (vm.count("help")){
+        std::cout << boost::format("UHD TX Timed Samples %s") % desc << std::endl;
+        return ~0;
+    }
+
+    bool verbose = vm.count("dilv") == 0;
+
+    //create a usrp device
+    std::cout << std::endl;
+    std::cout << boost::format("Creating the usrp device with: %s...") % args << std::endl;
+    uhd::usrp::simple_usrp::sptr sdev = uhd::usrp::simple_usrp::make(args);
+    uhd::device::sptr dev = sdev->get_device();
+    std::cout << boost::format("Using Device: %s") % sdev->get_pp_string() << std::endl;
+
+    //set properties on the device
+    std::cout << boost::format("Setting TX Rate: %f Msps...") % (tx_rate/1e6) << std::endl;
+    sdev->set_tx_rate(tx_rate);
+    std::cout << boost::format("Actual TX Rate: %f Msps...") % (sdev->get_tx_rate()/1e6) << std::endl;
+    std::cout << boost::format("Setting device timestamp to 0...") << std::endl;
+    sdev->set_tx_freq(freq);
+    sdev->set_time_now(uhd::time_spec_t(0.0));
+
+    sdev->set_tx_gain(tx_gain);
+
+    //allocate data to send
+    std::vector<std::complex<short> > buff;
+    uhd::tx_metadata_t md;
+
+    std::cout << "Read data to send from file: in.dat" << std::endl;
+    std::ifstream infile("in.dat", std::ifstream::binary);
+    while (!infile.eof()) {
+        std::complex<short> c;
+        infile.read((char *)&c, sizeof(std::complex<short>));
+        if (!((c.real() == 0) && (c.imag() == 0))) {
+            buff.push_back(c); 
+//std::cout << "C = " << c << std::endl;
+        }
+    }
+    samps_per_packet = buff.size();
+    infile.close();
+    std::cout << "Number of samples in file: " << samps_per_packet << std::endl;
+
+    //send the data in multiple packets
+    size_t num_packets = (total_num_samps+samps_per_packet-1)/samps_per_packet;
+    for (size_t i = 0; i < num_packets; i++){
+        //setup the metadata flags and time spec
+        md.start_of_burst = true;                  //always SOB (good for continuous streaming)
+        md.end_of_burst   = (i == num_packets-1);  //only last packet has EOB
+        md.has_time_spec  = (i == 0);              //only first packet has time
+        md.time_spec = uhd::time_spec_t(seconds_in_future);
+
+        size_t samps_to_send = std::min(total_num_samps - samps_per_packet*i, samps_per_packet);
+
+        //send the entire packet (driver fragments internally)
+        size_t num_tx_samps = dev->send(
+            &buff.front(), samps_to_send, md,
+            uhd::io_type_t::COMPLEX_INT16,
+            uhd::device::SEND_MODE_FULL_BUFF
+        );
+        if(verbose) std::cout << std::endl << boost::format("Sent %d samples") % num_tx_samps << std::endl;
+    }
+
+    //finished
+    std::cout << std::endl << "Done!" << std::endl << std::endl;
+
+    return 0;
+}
diff --git a/host/include/uhd/usrp/mboard_eeprom.hpp b/host/include/uhd/usrp/mboard_eeprom.hpp
index 530b177be..52363b95c 100644
--- a/host/include/uhd/usrp/mboard_eeprom.hpp
+++ b/host/include/uhd/usrp/mboard_eeprom.hpp
@@ -37,7 +37,8 @@ namespace uhd{ namespace usrp{
         //! Possible EEPROM maps types
         enum map_type{
             MAP_N100,
-            MAP_B000
+            MAP_B000,
+            MAP_E100
         };
 
         //! Make a new empty mboard eeprom
diff --git a/host/include/uhd/utils/pimpl.hpp b/host/include/uhd/utils/pimpl.hpp
index 18454f0c4..09bf0c0a2 100644
--- a/host/include/uhd/utils/pimpl.hpp
+++ b/host/include/uhd/utils/pimpl.hpp
@@ -20,7 +20,6 @@
 
 #include <uhd/config.hpp>
 #include <boost/shared_ptr.hpp>
-#include <boost/make_shared.hpp>
 
 /*! \file pimpl.hpp
  * "Pimpl idiom" (pointer to implementation idiom).
@@ -51,6 +50,6 @@
  * \param _args the constructor args for the pimpl
  */
 #define UHD_PIMPL_MAKE(_name, _args) \
-    boost::make_shared<_name> _args
+    boost::shared_ptr<_name>(new _name _args)
 
 #endif /* INCLUDED_UHD_UTILS_PIMPL_HPP */
diff --git a/host/lib/ic_reg_maps/gen_ad9522_regs.py b/host/lib/ic_reg_maps/gen_ad9522_regs.py
index ed6b5f48d..a5debe568 100755
--- a/host/lib/ic_reg_maps/gen_ad9522_regs.py
+++ b/host/lib/ic_reg_maps/gen_ad9522_regs.py
@@ -134,8 +134,8 @@ reg2eeprom                   0xB03[0]                0
 # Template for methods in the body of the struct
 ########################################################################
 BODY_TMPL="""\
-boost::uint8_t get_reg(boost::uint16_t addr){
-    boost::uint8_t reg = 0;
+boost::uint32_t get_reg(boost::uint16_t addr){
+    boost::uint32_t reg = 0;
     switch(addr){
     #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs)))
     case $addr:
@@ -154,7 +154,7 @@ boost::uint8_t get_reg(boost::uint16_t addr){
     return reg;
 }
 
-void set_reg(boost::uint8_t addr, boost::uint32_t reg){
+void set_reg(boost::uint16_t addr, boost::uint32_t reg){
     switch(addr){
     #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs)))
     case $addr:
diff --git a/host/lib/transport/CMakeLists.txt b/host/lib/transport/CMakeLists.txt
index b9ec7a6ad..b95d46381 100644
--- a/host/lib/transport/CMakeLists.txt
+++ b/host/lib/transport/CMakeLists.txt
@@ -58,6 +58,12 @@ IF(HAVE_EMMINTRIN_H)
     ADD_DEFINITIONS(-DHAVE_EMMINTRIN_H)
 ENDIF(HAVE_EMMINTRIN_H)
 
+INCLUDE(CheckIncludeFileCXX)
+CHECK_INCLUDE_FILE_CXX(arm_neon.h HAVE_ARM_NEON_H)
+
+IF(HAVE_ARM_NEON_H)
+    ADD_DEFINITIONS(-DHAVE_ARM_NEON_H)
+ENDIF(HAVE_ARM_NEON_H)
 ########################################################################
 # Setup defines for interface address discovery
 ########################################################################
diff --git a/host/lib/transport/convert_types_impl.hpp b/host/lib/transport/convert_types_impl.hpp
index 90618dec6..48ff99725 100644
--- a/host/lib/transport/convert_types_impl.hpp
+++ b/host/lib/transport/convert_types_impl.hpp
@@ -32,6 +32,14 @@
     #include <emmintrin.h>
 #endif
 
+#ifdef HAVE_ARM_NEON_H
+    #define USE_ARM_NEON_H
+#endif
+
+#if defined(USE_ARM_NEON_H)
+    #include <arm_neon.h>
+#endif
+
 /***********************************************************************
  * Typedefs
  **********************************************************************/
@@ -135,6 +143,26 @@ static UHD_INLINE void fc32_to_item32_nswap(
     }
 }
 
+#elif defined(USE_ARM_NEON_H)
+static UHD_INLINE void fc32_to_item32_nswap(
+    const fc32_t *input, item32_t *output, size_t nsamps)
+{
+    size_t i;
+
+    float32x4_t Q0 = vdupq_n_f32(shorts_per_float);
+    for (i=0; i < (nsamps & ~0x03); i+=2) {
+        float32x4_t Q1 = vld1q_f32(reinterpret_cast<const float *>(&input[i]));
+        float32x4_t Q2 = vmulq_f32(Q1, Q0);
+        int32x4_t Q3 = vcvtq_s32_f32(Q2);
+        int16x4_t D8 = vmovn_s32(Q3);
+        int16x4_t D9 = vrev32_s16(D8);
+        vst1_s16((reinterpret_cast<int16_t *>(&output[i])), D9);
+    }
+
+    for (; i < nsamps; i++)
+        output[i] = fc32_to_item32(input[i]);
+}
+
 #else
 static UHD_INLINE void fc32_to_item32_nswap(
     const fc32_t *input, item32_t *output, size_t nsamps
@@ -238,6 +266,26 @@ static UHD_INLINE void item32_to_fc32_nswap(
     }
 }
 
+#elif defined(USE_ARM_NEON_H)
+static UHD_INLINE void item32_to_fc32_nswap(
+    const item32_t *input, fc32_t *output, size_t nsamps)
+{
+    size_t i;
+
+    float32x4_t Q1 = vdupq_n_f32(floats_per_short);
+    for (i=0; i < (nsamps & ~0x03); i+=2) {
+        int16x4_t D0 = vld1_s16(reinterpret_cast<const int16_t *>(&input[i]));
+        int16x4_t D1 = vrev32_s16(D0);
+        int32x4_t Q2 = vmovl_s16(D1);
+        float32x4_t Q3 = vcvtq_f32_s32(Q2);
+        float32x4_t Q4 = vmulq_f32(Q3, Q1);
+        vst1q_f32((reinterpret_cast<float *>(&output[i])), Q4);
+    }
+
+    for (; i < nsamps; i++)
+        output[i] = item32_to_fc32(input[i]);
+}
+
 #else
 static UHD_INLINE void item32_to_fc32_nswap(
     const item32_t *input, fc32_t *output, size_t nsamps
diff --git a/host/lib/usrp/CMakeLists.txt b/host/lib/usrp/CMakeLists.txt
index 3d832c356..073b3c80b 100644
--- a/host/lib/usrp/CMakeLists.txt
+++ b/host/lib/usrp/CMakeLists.txt
@@ -35,3 +35,4 @@ LIBUHD_APPEND_SOURCES(
 INCLUDE(${CMAKE_SOURCE_DIR}/lib/usrp/dboard/CMakeLists.txt)
 INCLUDE(${CMAKE_SOURCE_DIR}/lib/usrp/usrp1/CMakeLists.txt)
 INCLUDE(${CMAKE_SOURCE_DIR}/lib/usrp/usrp2/CMakeLists.txt)
+INCLUDE(${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/CMakeLists.txt)
diff --git a/host/lib/usrp/mboard_eeprom.cpp b/host/lib/usrp/mboard_eeprom.cpp
index e7470944c..a9270cda6 100644
--- a/host/lib/usrp/mboard_eeprom.cpp
+++ b/host/lib/usrp/mboard_eeprom.cpp
@@ -18,10 +18,12 @@
 #include <uhd/usrp/mboard_eeprom.hpp>
 #include <uhd/types/mac_addr.hpp>
 #include <uhd/utils/algorithm.hpp>
+#include <uhd/utils/byteswap.hpp>
 #include <boost/asio/ip/address_v4.hpp>
 #include <boost/assign/list_of.hpp>
 #include <boost/lexical_cast.hpp>
 #include <boost/foreach.hpp>
+#include <cstddef>
 
 using namespace uhd;
 using namespace uhd::usrp;
@@ -171,6 +173,85 @@ static void store_b000(const mboard_eeprom_t &mb_eeprom, i2c_iface &iface){
         string_to_bytes(mb_eeprom["name"], NAME_MAX_LEN)
     );
 }
+/***********************************************************************
+ * Implementation of E100 load/store
+ **********************************************************************/
+static const boost::uint8_t E100_EEPROM_ADDR = 0x51;
+
+struct e100_eeprom_map{
+    boost::uint16_t vendor;
+    boost::uint16_t device;
+    unsigned char revision;
+    unsigned char content;
+    unsigned char model[8];
+    unsigned char env_var[16];
+    unsigned char env_setting[64];
+    unsigned char serial[10];
+    unsigned char name[NAME_MAX_LEN];
+};
+
+template <typename T> static const byte_vector_t to_bytes(const T &item){
+    return byte_vector_t(
+        reinterpret_cast<const byte_vector_t::value_type *>(&item),
+        reinterpret_cast<const byte_vector_t::value_type *>(&item)+sizeof(item)
+    );
+}
+
+static void load_e100(mboard_eeprom_t &mb_eeprom, i2c_iface &iface){
+    const size_t num_bytes = offsetof(e100_eeprom_map, model);
+    byte_vector_t map_bytes = iface.read_eeprom(E100_EEPROM_ADDR, 0, num_bytes);
+    e100_eeprom_map map; std::memcpy(&map, &map_bytes[0], map_bytes.size());
+
+    mb_eeprom["vendor"] = boost::lexical_cast<std::string>(uhd::ntohx(map.vendor));
+    mb_eeprom["device"] = boost::lexical_cast<std::string>(uhd::ntohx(map.device));
+    mb_eeprom["revision"] = boost::lexical_cast<std::string>(unsigned(map.revision));
+    mb_eeprom["content"] = boost::lexical_cast<std::string>(unsigned(map.content));
+
+    #define load_e100_string_xx(key) mb_eeprom[#key] = bytes_to_string(iface.read_eeprom( \
+        E100_EEPROM_ADDR, offsetof(e100_eeprom_map, key), sizeof(e100_eeprom_map::key) \
+    ));
+
+    load_e100_string_xx(model);
+    load_e100_string_xx(env_var);
+    load_e100_string_xx(env_setting);
+    load_e100_string_xx(serial);
+    load_e100_string_xx(name);
+}
+
+static void store_e100(const mboard_eeprom_t &mb_eeprom, i2c_iface &iface){
+
+    if (mb_eeprom.has_key("vendor")) iface.write_eeprom(
+        E100_EEPROM_ADDR, offsetof(e100_eeprom_map, vendor),
+        to_bytes(uhd::htonx(boost::lexical_cast<boost::uint16_t>(mb_eeprom["vendor"])))
+    );
+
+    if (mb_eeprom.has_key("device")) iface.write_eeprom(
+        E100_EEPROM_ADDR, offsetof(e100_eeprom_map, device),
+        to_bytes(uhd::htonx(boost::lexical_cast<boost::uint16_t>(mb_eeprom["device"])))
+    );
+
+    if (mb_eeprom.has_key("revision")) iface.write_eeprom(
+        E100_EEPROM_ADDR, offsetof(e100_eeprom_map, revision),
+        byte_vector_t(1, boost::lexical_cast<unsigned>(mb_eeprom["revision"]))
+    );
+
+    if (mb_eeprom.has_key("content")) iface.write_eeprom(
+        E100_EEPROM_ADDR, offsetof(e100_eeprom_map, content),
+        byte_vector_t(1, boost::lexical_cast<unsigned>(mb_eeprom["content"]))
+    );
+
+    #define store_e100_string_xx(key) if (mb_eeprom.has_key(#key)) iface.write_eeprom( \
+        E100_EEPROM_ADDR, offsetof(e100_eeprom_map, key), \
+        string_to_bytes(mb_eeprom[#key], sizeof(e100_eeprom_map::key)) \
+    );
+
+    store_e100_string_xx(model);
+    store_e100_string_xx(env_var);
+    store_e100_string_xx(env_setting);
+    store_e100_string_xx(serial);
+    store_e100_string_xx(name);
+
+}
 
 /***********************************************************************
  * Implementation of mboard eeprom
@@ -183,6 +264,7 @@ mboard_eeprom_t::mboard_eeprom_t(i2c_iface &iface, map_type map){
     switch(map){
     case MAP_N100: load_n100(*this, iface); break;
     case MAP_B000: load_b000(*this, iface); break;
+    case MAP_E100: load_e100(*this, iface); break;
     }
 }
 
@@ -190,5 +272,6 @@ void mboard_eeprom_t::commit(i2c_iface &iface, map_type map){
     switch(map){
     case MAP_N100: store_n100(*this, iface); break;
     case MAP_B000: store_b000(*this, iface); break;
+    case MAP_E100: store_e100(*this, iface); break;
     }
 }
diff --git a/host/lib/usrp/usrp_e100/CMakeLists.txt b/host/lib/usrp/usrp_e100/CMakeLists.txt
new file mode 100644
index 000000000..66c87e0d8
--- /dev/null
+++ b/host/lib/usrp/usrp_e100/CMakeLists.txt
@@ -0,0 +1,60 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+#This file will be included by cmake, use absolute paths!
+
+########################################################################
+# Conditionally configure the USRP-E100 support
+########################################################################
+MESSAGE(STATUS "Configuring USRP-E100 support...")
+
+IF(DEFINED ENABLE_USRP_E100)
+    IF(ENABLE_USRP_E100)
+        MESSAGE(STATUS "USRP-E100 support enabled by configure flag")
+    ELSE(ENABLE_USRP_E100)
+        MESSAGE(STATUS "USRP-E100 support disabled by configure flag")
+    ENDIF(ENABLE_USRP_E100)
+ELSE(DEFINED ENABLE_USRP_E100) #not defined: automatic disabling of component
+    SET(ENABLE_USRP_E100 FALSE)
+ENDIF(DEFINED ENABLE_USRP_E100)
+SET(ENABLE_USRP_E100 ${ENABLE_USRP_E100} CACHE BOOL "enable USRP-E100 support")
+
+IF(ENABLE_USRP_E100)
+    MESSAGE(STATUS "  Building USRP-E100 support.")
+    INCLUDE_DIRECTORIES(${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/include)
+    LIBUHD_APPEND_SOURCES(
+        ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/clock_ctrl.cpp
+        ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/clock_ctrl.hpp
+        ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/codec_ctrl.cpp
+        ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/codec_ctrl.hpp
+        ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/codec_impl.cpp
+        ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/dboard_impl.cpp
+        ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/dboard_iface.cpp
+        ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/dsp_impl.cpp
+        ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/fpga-downloader.cc
+        ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/io_impl.cpp
+        ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/mboard_impl.cpp
+        ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e100_impl.cpp
+        ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e100_impl.hpp
+        ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e100_iface.cpp
+        ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e100_iface.hpp
+        ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e100_mmap_zero_copy.cpp
+        ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e100_regs.hpp
+    )
+ELSE(ENABLE_USRP_E100)
+    MESSAGE(STATUS "  Skipping USRP-E100 support.")
+ENDIF(ENABLE_USRP_E100)
diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp
new file mode 100644
index 000000000..1fb1a7125
--- /dev/null
+++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp
@@ -0,0 +1,263 @@
+//
+// Copyright 2010 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include "clock_ctrl.hpp"
+#include "ad9522_regs.hpp"
+#include <uhd/utils/assert.hpp>
+#include <boost/cstdint.hpp>
+#include "usrp_e100_regs.hpp" //spi slave constants
+#include <boost/assign/list_of.hpp>
+#include <boost/foreach.hpp>
+#include <utility>
+#include <iostream>
+
+using namespace uhd;
+
+template <typename div_type, typename bypass_type> static void set_clock_divider(
+    size_t divider, div_type &low, div_type &high, bypass_type &bypass
+){
+    high = divider/2 - 1;
+    low = divider - high - 2;
+    bypass = (divider == 1)? 1 : 0;
+}
+
+/***********************************************************************
+ * Constants
+ **********************************************************************/
+static const bool enable_test_clock = false;
+static const size_t ref_clock_doubler = 2; //enabled below
+static const double ref_clock_rate = 10e6 * ref_clock_doubler;
+
+static const size_t r_counter = 1;
+static const size_t a_counter = 0;
+static const size_t b_counter = 20 / ref_clock_doubler;
+static const size_t prescaler = 8; //set below with enum, set to 8 when input is under 2400 MHz
+static const size_t vco_divider = 5; //set below with enum
+
+static const size_t n_counter = prescaler * b_counter + a_counter;
+static const size_t vco_clock_rate = ref_clock_rate/r_counter * n_counter; //between 1400 and 1800 MHz
+static const double master_clock_rate = vco_clock_rate/vco_divider;
+
+static const size_t fpga_clock_divider = size_t(master_clock_rate/64e6);
+static const size_t codec_clock_divider = size_t(master_clock_rate/64e6);
+
+/***********************************************************************
+ * Clock Control Implementation
+ **********************************************************************/
+class usrp_e100_clock_ctrl_impl : public usrp_e100_clock_ctrl{
+public:
+    usrp_e100_clock_ctrl_impl(usrp_e100_iface::sptr iface){
+        _iface = iface;
+
+        //init the clock gen registers
+        //Note: out0 should already be clocking the FPGA or this isnt going to work
+        _ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO;
+        _ad9522_regs.enable_clock_doubler = 1; //enable ref clock doubler
+        _ad9522_regs.enb_stat_eeprom_at_stat_pin = 0; //use status pin
+        _ad9522_regs.status_pin_control = 0x1; //n divider
+        _ad9522_regs.ld_pin_control = 0x00; //dld
+        _ad9522_regs.refmon_pin_control = 0x12; //show ref2
+
+        _ad9522_regs.enable_ref2 = 1;
+        _ad9522_regs.enable_ref1 = 0;
+        _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF2;
+
+        _ad9522_regs.set_r_counter(r_counter);
+        _ad9522_regs.a_counter = a_counter;
+        _ad9522_regs.set_b_counter(b_counter);
+        _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV8_9;
+
+        _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL;
+        _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA;
+
+        _ad9522_regs.vco_calibration_now = 1; //calibrate it!
+        _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5;
+        _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_VCO;
+
+        //setup fpga master clock
+        _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS;
+        set_clock_divider(fpga_clock_divider,
+            _ad9522_regs.divider0_low_cycles,
+            _ad9522_regs.divider0_high_cycles,
+            _ad9522_regs.divider0_bypass
+        );
+
+        //setup codec clock
+        _ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS;
+        set_clock_divider(codec_clock_divider,
+            _ad9522_regs.divider1_low_cycles,
+            _ad9522_regs.divider1_high_cycles,
+            _ad9522_regs.divider1_bypass
+        );
+
+        //setup test clock (same divider as codec clock)
+        _ad9522_regs.out4_format = ad9522_regs_t::OUT4_FORMAT_CMOS;
+        _ad9522_regs.out4_cmos_configuration = (enable_test_clock)?
+            ad9522_regs_t::OUT4_CMOS_CONFIGURATION_A_ON :
+            ad9522_regs_t::OUT4_CMOS_CONFIGURATION_OFF;
+
+        //setup a list of register ranges to write
+        typedef std::pair<boost::uint16_t, boost::uint16_t> range_t;
+        static const std::vector<range_t> ranges = boost::assign::list_of
+            (range_t(0x000, 0x000)) (range_t(0x010, 0x01F))
+            (range_t(0x0F0, 0x0FD)) (range_t(0x190, 0x19B))
+            (range_t(0x1E0, 0x1E1)) (range_t(0x230, 0x230))
+        ;
+
+        //write initial register values and latch/update
+        BOOST_FOREACH(const range_t &range, ranges){
+            for(boost::uint16_t addr = range.first; addr <= range.second; addr++){
+                this->send_reg(addr);
+            }
+        }
+        this->latch_regs();
+        //test read:
+        //boost::uint32_t reg = _ad9522_regs.get_read_reg(0x01b);
+        //boost::uint32_t result = _iface->transact_spi(
+        //    UE_SPI_SS_AD9522,
+        //    spi_config_t::EDGE_RISE,
+        //    reg, 24, true /*no*/
+        //);
+        //std::cout << "result " << std::hex << result << std::endl;
+        this->enable_rx_dboard_clock(false);
+        this->enable_tx_dboard_clock(false);
+    }
+
+    ~usrp_e100_clock_ctrl_impl(void){
+        this->enable_rx_dboard_clock(false);
+        this->enable_tx_dboard_clock(false);
+    }
+
+    double get_fpga_clock_rate(void){
+        return master_clock_rate/fpga_clock_divider;
+    }
+
+    /***********************************************************************
+     * RX Dboard Clock Control (output 9, divider 3)
+     **********************************************************************/
+    void enable_rx_dboard_clock(bool enb){
+        _ad9522_regs.out9_format = ad9522_regs_t::OUT9_FORMAT_CMOS;
+        _ad9522_regs.out9_cmos_configuration = (enb)?
+            ad9522_regs_t::OUT9_CMOS_CONFIGURATION_B_ON :
+            ad9522_regs_t::OUT9_CMOS_CONFIGURATION_OFF;
+        this->send_reg(0x0F9);
+        this->latch_regs();
+    }
+
+    std::vector<double> get_rx_dboard_clock_rates(void){
+        std::vector<double> rates;
+        for(size_t div = 1; div <= 16+16; div++)
+            rates.push_back(master_clock_rate/div);
+        return rates;
+    }
+
+    void set_rx_dboard_clock_rate(double rate){
+        assert_has(get_rx_dboard_clock_rates(), rate, "rx dboard clock rate");
+        size_t divider = size_t(master_clock_rate/rate);
+        //set the divider registers
+        set_clock_divider(divider,
+            _ad9522_regs.divider3_low_cycles,
+            _ad9522_regs.divider3_high_cycles,
+            _ad9522_regs.divider3_bypass
+        );
+        this->send_reg(0x199);
+        this->send_reg(0x19a);
+        this->latch_regs();
+    }
+
+    /***********************************************************************
+     * TX Dboard Clock Control (output 6, divider 2)
+     **********************************************************************/
+    void enable_tx_dboard_clock(bool enb){
+        _ad9522_regs.out6_format = ad9522_regs_t::OUT6_FORMAT_CMOS;
+        _ad9522_regs.out6_cmos_configuration = (enb)?
+            ad9522_regs_t::OUT6_CMOS_CONFIGURATION_B_ON :
+            ad9522_regs_t::OUT6_CMOS_CONFIGURATION_OFF;
+        this->send_reg(0x0F6);
+        this->latch_regs();
+    }
+
+    std::vector<double> get_tx_dboard_clock_rates(void){
+        return get_rx_dboard_clock_rates(); //same master clock, same dividers...
+    }
+
+    void set_tx_dboard_clock_rate(double rate){
+        assert_has(get_tx_dboard_clock_rates(), rate, "tx dboard clock rate");
+        size_t divider = size_t(master_clock_rate/rate);
+        //set the divider registers
+        set_clock_divider(divider,
+            _ad9522_regs.divider2_low_cycles,
+            _ad9522_regs.divider2_high_cycles,
+            _ad9522_regs.divider2_bypass
+        );
+        this->send_reg(0x196);
+        this->send_reg(0x197);
+        this->latch_regs();
+    }
+    
+    /***********************************************************************
+     * Clock reference control
+     **********************************************************************/
+    void use_internal_ref(void) {
+        _ad9522_regs.enable_ref2 = 1;
+        _ad9522_regs.enable_ref1 = 0;
+        _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF2;
+        _ad9522_regs.enb_auto_ref_switchover = ad9522_regs_t::ENB_AUTO_REF_SWITCHOVER_MANUAL;
+        this->send_reg(0x01C);
+    }
+    
+    void use_external_ref(void) {
+        _ad9522_regs.enable_ref2 = 0;
+        _ad9522_regs.enable_ref1 = 1;
+        _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF1;
+        _ad9522_regs.enb_auto_ref_switchover = ad9522_regs_t::ENB_AUTO_REF_SWITCHOVER_MANUAL;
+        this->send_reg(0x01C);
+    }
+    
+    void use_auto_ref(void) {
+        _ad9522_regs.enable_ref2 = 1;
+        _ad9522_regs.enable_ref1 = 1;
+        _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF1;
+        _ad9522_regs.enb_auto_ref_switchover = ad9522_regs_t::ENB_AUTO_REF_SWITCHOVER_AUTO;
+    }
+
+private:
+    usrp_e100_iface::sptr _iface;
+    ad9522_regs_t _ad9522_regs;
+
+    void latch_regs(void){
+        _ad9522_regs.io_update = 1;
+        this->send_reg(0x232);
+    }
+
+    void send_reg(boost::uint16_t addr){
+        boost::uint32_t reg = _ad9522_regs.get_write_reg(addr);
+        //std::cout << "clock control write reg: " << std::hex << reg << std::endl;
+        _iface->transact_spi(
+            UE_SPI_SS_AD9522,
+            spi_config_t::EDGE_RISE,
+            reg, 24, false /*no rb*/
+        );
+    }
+};
+
+/***********************************************************************
+ * Clock Control Make
+ **********************************************************************/
+usrp_e100_clock_ctrl::sptr usrp_e100_clock_ctrl::make(usrp_e100_iface::sptr iface){
+    return sptr(new usrp_e100_clock_ctrl_impl(iface));
+}
diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.hpp b/host/lib/usrp/usrp_e100/clock_ctrl.hpp
new file mode 100644
index 000000000..d613d1473
--- /dev/null
+++ b/host/lib/usrp/usrp_e100/clock_ctrl.hpp
@@ -0,0 +1,103 @@
+//
+// Copyright 2010 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#ifndef INCLUDED_USRP_E100_CLOCK_CTRL_HPP
+#define INCLUDED_USRP_E100_CLOCK_CTRL_HPP
+
+#include "usrp_e100_iface.hpp"
+#include <boost/shared_ptr.hpp>
+#include <boost/utility.hpp>
+#include <vector>
+
+/*!
+ * The usrp-e clock control:
+ * - Setup system clocks.
+ * - Disable/enable clock lines.
+ */
+class usrp_e100_clock_ctrl : boost::noncopyable{
+public:
+    typedef boost::shared_ptr<usrp_e100_clock_ctrl> sptr;
+
+    /*!
+     * Make a new clock control object.
+     * \param iface the usrp_e100 iface object
+     * \return the clock control object
+     */
+    static sptr make(usrp_e100_iface::sptr iface);
+
+    /*!
+     * Get the rate of the fpga clock line.
+     * \return the fpga clock rate in Hz
+     */
+    virtual double get_fpga_clock_rate(void) = 0;
+
+    /*!
+     * Get the possible rates of the rx dboard clock.
+     * \return a vector of clock rates in Hz
+     */
+    virtual std::vector<double> get_rx_dboard_clock_rates(void) = 0;
+
+    /*!
+     * Get the possible rates of the tx dboard clock.
+     * \return a vector of clock rates in Hz
+     */
+    virtual std::vector<double> get_tx_dboard_clock_rates(void) = 0;
+
+    /*!
+     * Set the rx dboard clock rate to a possible rate.
+     * \param rate the new clock rate in Hz
+     * \throw exception when rate cannot be achieved
+     */
+    virtual void set_rx_dboard_clock_rate(double rate) = 0;
+
+    /*!
+     * Set the tx dboard clock rate to a possible rate.
+     * \param rate the new clock rate in Hz
+     * \throw exception when rate cannot be achieved
+     */
+    virtual void set_tx_dboard_clock_rate(double rate) = 0;
+
+    /*!
+     * Enable/disable the rx dboard clock.
+     * \param enb true to enable
+     */
+    virtual void enable_rx_dboard_clock(bool enb) = 0;
+
+    /*!
+     * Enable/disable the tx dboard clock.
+     * \param enb true to enable
+     */
+    virtual void enable_tx_dboard_clock(bool enb) = 0;
+    
+    /*!
+     * Use the internal TCXO reference
+     */
+    virtual void use_internal_ref(void) = 0;
+    
+    /*!
+     * Use the external SMA reference
+     */
+    virtual void use_external_ref(void) = 0;
+    
+    /*!
+     * Use external if available, internal otherwise
+     */
+    virtual void use_auto_ref(void) = 0;
+
+};
+
+#endif /* INCLUDED_USRP_E100_CLOCK_CTRL_HPP */
diff --git a/host/lib/usrp/usrp_e100/codec_ctrl.cpp b/host/lib/usrp/usrp_e100/codec_ctrl.cpp
new file mode 100644
index 000000000..e7fd9792e
--- /dev/null
+++ b/host/lib/usrp/usrp_e100/codec_ctrl.cpp
@@ -0,0 +1,296 @@
+//
+// Copyright 2010 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include "codec_ctrl.hpp"
+#include "ad9862_regs.hpp"
+#include <uhd/types/dict.hpp>
+#include <uhd/utils/assert.hpp>
+#include <uhd/utils/algorithm.hpp>
+#include <boost/cstdint.hpp>
+#include <boost/tuple/tuple.hpp>
+#include <boost/math/special_functions/round.hpp>
+#include "usrp_e100_regs.hpp" //spi slave constants
+#include <boost/assign/list_of.hpp>
+#include <iostream>
+
+using namespace uhd;
+
+static const bool codec_debug = false;
+
+const gain_range_t usrp_e100_codec_ctrl::tx_pga_gain_range(-20, 0, float(0.1));
+const gain_range_t usrp_e100_codec_ctrl::rx_pga_gain_range(0, 20, 1);
+
+/***********************************************************************
+ * Codec Control Implementation
+ **********************************************************************/
+class usrp_e100_codec_ctrl_impl : public usrp_e100_codec_ctrl{
+public:
+    //structors
+    usrp_e100_codec_ctrl_impl(usrp_e100_iface::sptr iface);
+    ~usrp_e100_codec_ctrl_impl(void);
+
+    //aux adc and dac control
+    float read_aux_adc(aux_adc_t which);
+    void write_aux_dac(aux_dac_t which, float volts);
+
+    //pga gain control
+    void set_tx_pga_gain(float);
+    float get_tx_pga_gain(void);
+    void set_rx_pga_gain(float, char);
+    float get_rx_pga_gain(char);
+
+private:
+    usrp_e100_iface::sptr _iface;
+    ad9862_regs_t _ad9862_regs;
+    aux_adc_t _last_aux_adc_a, _last_aux_adc_b;
+    void send_reg(boost::uint8_t addr);
+    void recv_reg(boost::uint8_t addr);
+};
+
+/***********************************************************************
+ * Codec Control Structors
+ **********************************************************************/
+usrp_e100_codec_ctrl_impl::usrp_e100_codec_ctrl_impl(usrp_e100_iface::sptr iface){
+    _iface = iface;
+
+    //soft reset
+    _ad9862_regs.soft_reset = 1;
+    this->send_reg(0);
+
+    //initialize the codec register settings
+    _ad9862_regs.sdio_bidir = ad9862_regs_t::SDIO_BIDIR_SDIO_SDO;
+    _ad9862_regs.lsb_first = ad9862_regs_t::LSB_FIRST_MSB;
+    _ad9862_regs.soft_reset = 0;
+
+    //setup rx side of codec
+    _ad9862_regs.byp_buffer_a = 1;
+    _ad9862_regs.byp_buffer_b = 1;
+    _ad9862_regs.buffer_a_pd = 1;
+    _ad9862_regs.buffer_b_pd = 1;
+    _ad9862_regs.rx_pga_a = 0;//0x1f;  //TODO bring under api control
+    _ad9862_regs.rx_pga_b = 0;//0x1f;  //TODO bring under api control
+    _ad9862_regs.rx_twos_comp = 1;
+    _ad9862_regs.rx_hilbert = ad9862_regs_t::RX_HILBERT_DIS;
+
+    //setup tx side of codec
+    _ad9862_regs.two_data_paths = ad9862_regs_t::TWO_DATA_PATHS_BOTH;
+    _ad9862_regs.interleaved = ad9862_regs_t::INTERLEAVED_INTERLEAVED;
+    _ad9862_regs.tx_retime = ad9862_regs_t::TX_RETIME_CLKOUT2;
+    _ad9862_regs.tx_pga_gain = 199; //TODO bring under api control
+    _ad9862_regs.tx_hilbert = ad9862_regs_t::TX_HILBERT_DIS;
+    _ad9862_regs.interp = ad9862_regs_t::INTERP_2;
+    _ad9862_regs.tx_twos_comp = 1;
+    _ad9862_regs.fine_mode = ad9862_regs_t::FINE_MODE_BYPASS;
+    _ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_BYPASS;
+    _ad9862_regs.dac_a_coarse_gain = 0x3;
+    _ad9862_regs.dac_b_coarse_gain = 0x3;
+    _ad9862_regs.edges = ad9862_regs_t::EDGES_NORMAL;
+
+    //setup the dll
+    _ad9862_regs.input_clk_ctrl = ad9862_regs_t::INPUT_CLK_CTRL_EXTERNAL;
+    _ad9862_regs.dll_mult = ad9862_regs_t::DLL_MULT_2;
+    _ad9862_regs.dll_mode = ad9862_regs_t::DLL_MODE_FAST;
+
+    //write the register settings to the codec
+    for (uint8_t addr = 0; addr <= 25; addr++){
+        this->send_reg(addr);
+    }
+
+    //aux adc clock
+    _ad9862_regs.clk_4 = ad9862_regs_t::CLK_4_1_4;
+    this->send_reg(34);
+}
+
+usrp_e100_codec_ctrl_impl::~usrp_e100_codec_ctrl_impl(void){
+    //set aux dacs to zero
+    this->write_aux_dac(AUX_DAC_A, 0);
+    this->write_aux_dac(AUX_DAC_B, 0);
+    this->write_aux_dac(AUX_DAC_C, 0);
+    this->write_aux_dac(AUX_DAC_D, 0);
+
+    //power down
+    _ad9862_regs.all_rx_pd = 1;
+    this->send_reg(1);
+    _ad9862_regs.tx_digital_pd = 1;
+    _ad9862_regs.tx_analog_pd = ad9862_regs_t::TX_ANALOG_PD_BOTH;
+    this->send_reg(8);
+}
+
+/***********************************************************************
+ * Codec Control Gain Control Methods
+ **********************************************************************/
+static const int mtpgw = 255; //maximum tx pga gain word
+
+void usrp_e100_codec_ctrl_impl::set_tx_pga_gain(float gain){
+    int gain_word = int(mtpgw*(gain - tx_pga_gain_range.min)/(tx_pga_gain_range.max - tx_pga_gain_range.min));
+    _ad9862_regs.tx_pga_gain = std::clip(gain_word, 0, mtpgw);
+    this->send_reg(16);
+}
+
+float usrp_e100_codec_ctrl_impl::get_tx_pga_gain(void){
+    return (_ad9862_regs.tx_pga_gain*(tx_pga_gain_range.max - tx_pga_gain_range.min)/mtpgw) + tx_pga_gain_range.min;
+}
+
+static const int mrpgw = 0x14; //maximum rx pga gain word
+
+void usrp_e100_codec_ctrl_impl::set_rx_pga_gain(float gain, char which){
+    int gain_word = int(mrpgw*(gain - rx_pga_gain_range.min)/(rx_pga_gain_range.max - rx_pga_gain_range.min));
+    gain_word = std::clip(gain_word, 0, mrpgw);
+    switch(which){
+    case 'A':
+        _ad9862_regs.rx_pga_a = gain_word;
+        this->send_reg(2);
+        return;
+    case 'B':
+        _ad9862_regs.rx_pga_b = gain_word;
+        this->send_reg(3);
+        return;
+    default: UHD_THROW_INVALID_CODE_PATH();
+    }
+}
+
+float usrp_e100_codec_ctrl_impl::get_rx_pga_gain(char which){
+    int gain_word;
+    switch(which){
+    case 'A': gain_word = _ad9862_regs.rx_pga_a; break;
+    case 'B': gain_word = _ad9862_regs.rx_pga_b; break;
+    default: UHD_THROW_INVALID_CODE_PATH();
+    }
+    return (gain_word*(rx_pga_gain_range.max - rx_pga_gain_range.min)/mrpgw) + rx_pga_gain_range.min;
+}
+
+/***********************************************************************
+ * Codec Control AUX ADC Methods
+ **********************************************************************/
+static float aux_adc_to_volts(boost::uint8_t high, boost::uint8_t low){
+    return float((boost::uint16_t(high) << 2) | low)*3.3/0x3ff;
+}
+
+float usrp_e100_codec_ctrl_impl::read_aux_adc(aux_adc_t which){
+    //check to see if the switch needs to be set
+    bool write_switch = false;
+    switch(which){
+
+    case AUX_ADC_A1:
+    case AUX_ADC_A2:
+        if (which != _last_aux_adc_a){
+            _ad9862_regs.select_a = (which == AUX_ADC_A1)?
+                ad9862_regs_t::SELECT_A_AUX_ADC1: ad9862_regs_t::SELECT_A_AUX_ADC2;
+            _last_aux_adc_a = which;
+            write_switch = true;
+        }
+        break;
+
+    case AUX_ADC_B1:
+    case AUX_ADC_B2:
+        if (which != _last_aux_adc_b){
+            _ad9862_regs.select_b = (which == AUX_ADC_B1)?
+                ad9862_regs_t::SELECT_B_AUX_ADC1: ad9862_regs_t::SELECT_B_AUX_ADC2;
+            _last_aux_adc_b = which;
+            write_switch = true;
+        }
+        break;
+
+    }
+
+    //write the switch if it changed
+    if(write_switch) this->send_reg(34);
+
+    //map aux adcs to register values to read
+    static const uhd::dict<aux_adc_t, boost::uint8_t> aux_dac_to_addr = boost::assign::map_list_of
+        (AUX_ADC_A2, 26) (AUX_ADC_A1, 28)
+        (AUX_ADC_B2, 30) (AUX_ADC_B1, 32)
+    ;
+
+    //read the value
+    this->recv_reg(aux_dac_to_addr[which]+0);
+    this->recv_reg(aux_dac_to_addr[which]+1);
+
+    //return the value scaled to volts
+    switch(which){
+    case AUX_ADC_A1: return aux_adc_to_volts(_ad9862_regs.aux_adc_a1_9_2, _ad9862_regs.aux_adc_a1_1_0);
+    case AUX_ADC_A2: return aux_adc_to_volts(_ad9862_regs.aux_adc_a2_9_2, _ad9862_regs.aux_adc_a2_1_0);
+    case AUX_ADC_B1: return aux_adc_to_volts(_ad9862_regs.aux_adc_b1_9_2, _ad9862_regs.aux_adc_b1_1_0);
+    case AUX_ADC_B2: return aux_adc_to_volts(_ad9862_regs.aux_adc_b2_9_2, _ad9862_regs.aux_adc_b2_1_0);
+    }
+    UHD_ASSERT_THROW(false);
+}
+
+/***********************************************************************
+ * Codec Control AUX DAC Methods
+ **********************************************************************/
+void usrp_e100_codec_ctrl_impl::write_aux_dac(aux_dac_t which, float volts){
+    //special case for aux dac d (aka sigma delta word)
+    if (which == AUX_DAC_D){
+        boost::uint16_t dac_word = std::clip(boost::math::iround(volts*0xfff/3.3), 0, 0xfff);
+        _ad9862_regs.sig_delt_11_4 = boost::uint8_t(dac_word >> 4);
+        _ad9862_regs.sig_delt_3_0 = boost::uint8_t(dac_word & 0xf);
+        this->send_reg(42);
+        this->send_reg(43);
+        return;
+    }
+
+    //calculate the dac word for aux dac a, b, c
+    boost::uint8_t dac_word = std::clip(boost::math::iround(volts*0xff/3.3), 0, 0xff);
+
+    //setup a lookup table for the aux dac params (reg ref, reg addr)
+    typedef boost::tuple<boost::uint8_t*, boost::uint8_t> dac_params_t;
+    uhd::dict<aux_dac_t, dac_params_t> aux_dac_to_params = boost::assign::map_list_of
+        (AUX_DAC_A, dac_params_t(&_ad9862_regs.aux_dac_a, 36))
+        (AUX_DAC_B, dac_params_t(&_ad9862_regs.aux_dac_b, 37))
+        (AUX_DAC_C, dac_params_t(&_ad9862_regs.aux_dac_c, 38))
+    ;
+
+    //set the aux dac register
+    UHD_ASSERT_THROW(aux_dac_to_params.has_key(which));
+    boost::uint8_t *reg_ref, reg_addr;
+    boost::tie(reg_ref, reg_addr) = aux_dac_to_params[which];
+    *reg_ref = dac_word;
+    this->send_reg(reg_addr);
+}
+
+/***********************************************************************
+ * Codec Control SPI Methods
+ **********************************************************************/
+void usrp_e100_codec_ctrl_impl::send_reg(boost::uint8_t addr){
+    boost::uint32_t reg = _ad9862_regs.get_write_reg(addr);
+    if (codec_debug) std::cout << "codec control write reg: " << std::hex << reg << std::endl;
+    _iface->transact_spi(
+        UE_SPI_SS_AD9862,
+        spi_config_t::EDGE_RISE,
+        reg, 16, false /*no rb*/
+    );
+}
+
+void usrp_e100_codec_ctrl_impl::recv_reg(boost::uint8_t addr){
+    boost::uint32_t reg = _ad9862_regs.get_read_reg(addr);
+    if (codec_debug) std::cout << "codec control read reg: " << std::hex << reg << std::endl;
+    boost::uint32_t ret = _iface->transact_spi(
+        UE_SPI_SS_AD9862,
+        spi_config_t::EDGE_RISE,
+        reg, 16, true /*rb*/
+    );
+    if (codec_debug) std::cout << "codec control read ret: " << std::hex << ret << std::endl;
+    _ad9862_regs.set_reg(addr, boost::uint16_t(ret));
+}
+
+/***********************************************************************
+ * Codec Control Make
+ **********************************************************************/
+usrp_e100_codec_ctrl::sptr usrp_e100_codec_ctrl::make(usrp_e100_iface::sptr iface){
+    return sptr(new usrp_e100_codec_ctrl_impl(iface));
+}
diff --git a/host/lib/usrp/usrp_e100/codec_ctrl.hpp b/host/lib/usrp/usrp_e100/codec_ctrl.hpp
new file mode 100644
index 000000000..74ce9bd9a
--- /dev/null
+++ b/host/lib/usrp/usrp_e100/codec_ctrl.hpp
@@ -0,0 +1,90 @@
+//
+// Copyright 2010 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#ifndef INCLUDED_USRP_E100_CODEC_CTRL_HPP
+#define INCLUDED_USRP_E100_CODEC_CTRL_HPP
+
+#include "usrp_e100_iface.hpp"
+#include <uhd/types/ranges.hpp>
+#include <boost/shared_ptr.hpp>
+#include <boost/utility.hpp>
+
+/*!
+ * The usrp-e codec control:
+ * - Init/power down codec.
+ * - Read aux adc, write aux dac.
+ */
+class usrp_e100_codec_ctrl : boost::noncopyable{
+public:
+    typedef boost::shared_ptr<usrp_e100_codec_ctrl> sptr;
+
+    static const uhd::gain_range_t tx_pga_gain_range;
+    static const uhd::gain_range_t rx_pga_gain_range;
+
+    /*!
+     * Make a new codec control object.
+     * \param iface the usrp_e100 iface object
+     * \return the codec control object
+     */
+    static sptr make(usrp_e100_iface::sptr iface);
+
+    //! aux adc identifier constants
+    enum aux_adc_t{
+        AUX_ADC_A2 = 0xA2,
+        AUX_ADC_A1 = 0xA1,
+        AUX_ADC_B2 = 0xB2,
+        AUX_ADC_B1 = 0xB1
+    };
+
+    /*!
+     * Read an auxiliary adc:
+     * The internals remember which aux adc was read last.
+     * Therefore, the aux adc switch is only changed as needed.
+     * \param which which of the 4 adcs
+     * \return a value in volts
+     */
+    virtual float read_aux_adc(aux_adc_t which) = 0;
+
+    //! aux dac identifier constants
+    enum aux_dac_t{
+        AUX_DAC_A = 0xA,
+        AUX_DAC_B = 0xB,
+        AUX_DAC_C = 0xC,
+        AUX_DAC_D = 0xD //really the sigma delta output
+    };
+
+    /*!
+     * Write an auxiliary dac.
+     * \param which which of the 4 dacs
+     * \param volts the level in in volts
+     */
+    virtual void write_aux_dac(aux_dac_t which, float volts) = 0;
+
+    //! Set the TX PGA gain
+    virtual void set_tx_pga_gain(float gain) = 0;
+
+    //! Get the TX PGA gain
+    virtual float get_tx_pga_gain(void) = 0;
+
+    //! Set the RX PGA gain ('A' or 'B')
+    virtual void set_rx_pga_gain(float gain, char which) = 0;
+
+    //! Get the RX PGA gain ('A' or 'B')
+    virtual float get_rx_pga_gain(char which) = 0;
+};
+
+#endif /* INCLUDED_USRP_E100_CODEC_CTRL_HPP */
diff --git a/host/lib/usrp/usrp_e100/codec_impl.cpp b/host/lib/usrp/usrp_e100/codec_impl.cpp
new file mode 100644
index 000000000..6fd44bad3
--- /dev/null
+++ b/host/lib/usrp/usrp_e100/codec_impl.cpp
@@ -0,0 +1,149 @@
+//
+// Copyright 2010 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include "usrp_e100_impl.hpp"
+#include <uhd/utils/assert.hpp>
+#include <uhd/usrp/codec_props.hpp>
+#include <boost/bind.hpp>
+
+using namespace uhd;
+using namespace uhd::usrp;
+
+/***********************************************************************
+ * Helper Methods
+ **********************************************************************/
+void usrp_e100_impl::codec_init(void){
+    //make proxies
+    _rx_codec_proxy = wax_obj_proxy::make(
+        boost::bind(&usrp_e100_impl::rx_codec_get, this, _1, _2),
+        boost::bind(&usrp_e100_impl::rx_codec_set, this, _1, _2)
+    );
+    _tx_codec_proxy = wax_obj_proxy::make(
+        boost::bind(&usrp_e100_impl::tx_codec_get, this, _1, _2),
+        boost::bind(&usrp_e100_impl::tx_codec_set, this, _1, _2)
+    );
+}
+
+/***********************************************************************
+ * RX Codec Properties
+ **********************************************************************/
+static const std::string ad9862_pga_gain_name = "ad9862 pga";
+
+void usrp_e100_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){
+    named_prop_t key = named_prop_t::extract(key_);
+
+    //handle the get request conditioned on the key
+    switch(key.as<codec_prop_t>()){
+    case CODEC_PROP_NAME:
+        val = std::string("usrp-e adc - ad9522");
+        return;
+
+    case CODEC_PROP_OTHERS:
+        val = prop_names_t();
+        return;
+
+    case CODEC_PROP_GAIN_NAMES:
+        val = prop_names_t(1, ad9862_pga_gain_name);
+        return;
+
+    case CODEC_PROP_GAIN_RANGE:
+        UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name);
+        val = usrp_e100_codec_ctrl::rx_pga_gain_range;
+        return;
+
+    case CODEC_PROP_GAIN_I:
+        UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name);
+        val = _codec_ctrl->get_rx_pga_gain('A');
+        return;
+
+    case CODEC_PROP_GAIN_Q:
+        UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name);
+        val = _codec_ctrl->get_rx_pga_gain('B');
+        return;
+
+    default: UHD_THROW_PROP_GET_ERROR();
+    }
+}
+
+void usrp_e100_impl::rx_codec_set(const wax::obj &key_, const wax::obj &val){
+    named_prop_t key = named_prop_t::extract(key_);
+
+    //handle the set request conditioned on the key
+    switch(key.as<codec_prop_t>()){
+    case CODEC_PROP_GAIN_I:
+        UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name);
+        _codec_ctrl->set_rx_pga_gain(val.as<float>(), 'A');
+        return;
+
+    case CODEC_PROP_GAIN_Q:
+        UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name);
+        _codec_ctrl->set_rx_pga_gain(val.as<float>(), 'B');
+        return;
+
+    default: UHD_THROW_PROP_SET_ERROR();
+    }
+}
+
+/***********************************************************************
+ * TX Codec Properties
+ **********************************************************************/
+void usrp_e100_impl::tx_codec_get(const wax::obj &key_, wax::obj &val){
+    named_prop_t key = named_prop_t::extract(key_);
+
+    //handle the get request conditioned on the key
+    switch(key.as<codec_prop_t>()){
+    case CODEC_PROP_NAME:
+        val = std::string("usrp-e dac - ad9522");
+        return;
+
+    case CODEC_PROP_OTHERS:
+        val = prop_names_t();
+        return;
+
+    case CODEC_PROP_GAIN_NAMES:
+        val = prop_names_t(1, ad9862_pga_gain_name);
+        return;
+
+    case CODEC_PROP_GAIN_RANGE:
+        UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name);
+        val = usrp_e100_codec_ctrl::tx_pga_gain_range;
+        return;
+
+    case CODEC_PROP_GAIN_I: //only one gain for I and Q
+    case CODEC_PROP_GAIN_Q:
+        UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name);
+        val = _codec_ctrl->get_tx_pga_gain();
+        return;
+
+    default: UHD_THROW_PROP_GET_ERROR();
+    }
+}
+
+void usrp_e100_impl::tx_codec_set(const wax::obj &key_, const wax::obj &val){
+    named_prop_t key = named_prop_t::extract(key_);
+
+    //handle the set request conditioned on the key
+    switch(key.as<codec_prop_t>()){
+    case CODEC_PROP_GAIN_I: //only one gain for I and Q
+    case CODEC_PROP_GAIN_Q:
+        UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name);
+        _codec_ctrl->set_tx_pga_gain(val.as<float>());
+        return;
+
+    default: UHD_THROW_PROP_SET_ERROR();
+    }
+}
diff --git a/host/lib/usrp/usrp_e100/dboard_iface.cpp b/host/lib/usrp/usrp_e100/dboard_iface.cpp
new file mode 100644
index 000000000..aa96171d6
--- /dev/null
+++ b/host/lib/usrp/usrp_e100/dboard_iface.cpp
@@ -0,0 +1,298 @@
+//
+// Copyright 2010 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include "usrp_e100_iface.hpp"
+#include "usrp_e100_regs.hpp"
+#include "clock_ctrl.hpp"
+#include "codec_ctrl.hpp"
+#include <uhd/usrp/dboard_iface.hpp>
+#include <uhd/types/dict.hpp>
+#include <uhd/utils/assert.hpp>
+#include <boost/assign/list_of.hpp>
+#include <linux/usrp_e.h> //i2c and spi constants
+
+using namespace uhd;
+using namespace uhd::usrp;
+using namespace boost::assign;
+
+class usrp_e100_dboard_iface : public dboard_iface{
+public:
+
+    usrp_e100_dboard_iface(
+        usrp_e100_iface::sptr iface,
+        usrp_e100_clock_ctrl::sptr clock,
+        usrp_e100_codec_ctrl::sptr codec
+    ){
+        _iface = iface;
+        _clock = clock;
+        _codec = codec;
+
+        //init the clock rate shadows
+        this->set_clock_rate(UNIT_RX, _clock->get_fpga_clock_rate());
+        this->set_clock_rate(UNIT_TX, _clock->get_fpga_clock_rate());
+
+        _iface->poke16(UE_REG_GPIO_RX_DBG, 0);
+        _iface->poke16(UE_REG_GPIO_TX_DBG, 0);
+    }
+
+    ~usrp_e100_dboard_iface(void){
+        /* NOP */
+    }
+
+    special_props_t get_special_props(void){
+        special_props_t props;
+        props.soft_clock_divider = false;
+        props.mangle_i2c_addrs = false;
+        return props;
+    }
+
+    void write_aux_dac(unit_t, aux_dac_t, float);
+    float read_aux_adc(unit_t, aux_adc_t);
+
+    void set_pin_ctrl(unit_t, boost::uint16_t);
+    void set_atr_reg(unit_t, atr_reg_t, boost::uint16_t);
+    void set_gpio_ddr(unit_t, boost::uint16_t);
+    void write_gpio(unit_t, boost::uint16_t);
+    void set_gpio_debug(unit_t, int);
+    boost::uint16_t read_gpio(unit_t);
+
+    void write_i2c(boost::uint8_t, const byte_vector_t &);
+    byte_vector_t read_i2c(boost::uint8_t, size_t);
+
+    void write_spi(
+        unit_t unit,
+        const spi_config_t &config,
+        boost::uint32_t data,
+        size_t num_bits
+    );
+
+    boost::uint32_t read_write_spi(
+        unit_t unit,
+        const spi_config_t &config,
+        boost::uint32_t data,
+        size_t num_bits
+    );
+
+    void set_clock_rate(unit_t, double);
+    std::vector<double> get_clock_rates(unit_t);
+    double get_clock_rate(unit_t);
+    void set_clock_enabled(unit_t, bool);
+    double get_codec_rate(unit_t);
+
+private:
+    usrp_e100_iface::sptr _iface;
+    usrp_e100_clock_ctrl::sptr _clock;
+    usrp_e100_codec_ctrl::sptr _codec;
+    uhd::dict<unit_t, double> _clock_rates;
+};
+
+/***********************************************************************
+ * Make Function
+ **********************************************************************/
+dboard_iface::sptr make_usrp_e100_dboard_iface(
+    usrp_e100_iface::sptr iface,
+    usrp_e100_clock_ctrl::sptr clock,
+    usrp_e100_codec_ctrl::sptr codec
+){
+    return dboard_iface::sptr(new usrp_e100_dboard_iface(iface, clock, codec));
+}
+
+/***********************************************************************
+ * Clock Rates
+ **********************************************************************/
+void usrp_e100_dboard_iface::set_clock_rate(unit_t unit, double rate){
+    _clock_rates[unit] = rate;
+    switch(unit){
+    case UNIT_RX: return _clock->set_rx_dboard_clock_rate(rate);
+    case UNIT_TX: return _clock->set_tx_dboard_clock_rate(rate);
+    }
+}
+
+std::vector<double> usrp_e100_dboard_iface::get_clock_rates(unit_t unit){
+    switch(unit){
+    case UNIT_RX: return _clock->get_rx_dboard_clock_rates();
+    case UNIT_TX: return _clock->get_tx_dboard_clock_rates();
+    default: UHD_THROW_INVALID_CODE_PATH();
+    }
+}
+
+double usrp_e100_dboard_iface::get_clock_rate(unit_t unit){
+    return _clock_rates[unit];
+}
+
+void usrp_e100_dboard_iface::set_clock_enabled(unit_t unit, bool enb){
+    switch(unit){
+    case UNIT_RX: return _clock->enable_rx_dboard_clock(enb);
+    case UNIT_TX: return _clock->enable_tx_dboard_clock(enb);
+    }
+}
+
+double usrp_e100_dboard_iface::get_codec_rate(unit_t){
+    return _clock->get_fpga_clock_rate();
+}
+
+/***********************************************************************
+ * GPIO
+ **********************************************************************/
+void usrp_e100_dboard_iface::set_pin_ctrl(unit_t unit, boost::uint16_t value){
+    UHD_ASSERT_THROW(GPIO_SEL_ATR == 1); //make this assumption
+    switch(unit){
+    case UNIT_RX: _iface->poke16(UE_REG_GPIO_RX_SEL, value); return;
+    case UNIT_TX: _iface->poke16(UE_REG_GPIO_TX_SEL, value); return;
+    }
+}
+
+void usrp_e100_dboard_iface::set_gpio_ddr(unit_t unit, boost::uint16_t value){
+    switch(unit){
+    case UNIT_RX: _iface->poke16(UE_REG_GPIO_RX_DDR, value); return;
+    case UNIT_TX: _iface->poke16(UE_REG_GPIO_TX_DDR, value); return;
+    }
+}
+
+void usrp_e100_dboard_iface::write_gpio(unit_t unit, boost::uint16_t value){
+    switch(unit){
+    case UNIT_RX: _iface->poke16(UE_REG_GPIO_RX_IO, value); return;
+    case UNIT_TX: _iface->poke16(UE_REG_GPIO_TX_IO, value); return;
+    }
+}
+
+boost::uint16_t usrp_e100_dboard_iface::read_gpio(unit_t unit){
+    switch(unit){
+    case UNIT_RX: return _iface->peek16(UE_REG_GPIO_RX_IO);
+    case UNIT_TX: return _iface->peek16(UE_REG_GPIO_TX_IO);
+    default: UHD_THROW_INVALID_CODE_PATH();
+    }
+}
+
+void usrp_e100_dboard_iface::set_atr_reg(unit_t unit, atr_reg_t atr, boost::uint16_t value){
+    //define mapping of unit to atr regs to register address
+    static const uhd::dict<
+        unit_t, uhd::dict<atr_reg_t, boost::uint32_t>
+    > unit_to_atr_to_addr = map_list_of
+        (UNIT_RX, map_list_of
+            (ATR_REG_IDLE,        UE_REG_ATR_IDLE_RXSIDE)
+            (ATR_REG_TX_ONLY,     UE_REG_ATR_INTX_RXSIDE)
+            (ATR_REG_RX_ONLY,     UE_REG_ATR_INRX_RXSIDE)
+            (ATR_REG_FULL_DUPLEX, UE_REG_ATR_FULL_RXSIDE)
+        )
+        (UNIT_TX, map_list_of
+            (ATR_REG_IDLE,        UE_REG_ATR_IDLE_TXSIDE)
+            (ATR_REG_TX_ONLY,     UE_REG_ATR_INTX_TXSIDE)
+            (ATR_REG_RX_ONLY,     UE_REG_ATR_INRX_TXSIDE)
+            (ATR_REG_FULL_DUPLEX, UE_REG_ATR_FULL_TXSIDE)
+        )
+    ;
+    _iface->poke16(unit_to_atr_to_addr[unit][atr], value);
+}
+
+void usrp_e100_dboard_iface::set_gpio_debug(unit_t unit, int which){
+    //set this unit to all outputs
+    this->set_gpio_ddr(unit, 0xffff);
+
+    //calculate the debug selections
+    boost::uint32_t dbg_sels = 0x0;
+    int sel = (which == 0)? GPIO_SEL_DEBUG_0 : GPIO_SEL_DEBUG_1;
+    for(size_t i = 0; i < 16; i++) dbg_sels |= sel << i;
+
+    //set the debug on and which debug selection
+    switch(unit){
+    case UNIT_RX:
+        _iface->poke16(UE_REG_GPIO_RX_DBG, 0xffff);
+        _iface->poke16(UE_REG_GPIO_RX_SEL, dbg_sels);
+        return;
+
+    case UNIT_TX:
+        _iface->poke16(UE_REG_GPIO_TX_DBG, 0xffff);
+        _iface->poke16(UE_REG_GPIO_TX_SEL, dbg_sels);
+        return;
+    }
+}
+
+/***********************************************************************
+ * SPI
+ **********************************************************************/
+/*!
+ * Static function to convert a unit type to a spi slave device number.
+ * \param unit the dboard interface unit type enum
+ * \return the slave device number
+ */
+static boost::uint32_t unit_to_otw_spi_dev(dboard_iface::unit_t unit){
+    switch(unit){
+    case dboard_iface::UNIT_TX: return UE_SPI_SS_TX_DB;
+    case dboard_iface::UNIT_RX: return UE_SPI_SS_RX_DB;
+    }
+    throw std::invalid_argument("unknown unit type");
+}
+
+void usrp_e100_dboard_iface::write_spi(
+    unit_t unit,
+    const spi_config_t &config,
+    boost::uint32_t data,
+    size_t num_bits
+){
+    _iface->transact_spi(unit_to_otw_spi_dev(unit), config, data, num_bits, false /*no rb*/);
+}
+
+boost::uint32_t usrp_e100_dboard_iface::read_write_spi(
+    unit_t unit,
+    const spi_config_t &config,
+    boost::uint32_t data,
+    size_t num_bits
+){
+    return _iface->transact_spi(unit_to_otw_spi_dev(unit), config, data, num_bits, true /*rb*/);
+}
+
+/***********************************************************************
+ * I2C
+ **********************************************************************/
+void usrp_e100_dboard_iface::write_i2c(boost::uint8_t addr, const byte_vector_t &bytes){
+    return _iface->write_i2c(addr, bytes);
+}
+
+byte_vector_t usrp_e100_dboard_iface::read_i2c(boost::uint8_t addr, size_t num_bytes){
+    return _iface->read_i2c(addr, num_bytes);
+}
+
+/***********************************************************************
+ * Aux DAX/ADC
+ **********************************************************************/
+void usrp_e100_dboard_iface::write_aux_dac(dboard_iface::unit_t, aux_dac_t which, float value){
+    //same aux dacs for each unit
+    static const uhd::dict<aux_dac_t, usrp_e100_codec_ctrl::aux_dac_t> which_to_aux_dac = map_list_of
+        (AUX_DAC_A, usrp_e100_codec_ctrl::AUX_DAC_A)
+        (AUX_DAC_B, usrp_e100_codec_ctrl::AUX_DAC_B)
+        (AUX_DAC_C, usrp_e100_codec_ctrl::AUX_DAC_C)
+        (AUX_DAC_D, usrp_e100_codec_ctrl::AUX_DAC_D)
+    ;
+    _codec->write_aux_dac(which_to_aux_dac[which], value);
+}
+
+float usrp_e100_dboard_iface::read_aux_adc(dboard_iface::unit_t unit, aux_adc_t which){
+    static const uhd::dict<
+        unit_t, uhd::dict<aux_adc_t, usrp_e100_codec_ctrl::aux_adc_t>
+    > unit_to_which_to_aux_adc = map_list_of
+        (UNIT_RX, map_list_of
+            (AUX_ADC_A, usrp_e100_codec_ctrl::AUX_ADC_A1)
+            (AUX_ADC_B, usrp_e100_codec_ctrl::AUX_ADC_B1)
+        )
+        (UNIT_TX, map_list_of
+            (AUX_ADC_A, usrp_e100_codec_ctrl::AUX_ADC_A2)
+            (AUX_ADC_B, usrp_e100_codec_ctrl::AUX_ADC_B2)
+        )
+    ;
+    return _codec->read_aux_adc(unit_to_which_to_aux_adc[unit][which]);
+}
diff --git a/host/lib/usrp/usrp_e100/dboard_impl.cpp b/host/lib/usrp/usrp_e100/dboard_impl.cpp
new file mode 100644
index 000000000..9f2bfb8ae
--- /dev/null
+++ b/host/lib/usrp/usrp_e100/dboard_impl.cpp
@@ -0,0 +1,172 @@
+//
+// Copyright 2010 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include "usrp_e100_impl.hpp"
+#include "usrp_e100_regs.hpp"
+#include <uhd/utils/assert.hpp>
+#include <uhd/usrp/dboard_props.hpp>
+#include <uhd/usrp/subdev_props.hpp>
+#include <uhd/usrp/misc_utils.hpp>
+#include <boost/bind.hpp>
+#include <iostream>
+
+using namespace uhd;
+using namespace uhd::usrp;
+
+/***********************************************************************
+ * Dboard Initialization
+ **********************************************************************/
+void usrp_e100_impl::dboard_init(void){
+    _rx_db_eeprom = dboard_eeprom_t(_iface->read_eeprom(I2C_ADDR_RX_DB, 0, dboard_eeprom_t::num_bytes()));
+    _tx_db_eeprom = dboard_eeprom_t(_iface->read_eeprom(I2C_ADDR_TX_DB, 0, dboard_eeprom_t::num_bytes()));
+
+    //create a new dboard interface and manager
+    _dboard_iface = make_usrp_e100_dboard_iface(
+        _iface, _clock_ctrl, _codec_ctrl
+    );
+    _dboard_manager = dboard_manager::make(
+        _rx_db_eeprom.id, _tx_db_eeprom.id, _dboard_iface
+    );
+
+    //setup the dboard proxies
+    _rx_dboard_proxy = wax_obj_proxy::make(
+        boost::bind(&usrp_e100_impl::rx_dboard_get, this, _1, _2),
+        boost::bind(&usrp_e100_impl::rx_dboard_set, this, _1, _2)
+    );
+    _tx_dboard_proxy = wax_obj_proxy::make(
+        boost::bind(&usrp_e100_impl::tx_dboard_get, this, _1, _2),
+        boost::bind(&usrp_e100_impl::tx_dboard_set, this, _1, _2)
+    );
+}
+
+/***********************************************************************
+ * RX Dboard Get
+ **********************************************************************/
+void usrp_e100_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){
+    named_prop_t key = named_prop_t::extract(key_);
+
+    //handle the get request conditioned on the key
+    switch(key.as<dboard_prop_t>()){
+    case DBOARD_PROP_NAME:
+        val = std::string("usrp-e dboard (rx unit)");
+        return;
+
+    case DBOARD_PROP_SUBDEV:
+        val = _dboard_manager->get_rx_subdev(key.name);
+        return;
+
+    case DBOARD_PROP_SUBDEV_NAMES:
+        val = _dboard_manager->get_rx_subdev_names();
+        return;
+
+    case DBOARD_PROP_DBOARD_ID:
+        val = _rx_db_eeprom.id;
+        return;
+
+    case DBOARD_PROP_DBOARD_IFACE:
+        val = _dboard_iface;
+        return;
+
+    case DBOARD_PROP_CODEC:
+        val = _rx_codec_proxy->get_link();
+        return;
+
+    case DBOARD_PROP_GAIN_GROUP:
+        val = make_gain_group(
+            _rx_db_eeprom.id,
+            _dboard_manager->get_rx_subdev(key.name),
+            _rx_codec_proxy->get_link(),
+            GAIN_GROUP_POLICY_RX
+        );
+        return;
+
+    default: UHD_THROW_PROP_GET_ERROR();
+    }
+}
+
+/***********************************************************************
+ * RX Dboard Set
+ **********************************************************************/
+void usrp_e100_impl::rx_dboard_set(const wax::obj &key, const wax::obj &val){
+    switch(key.as<dboard_prop_t>()){
+    case DBOARD_PROP_DBOARD_ID:
+        _rx_db_eeprom.id = val.as<dboard_id_t>();
+        _iface->write_eeprom(I2C_ADDR_RX_DB, 0, _rx_db_eeprom.get_eeprom_bytes());
+        return;
+
+    default: UHD_THROW_PROP_SET_ERROR();
+    }
+}
+
+/***********************************************************************
+ * TX Dboard Get
+ **********************************************************************/
+void usrp_e100_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){
+    named_prop_t key = named_prop_t::extract(key_);
+
+    //handle the get request conditioned on the key
+    switch(key.as<dboard_prop_t>()){
+    case DBOARD_PROP_NAME:
+        val = std::string("usrp-e dboard (tx unit)");
+        return;
+
+    case DBOARD_PROP_SUBDEV:
+        val = _dboard_manager->get_tx_subdev(key.name);
+        return;
+
+    case DBOARD_PROP_SUBDEV_NAMES:
+        val = _dboard_manager->get_tx_subdev_names();
+        return;
+
+    case DBOARD_PROP_DBOARD_ID:
+        val = _tx_db_eeprom.id;
+        return;
+
+    case DBOARD_PROP_DBOARD_IFACE:
+        val = _dboard_iface;
+        return;
+
+    case DBOARD_PROP_CODEC:
+        val = _tx_codec_proxy->get_link();
+        return;
+
+    case DBOARD_PROP_GAIN_GROUP:
+        val = make_gain_group(
+            _tx_db_eeprom.id,
+            _dboard_manager->get_tx_subdev(key.name),
+            _tx_codec_proxy->get_link(),
+            GAIN_GROUP_POLICY_TX
+        );
+        return;
+
+    default: UHD_THROW_PROP_GET_ERROR();
+    }
+}
+
+/***********************************************************************
+ * TX Dboard Set
+ **********************************************************************/
+void usrp_e100_impl::tx_dboard_set(const wax::obj &key, const wax::obj &val){
+    switch(key.as<dboard_prop_t>()){
+    case DBOARD_PROP_DBOARD_ID:
+        _tx_db_eeprom.id = val.as<dboard_id_t>();
+        _iface->write_eeprom(I2C_ADDR_TX_DB, 0, _tx_db_eeprom.get_eeprom_bytes());
+        return;
+
+    default: UHD_THROW_PROP_SET_ERROR();
+    }
+}
diff --git a/host/lib/usrp/usrp_e100/dsp_impl.cpp b/host/lib/usrp/usrp_e100/dsp_impl.cpp
new file mode 100644
index 000000000..43a3bd3be
--- /dev/null
+++ b/host/lib/usrp/usrp_e100/dsp_impl.cpp
@@ -0,0 +1,192 @@
+//
+// Copyright 2010 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include "usrp_e100_impl.hpp"
+#include "usrp_e100_regs.hpp"
+#include <uhd/usrp/dsp_utils.hpp>
+#include <uhd/usrp/dsp_props.hpp>
+#include <boost/math/special_functions/round.hpp>
+#include <boost/bind.hpp>
+
+#define rint boost::math::iround
+
+using namespace uhd;
+using namespace uhd::usrp;
+
+/***********************************************************************
+ * RX DDC Initialization
+ **********************************************************************/
+void usrp_e100_impl::rx_ddc_init(void){
+    _rx_ddc_proxy = wax_obj_proxy::make(
+        boost::bind(&usrp_e100_impl::rx_ddc_get, this, _1, _2),
+        boost::bind(&usrp_e100_impl::rx_ddc_set, this, _1, _2)
+    );
+
+    //initial config and update
+    rx_ddc_set(DSP_PROP_FREQ_SHIFT, double(0));
+    rx_ddc_set(DSP_PROP_HOST_RATE, double(64e6/10));
+}
+
+/***********************************************************************
+ * RX DDC Get
+ **********************************************************************/
+void usrp_e100_impl::rx_ddc_get(const wax::obj &key_, wax::obj &val){
+    named_prop_t key = named_prop_t::extract(key_);
+
+    switch(key.as<dsp_prop_t>()){
+    case DSP_PROP_NAME:
+        val = std::string("usrp-e ddc0");
+        return;
+
+    case DSP_PROP_OTHERS:
+        val = prop_names_t(); //empty
+        return;
+
+    case DSP_PROP_FREQ_SHIFT:
+        val = _ddc_freq;
+        return;
+
+    case DSP_PROP_FREQ_SHIFT_NAMES:
+        val = prop_names_t(1, "");
+        return;
+
+    case DSP_PROP_CODEC_RATE:
+        val = _clock_ctrl->get_fpga_clock_rate();
+        return;
+
+    case DSP_PROP_HOST_RATE:
+        val = _clock_ctrl->get_fpga_clock_rate()/_ddc_decim;
+        return;
+
+    default: UHD_THROW_PROP_GET_ERROR();
+    }
+}
+
+/***********************************************************************
+ * RX DDC Set
+ **********************************************************************/
+void usrp_e100_impl::rx_ddc_set(const wax::obj &key_, const wax::obj &val){
+    named_prop_t key = named_prop_t::extract(key_);
+
+    switch(key.as<dsp_prop_t>()){
+
+    case DSP_PROP_FREQ_SHIFT:{
+            double new_freq = val.as<double>();
+            _iface->poke32(UE_REG_DSP_RX_FREQ,
+                dsp_type1::calc_cordic_word_and_update(new_freq, _clock_ctrl->get_fpga_clock_rate())
+            );
+            _ddc_freq = new_freq; //shadow
+        }
+        return;
+
+    case DSP_PROP_HOST_RATE:{
+            //set the decimation
+            _ddc_decim = rint(_clock_ctrl->get_fpga_clock_rate()/val.as<double>());
+            _iface->poke32(UE_REG_DSP_RX_DECIM_RATE, dsp_type1::calc_cic_filter_word(_ddc_decim));
+
+            //set the scaling
+            static const boost::int16_t default_rx_scale_iq = 1024;
+            _iface->poke32(UE_REG_DSP_RX_SCALE_IQ,
+                dsp_type1::calc_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq)
+            );
+        }
+        return;
+
+    default: UHD_THROW_PROP_SET_ERROR();
+    }
+}
+
+/***********************************************************************
+ * TX DUC Initialization
+ **********************************************************************/
+void usrp_e100_impl::tx_duc_init(void){
+    _tx_duc_proxy = wax_obj_proxy::make(
+        boost::bind(&usrp_e100_impl::tx_duc_get, this, _1, _2),
+        boost::bind(&usrp_e100_impl::tx_duc_set, this, _1, _2)
+    );
+
+    //initial config and update
+    tx_duc_set(DSP_PROP_FREQ_SHIFT, double(0));
+    tx_duc_set(DSP_PROP_HOST_RATE, double(64e6/10));
+}
+
+/***********************************************************************
+ * TX DUC Get
+ **********************************************************************/
+void usrp_e100_impl::tx_duc_get(const wax::obj &key_, wax::obj &val){
+    named_prop_t key = named_prop_t::extract(key_);
+
+    switch(key.as<dsp_prop_t>()){
+    case DSP_PROP_NAME:
+        val = std::string("usrp-e duc0");
+        return;
+
+    case DSP_PROP_OTHERS:
+        val = prop_names_t(); //empty
+        return;
+
+    case DSP_PROP_FREQ_SHIFT:
+        val = _duc_freq;
+        return;
+
+    case DSP_PROP_FREQ_SHIFT_NAMES:
+        val = prop_names_t(1, "");
+        return;
+
+    case DSP_PROP_CODEC_RATE:
+        val = _clock_ctrl->get_fpga_clock_rate();
+        return;
+
+    case DSP_PROP_HOST_RATE:
+        val = _clock_ctrl->get_fpga_clock_rate()/_duc_interp;
+        return;
+
+    default: UHD_THROW_PROP_GET_ERROR();
+    }
+}
+
+/***********************************************************************
+ * TX DUC Set
+ **********************************************************************/
+void usrp_e100_impl::tx_duc_set(const wax::obj &key_, const wax::obj &val){
+    named_prop_t key = named_prop_t::extract(key_);
+
+    switch(key.as<dsp_prop_t>()){
+
+    case DSP_PROP_FREQ_SHIFT:{
+            double new_freq = val.as<double>();
+            _iface->poke32(UE_REG_DSP_TX_FREQ,
+                dsp_type1::calc_cordic_word_and_update(new_freq, _clock_ctrl->get_fpga_clock_rate())
+            );
+            _duc_freq = new_freq; //shadow
+        }
+        return;
+
+    case DSP_PROP_HOST_RATE:{
+            _duc_interp = rint(_clock_ctrl->get_fpga_clock_rate()/val.as<double>());
+
+            //set the interpolation
+            _iface->poke32(UE_REG_DSP_TX_INTERP_RATE, dsp_type1::calc_cic_filter_word(_duc_interp));
+
+            //set the scaling
+            _iface->poke32(UE_REG_DSP_TX_SCALE_IQ, dsp_type1::calc_iq_scale_word(_duc_interp));
+        }
+        return;
+
+    default: UHD_THROW_PROP_SET_ERROR();
+    }
+}
diff --git a/host/lib/usrp/usrp_e100/fpga-downloader.cc b/host/lib/usrp/usrp_e100/fpga-downloader.cc
new file mode 100644
index 000000000..4a3d3b9af
--- /dev/null
+++ b/host/lib/usrp/usrp_e100/fpga-downloader.cc
@@ -0,0 +1,274 @@
+//
+// Copyright 2010 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include <uhd/config.hpp>
+#include <uhd/utils/assert.hpp>
+
+#include <iostream>
+#include <sstream>
+#include <fstream>
+#include <string>
+#include <cstdlib>
+#include <stdexcept>
+
+#include <fcntl.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/ioctl.h>
+
+#include <linux/spi/spidev.h>
+
+/*
+ * Configuration connections
+ *
+ * CCK    - MCSPI1_CLK
+ * DIN    - MCSPI1_MOSI
+ * PROG_B - GPIO_175     - output (change mux)
+ * DONE   - GPIO_173     - input  (change mux)
+ * INIT_B - GPIO_114     - input  (change mux)
+ *
+*/
+
+const unsigned int PROG_B = 175;
+const unsigned int DONE   = 173;
+const unsigned int INIT_B = 114;
+
+//static std::string bit_file = "safe_u1e.bin";
+
+const int BUF_SIZE = 4096;
+
+enum gpio_direction {IN, OUT};
+
+class gpio {
+	public:
+
+	gpio(unsigned int gpio_num, gpio_direction pin_direction);
+
+	bool get_value();
+	void set_value(bool state);
+
+	private:
+
+	std::stringstream base_path;
+	std::fstream value_file;	
+};
+
+class spidev {
+	public:
+
+	spidev(std::string dev_name);
+	~spidev();
+
+	void send(char *wbuf, char *rbuf, unsigned int nbytes);
+
+	private:
+
+	int fd;
+
+};
+
+gpio::gpio(unsigned int gpio_num, gpio_direction pin_direction)
+{
+	std::fstream export_file;
+
+	export_file.open("/sys/class/gpio/export", std::ios::out);
+	if (not export_file.is_open()) throw std::runtime_error(
+		"Failed to open gpio export file."
+	);
+
+	export_file << gpio_num << std::endl;
+
+	base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush;
+
+	std::fstream direction_file;
+	std::string direction_file_name;
+
+	if (gpio_num != 114) {
+		direction_file_name = base_path.str() + "/direction";
+
+		direction_file.open(direction_file_name.c_str());
+		if (!direction_file.is_open())
+			std::cout << "Failed to open direction file." << std::endl;
+		if (pin_direction == OUT)
+			direction_file << "out" << std::endl;
+		else
+			direction_file << "in" << std::endl;
+	}
+
+	std::string value_file_name;
+
+	value_file_name = base_path.str() + "/value";
+
+	value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out);
+	if (!value_file.is_open())
+		std::cout << "Failed to open value file." << std::endl;
+}
+
+bool gpio::get_value()
+{
+
+	std::string val;
+
+	std::getline(value_file, val);
+	value_file.seekg(0);
+
+	if (val == "0")
+		return false;
+	else if (val == "1")
+		return true;
+	else
+		std::cout << "Data read from value file|" << val << "|" << std::endl;
+
+	return false;
+}
+
+void gpio::set_value(bool state)
+{
+
+	if (state)
+		value_file << "1" << std::endl;
+	else
+		value_file << "0" << std::endl;
+}
+
+static void prepare_fpga_for_configuration(gpio &prog, gpio &)//init)
+{
+
+	prog.set_value(true);
+	prog.set_value(false);
+	prog.set_value(true);
+
+#if 0
+	bool ready_to_program(false);
+	unsigned int count(0);
+	do {
+		ready_to_program = init.get_value();
+		count++;
+
+		sleep(1);
+	} while (count < 10 && !ready_to_program);
+
+	if (count == 10) {
+		std::cout << "FPGA not ready for programming." << std::endl;
+		exit(-1);
+	}
+#endif
+}
+
+spidev::spidev(std::string fname)
+{
+	int ret;
+	int mode = 0;
+	int speed = 12000000;
+	int bits = 8;
+
+	fd = open(fname.c_str(), O_RDWR);
+
+	ret = ioctl(fd, SPI_IOC_WR_MODE, &mode);
+	ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed);
+	ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits);
+}
+	
+
+spidev::~spidev()
+{
+	close(fd);
+}
+
+void spidev::send(char *buf, char *rbuf, unsigned int nbytes)
+{
+	int ret;
+
+	struct spi_ioc_transfer tr;
+	tr.tx_buf = (unsigned long) buf;
+	tr.rx_buf = (unsigned long) rbuf;
+	tr.len = nbytes;
+	tr.delay_usecs = 0;
+	tr.speed_hz = 48000000;
+	tr.bits_per_word = 8;
+
+	ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);	
+
+}
+
+static void send_file_to_fpga(const std::string &file_name, gpio &error, gpio &done)
+{
+	std::ifstream bitstream;
+
+	std::cout << "File name - " << file_name.c_str() << std::endl;
+
+	bitstream.open(file_name.c_str(), std::ios::binary);
+	if (!bitstream.is_open())
+		std::cout << "File " << file_name << " not opened succesfully." << std::endl;
+
+	spidev spi("/dev/spidev1.0");
+	char buf[BUF_SIZE];
+	char rbuf[BUF_SIZE];
+
+	do {
+		bitstream.read(buf, BUF_SIZE);
+		spi.send(buf, rbuf, bitstream.gcount());
+
+		if (error.get_value())
+			std::cout << "INIT_B went high, error occured." << std::endl;
+
+		if (!done.get_value())
+			std::cout << "Configuration complete." << std::endl;
+
+	} while (bitstream.gcount() == BUF_SIZE);
+}
+
+/*
+int main(int argc, char *argv[])
+{
+
+	gpio gpio_prog_b(PROG_B, OUT);
+	gpio gpio_init_b(INIT_B, IN);
+	gpio gpio_done  (DONE,   IN);
+
+	if (argc == 2)
+		bit_file = argv[1];
+
+	std::cout << "FPGA config file: " << bit_file << std::endl;
+
+	prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b);
+
+	std::cout << "Done = " << gpio_done.get_value() << std::endl;
+
+	send_file_to_fpga(bit_file, gpio_init_b, gpio_done);
+}
+*/
+
+void usrp_e100_load_fpga(const std::string &bin_file){
+	gpio gpio_prog_b(PROG_B, OUT);
+	gpio gpio_init_b(INIT_B, IN);
+	gpio gpio_done  (DONE,   IN);
+
+	std::cout << "Loading FPGA image: " << bin_file << "... " << std::flush;
+
+	UHD_ASSERT_THROW(std::system("/sbin/rmmod usrp_e") == 0);
+
+	prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b);
+
+	std::cout << "done = " << gpio_done.get_value() << std::endl;
+
+	send_file_to_fpga(bin_file, gpio_init_b, gpio_done);
+
+	UHD_ASSERT_THROW(std::system("/sbin/modprobe usrp_e") == 0);
+
+}
+
diff --git a/host/lib/usrp/usrp_e100/include/linux/usrp_e.h b/host/lib/usrp/usrp_e100/include/linux/usrp_e.h
new file mode 100644
index 000000000..4c6a5dd89
--- /dev/null
+++ b/host/lib/usrp/usrp_e100/include/linux/usrp_e.h
@@ -0,0 +1,91 @@
+
+/*
+ *  Copyright (C) 2010 Ettus Research, LLC
+ *
+ *  Written by Philip Balister <philip@opensdr.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ */
+
+#ifndef __USRP_E_H
+#define __USRP_E_H
+
+#include <linux/types.h>
+#include <linux/ioctl.h>
+
+struct usrp_e_ctl16 {
+	__u32 offset;
+	__u32 count;
+	__u16 buf[20];
+};
+
+struct usrp_e_ctl32 {
+	__u32 offset;
+	__u32 count;
+	__u32 buf[10];
+};
+
+/* SPI interface */
+
+#define UE_SPI_TXONLY	0
+#define UE_SPI_TXRX	1
+
+/* Defines for spi ctrl register */
+#define UE_SPI_CTRL_TXNEG	(1<<10)
+#define UE_SPI_CTRL_RXNEG	(1<<9)
+
+#define UE_SPI_PUSH_RISE	0
+#define UE_SPI_PUSH_FALL	UE_SPI_CTRL_TXNEG
+#define UE_SPI_LATCH_RISE	0
+#define UE_SPI_LATCH_FALL	UE_SPI_CTRL_RXNEG
+
+struct usrp_e_spi {
+	__u8 readback;
+	__u32 slave;
+	__u32 data;
+	__u32 length;
+	__u32 flags;
+};
+
+struct usrp_e_i2c {
+	__u8 addr;
+	__u32 len;
+	__u8 data[];
+};
+
+#define USRP_E_IOC_MAGIC	'u'
+#define USRP_E_WRITE_CTL16	_IOW(USRP_E_IOC_MAGIC, 0x20, struct usrp_e_ctl16)
+#define USRP_E_READ_CTL16	_IOWR(USRP_E_IOC_MAGIC, 0x21, struct usrp_e_ctl16)
+#define USRP_E_WRITE_CTL32	_IOW(USRP_E_IOC_MAGIC, 0x22, struct usrp_e_ctl32)
+#define USRP_E_READ_CTL32	_IOWR(USRP_E_IOC_MAGIC, 0x23, struct usrp_e_ctl32)
+#define USRP_E_SPI		_IOWR(USRP_E_IOC_MAGIC, 0x24, struct usrp_e_spi)
+#define USRP_E_I2C_READ		_IOWR(USRP_E_IOC_MAGIC, 0x25, struct usrp_e_i2c)
+#define USRP_E_I2C_WRITE	_IOW(USRP_E_IOC_MAGIC, 0x26, struct usrp_e_i2c)
+#define USRP_E_GET_RB_INFO      _IOR(USRP_E_IOC_MAGIC, 0x27, struct usrp_e_ring_buffer_size_t)
+#define USRP_E_GET_COMPAT_NUMBER _IO(USRP_E_IOC_MAGIC, 0x28)
+
+#define USRP_E_COMPAT_NUMBER 1
+
+/* Flag defines */
+#define RB_USER (1<<0)
+#define RB_KERNEL (1<<1)
+#define RB_OVERRUN (1<<2)
+#define RB_DMA_ACTIVE (1<<3)
+#define RB_USER_PROCESS (1<<4)
+
+struct ring_buffer_info {
+	int flags;
+	int len;
+};
+
+struct usrp_e_ring_buffer_size_t {
+	int num_pages_rx_flags;
+	int num_rx_frames;
+	int num_pages_tx_flags;
+	int num_tx_frames;
+};
+
+#endif
diff --git a/host/lib/usrp/usrp_e100/io_impl.cpp b/host/lib/usrp/usrp_e100/io_impl.cpp
new file mode 100644
index 000000000..7cb3e25e5
--- /dev/null
+++ b/host/lib/usrp/usrp_e100/io_impl.cpp
@@ -0,0 +1,272 @@
+//
+// Copyright 2010 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include "usrp_e100_impl.hpp"
+#include "usrp_e100_regs.hpp"
+#include <uhd/usrp/dsp_utils.hpp>
+#include <uhd/utils/thread_priority.hpp>
+#include <uhd/transport/bounded_buffer.hpp>
+#include "../../transport/vrt_packet_handler.hpp"
+#include <boost/bind.hpp>
+#include <boost/format.hpp>
+#include <boost/thread.hpp>
+#include <iostream>
+
+using namespace uhd;
+using namespace uhd::usrp;
+using namespace uhd::transport;
+
+zero_copy_if::sptr usrp_e100_make_mmap_zero_copy(usrp_e100_iface::sptr iface);
+
+/***********************************************************************
+ * Constants
+ **********************************************************************/
+static const size_t tx_async_report_sid = 1;
+static const int underflow_flags = async_metadata_t::EVENT_CODE_UNDERFLOW | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET;
+static const bool recv_debug = false;
+
+/***********************************************************************
+ * io impl details (internal to this file)
+ * - pirate crew of 1
+ * - bounded buffer
+ * - thread loop
+ * - vrt packet handler states
+ **********************************************************************/
+struct usrp_e100_impl::io_impl{
+    //state management for the vrt packet handler code
+    vrt_packet_handler::recv_state packet_handler_recv_state;
+    vrt_packet_handler::send_state packet_handler_send_state;
+    zero_copy_if::sptr data_xport;
+    bool continuous_streaming;
+    io_impl(usrp_e100_iface::sptr iface):
+        data_xport(usrp_e100_make_mmap_zero_copy(iface)),
+        recv_pirate_booty(recv_booty_type::make(data_xport->get_num_recv_frames())),
+        async_msg_fifo(bounded_buffer<async_metadata_t>::make(100/*messages deep*/))
+    {
+        /* NOP */
+    }
+
+    ~io_impl(void){
+        recv_pirate_crew_raiding = false;
+        recv_pirate_crew.interrupt_all();
+        recv_pirate_crew.join_all();
+    }
+
+    bool get_recv_buffs(vrt_packet_handler::managed_recv_buffs_t &buffs, double timeout){
+        UHD_ASSERT_THROW(buffs.size() == 1);
+        boost::this_thread::disable_interruption di; //disable because the wait can throw
+        return recv_pirate_booty->pop_with_timed_wait(buffs.front(), timeout);
+    }
+
+    //a pirate's life is the life for me!
+    void recv_pirate_loop(usrp_e100_clock_ctrl::sptr);
+    typedef bounded_buffer<managed_recv_buffer::sptr> recv_booty_type;
+    recv_booty_type::sptr recv_pirate_booty;
+    bounded_buffer<async_metadata_t>::sptr async_msg_fifo;
+    boost::thread_group recv_pirate_crew;
+    bool recv_pirate_crew_raiding;
+};
+
+/***********************************************************************
+ * Receive Pirate Loop
+ * - while raiding, loot for recv buffers
+ * - put booty into the alignment buffer
+ **********************************************************************/
+void usrp_e100_impl::io_impl::recv_pirate_loop(usrp_e100_clock_ctrl::sptr clock_ctrl)
+{
+    set_thread_priority_safe();
+    recv_pirate_crew_raiding = true;
+
+    while(recv_pirate_crew_raiding){
+        managed_recv_buffer::sptr buff = this->data_xport->get_recv_buff();
+        if (not buff.get()) continue; //ignore timeout/error buffers
+
+        if (recv_debug){
+            std::cout << "len " << buff->size() << std::endl;
+            for (size_t i = 0; i < 9; i++){
+                std::cout << boost::format("    0x%08x") % buff->cast<const boost::uint32_t *>()[i] << std::endl;
+            }
+            std::cout << std::endl << std::endl;
+        }
+
+        try{
+            //extract the vrt header packet info
+            vrt::if_packet_info_t if_packet_info;
+            if_packet_info.num_packet_words32 = buff->size()/sizeof(boost::uint32_t);
+            const boost::uint32_t *vrt_hdr = buff->cast<const boost::uint32_t *>();
+            vrt::if_hdr_unpack_le(vrt_hdr, if_packet_info);
+
+            //handle a tx async report message
+            if (if_packet_info.sid == tx_async_report_sid and if_packet_info.packet_type != vrt::if_packet_info_t::PACKET_TYPE_DATA){
+
+                //fill in the async metadata
+                async_metadata_t metadata;
+                metadata.channel = 0;
+                metadata.has_time_spec = if_packet_info.has_tsi and if_packet_info.has_tsf;
+                metadata.time_spec = time_spec_t(
+                    time_t(if_packet_info.tsi), size_t(if_packet_info.tsf), clock_ctrl->get_fpga_clock_rate()
+                );
+                metadata.event_code = vrt_packet_handler::get_context_code<async_metadata_t::event_code_t>(vrt_hdr, if_packet_info);
+
+                //print the famous U, and push the metadata into the message queue
+                if (metadata.event_code & underflow_flags) std::cerr << "U" << std::flush;
+                async_msg_fifo->push_with_pop_on_full(metadata);
+                continue;
+            }
+
+            //same number of frames as the data transport -> always immediate
+            recv_pirate_booty->push_with_wait(buff);
+
+        }catch(const std::exception &e){
+            std::cerr << "Error (usrp-e recv pirate loop): " << e.what() << std::endl;
+        }
+    }
+}
+
+/***********************************************************************
+ * Helper Functions
+ **********************************************************************/
+void usrp_e100_impl::io_init(void){
+    //setup otw types
+    _send_otw_type.width = 16;
+    _send_otw_type.shift = 0;
+    _send_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN;
+
+    _recv_otw_type.width = 16;
+    _recv_otw_type.shift = 0;
+    _recv_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN;
+
+    //setup before the registers (transport called to calculate max spp)
+    _io_impl = UHD_PIMPL_MAKE(io_impl, (_iface));
+
+    //setup rx data path
+    _iface->poke32(UE_REG_CTRL_RX_NSAMPS_PER_PKT, get_max_recv_samps_per_packet());
+    _iface->poke32(UE_REG_CTRL_RX_NCHANNELS, 1);
+    _iface->poke32(UE_REG_CTRL_RX_CLEAR_OVERRUN, 1); //reset
+    _iface->poke32(UE_REG_CTRL_RX_VRT_HEADER, 0
+        | (0x1 << 28) //if data with stream id
+        | (0x1 << 26) //has trailer
+        | (0x3 << 22) //integer time other
+        | (0x1 << 20) //fractional time sample count
+    );
+    _iface->poke32(UE_REG_CTRL_RX_VRT_STREAM_ID, 0);
+    _iface->poke32(UE_REG_CTRL_RX_VRT_TRAILER, 0);
+
+    //setup the tx policy
+    _iface->poke32(UE_REG_CTRL_TX_REPORT_SID, tx_async_report_sid);
+    _iface->poke32(UE_REG_CTRL_TX_POLICY, UE_FLAG_CTRL_TX_POLICY_NEXT_PACKET);
+
+    //spawn a pirate, yarrr!
+    _io_impl->recv_pirate_crew.create_thread(boost::bind(
+        &usrp_e100_impl::io_impl::recv_pirate_loop, _io_impl.get(), _clock_ctrl
+    ));
+}
+
+void usrp_e100_impl::issue_stream_cmd(const stream_cmd_t &stream_cmd){
+    _io_impl->continuous_streaming = (stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_START_CONTINUOUS);
+    _iface->poke32(UE_REG_CTRL_RX_STREAM_CMD, dsp_type1::calc_stream_cmd_word(
+        stream_cmd, get_max_recv_samps_per_packet()
+    ));
+    _iface->poke32(UE_REG_CTRL_RX_TIME_SECS,  boost::uint32_t(stream_cmd.time_spec.get_full_secs()));
+    _iface->poke32(UE_REG_CTRL_RX_TIME_TICKS, stream_cmd.time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate()));
+}
+
+void usrp_e100_impl::handle_overrun(size_t){
+    std::cerr << "O"; //the famous OOOOOOOOOOO
+    _iface->poke32(UE_REG_CTRL_RX_CLEAR_OVERRUN, 0);
+    if (_io_impl->continuous_streaming){
+        this->issue_stream_cmd(stream_cmd_t::STREAM_MODE_START_CONTINUOUS);
+    }
+}
+
+/***********************************************************************
+ * Data Send
+ **********************************************************************/
+bool get_send_buffs(
+    zero_copy_if::sptr trans, double timeout,
+    vrt_packet_handler::managed_send_buffs_t &buffs
+){
+    UHD_ASSERT_THROW(buffs.size() == 1);
+    buffs[0] = trans->get_send_buff(timeout);
+    return buffs[0].get() != NULL;
+}
+
+size_t usrp_e100_impl::get_max_send_samps_per_packet(void) const{
+    static const size_t hdr_size = 0
+        + vrt::max_if_hdr_words32*sizeof(boost::uint32_t)
+        - sizeof(vrt::if_packet_info_t().cid) //no class id ever used
+    ;
+    size_t bpp = _io_impl->data_xport->get_send_frame_size() - hdr_size;
+    return bpp/_send_otw_type.get_sample_size();
+}
+
+size_t usrp_e100_impl::send(
+    const std::vector<const void *> &buffs, size_t num_samps,
+    const tx_metadata_t &metadata, const io_type_t &io_type,
+    send_mode_t send_mode, double timeout
+){
+    return vrt_packet_handler::send(
+        _io_impl->packet_handler_send_state,       //last state of the send handler
+        buffs, num_samps,                          //buffer to fill
+        metadata, send_mode,                       //samples metadata
+        io_type, _send_otw_type,                   //input and output types to convert
+        _clock_ctrl->get_fpga_clock_rate(),        //master clock tick rate
+        uhd::transport::vrt::if_hdr_pack_le,
+        boost::bind(&get_send_buffs, _io_impl->data_xport, timeout, _1),
+        get_max_send_samps_per_packet()
+    );
+}
+
+/***********************************************************************
+ * Data Recv
+ **********************************************************************/
+size_t usrp_e100_impl::get_max_recv_samps_per_packet(void) const{
+    static const size_t hdr_size = 0
+        + vrt::max_if_hdr_words32*sizeof(boost::uint32_t)
+        + sizeof(vrt::if_packet_info_t().tlr) //forced to have trailer
+        - sizeof(vrt::if_packet_info_t().cid) //no class id ever used
+    ;
+    size_t bpp = _io_impl->data_xport->get_recv_frame_size() - hdr_size;
+    return bpp/_recv_otw_type.get_sample_size();
+}
+
+size_t usrp_e100_impl::recv(
+    const std::vector<void *> &buffs, size_t num_samps,
+    rx_metadata_t &metadata, const io_type_t &io_type,
+    recv_mode_t recv_mode, double timeout
+){
+    return vrt_packet_handler::recv(
+        _io_impl->packet_handler_recv_state,       //last state of the recv handler
+        buffs, num_samps,                          //buffer to fill
+        metadata, recv_mode,                       //samples metadata
+        io_type, _recv_otw_type,                   //input and output types to convert
+        _clock_ctrl->get_fpga_clock_rate(),        //master clock tick rate
+        uhd::transport::vrt::if_hdr_unpack_le,
+        boost::bind(&usrp_e100_impl::io_impl::get_recv_buffs, _io_impl.get(), _1, timeout),
+        boost::bind(&usrp_e100_impl::handle_overrun, this, _1)
+    );
+}
+
+/***********************************************************************
+ * Async Recv
+ **********************************************************************/
+bool usrp_e100_impl::recv_async_msg(
+    async_metadata_t &async_metadata, double timeout
+){
+    boost::this_thread::disable_interruption di; //disable because the wait can throw
+    return _io_impl->async_msg_fifo->pop_with_timed_wait(async_metadata, timeout);
+}
diff --git a/host/lib/usrp/usrp_e100/mboard_impl.cpp b/host/lib/usrp/usrp_e100/mboard_impl.cpp
new file mode 100644
index 000000000..03c4385aa
--- /dev/null
+++ b/host/lib/usrp/usrp_e100/mboard_impl.cpp
@@ -0,0 +1,198 @@
+//
+// Copyright 2010 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include "usrp_e100_impl.hpp"
+#include "usrp_e100_regs.hpp"
+#include <uhd/usrp/dsp_utils.hpp>
+#include <uhd/usrp/misc_utils.hpp>
+#include <uhd/utils/assert.hpp>
+#include <uhd/usrp/mboard_props.hpp>
+#include <boost/bind.hpp>
+#include <iostream>
+
+using namespace uhd;
+using namespace uhd::usrp;
+
+/***********************************************************************
+ * Mboard Initialization
+ **********************************************************************/
+void usrp_e100_impl::mboard_init(void){
+    _mboard_proxy = wax_obj_proxy::make(
+        boost::bind(&usrp_e100_impl::mboard_get, this, _1, _2),
+        boost::bind(&usrp_e100_impl::mboard_set, this, _1, _2)
+    );
+
+    //init the clock config
+    _clock_config.ref_source = clock_config_t::REF_AUTO;
+    _clock_config.pps_source = clock_config_t::PPS_SMA;
+    _clock_config.pps_polarity = clock_config_t::PPS_NEG;
+
+    update_clock_config();
+}
+
+void usrp_e100_impl::update_clock_config(void){
+    boost::uint32_t pps_flags = 0;
+
+    //translate pps polarity enums
+    switch(_clock_config.pps_polarity){
+    case clock_config_t::PPS_POS: pps_flags |= UE_FLAG_TIME64_PPS_POSEDGE; break;
+    case clock_config_t::PPS_NEG: pps_flags |= UE_FLAG_TIME64_PPS_NEGEDGE; break;
+    default: throw std::runtime_error("unhandled clock configuration pps polarity");
+    }
+
+    //set the pps flags
+    _iface->poke32(UE_REG_TIME64_FLAGS, pps_flags);
+
+    //clock source ref 10mhz
+    switch(_clock_config.ref_source){
+    case clock_config_t::REF_AUTO: _clock_ctrl->use_auto_ref();
+    case clock_config_t::REF_INT: _clock_ctrl->use_internal_ref();
+    case clock_config_t::REF_SMA: _clock_ctrl->use_external_ref();
+    default: throw std::runtime_error("unhandled clock configuration ref source");
+    }
+}
+
+/***********************************************************************
+ * Mboard Get
+ **********************************************************************/
+void usrp_e100_impl::mboard_get(const wax::obj &key_, wax::obj &val){
+    named_prop_t key = named_prop_t::extract(key_);
+
+    //handle the get request conditioned on the key
+    switch(key.as<mboard_prop_t>()){
+    case MBOARD_PROP_NAME:
+        val = std::string("usrp-e mboard");
+        return;
+
+    case MBOARD_PROP_OTHERS:
+        val = prop_names_t();
+        return;
+
+    case MBOARD_PROP_RX_DBOARD:
+        UHD_ASSERT_THROW(key.name == "");
+        val = _rx_dboard_proxy->get_link();
+        return;
+
+    case MBOARD_PROP_RX_DBOARD_NAMES:
+        val = prop_names_t(1, ""); //vector of size 1 with empty string
+        return;
+
+    case MBOARD_PROP_TX_DBOARD:
+        UHD_ASSERT_THROW(key.name == "");
+        val = _tx_dboard_proxy->get_link();
+        return;
+
+    case MBOARD_PROP_TX_DBOARD_NAMES:
+        val = prop_names_t(1, ""); //vector of size 1 with empty string
+        return;
+
+    case MBOARD_PROP_RX_DSP:
+        UHD_ASSERT_THROW(key.name == "");
+        val = _rx_ddc_proxy->get_link();
+        return;
+
+    case MBOARD_PROP_RX_DSP_NAMES:
+        val = prop_names_t(1, "");
+        return;
+
+    case MBOARD_PROP_TX_DSP:
+        UHD_ASSERT_THROW(key.name == "");
+        val = _tx_duc_proxy->get_link();
+        return;
+
+    case MBOARD_PROP_TX_DSP_NAMES:
+        val = prop_names_t(1, "");
+        return;
+
+    case MBOARD_PROP_CLOCK_CONFIG:
+        val = _clock_config;
+        return;
+
+    case MBOARD_PROP_RX_SUBDEV_SPEC:
+        val = _rx_subdev_spec;
+        return;
+
+    case MBOARD_PROP_TX_SUBDEV_SPEC:
+        val = _tx_subdev_spec;
+        return;
+
+    case MBOARD_PROP_EEPROM_MAP:
+        val = _iface->mb_eeprom;
+        return;
+
+    default: UHD_THROW_PROP_GET_ERROR();
+    }
+}
+
+/***********************************************************************
+ * Mboard Set
+ **********************************************************************/
+void usrp_e100_impl::mboard_set(const wax::obj &key, const wax::obj &val){
+    //handle the get request conditioned on the key
+    switch(key.as<mboard_prop_t>()){
+
+    case MBOARD_PROP_STREAM_CMD:
+        issue_stream_cmd(val.as<stream_cmd_t>());
+        return;
+
+    case MBOARD_PROP_TIME_NOW:
+    case MBOARD_PROP_TIME_NEXT_PPS:{
+            time_spec_t time_spec = val.as<time_spec_t>();
+            _iface->poke32(UE_REG_TIME64_TICKS, time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate()));
+            boost::uint32_t imm_flags = (key.as<mboard_prop_t>() == MBOARD_PROP_TIME_NOW)? 1 : 0;
+            _iface->poke32(UE_REG_TIME64_IMM, imm_flags);
+            _iface->poke32(UE_REG_TIME64_SECS, time_spec.get_full_secs());
+        }
+        return;
+
+    case MBOARD_PROP_RX_SUBDEV_SPEC:
+        _rx_subdev_spec = val.as<subdev_spec_t>();
+        verify_rx_subdev_spec(_rx_subdev_spec, _mboard_proxy->get_link());
+        //sanity check
+        UHD_ASSERT_THROW(_rx_subdev_spec.size() == 1);
+        //set the mux
+        _iface->poke32(UE_REG_DSP_RX_MUX, dsp_type1::calc_rx_mux_word(
+            _dboard_manager->get_rx_subdev(_rx_subdev_spec.front().sd_name)[SUBDEV_PROP_CONNECTION].as<subdev_conn_t>()
+        ));
+        return;
+
+    case MBOARD_PROP_TX_SUBDEV_SPEC:
+        _tx_subdev_spec = val.as<subdev_spec_t>();
+        verify_tx_subdev_spec(_tx_subdev_spec, _mboard_proxy->get_link());
+        //sanity check
+        UHD_ASSERT_THROW(_tx_subdev_spec.size() == 1);
+        //set the mux
+        _iface->poke32(UE_REG_DSP_TX_MUX, dsp_type1::calc_tx_mux_word(
+            _dboard_manager->get_tx_subdev(_tx_subdev_spec.front().sd_name)[SUBDEV_PROP_CONNECTION].as<subdev_conn_t>()
+        ));
+        return;
+
+    case MBOARD_PROP_EEPROM_MAP:
+        // Step1: commit the map, writing only those values set.
+        // Step2: readback the entire eeprom map into the iface.
+        val.as<mboard_eeprom_t>().commit(_iface->get_i2c_dev_iface(), mboard_eeprom_t::MAP_E100);
+        _iface->mb_eeprom = mboard_eeprom_t(_iface->get_i2c_dev_iface(), mboard_eeprom_t::MAP_E100);
+        return;
+        
+    case MBOARD_PROP_CLOCK_CONFIG:
+        _clock_config = val.as<clock_config_t>();
+        update_clock_config();
+        return;
+
+    default: UHD_THROW_PROP_SET_ERROR();
+    }
+}
diff --git a/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp b/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp
new file mode 100644
index 000000000..40c7afabb
--- /dev/null
+++ b/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp
@@ -0,0 +1,268 @@
+//
+// Copyright 2010 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include "usrp_e100_iface.hpp"
+#include <uhd/utils/assert.hpp>
+#include <sys/ioctl.h> //ioctl
+#include <fcntl.h> //open, close
+#include <linux/usrp_e.h> //ioctl structures and constants
+#include <boost/format.hpp>
+#include <boost/thread.hpp> //mutex
+#include <linux/i2c-dev.h>
+#include <linux/i2c.h>
+#include <stdexcept>
+
+using namespace uhd;
+using namespace uhd::usrp;
+
+/***********************************************************************
+ * I2C device node implementation wrapper
+ **********************************************************************/
+class i2c_dev_iface : public i2c_iface{
+public:
+    i2c_dev_iface(const std::string &node){
+        if ((_node_fd = ::open(node.c_str(), O_RDWR)) < 0){
+            throw std::runtime_error("Failed to open " + node);
+        }
+    }
+
+    ~i2c_dev_iface(void){
+        ::close(_node_fd);
+    }
+
+    void write_i2c(boost::uint8_t addr, const byte_vector_t &bytes){
+        byte_vector_t rw_bytes(bytes);
+
+        //setup the message
+        i2c_msg msg;
+        msg.addr = addr;
+        msg.flags = 0;
+        msg.len = bytes.size();
+        msg.buf = &rw_bytes.front();
+
+        //setup the data
+        i2c_rdwr_ioctl_data data;
+        data.msgs = &msg;
+        data.nmsgs = 1;
+
+        //call the ioctl
+        UHD_ASSERT_THROW(::ioctl(_node_fd, I2C_RDWR, &data) >= 0);
+    }
+
+    byte_vector_t read_i2c(boost::uint8_t addr, size_t num_bytes){
+        byte_vector_t bytes(num_bytes);
+
+        //setup the message
+        i2c_msg msg;
+        msg.addr = addr;
+        msg.flags = I2C_M_RD;
+        msg.len = bytes.size();
+        msg.buf = &bytes.front();
+
+        //setup the data
+        i2c_rdwr_ioctl_data data;
+        data.msgs = &msg;
+        data.nmsgs = 1;
+
+        //call the ioctl
+        UHD_ASSERT_THROW(::ioctl(_node_fd, I2C_RDWR, &data) >= 0);
+
+        return bytes;
+    }
+
+private: int _node_fd;
+};
+
+/***********************************************************************
+ * USRP-E100 interface implementation
+ **********************************************************************/
+class usrp_e100_iface_impl : public usrp_e100_iface{
+public:
+
+    int get_file_descriptor(void){
+        return _node_fd;
+    }
+
+    /*******************************************************************
+     * Structors
+     ******************************************************************/
+    usrp_e100_iface_impl(const std::string &node):
+        _i2c_dev_iface(i2c_dev_iface("/dev/i2c-3"))
+    {
+        //open the device node and check file descriptor
+        if ((_node_fd = ::open(node.c_str(), O_RDWR)) < 0){
+            throw std::runtime_error("Failed to open " + node);
+        }
+
+        mb_eeprom = mboard_eeprom_t(get_i2c_dev_iface(), mboard_eeprom_t::MAP_E100);
+    }
+
+    ~usrp_e100_iface_impl(void){
+        //close the device node file descriptor
+        ::close(_node_fd);
+    }
+
+    /*******************************************************************
+     * IOCTL: provides the communication base for all other calls
+     ******************************************************************/
+    void ioctl(int request, void *mem){
+        boost::mutex::scoped_lock lock(_ctrl_mutex);
+
+        if (::ioctl(_node_fd, request, mem) < 0){
+            throw std::runtime_error(str(
+                boost::format("ioctl failed with request %d") % request
+            ));
+        }
+    }
+
+    /*******************************************************************
+     * I2C device node interface
+     ******************************************************************/
+    i2c_iface &get_i2c_dev_iface(void){
+        return _i2c_dev_iface;
+    }
+
+    /*******************************************************************
+     * Peek and Poke
+     ******************************************************************/
+    void poke32(boost::uint32_t addr, boost::uint32_t value){
+        //load the data struct
+        usrp_e_ctl32 data;
+        data.offset = addr;
+        data.count = 1;
+        data.buf[0] = value;
+
+        //call the ioctl
+        this->ioctl(USRP_E_WRITE_CTL32, &data);
+    }
+
+    void poke16(boost::uint32_t addr, boost::uint16_t value){
+        //load the data struct
+        usrp_e_ctl16 data;
+        data.offset = addr;
+        data.count = 1;
+        data.buf[0] = value;
+
+        //call the ioctl
+        this->ioctl(USRP_E_WRITE_CTL16, &data);
+    }
+
+    boost::uint32_t peek32(boost::uint32_t addr){
+        //load the data struct
+        usrp_e_ctl32 data;
+        data.offset = addr;
+        data.count = 1;
+
+        //call the ioctl
+        this->ioctl(USRP_E_READ_CTL32, &data);
+
+        return data.buf[0];
+    }
+
+    boost::uint16_t peek16(boost::uint32_t addr){
+        //load the data struct
+        usrp_e_ctl16 data;
+        data.offset = addr;
+        data.count = 1;
+
+        //call the ioctl
+        this->ioctl(USRP_E_READ_CTL16, &data);
+
+        return data.buf[0];
+    }
+
+    /*******************************************************************
+     * I2C
+     ******************************************************************/
+    static const size_t max_i2c_data_bytes = 10;
+
+    void write_i2c(boost::uint8_t addr, const byte_vector_t &bytes){
+        //allocate some memory for this transaction
+        UHD_ASSERT_THROW(bytes.size() <= max_i2c_data_bytes);
+        boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes];
+
+        //load the data struct
+        usrp_e_i2c *data = reinterpret_cast<usrp_e_i2c*>(mem);
+        data->addr = addr;
+        data->len = bytes.size();
+        std::copy(bytes.begin(), bytes.end(), data->data);
+
+        //call the spi ioctl
+        this->ioctl(USRP_E_I2C_WRITE, data);
+    }
+
+    byte_vector_t read_i2c(boost::uint8_t addr, size_t num_bytes){
+        //allocate some memory for this transaction
+        UHD_ASSERT_THROW(num_bytes <= max_i2c_data_bytes);
+        boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes];
+
+        //load the data struct
+        usrp_e_i2c *data = reinterpret_cast<usrp_e_i2c*>(mem);
+        data->addr = addr;
+        data->len = num_bytes;
+
+        //call the spi ioctl
+        this->ioctl(USRP_E_I2C_READ, data);
+
+        //unload the data
+        byte_vector_t bytes(data->len);
+        UHD_ASSERT_THROW(bytes.size() == num_bytes);
+        std::copy(data->data, data->data+bytes.size(), bytes.begin());
+        return bytes;
+    }
+
+    /*******************************************************************
+     * SPI
+     ******************************************************************/
+    boost::uint32_t transact_spi(
+        int which_slave,
+        const spi_config_t &config,
+        boost::uint32_t bits,
+        size_t num_bits,
+        bool readback
+    ){
+        //load data struct
+        usrp_e_spi data;
+        data.readback = (readback)? UE_SPI_TXRX : UE_SPI_TXONLY;
+        data.slave = which_slave;
+        data.length = num_bits;
+        data.data = bits;
+
+        //load the flags
+        data.flags = 0;
+        data.flags |= (config.miso_edge == spi_config_t::EDGE_RISE)? UE_SPI_LATCH_RISE : UE_SPI_LATCH_FALL;
+        data.flags |= (config.mosi_edge == spi_config_t::EDGE_RISE)? UE_SPI_PUSH_FALL  : UE_SPI_PUSH_RISE;
+
+        //call the spi ioctl
+        this->ioctl(USRP_E_SPI, &data);
+
+        //unload the data
+        return data.data;
+    }
+
+private:
+    int _node_fd;
+    i2c_dev_iface _i2c_dev_iface;
+    boost::mutex _ctrl_mutex;
+};
+
+/***********************************************************************
+ * Public Make Function
+ **********************************************************************/
+usrp_e100_iface::sptr usrp_e100_iface::make(const std::string &node){
+    return sptr(new usrp_e100_iface_impl(node));
+}
diff --git a/host/lib/usrp/usrp_e100/usrp_e100_iface.hpp b/host/lib/usrp/usrp_e100/usrp_e100_iface.hpp
new file mode 100644
index 000000000..12283fb52
--- /dev/null
+++ b/host/lib/usrp/usrp_e100/usrp_e100_iface.hpp
@@ -0,0 +1,119 @@
+//
+// Copyright 2010 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#ifndef INCLUDED_USRP_E100_IFACE_HPP
+#define INCLUDED_USRP_E100_IFACE_HPP
+
+#include <uhd/transport/udp_simple.hpp>
+#include <uhd/usrp/mboard_eeprom.hpp>
+#include <uhd/types/serial.hpp>
+#include <boost/shared_ptr.hpp>
+#include <boost/utility.hpp>
+#include <boost/cstdint.hpp>
+
+////////////////////////////////////////////////////////////////////////
+// I2C addresses
+////////////////////////////////////////////////////////////////////////
+#define I2C_DEV_EEPROM  0x50 // 24LC02[45]:  7-bits 1010xxx
+#define	I2C_ADDR_MBOARD (I2C_DEV_EEPROM | 0x0)
+#define	I2C_ADDR_TX_DB  (I2C_DEV_EEPROM | 0x4)
+#define	I2C_ADDR_RX_DB  (I2C_DEV_EEPROM | 0x5)
+////////////////////////////////////////////////////////////////////////
+
+/*!
+ * The usrp-e interface class:
+ * Provides a set of functions to implementation layer.
+ * Including spi, peek, poke, control...
+ */
+class usrp_e100_iface : boost::noncopyable, public uhd::i2c_iface{
+public:
+    typedef boost::shared_ptr<usrp_e100_iface> sptr;
+
+    /*!
+     * Make a new usrp-e interface with the control transport.
+     * \param node the device node name
+     * \return a new usrp-e interface object
+     */
+    static sptr make(const std::string &node);
+
+    /*!
+     * Get the underlying file descriptor.
+     * \return the file descriptor
+     */
+    virtual int get_file_descriptor(void) = 0;
+
+    /*!
+     * Perform an ioctl call on the device node file descriptor.
+     * This will throw when the internal ioctl call fails.
+     * \param request the control word
+     * \param mem pointer to some memory
+     */
+    virtual void ioctl(int request, void *mem) = 0;
+
+    //! Get the I2C interface for the I2C device node
+    virtual uhd::i2c_iface &get_i2c_dev_iface(void) = 0;
+
+    /*!
+     * Write a register (32 bits)
+     * \param addr the address
+     * \param data the 32bit data
+     */
+    virtual void poke32(boost::uint32_t addr, boost::uint32_t data) = 0;
+
+    /*!
+     * Read a register (32 bits)
+     * \param addr the address
+     * \return the 32bit data
+     */
+    virtual boost::uint32_t peek32(boost::uint32_t addr) = 0;
+
+    /*!
+     * Write a register (16 bits)
+     * \param addr the address
+     * \param data the 16bit data
+     */
+    virtual void poke16(boost::uint32_t addr, boost::uint16_t data) = 0;
+
+    /*!
+     * Read a register (16 bits)
+     * \param addr the address
+     * \return the 16bit data
+     */
+    virtual boost::uint16_t peek16(boost::uint32_t addr) = 0;
+
+    /*!
+     * Perform an spi transaction.
+     * \param which_slave the slave device number
+     * \param config spi config args
+     * \param data the bits to write
+     * \param num_bits how many bits in data
+     * \param readback true to readback a value
+     * \return spi data if readback set
+     */
+    virtual boost::uint32_t transact_spi(
+        int which_slave,
+        const uhd::spi_config_t &config,
+        boost::uint32_t data,
+        size_t num_bits,
+        bool readback
+    ) = 0;
+
+    //motherboard eeprom map structure
+    uhd::usrp::mboard_eeprom_t mb_eeprom;
+};
+
+#endif /* INCLUDED_USRP_E100_IFACE_HPP */
diff --git a/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp b/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp
new file mode 100644
index 000000000..40ea56466
--- /dev/null
+++ b/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp
@@ -0,0 +1,212 @@
+//
+// Copyright 2010 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include "usrp_e100_impl.hpp"
+#include "usrp_e100_regs.hpp"
+#include <uhd/usrp/device_props.hpp>
+#include <uhd/usrp/mboard_props.hpp>
+#include <uhd/utils/assert.hpp>
+#include <uhd/utils/static.hpp>
+#include <uhd/utils/images.hpp>
+#include <uhd/utils/warning.hpp>
+#include <boost/format.hpp>
+#include <boost/filesystem.hpp>
+#include <boost/functional/hash.hpp>
+#include <iostream>
+#include <fstream>
+
+using namespace uhd;
+using namespace uhd::usrp;
+namespace fs = boost::filesystem;
+
+/***********************************************************************
+ * Discovery
+ **********************************************************************/
+static device_addrs_t usrp_e100_find(const device_addr_t &hint){
+    device_addrs_t usrp_e100_addrs;
+
+    //return an empty list of addresses when type is set to non-usrp-e
+    if (hint.has_key("type") and hint["type"] != "usrp-e") return usrp_e100_addrs;
+
+    //device node not provided, assume its 0
+    if (not hint.has_key("node")){
+        device_addr_t new_addr = hint;
+        new_addr["node"] = "/dev/usrp_e0";
+        return usrp_e100_find(new_addr);
+    }
+
+    //use the given device node name
+    if (fs::exists(hint["node"])){
+        device_addr_t new_addr;
+        new_addr["type"] = "usrp-e";
+        new_addr["node"] = fs::system_complete(fs::path(hint["node"])).file_string();
+        try{
+            usrp_e100_iface::sptr iface = usrp_e100_iface::make(new_addr["node"]);
+            new_addr["name"] = iface->mb_eeprom["name"];
+            new_addr["serial"] = iface->mb_eeprom["serial"];
+            if (
+                (not hint.has_key("name")   or hint["name"]   == new_addr["name"]) and
+                (not hint.has_key("serial") or hint["serial"] == new_addr["serial"])
+            ){
+                usrp_e100_addrs.push_back(new_addr);
+            }
+        }
+        catch(const std::exception &e){
+            uhd::warning::post(
+                std::string("Ignoring discovered device\n")
+                + e.what()
+            );
+        }
+    }
+
+    return usrp_e100_addrs;
+}
+
+/***********************************************************************
+ * Make
+ **********************************************************************/
+static device::sptr usrp_e100_make(const device_addr_t &device_addr){
+
+    //setup the main interface into fpga
+    std::string node = device_addr["node"];
+    std::cout << boost::format("Opening USRP-E on %s") % node << std::endl;
+    usrp_e100_iface::sptr iface = usrp_e100_iface::make(node);
+
+    //------------------------------------------------------------------
+    //-- Handle the FPGA loading...
+    //-- The image can be confimed as already loaded when:
+    //--   1) The compatibility number matches.
+    //--   2) The hash in the hash-file matches.
+    //------------------------------------------------------------------
+    static const char *hash_file_path = "/tmp/usrp_e100_hash";
+
+    //extract the fpga path for usrp-e
+    std::string usrp_e100_fpga_image = find_image_path(
+        device_addr.has_key("fpga")? device_addr["fpga"] : "usrp_e100_fpga.bin"
+    );
+
+    //calculate a hash of the fpga file
+    size_t fpga_hash = 0;
+    {
+        std::ifstream file(usrp_e100_fpga_image.c_str());
+        if (not file.good()) throw std::runtime_error(
+            "cannot open fpga file for read: " + usrp_e100_fpga_image
+        );
+        do{
+            boost::hash_combine(fpga_hash, file.get());
+        } while (file.good());
+        file.close();
+    }
+
+    //read the compatibility number
+    boost::uint16_t fpga_compat_num = iface->peek16(UE_REG_MISC_COMPAT);
+
+    //read the hash in the hash-file
+    size_t loaded_hash = 0;
+    try{std::ifstream(hash_file_path) >> loaded_hash;}catch(...){}
+
+    //if not loaded: load the fpga image and write the hash-file
+    if (fpga_compat_num != USRP_E_COMPAT_NUM or loaded_hash != fpga_hash){
+        iface.reset();
+        usrp_e100_load_fpga(usrp_e100_fpga_image);
+	sleep(1); ///\todo do this better one day.
+        std::cout << boost::format("re-Opening USRP-E on %s") % node << std::endl;
+        iface = usrp_e100_iface::make(node);
+        try{std::ofstream(hash_file_path) << fpga_hash;}catch(...){}
+    }
+
+    //check that the compatibility is correct
+    fpga_compat_num = iface->peek16(UE_REG_MISC_COMPAT);
+    if (fpga_compat_num != USRP_E_COMPAT_NUM){
+        throw std::runtime_error(str(boost::format(
+            "Expected fpga compatibility number 0x%x, but got 0x%x:\n"
+            "The fpga build is not compatible with the host code build."
+        ) % USRP_E_COMPAT_NUM % fpga_compat_num));
+    }
+
+    return device::sptr(new usrp_e100_impl(iface));
+}
+
+UHD_STATIC_BLOCK(register_usrp_e100_device){
+    device::register_device(&usrp_e100_find, &usrp_e100_make);
+}
+
+/***********************************************************************
+ * Structors
+ **********************************************************************/
+usrp_e100_impl::usrp_e100_impl(usrp_e100_iface::sptr iface): _iface(iface){
+
+    //setup interfaces into hardware
+    _clock_ctrl = usrp_e100_clock_ctrl::make(_iface);
+    _codec_ctrl = usrp_e100_codec_ctrl::make(_iface);
+
+    //initialize the mboard
+    mboard_init();
+
+    //initialize the dboards
+    dboard_init();
+
+    //initialize the dsps
+    rx_ddc_init();
+    tx_duc_init();
+
+    //init the codec properties
+    codec_init();
+
+    //init the io send/recv
+    io_init();
+
+    //set default subdev specs
+    this->mboard_set(MBOARD_PROP_RX_SUBDEV_SPEC, subdev_spec_t());
+    this->mboard_set(MBOARD_PROP_TX_SUBDEV_SPEC, subdev_spec_t());
+}
+
+usrp_e100_impl::~usrp_e100_impl(void){
+    /* NOP */
+}
+
+/***********************************************************************
+ * Device Get
+ **********************************************************************/
+void usrp_e100_impl::get(const wax::obj &key_, wax::obj &val){
+    named_prop_t key = named_prop_t::extract(key_);
+
+    //handle the get request conditioned on the key
+    switch(key.as<device_prop_t>()){
+    case DEVICE_PROP_NAME:
+        val = std::string("usrp-e device");
+        return;
+
+    case DEVICE_PROP_MBOARD:
+        UHD_ASSERT_THROW(key.name == "");
+        val = _mboard_proxy->get_link();
+        return;
+
+    case DEVICE_PROP_MBOARD_NAMES:
+        val = prop_names_t(1, ""); //vector of size 1 with empty string
+        return;
+
+    default: UHD_THROW_PROP_GET_ERROR();
+    }
+}
+
+/***********************************************************************
+ * Device Set
+ **********************************************************************/
+void usrp_e100_impl::set(const wax::obj &, const wax::obj &){
+    UHD_THROW_PROP_SET_ERROR();
+}
diff --git a/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp b/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp
new file mode 100644
index 000000000..de158ea5e
--- /dev/null
+++ b/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp
@@ -0,0 +1,167 @@
+//
+// Copyright 2010 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include "usrp_e100_iface.hpp"
+#include "clock_ctrl.hpp"
+#include "codec_ctrl.hpp"
+#include <uhd/device.hpp>
+#include <uhd/utils/pimpl.hpp>
+#include <uhd/usrp/subdev_spec.hpp>
+#include <uhd/usrp/dboard_eeprom.hpp>
+#include <uhd/types/otw_type.hpp>
+#include <uhd/types/clock_config.hpp>
+#include <uhd/types/stream_cmd.hpp>
+#include <uhd/usrp/dboard_manager.hpp>
+
+#ifndef INCLUDED_USRP_E100_IMPL_HPP
+#define INCLUDED_USRP_E100_IMPL_HPP
+
+static const boost::uint16_t USRP_E_COMPAT_NUM = 0x02;
+
+//! load an fpga image from a bin file into the usrp-e fpga
+extern void usrp_e100_load_fpga(const std::string &bin_file);
+
+/*!
+ * Make a usrp-e dboard interface.
+ * \param iface the usrp-e interface object
+ * \param clock the clock control interface
+ * \param codec the codec control interface
+ * \return a sptr to a new dboard interface
+ */
+uhd::usrp::dboard_iface::sptr make_usrp_e100_dboard_iface(
+    usrp_e100_iface::sptr iface,
+    usrp_e100_clock_ctrl::sptr clock,
+    usrp_e100_codec_ctrl::sptr codec
+);
+
+/*!
+ * Simple wax obj proxy class:
+ * Provides a wax obj interface for a set and a get function.
+ * This allows us to create nested properties structures
+ * while maintaining flattened code within the implementation.
+ */
+class wax_obj_proxy : public wax::obj{
+public:
+    typedef boost::function<void(const wax::obj &, wax::obj &)>       get_t;
+    typedef boost::function<void(const wax::obj &, const wax::obj &)> set_t;
+    typedef boost::shared_ptr<wax_obj_proxy> sptr;
+
+    static sptr make(const get_t &get, const set_t &set){
+        return sptr(new wax_obj_proxy(get, set));
+    }
+
+private:
+    get_t _get; set_t _set;
+    wax_obj_proxy(const get_t &get, const set_t &set): _get(get), _set(set){};
+    void get(const wax::obj &key, wax::obj &val){return _get(key, val);}
+    void set(const wax::obj &key, const wax::obj &val){return _set(key, val);}
+};
+
+/*!
+ * USRP-E100 implementation guts:
+ * The implementation details are encapsulated here.
+ * Handles properties on the mboard, dboard, dsps...
+ */
+class usrp_e100_impl : public uhd::device{
+public:
+    //structors
+    usrp_e100_impl(usrp_e100_iface::sptr);
+    ~usrp_e100_impl(void);
+
+    //the io interface
+    size_t send(const std::vector<const void *> &, size_t, const uhd::tx_metadata_t &, const uhd::io_type_t &, send_mode_t, double);
+    size_t recv(const std::vector<void *> &, size_t, uhd::rx_metadata_t &, const uhd::io_type_t &, recv_mode_t, double);
+    bool recv_async_msg(uhd::async_metadata_t &, double);
+    size_t get_max_send_samps_per_packet(void) const;
+    size_t get_max_recv_samps_per_packet(void) const;
+
+private:
+    //interface to ioctls and file descriptor
+    usrp_e100_iface::sptr _iface;
+
+    //handle io stuff
+    UHD_PIMPL_DECL(io_impl) _io_impl;
+    uhd::otw_type_t _send_otw_type, _recv_otw_type;
+    void io_init(void);
+    void issue_stream_cmd(const uhd::stream_cmd_t &stream_cmd);
+    void handle_overrun(size_t);
+
+    //configuration shadows
+    uhd::clock_config_t _clock_config;
+
+    //ad9522 clock control
+    usrp_e100_clock_ctrl::sptr _clock_ctrl;
+
+    //ad9862 codec control
+    usrp_e100_codec_ctrl::sptr _codec_ctrl;
+
+    //device functions and settings
+    void get(const wax::obj &, wax::obj &);
+    void set(const wax::obj &, const wax::obj &);
+
+    //mboard functions and settings
+    void mboard_init(void);
+    void mboard_get(const wax::obj &, wax::obj &);
+    void mboard_set(const wax::obj &, const wax::obj &);
+    wax_obj_proxy::sptr _mboard_proxy;
+    uhd::usrp::subdev_spec_t _rx_subdev_spec, _tx_subdev_spec;
+
+    //xx dboard functions and settings
+    void dboard_init(void);
+    uhd::usrp::dboard_manager::sptr _dboard_manager;
+    uhd::usrp::dboard_iface::sptr _dboard_iface;
+
+    //rx dboard functions and settings
+    uhd::usrp::dboard_eeprom_t _rx_db_eeprom;
+    void rx_dboard_get(const wax::obj &, wax::obj &);
+    void rx_dboard_set(const wax::obj &, const wax::obj &);
+    wax_obj_proxy::sptr _rx_dboard_proxy;
+
+    //tx dboard functions and settings
+    uhd::usrp::dboard_eeprom_t _tx_db_eeprom;
+    void tx_dboard_get(const wax::obj &, wax::obj &);
+    void tx_dboard_set(const wax::obj &, const wax::obj &);
+    wax_obj_proxy::sptr _tx_dboard_proxy;
+
+    //rx ddc functions and settings
+    void rx_ddc_init(void);
+    void rx_ddc_get(const wax::obj &, wax::obj &);
+    void rx_ddc_set(const wax::obj &, const wax::obj &);
+    double _ddc_freq; size_t _ddc_decim;
+    wax_obj_proxy::sptr _rx_ddc_proxy;
+
+    //tx duc functions and settings
+    void tx_duc_init(void);
+    void tx_duc_get(const wax::obj &, wax::obj &);
+    void tx_duc_set(const wax::obj &, const wax::obj &);
+    double _duc_freq; size_t _duc_interp;
+    wax_obj_proxy::sptr _tx_duc_proxy;
+
+    //codec functions and settings
+    void codec_init(void);
+    void rx_codec_get(const wax::obj &, wax::obj &);
+    void rx_codec_set(const wax::obj &, const wax::obj &);
+    void tx_codec_get(const wax::obj &, wax::obj &);
+    void tx_codec_set(const wax::obj &, const wax::obj &);
+    wax_obj_proxy::sptr _rx_codec_proxy, _tx_codec_proxy;
+    
+    //clock control functions and settings
+    void init_clock_config(void);
+    void update_clock_config(void);
+};
+
+#endif /* INCLUDED_USRP_E100_IMPL_HPP */
diff --git a/host/lib/usrp/usrp_e100/usrp_e100_mmap_zero_copy.cpp b/host/lib/usrp/usrp_e100/usrp_e100_mmap_zero_copy.cpp
new file mode 100644
index 000000000..bf378a9b1
--- /dev/null
+++ b/host/lib/usrp/usrp_e100/usrp_e100_mmap_zero_copy.cpp
@@ -0,0 +1,215 @@
+//
+// Copyright 2010 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include "usrp_e100_iface.hpp"
+#include <uhd/transport/zero_copy.hpp>
+#include <uhd/utils/assert.hpp>
+#include <linux/usrp_e.h>
+#include <sys/mman.h> //mmap
+#include <unistd.h> //getpagesize
+#include <poll.h> //poll
+#include <boost/bind.hpp>
+#include <boost/enable_shared_from_this.hpp>
+#include <iostream>
+
+using namespace uhd;
+using namespace uhd::transport;
+
+static const bool fp_verbose = false; //fast-path verbose
+static const bool sp_verbose = false; //slow-path verbose
+static const size_t poll_breakout = 10; //how many poll timeouts constitute a full timeout
+
+/***********************************************************************
+ * The zero copy interface implementation
+ **********************************************************************/
+class usrp_e100_mmap_zero_copy_impl : public zero_copy_if, public boost::enable_shared_from_this<usrp_e100_mmap_zero_copy_impl> {
+public:
+    usrp_e100_mmap_zero_copy_impl(usrp_e100_iface::sptr iface):
+        _fd(iface->get_file_descriptor()), _recv_index(0), _send_index(0)
+    {
+        //get system sizes
+        iface->ioctl(USRP_E_GET_RB_INFO, &_rb_size);
+        size_t page_size = getpagesize();
+        _frame_size = page_size/2;
+
+        //calculate the memory size
+        _map_size =
+            (_rb_size.num_pages_rx_flags + _rb_size.num_pages_tx_flags) * page_size +
+            (_rb_size.num_rx_frames + _rb_size.num_tx_frames) * _frame_size;
+
+        //print sizes summary
+        if (sp_verbose){
+            std::cout << "page_size:          " << page_size                   << std::endl;
+            std::cout << "frame_size:         " << _frame_size                 << std::endl;
+            std::cout << "num_pages_rx_flags: " << _rb_size.num_pages_rx_flags << std::endl;
+            std::cout << "num_rx_frames:      " << _rb_size.num_rx_frames      << std::endl;
+            std::cout << "num_pages_tx_flags: " << _rb_size.num_pages_tx_flags << std::endl;
+            std::cout << "num_tx_frames:      " << _rb_size.num_tx_frames      << std::endl;
+            std::cout << "map_size:           " << _map_size                   << std::endl;
+        }
+
+        //call mmap to get the memory
+        _mapped_mem = ::mmap(
+            NULL, _map_size, PROT_READ | PROT_WRITE, MAP_SHARED, _fd, 0
+        );
+        UHD_ASSERT_THROW(_mapped_mem != MAP_FAILED);
+
+        //calculate the memory offsets for info and buffers
+        size_t recv_info_off = 0;
+        size_t recv_buff_off = recv_info_off + (_rb_size.num_pages_rx_flags * page_size);
+        size_t send_info_off = recv_buff_off + (_rb_size.num_rx_frames * _frame_size);
+        size_t send_buff_off = send_info_off + (_rb_size.num_pages_tx_flags * page_size);
+
+        //print offset summary
+        if (sp_verbose){
+            std::cout << "recv_info_off: " << recv_info_off << std::endl;
+            std::cout << "recv_buff_off: " << recv_buff_off << std::endl;
+            std::cout << "send_info_off: " << send_info_off << std::endl;
+            std::cout << "send_buff_off: " << send_buff_off << std::endl;
+        }
+
+        //set the internal pointers for info and buffers
+        typedef ring_buffer_info (*rbi_pta)[];
+        char *rb_ptr = reinterpret_cast<char *>(_mapped_mem);
+        _recv_info = reinterpret_cast<rbi_pta>(rb_ptr + recv_info_off);
+        _recv_buff = rb_ptr + recv_buff_off;
+        _send_info = reinterpret_cast<rbi_pta>(rb_ptr + send_info_off);
+        _send_buff = rb_ptr + send_buff_off;
+    }
+
+    ~usrp_e100_mmap_zero_copy_impl(void){
+        if (sp_verbose) std::cout << "cleanup: munmap" << std::endl;
+        ::munmap(_mapped_mem, _map_size);
+    }
+
+    managed_recv_buffer::sptr get_recv_buff(double timeout){
+        if (fp_verbose) std::cout << "get_recv_buff: " << _recv_index << std::endl;
+
+        //grab pointers to the info and buffer
+        ring_buffer_info *info = (*_recv_info) + _recv_index;
+        void *mem = _recv_buff + _frame_size*_recv_index;
+
+        //poll/wait for a ready frame
+        if (not (info->flags & RB_USER)){
+            for (size_t i = 0; i < poll_breakout; i++){
+                pollfd pfd;
+                pfd.fd = _fd;
+                pfd.events = POLLIN;
+                ssize_t poll_ret = ::poll(&pfd, 1, size_t(timeout*1e3/poll_breakout));
+                if (fp_verbose) std::cout << "  POLLIN: " << poll_ret << std::endl;
+                if (poll_ret > 0) goto found_user_frame; //good poll, continue on
+            }
+            return managed_recv_buffer::sptr(); //timed-out for real
+        } found_user_frame:
+
+        //the process has claimed the frame
+        info->flags = RB_USER_PROCESS;
+
+        //increment the index for the next call
+        if (++_recv_index == size_t(_rb_size.num_rx_frames)) _recv_index = 0;
+
+        //return the managed buffer for this frame
+        if (fp_verbose) std::cout << "  make_recv_buff: " << info->len << std::endl;
+        return managed_recv_buffer::make_safe(
+            boost::asio::const_buffer(mem, info->len),
+            boost::bind(&usrp_e100_mmap_zero_copy_impl::release, shared_from_this(), info)
+        );
+    }
+
+    size_t get_num_recv_frames(void) const{
+        return _rb_size.num_rx_frames;
+    }
+
+    size_t get_recv_frame_size(void) const{
+        return _frame_size;
+    }
+
+    managed_send_buffer::sptr get_send_buff(double timeout){
+        if (fp_verbose) std::cout << "get_send_buff: " << _send_index << std::endl;
+
+        //grab pointers to the info and buffer
+        ring_buffer_info *info = (*_send_info) + _send_index;
+        void *mem = _send_buff + _frame_size*_send_index;
+
+        //poll/wait for a ready frame
+        if (not (info->flags & RB_KERNEL)){
+            pollfd pfd;
+            pfd.fd = _fd;
+            pfd.events = POLLOUT;
+            ssize_t poll_ret = ::poll(&pfd, 1, size_t(timeout*1e3));
+            if (fp_verbose) std::cout << "  POLLOUT: " << poll_ret << std::endl;
+            if (poll_ret <= 0) return managed_send_buffer::sptr();
+        }
+
+        //increment the index for the next call
+        if (++_send_index == size_t(_rb_size.num_tx_frames)) _send_index = 0;
+
+        //return the managed buffer for this frame
+        if (fp_verbose) std::cout << "  make_send_buff: " << _frame_size << std::endl;
+        return managed_send_buffer::make_safe(
+            boost::asio::mutable_buffer(mem, _frame_size),
+            boost::bind(&usrp_e100_mmap_zero_copy_impl::commit, shared_from_this(), info, _1)
+        );
+    }
+
+    size_t get_num_send_frames(void) const{
+        return _rb_size.num_tx_frames;
+    }
+
+    size_t get_send_frame_size(void) const{
+        return _frame_size;
+    }
+
+private:
+
+    void release(ring_buffer_info *info){
+        if (fp_verbose) std::cout << "recv buff: release" << std::endl;
+        info->flags = RB_KERNEL;
+    }
+
+    void commit(ring_buffer_info *info, size_t len){
+        if (fp_verbose) std::cout << "send buff: commit " << len << std::endl;
+        info->len = len;
+        info->flags = RB_USER;
+        if (::write(_fd, NULL, 0) < 0){
+            std::cerr << UHD_THROW_SITE_INFO("write error") << std::endl;
+        }
+    }
+
+    int _fd;
+
+    //the mapped memory itself
+    void *_mapped_mem;
+
+    //mapped memory sizes
+    usrp_e_ring_buffer_size_t _rb_size;
+    size_t _frame_size, _map_size;
+
+    //pointers to sections in the mapped memory
+    ring_buffer_info (*_recv_info)[], (*_send_info)[];
+    char *_recv_buff, *_send_buff;
+
+    //indexes into sub-sections of mapped memory
+    size_t _recv_index, _send_index;
+};
+
+/***********************************************************************
+ * The zero copy interface make function
+ **********************************************************************/
+zero_copy_if::sptr usrp_e100_make_mmap_zero_copy(usrp_e100_iface::sptr iface){
+    return zero_copy_if::sptr(new usrp_e100_mmap_zero_copy_impl(iface));
+}
diff --git a/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp b/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp
new file mode 100644
index 000000000..625fb2c35
--- /dev/null
+++ b/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp
@@ -0,0 +1,198 @@
+
+
+////////////////////////////////////////////////////////////////
+//
+//         Memory map for embedded wishbone bus
+//
+////////////////////////////////////////////////////////////////
+
+// All addresses are byte addresses.  All accesses are word (16-bit) accesses.
+//  This means that address bit 0 is usually 0.
+//  There are 11 bits of address for the control.
+
+#ifndef INCLUDED_USRP_E100_REGS_HPP
+#define INCLUDED_USRP_E100_REGS_HPP
+
+/////////////////////////////////////////////////////
+// Slave pointers
+
+#define UE_REG_SLAVE(n) ((n)<<7)
+#define UE_REG_SR_ADDR(n) ((UE_REG_SLAVE(5)) + (4*(n)))
+
+/////////////////////////////////////////////////////
+// Slave 0 -- Misc Regs
+
+#define UE_REG_MISC_BASE UE_REG_SLAVE(0)
+
+#define UE_REG_MISC_LED        UE_REG_MISC_BASE + 0
+#define UE_REG_MISC_SW         UE_REG_MISC_BASE + 2
+#define UE_REG_MISC_CGEN_CTRL  UE_REG_MISC_BASE + 4
+#define UE_REG_MISC_CGEN_ST    UE_REG_MISC_BASE + 6
+#define UE_REG_MISC_TEST       UE_REG_MISC_BASE + 8
+#define UE_REG_MISC_RX_LEN     UE_REG_MISC_BASE + 10
+#define UE_REG_MISC_TX_LEN     UE_REG_MISC_BASE + 12
+#define UE_REG_MISC_XFER_RATE  UE_REG_MISC_BASE + 14
+#define UE_REG_MISC_COMPAT     UE_REG_MISC_BASE + 16
+
+/////////////////////////////////////////////////////
+// Slave 1 -- UART
+//   CLKDIV is 16 bits, others are only 8
+
+#define UE_REG_UART_BASE UE_REG_SLAVE(1)
+
+#define UE_REG_UART_CLKDIV  UE_REG_UART_BASE + 0
+#define UE_REG_UART_TXLEVEL UE_REG_UART_BASE + 2
+#define UE_REG_UART_RXLEVEL UE_REG_UART_BASE + 4
+#define UE_REG_UART_TXCHAR  UE_REG_UART_BASE + 6
+#define UE_REG_UART_RXCHAR  UE_REG_UART_BASE + 8
+
+/////////////////////////////////////////////////////
+// Slave 2 -- SPI Core
+//   This should be accessed through the IOCTL
+//   Users should not touch directly
+
+#define UE_REG_SPI_BASE UE_REG_SLAVE(2)
+
+//spi slave constants
+#define UE_SPI_SS_AD9522    (1 << 3)
+#define UE_SPI_SS_AD9862    (1 << 2)
+#define UE_SPI_SS_TX_DB     (1 << 1)
+#define UE_SPI_SS_RX_DB     (1 << 0)
+
+////////////////////////////////////////////////
+// Slave 3 -- I2C Core
+//   This should be accessed through the IOCTL
+//   Users should not touch directly
+
+#define UE_REG_I2C_BASE UE_REG_SLAVE(3)
+
+
+////////////////////////////////////////////////
+// Slave 4 -- GPIO
+
+#define UE_REG_GPIO_BASE UE_REG_SLAVE(4)
+
+#define UE_REG_GPIO_RX_IO      UE_REG_GPIO_BASE + 0
+#define UE_REG_GPIO_TX_IO      UE_REG_GPIO_BASE + 2
+#define UE_REG_GPIO_RX_DDR     UE_REG_GPIO_BASE + 4
+#define UE_REG_GPIO_TX_DDR     UE_REG_GPIO_BASE + 6
+#define UE_REG_GPIO_RX_SEL     UE_REG_GPIO_BASE + 8
+#define UE_REG_GPIO_TX_SEL     UE_REG_GPIO_BASE + 10
+#define UE_REG_GPIO_RX_DBG     UE_REG_GPIO_BASE + 12
+#define UE_REG_GPIO_TX_DBG     UE_REG_GPIO_BASE + 14
+
+//possible bit values for sel when dbg is 0:
+#define GPIO_SEL_SW    0 // if pin is an output, set by software in the io reg
+#define GPIO_SEL_ATR   1 // if pin is an output, set by ATR logic
+
+//possible bit values for sel when dbg is 1:
+#define GPIO_SEL_DEBUG_0   0 // if pin is an output, debug lines from FPGA fabric
+#define GPIO_SEL_DEBUG_1   1 // if pin is an output, debug lines from FPGA fabric
+
+
+////////////////////////////////////////////////////
+// Slave 5 -- Settings Bus
+//
+// Output-only, no readback, 32 registers total
+//  Each register must be written 32 bits at a time
+//  First the address xxx_xx00 and then xxx_xx10
+
+#define UE_REG_SETTINGS_BASE UE_REG_SLAVE(5)
+
+///////////////////////////////////////////////////
+// Slave 6 -- ATR Controller
+//   16 regs
+
+#define UE_REG_ATR_BASE  UE_REG_SLAVE(6)
+
+#define	UE_REG_ATR_IDLE_RXSIDE  UE_REG_ATR_BASE + 0
+#define	UE_REG_ATR_IDLE_TXSIDE  UE_REG_ATR_BASE + 2
+#define UE_REG_ATR_INTX_RXSIDE  UE_REG_ATR_BASE + 4
+#define UE_REG_ATR_INTX_TXSIDE  UE_REG_ATR_BASE + 6
+#define	UE_REG_ATR_INRX_RXSIDE  UE_REG_ATR_BASE + 8
+#define	UE_REG_ATR_INRX_TXSIDE  UE_REG_ATR_BASE + 10
+#define	UE_REG_ATR_FULL_RXSIDE  UE_REG_ATR_BASE + 12
+#define	UE_REG_ATR_FULL_TXSIDE  UE_REG_ATR_BASE + 14
+
+/////////////////////////////////////////////////
+// DSP RX Regs
+////////////////////////////////////////////////
+#define UE_REG_DSP_RX_FREQ         UE_REG_SR_ADDR(0)
+#define UE_REG_DSP_RX_SCALE_IQ     UE_REG_SR_ADDR(1)  // {scale_i,scale_q}
+#define UE_REG_DSP_RX_DECIM_RATE   UE_REG_SR_ADDR(2)  // hb and decim rate
+#define UE_REG_DSP_RX_DCOFFSET_I   UE_REG_SR_ADDR(3) // Bit 31 high sets fixed offset mode, using lower 14 bits, // otherwise it is automatic
+#define UE_REG_DSP_RX_DCOFFSET_Q   UE_REG_SR_ADDR(4) // Bit 31 high sets fixed offset mode, using lower 14 bits
+#define UE_REG_DSP_RX_MUX          UE_REG_SR_ADDR(5)
+
+///////////////////////////////////////////////////
+// VITA RX CTRL regs
+///////////////////////////////////////////////////
+// The following 3 are logically a single command register.
+// They are clocked into the underlying fifo when time_ticks is written.
+#define UE_REG_CTRL_RX_STREAM_CMD        UE_REG_SR_ADDR(8) // {now, chain, num_samples(30)
+#define UE_REG_CTRL_RX_TIME_SECS         UE_REG_SR_ADDR(9)
+#define UE_REG_CTRL_RX_TIME_TICKS        UE_REG_SR_ADDR(10)
+#define UE_REG_CTRL_RX_CLEAR_OVERRUN     UE_REG_SR_ADDR(11) // write anything to clear overrun
+#define UE_REG_CTRL_RX_VRT_HEADER        UE_REG_SR_ADDR(12) // word 0 of packet.  FPGA fills in packet counter
+#define UE_REG_CTRL_RX_VRT_STREAM_ID     UE_REG_SR_ADDR(13) // word 1 of packet.
+#define UE_REG_CTRL_RX_VRT_TRAILER       UE_REG_SR_ADDR(14)
+#define UE_REG_CTRL_RX_NSAMPS_PER_PKT    UE_REG_SR_ADDR(15)
+#define UE_REG_CTRL_RX_NCHANNELS         UE_REG_SR_ADDR(16) // 1 in basic case, up to 4 for vector sources
+
+/////////////////////////////////////////////////
+// DSP TX Regs
+////////////////////////////////////////////////
+#define UE_REG_DSP_TX_FREQ         UE_REG_SR_ADDR(17)
+#define UE_REG_DSP_TX_SCALE_IQ     UE_REG_SR_ADDR(18) // {scale_i,scale_q}
+#define UE_REG_DSP_TX_INTERP_RATE  UE_REG_SR_ADDR(19)
+#define UE_REG_DSP_TX_UNUSED       UE_REG_SR_ADDR(20)
+#define UE_REG_DSP_TX_MUX          UE_REG_SR_ADDR(21)
+
+/////////////////////////////////////////////////
+// VITA TX CTRL regs
+////////////////////////////////////////////////
+#define UE_REG_CTRL_TX_NCHANNELS         UE_REG_SR_ADDR(24)
+#define UE_REG_CTRL_TX_CLEAR_UNDERRUN    UE_REG_SR_ADDR(25)
+#define UE_REG_CTRL_TX_REPORT_SID        UE_REG_SR_ADDR(26)
+#define UE_REG_CTRL_TX_POLICY            UE_REG_SR_ADDR(27)
+
+#define UE_FLAG_CTRL_TX_POLICY_WAIT          (0x1 << 0)
+#define UE_FLAG_CTRL_TX_POLICY_NEXT_PACKET   (0x1 << 1)
+#define UE_FLAG_CTRL_TX_POLICY_NEXT_BURST    (0x1 << 2)
+
+/////////////////////////////////////////////////
+// VITA49 64 bit time (write only)
+////////////////////////////////////////////////
+  /*!
+   * \brief Time 64 flags
+   *
+   * <pre>
+   *
+   *    3                   2                   1
+   *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   * +-----------------------------------------------------------+-+-+
+   * |                                                           |S|P|
+   * +-----------------------------------------------------------+-+-+
+   *
+   * P - PPS edge selection (0=negedge, 1=posedge, default=0)
+   * S - Source (0=sma, 1=mimo, 0=default)
+   *
+   * </pre>
+   */
+#define UE_REG_TIME64_SECS  UE_REG_SR_ADDR(28)  // value to set absolute secs to on next PPS
+#define UE_REG_TIME64_TICKS UE_REG_SR_ADDR(29)  // value to set absolute ticks to on next PPS
+#define UE_REG_TIME64_FLAGS UE_REG_SR_ADDR(30)  // flags - see chart above
+#define UE_REG_TIME64_IMM   UE_REG_SR_ADDR(31)  // set immediate (0=latch on next pps, 1=latch immediate, default=0)
+#define UE_REG_TIME64_TPS   UE_REG_SR_ADDR(31)  // clock ticks per second (counter rollover)
+
+//pps flags (see above)
+#define UE_FLAG_TIME64_PPS_NEGEDGE (0 << 0)
+#define UE_FLAG_TIME64_PPS_POSEDGE (1 << 0)
+#define UE_FLAG_TIME64_PPS_SMA     (0 << 1)
+#define UE_FLAG_TIME64_PPS_MIMO    (1 << 1)
+
+#define UE_FLAG_TIME64_LATCH_NOW 1
+#define UE_FLAG_TIME64_LATCH_NEXT_PPS 0
+
+#endif
+
diff --git a/host/test/CMakeLists.txt b/host/test/CMakeLists.txt
index 5d7433c67..bdbde4b2c 100644
--- a/host/test/CMakeLists.txt
+++ b/host/test/CMakeLists.txt
@@ -51,3 +51,7 @@ ENDFOREACH(test_source)
 # demo of a loadable module
 ########################################################################
 ADD_LIBRARY(module_test MODULE module_test.cpp)
+
+INSTALL(TARGETS
+   RUNTIME DESTINATION ${PKG_DATA_DIR}/tests
+)
diff --git a/host/utils/CMakeLists.txt b/host/utils/CMakeLists.txt
index 38e21c753..0edf5a78c 100644
--- a/host/utils/CMakeLists.txt
+++ b/host/utils/CMakeLists.txt
@@ -45,6 +45,18 @@ IF(ENABLE_USRP1)
     )
 ENDIF(ENABLE_USRP1)
 
+IF(ENABLE_USRP_E100)
+    INCLUDE_DIRECTORIES(${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/include)
+    LIST(APPEND util_share_sources
+        fpga-downloader.cpp
+        clkgen-config.cpp
+        usrp-e-loopback.c
+        usrp-e-debug-pins.c
+        usrp-e-i2c.c
+        usrp-e-spi.c
+    )
+ENDIF(ENABLE_USRP_E100)
+
 #for each source: build an executable and install
 FOREACH(util_source ${util_share_sources})
     GET_FILENAME_COMPONENT(util_name ${util_source} NAME_WE)
diff --git a/host/utils/clkgen-config.cpp b/host/utils/clkgen-config.cpp
new file mode 100644
index 000000000..e8279b4ae
--- /dev/null
+++ b/host/utils/clkgen-config.cpp
@@ -0,0 +1,296 @@
+/* -*- c++ -*- */
+/*
+ * Copyright 2003,2004,2008,2009 Free Software Foundation, Inc.
+ *
+ * This file is part of UHD
+ *
+ * GNU Radio is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3, or (at your option)
+ * any later version.
+ *
+ * GNU Radio is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with GNU Radio; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+*/
+
+#include <iostream>
+#include <sstream>
+#include <fstream>
+#include <string>
+#include <cstdlib>
+
+#include <fcntl.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/ioctl.h>
+
+#include <linux/spi/spidev.h>
+
+
+// Programming data for clock gen chip
+static const unsigned int config_data[] = {
+	0x000024,
+	0x023201,
+	0x000081,
+	0x000400,
+	0x00104c,
+	0x001101,
+	0x001200,
+	0x001300,
+	0x001414,
+	0x001500,
+	0x001604,
+	0x001704,
+	0x001807,
+	0x001900,
+	//0x001a00,//for debug
+	0x001a32,
+	0x001b12,
+	0x001c44,
+	0x001d00,
+	0x001e00,
+	0x00f062,
+	0x00f162,
+	0x00f262,
+	0x00f362,
+	0x00f462,
+	0x00f562,
+	0x00f662,
+	0x00f762,
+	0x00f862,
+	0x00f962,
+	0x00fa62,
+	0x00fb62,
+	0x00fc00,
+	0x00fd00,
+	0x019021,
+	0x019100,
+	0x019200,
+	0x019333,
+	0x019400,
+	0x019500,
+	0x019611,
+	0x019700,
+	0x019800,
+	0x019900,
+	0x019a00,
+	0x019b00,
+	0x01e003,
+	0x01e102,
+	0x023000,
+	0x023201,
+	0x0b0201,
+	0x0b0300,
+	0x001fff,
+	0x0a0000,
+	0x0a0100,
+	0x0a0200,
+	0x0a0302,
+	0x0a0400,
+	0x0a0504,
+	0x0a060e,
+	0x0a0700,
+	0x0a0810,
+	0x0a090e,
+	0x0a0a00,
+	0x0a0bf0,
+	0x0a0c0b,
+	0x0a0d01,
+	0x0a0e90,
+	0x0a0f01,
+	0x0a1001,
+	0x0a11e0,
+	0x0a1201,
+	0x0a1302,
+	0x0a1430,
+	0x0a1580,
+	0x0a16ff,
+	0x023201,
+	0x0b0301,
+	0x023201,
+};
+
+
+const unsigned int CLKGEN_SELECT = 145;
+
+
+enum gpio_direction {IN, OUT};
+
+class gpio {
+	public:
+
+	gpio(unsigned int gpio_num, gpio_direction pin_direction, bool close_action);
+	~gpio();
+
+	bool get_value();
+	void set_value(bool state);
+
+	private:
+
+	unsigned int gpio_num;
+
+	std::stringstream base_path;
+	std::fstream value_file;
+	std::fstream direction_file;
+	bool close_action; // True set to input and release, false do nothing
+};
+
+class spidev {
+	public:
+
+	spidev(std::string dev_name);
+	~spidev();
+
+	void send(char *wbuf, char *rbuf, unsigned int nbytes);
+
+	private:
+
+	int fd;
+
+};
+
+gpio::gpio(unsigned int _gpio_num, gpio_direction pin_direction, bool close_action)
+{
+	std::fstream export_file;
+
+	gpio_num = _gpio_num;
+
+	export_file.open("/sys/class/gpio/export", std::ios::out);
+	if (!export_file.is_open())  ///\todo Poor error handling
+		std::cout << "Failed to open gpio export file." << std::endl;
+
+	export_file << gpio_num << std::endl;
+
+	base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush;
+
+	std::string direction_file_name;
+
+	direction_file_name = base_path.str() + "/direction";
+
+	direction_file.open(direction_file_name.c_str()); 
+	if (!direction_file.is_open())
+		std::cout << "Failed to open direction file." << std::endl;
+	if (pin_direction == OUT)
+		direction_file << "out" << std::endl;
+	else
+		direction_file << "in" << std::endl;
+
+	std::string value_file_name;
+
+	value_file_name = base_path.str() + "/value";
+
+	value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out);
+	if (!value_file.is_open())
+		std::cout << "Failed to open value file." << std::endl;
+}
+
+bool gpio::get_value()
+{
+
+	std::string val;
+
+	std::getline(value_file, val);
+	value_file.seekg(0);
+
+	if (val == "0")
+		return false;
+	else if (val == "1")
+		return true;
+	else
+		std::cout << "Data read from value file|" << val << "|" << std::endl;
+
+	return false;
+}
+
+void gpio::set_value(bool state)
+{
+
+	if (state)
+		value_file << "1" << std::endl;
+	else
+		value_file << "0" << std::endl;
+}
+
+gpio::~gpio()
+{
+	if (close_action) {
+		std::fstream unexport_file;
+
+		direction_file << "in" << std::endl;
+
+		unexport_file.open("/sys/class/gpio/unexport", std::ios::out);
+		if (!unexport_file.is_open())  ///\todo Poor error handling
+			std::cout << "Failed to open gpio export file." << std::endl;
+
+		unexport_file << gpio_num << std::endl;
+		
+	 }
+
+}
+
+spidev::spidev(std::string fname)
+{
+	int ret;
+	int mode = 0;
+	int speed = 12000;
+	int bits = 24;
+
+	fd = open(fname.c_str(), O_RDWR);
+
+	ret = ioctl(fd, SPI_IOC_WR_MODE, &mode);
+	ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed);
+	ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits);
+}
+	
+
+spidev::~spidev()
+{
+	close(fd);
+}
+
+void spidev::send(char *buf, char *rbuf, unsigned int nbytes)
+{
+	int ret;
+
+	struct spi_ioc_transfer tr;
+	tr.tx_buf = (unsigned long) buf;
+	tr.rx_buf = (unsigned long) rbuf;
+	tr.len = nbytes;
+	tr.delay_usecs = 0;
+	tr.speed_hz = 12000000;
+	tr.bits_per_word = 24;
+
+	ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);	
+
+}
+
+static void send_config_to_clkgen(gpio &chip_select, const unsigned int data[], unsigned int data_size)
+{
+	spidev spi("/dev/spidev1.0");
+	unsigned int rbuf;
+
+	for (unsigned int i = 0; i < data_size; i++) {
+
+		std::cout << "sending " << std::hex << data[i] << std::endl;
+		chip_select.set_value(0);
+		spi.send((char *)&data[i], (char *)&rbuf, 4);
+		chip_select.set_value(1);
+
+	};
+}
+
+int main(int argc, char *argv[])
+{
+
+	gpio clkgen_select(CLKGEN_SELECT, OUT, true);
+
+	send_config_to_clkgen(clkgen_select, config_data, sizeof(config_data)/sizeof(unsigned int));
+}
+
diff --git a/host/utils/fpga-downloader.cpp b/host/utils/fpga-downloader.cpp
new file mode 100644
index 000000000..80ee71600
--- /dev/null
+++ b/host/utils/fpga-downloader.cpp
@@ -0,0 +1,267 @@
+/* -*- c++ -*- */
+/*
+ * Copyright 2003,2004,2008,2009 Free Software Foundation, Inc.
+ *
+ * This file is part of GNU Radio
+ *
+ * GNU Radio is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3, or (at your option)
+ * any later version.
+ *
+ * GNU Radio is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with GNU Radio; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+*/
+
+#include <iostream>
+#include <sstream>
+#include <fstream>
+#include <string>
+#include <cstdlib>
+
+#include <fcntl.h>
+#include <errno.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/ioctl.h>
+
+#include <linux/spi/spidev.h>
+
+/*
+ * Configuration connections
+ *
+ * CCK    - MCSPI1_CLK
+ * DIN    - MCSPI1_MOSI
+ * PROG_B - GPIO_175     - output (change mux)
+ * DONE   - GPIO_173     - input  (change mux)
+ * INIT_B - GPIO_114     - input  (change mux)
+ *
+*/
+
+const unsigned int PROG_B = 175;
+const unsigned int DONE   = 173;
+const unsigned int INIT_B = 114;
+
+static std::string bit_file = "safe_u1e.bin";
+
+const int BUF_SIZE = 4096;
+
+enum gpio_direction {IN, OUT};
+
+class gpio {
+	public:
+
+	gpio(unsigned int gpio_num, gpio_direction pin_direction);
+
+	bool get_value();
+	void set_value(bool state);
+
+	private:
+
+	std::stringstream base_path;
+	std::fstream value_file;	
+};
+
+class spidev {
+	public:
+
+	spidev(std::string dev_name);
+	~spidev();
+
+	void send(char *wbuf, char *rbuf, unsigned int nbytes);
+
+	private:
+
+	int fd;
+
+};
+
+gpio::gpio(unsigned int gpio_num, gpio_direction pin_direction)
+{
+	std::fstream export_file;
+
+	export_file.open("/sys/class/gpio/export", std::ios::out);
+	if (!export_file.is_open())  ///\todo Poor error handling
+		std::cout << "Failed to open gpio export file." << std::endl;
+
+	export_file << gpio_num << std::endl;
+
+	base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush;
+
+	std::fstream direction_file;
+	std::string direction_file_name;
+
+	direction_file_name = base_path.str() + "/direction";
+
+	direction_file.open(direction_file_name.c_str()); 
+	if (!direction_file.is_open())
+		std::cout << "Failed to open direction file." << std::endl;
+	if (pin_direction == OUT)
+		direction_file << "out" << std::endl;
+	else
+		direction_file << "in" << std::endl;
+
+	std::string value_file_name;
+
+	value_file_name = base_path.str() + "/value";
+
+	value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out);
+	if (!value_file.is_open())
+		std::cout << "Failed to open value file." << std::endl;
+}
+
+bool gpio::get_value()
+{
+
+	std::string val;
+
+	std::getline(value_file, val);
+	value_file.seekg(0);
+
+	if (val == "0")
+		return false;
+	else if (val == "1")
+		return true;
+	else
+		std::cout << "Data read from value file|" << val << "|" << std::endl;
+
+	return false;
+}
+
+void gpio::set_value(bool state)
+{
+
+	if (state)
+		value_file << "1" << std::endl;
+	else
+		value_file << "0" << std::endl;
+}
+
+static void prepare_fpga_for_configuration(gpio &prog, gpio &init)
+{
+
+	prog.set_value(true);
+	prog.set_value(false);
+	prog.set_value(true);
+
+#if 0
+	bool ready_to_program(false);
+	unsigned int count(0);
+	do {
+		ready_to_program = init.get_value();
+		count++;
+
+		sleep(1);
+	} while (count < 10 && !ready_to_program);
+
+	if (count == 10) {
+		std::cout << "FPGA not ready for programming." << std::endl;
+		exit(-1);
+	}
+#endif
+}
+
+spidev::spidev(std::string fname)
+{
+	int ret;
+	int mode = 0;
+	int speed = 12000000;
+	int bits = 8;
+
+	fd = open(fname.c_str(), O_RDWR);
+
+	ret = ioctl(fd, SPI_IOC_WR_MODE, &mode);
+	ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed);
+	ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits);
+}
+	
+
+spidev::~spidev()
+{
+	close(fd);
+}
+
+void spidev::send(char *buf, char *rbuf, unsigned int nbytes)
+{
+	int ret;
+
+	struct spi_ioc_transfer tr;
+	tr.tx_buf = (unsigned long) buf;
+	tr.rx_buf = (unsigned long) rbuf;
+	tr.len = nbytes;
+	tr.delay_usecs = 0;
+	tr.speed_hz = 48000000;
+	tr.bits_per_word = 8;
+
+	ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr);	
+
+}
+
+static void send_file_to_fpga(std::string &file_name, gpio &error, gpio &done)
+{
+	std::ifstream bitstream;
+
+	std::cout << "File name - " << file_name.c_str() << std::endl;
+
+	bitstream.open(file_name.c_str(), std::ios::binary);
+	if (!bitstream.is_open())
+		std::cout << "File " << file_name << " not opened succesfully." << std::endl;
+
+	spidev spi("/dev/spidev1.0");
+	char buf[BUF_SIZE];
+	char rbuf[BUF_SIZE];
+
+	do {
+		bitstream.read(buf, BUF_SIZE);
+		spi.send(buf, rbuf, bitstream.gcount());
+
+		if (error.get_value())
+			std::cout << "INIT_B went high, error occured." << std::endl;
+
+		if (!done.get_value())
+			std::cout << "Configuration complete." << std::endl;
+
+	} while (bitstream.gcount() == BUF_SIZE);
+}
+
+int main(int argc, char *argv[])
+{
+
+	gpio gpio_prog_b(PROG_B, OUT);
+	gpio gpio_init_b(INIT_B, IN);
+	gpio gpio_done  (DONE,   IN);
+
+	if (argc == 2)
+		bit_file = argv[1];
+
+	bool module_found(false);
+	std::ifstream mod_file("/proc/modules");
+	while (!mod_file.eof()) {
+		std::string line;
+		getline(mod_file, line);
+		if (line.find("usrp_e") != std::string::npos)
+			module_found = true;
+	}
+	mod_file.close();
+
+	if (module_found) {
+		std::cout << "USRP Embedded kernel module loaded, not loading FPGA." << std::endl;
+		return -1;
+	}
+
+	std::cout << "FPGA config file: " << bit_file << std::endl;
+
+	prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b);
+
+	std::cout << "Done = " << gpio_done.get_value() << std::endl;
+
+	send_file_to_fpga(bit_file, gpio_init_b, gpio_done);
+}
+
diff --git a/host/utils/usrp-e-debug-pins.c b/host/utils/usrp-e-debug-pins.c
new file mode 100644
index 000000000..1ed2c8983
--- /dev/null
+++ b/host/utils/usrp-e-debug-pins.c
@@ -0,0 +1,77 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include <fcntl.h>
+#include <string.h>
+#include <sys/ioctl.h>
+
+#include <linux/usrp_e.h>
+#include "usrp_e_regs.hpp"
+
+// Usage: usrp_e_gpio <string>
+
+static int fp;
+
+static int read_reg(__u16 reg)
+{
+	int ret;
+	struct usrp_e_ctl16 d;
+
+	d.offset = reg;
+	d.count = 1;
+	ret = ioctl(fp, USRP_E_READ_CTL16, &d);
+	return d.buf[0];
+}
+
+static void write_reg(__u16 reg, __u16 val)
+{
+	int ret;
+	struct usrp_e_ctl16 d;
+
+	d.offset = reg;
+	d.count = 1;
+	d.buf[0] = val;
+	ret = ioctl(fp, USRP_E_WRITE_CTL16, &d);
+}
+
+int main(int argc, char *argv[])
+{
+	int test;
+
+	test = 0;
+	if (argc < 2) {
+		printf("%s 0|1|off\n", argv[0]);
+	}
+
+        fp = open("/dev/usrp_e0", O_RDWR);
+        printf("fp = %d\n", fp);
+	if (fp < 0) {
+		perror("Open failed");
+		return -1;
+	}
+
+	if (strcmp(argv[1], "0") == 0) {
+		printf("Selected 0 based on %s\n", argv[1]);
+		write_reg(UE_REG_GPIO_TX_DDR, 0xFFFF);
+		write_reg(UE_REG_GPIO_RX_DDR, 0xFFFF);
+		write_reg(UE_REG_GPIO_TX_SEL, 0x0);
+		write_reg(UE_REG_GPIO_RX_SEL, 0x0);
+		write_reg(UE_REG_GPIO_TX_DBG, 0xFFFF);
+		write_reg(UE_REG_GPIO_RX_DBG, 0xFFFF);
+	} else if (strcmp(argv[1], "1") == 0) {
+		printf("Selected 1 based on %s\n", argv[1]);
+		write_reg(UE_REG_GPIO_TX_DDR, 0xFFFF);
+		write_reg(UE_REG_GPIO_RX_DDR, 0xFFFF);
+		write_reg(UE_REG_GPIO_TX_SEL, 0xFFFF);
+		write_reg(UE_REG_GPIO_RX_SEL, 0xFFFF);
+		write_reg(UE_REG_GPIO_TX_DBG, 0xFFFF);
+		write_reg(UE_REG_GPIO_RX_DBG, 0xFFFF);
+	} else {
+		printf("Selected off based on %s\n", argv[1]);
+		write_reg(UE_REG_GPIO_TX_DDR, 0x0);
+		write_reg(UE_REG_GPIO_RX_DDR, 0x0);
+	}
+
+	return 0;
+}
diff --git a/host/utils/usrp-e-i2c.c b/host/utils/usrp-e-i2c.c
new file mode 100644
index 000000000..c6fd4c632
--- /dev/null
+++ b/host/utils/usrp-e-i2c.c
@@ -0,0 +1,87 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include <fcntl.h>
+#include <sys/ioctl.h>
+
+#include <linux/usrp_e.h>
+
+// Usage: usrp_e_i2c w address data0 data1 data 2 ....
+// Usage: usrp_e_i2c r address count
+
+int main(int argc, char *argv[])
+{
+	int fp, ret, i, tmp;
+	struct usrp_e_i2c *i2c_msg;
+	int direction, address, count;
+
+	if (argc < 3) {
+		printf("Usage: usrp-e-i2c w address data0 data1 data2 ...\n");
+		printf("Usage: usrp-e-i2c r address count\n");
+		printf("All addresses and data in hex.\n");
+		exit(-1);
+	}
+
+	if (strcmp(argv[1], "r") == 0) {
+		direction = 0;
+	} else if (strcmp(argv[1], "w") == 0) {
+		direction = 1;
+	} else {
+		return -1;
+	}
+
+	sscanf(argv[2], "%X", &address);
+	printf("Address = %X\n", address);
+
+	fp = open("/dev/usrp_e0", O_RDWR);
+	printf("fp = %d\n", fp);
+	if (fp < 0) {
+		perror("Open failed");
+		return -1;
+	}
+
+//	sleep(1);
+
+	if (direction) {
+		count = argc - 3;
+	} else {
+		sscanf(argv[3], "%X", &count);
+	}
+	printf("Count = %X\n", count);
+
+	i2c_msg = malloc(sizeof(i2c_msg) + count * sizeof(char));
+
+	i2c_msg->addr = address;
+	i2c_msg->len = count;
+
+	for (i = 0; i < count; i++) {
+		i2c_msg->data[i] = i;
+	}
+
+	if (direction) {
+		// Write
+
+		for (i=0; i<count; i++) {
+			sscanf(argv[3+i], "%X", &tmp);
+			i2c_msg->data[i] = tmp;
+		}
+
+		ret = ioctl(fp, USRP_E_I2C_WRITE, i2c_msg);
+		printf("Return value from i2c_write ioctl: %d\n", ret);
+	} else {
+		// Read
+
+		ret = ioctl(fp, USRP_E_I2C_READ, i2c_msg);
+		printf("Return value from i2c_read ioctl: %d\n", ret);
+
+		printf("Ioctl: %d Data read :", ret);
+		for (i=0; i<count; i++) {
+			printf(" %X", i2c_msg->data[i]);
+		}
+		printf("\n");
+			
+	}
+	return 0;
+}
diff --git a/host/utils/usrp-e-loopback.c b/host/utils/usrp-e-loopback.c
new file mode 100644
index 000000000..454d81ba7
--- /dev/null
+++ b/host/utils/usrp-e-loopback.c
@@ -0,0 +1,231 @@
+#include <stdio.h>
+#include <sys/types.h>
+#include <fcntl.h>
+#include <pthread.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <stddef.h>
+#include <sys/mman.h>
+#include <linux/usrp_e.h>
+
+#define MAX_PACKET_SIZE 1016
+static int packet_data_length;
+static int error;
+
+struct pkt {
+	int len;
+	int checksum;
+	int seq_num;
+	short data[];
+};
+
+static int length_array[2048];
+static int length_array_tail = 0;
+static int length_array_head = 0;
+
+pthread_mutex_t length_array_mutex; //gotta lock the index to keep it from getting hosed
+
+//yes this is a circular buffer that does not check empty
+//no i don't want to hear about it
+void push_length_array(int length) {
+	pthread_mutex_lock(&length_array_mutex);
+	if(length_array_tail > 2047) length_array_tail = 0;
+	length_array[length_array_tail++] = length;
+	pthread_mutex_unlock(&length_array_mutex);
+}
+
+int pop_length_array(void) {
+	int retval;
+	pthread_mutex_lock(&length_array_mutex);
+	if(length_array_head > 2047) length_array_head = 0;
+	retval = length_array[length_array_head++];
+	pthread_mutex_unlock(&length_array_mutex);
+	return retval;
+}
+
+static int fp;
+
+static int calc_checksum(struct pkt *p)
+{
+	int i, sum;
+
+	i = 0;
+	sum = 0;
+
+	for (i=0; i < p->len; i++)
+		sum ^= p->data[i];
+
+	sum ^= p->seq_num;
+	sum ^= p->len;
+
+	return sum;
+}
+
+static void *read_thread(void *threadid)
+{
+	char *rx_data;
+	int cnt, prev_seq_num, pkt_count, seq_num_failure;
+	struct pkt *p;
+	unsigned long bytes_transfered, elapsed_seconds;
+	struct timeval start_time, finish_time;
+	int expected_count;
+
+	printf("Greetings from the reading thread!\n");
+
+	bytes_transfered = 0;
+	gettimeofday(&start_time, NULL);
+
+	// IMPORTANT: must assume max length packet from fpga
+	rx_data = malloc(2048);
+	p = (struct pkt *) ((void *)rx_data);
+
+	prev_seq_num = 0;
+	pkt_count = 0;
+	seq_num_failure = 0;
+
+	while (1) {
+
+		cnt = read(fp, rx_data, 2048);
+		if (cnt < 0)
+			printf("Error returned from read: %d, sequence number = %d\n", cnt, p->seq_num);
+
+//		printf("p->seq_num = %d\n", p->seq_num);
+
+
+		pkt_count++;
+
+		if (p->seq_num != prev_seq_num + 1) {
+			printf("Sequence number fail, current = %d, previous = %d, pkt_count = %d\n",
+				p->seq_num, prev_seq_num, pkt_count);
+
+			seq_num_failure ++;
+			if (seq_num_failure > 2)
+				error = 1;
+		}
+
+		expected_count = pop_length_array()*2+12;
+		if(cnt != expected_count) {
+			printf("Received %d bytes, expected %d\n", cnt, expected_count);
+		}
+
+		prev_seq_num = p->seq_num;
+
+		if (calc_checksum(p) != p->checksum) {
+			printf("Checksum fail packet = %X, expected = %X, pkt_count = %d\n",
+				calc_checksum(p), p->checksum, pkt_count);
+			error = 1;
+		}
+
+		bytes_transfered += cnt;
+
+		if (bytes_transfered > (100 * 1000000)) {
+			gettimeofday(&finish_time, NULL);
+			elapsed_seconds = finish_time.tv_sec - start_time.tv_sec;
+
+			printf("RX data transfer rate = %f K Samples/second\n",
+				(float) bytes_transfered / (float) elapsed_seconds / 4000);
+
+
+			start_time = finish_time;
+			bytes_transfered = 0;
+		}
+
+
+//		printf(".");
+//		fflush(stdout);
+//		printf("\n");
+	}
+
+}
+
+static void *write_thread(void *threadid)
+{
+	int seq_number, i, cnt;
+	void *tx_data;
+	struct pkt *p;
+
+	printf("Greetings from the write thread!\n");
+
+	tx_data = malloc(2048);
+	p = (struct pkt *) ((void *)tx_data);
+
+	for (i=0; i < packet_data_length; i++)
+//		p->data[i] = random() >> 16;
+		p->data[i] = i;
+
+	seq_number = 1;
+
+	while (1) {
+		p->seq_num = seq_number++;
+
+		if (packet_data_length > 0)
+			p->len = packet_data_length;
+		else
+			p->len = (random()<<1 & 0x1ff) + (1004 - 512);
+
+		push_length_array(p->len);
+
+		p->checksum = calc_checksum(p);
+
+		cnt = write(fp, tx_data, p->len * 2 + 12);
+		if (cnt < 0)
+			printf("Error returned from write: %d\n", cnt);
+//		sleep(1);
+	}
+}
+
+
+int main(int argc, char *argv[])
+{
+	pthread_t tx, rx;
+	pthread_mutex_init(&length_array_mutex, 0);
+	long int t;
+	struct sched_param s = {
+		.sched_priority = 1
+	};
+	void *rb;
+	struct usrp_transfer_frame *tx_rb, *rx_rb;
+
+	if (argc < 2) {
+		printf("%s data_size\n", argv[0]);
+		return -1;
+	}
+
+	packet_data_length = atoi(argv[1]);
+	if(packet_data_length > MAX_PACKET_SIZE) {
+		printf("Packet size must be smaller than %i\n", MAX_PACKET_SIZE);
+		exit(-1);
+	}
+
+	fp = open("/dev/usrp_e0", O_RDWR);
+	printf("fp = %d\n", fp);
+
+	rb = mmap(0, 202 * 4096, PROT_READ|PROT_WRITE, MAP_SHARED, fp, 0);
+	if (!rb) {
+		printf("mmap failed\n");
+		exit;
+	}
+
+
+	sched_setscheduler(0, SCHED_RR, &s);
+	error = 0;
+
+#if 1
+	if (pthread_create(&rx, NULL, read_thread, (void *) t)) {
+		printf("Failed to create rx thread\n");
+		exit(-1);
+	}
+
+	sleep(1);
+#endif
+
+	if (pthread_create(&tx, NULL, write_thread, (void *) t)) {
+		printf("Failed to create tx thread\n");
+		exit(-1);
+	}
+
+//	while (!error)
+		sleep(1000000000);
+
+	printf("Done sleeping\n");
+}
diff --git a/host/utils/usrp-e-spi.c b/host/utils/usrp-e-spi.c
new file mode 100644
index 000000000..5203f56a8
--- /dev/null
+++ b/host/utils/usrp-e-spi.c
@@ -0,0 +1,54 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include <fcntl.h>
+#include <sys/ioctl.h>
+
+#include <linux/usrp_e.h>
+
+// Usage: usrp_e_spi w|rb slave data
+
+int main(int argc, char *argv[])
+{
+	int fp, slave, length, ret;
+	unsigned int data;
+	struct usrp_e_spi spi_dat;
+
+	if (argc < 5) {
+		printf("Usage: usrp_e_spi w|rb slave transfer_length data\n");
+		exit(-1);
+	}
+
+	slave = atoi(argv[2]);
+	length = atoi(argv[3]);
+	data = atoll(argv[4]);
+
+	printf("Data = %X\n", data);
+
+	fp = open("/dev/usrp_e0", O_RDWR);
+	printf("fp = %d\n", fp);
+	if (fp < 0) {
+		perror("Open failed");
+		return -1;
+	}
+
+//	sleep(1);
+
+
+	spi_dat.slave = slave;
+	spi_dat.data = data;
+	spi_dat.length = length;
+	spi_dat.flags = UE_SPI_PUSH_FALL | UE_SPI_LATCH_RISE;
+
+	if (*argv[1] == 'r') {
+		spi_dat.readback = 1;
+		ret = ioctl(fp, USRP_E_SPI, &spi_dat);
+		printf("Ioctl returns: %d, Data returned = %d\n", ret, spi_dat.data);
+	} else {
+		spi_dat.readback = 0;
+		ioctl(fp, USRP_E_SPI, &spi_dat);
+	}
+
+	return 0;
+}
diff --git a/host/utils/usrp_e_regs.hpp b/host/utils/usrp_e_regs.hpp
new file mode 100644
index 000000000..a4f42093e
--- /dev/null
+++ b/host/utils/usrp_e_regs.hpp
@@ -0,0 +1,196 @@
+
+
+////////////////////////////////////////////////////////////////
+//
+//         Memory map for embedded wishbone bus
+//
+////////////////////////////////////////////////////////////////
+
+// All addresses are byte addresses.  All accesses are word (16-bit) accesses.
+//  This means that address bit 0 is usually 0.
+//  There are 11 bits of address for the control.
+
+#ifndef __USRP_E_REGS_H
+#define __USRP_E_REGS_H
+
+/////////////////////////////////////////////////////
+// Slave pointers
+
+#define UE_REG_SLAVE(n) ((n)<<7)
+#define UE_REG_SR_ADDR(n) ((UE_REG_SLAVE(5)) + (4*(n)))
+
+/////////////////////////////////////////////////////
+// Slave 0 -- Misc Regs
+
+#define UE_REG_MISC_BASE UE_REG_SLAVE(0)
+
+#define UE_REG_MISC_LED        UE_REG_MISC_BASE + 0
+#define UE_REG_MISC_SW         UE_REG_MISC_BASE + 2
+#define UE_REG_MISC_CGEN_CTRL  UE_REG_MISC_BASE + 4
+#define UE_REG_MISC_CGEN_ST    UE_REG_MISC_BASE + 6
+#define UE_REG_MISC_TEST       UE_REG_MISC_BASE + 8
+#define UE_REG_MISC_RX_LEN     UE_REG_MISC_BASE + 10
+#define UE_REG_MISC_TX_LEN     UE_REG_MISC_BASE + 12
+
+/////////////////////////////////////////////////////
+// Slave 1 -- UART
+//   CLKDIV is 16 bits, others are only 8
+
+#define UE_REG_UART_BASE UE_REG_SLAVE(1)
+
+#define UE_REG_UART_CLKDIV  UE_REG_UART_BASE + 0
+#define UE_REG_UART_TXLEVEL UE_REG_UART_BASE + 2
+#define UE_REG_UART_RXLEVEL UE_REG_UART_BASE + 4
+#define UE_REG_UART_TXCHAR  UE_REG_UART_BASE + 6
+#define UE_REG_UART_RXCHAR  UE_REG_UART_BASE + 8
+
+/////////////////////////////////////////////////////
+// Slave 2 -- SPI Core
+//   This should be accessed through the IOCTL
+//   Users should not touch directly
+
+#define UE_REG_SPI_BASE UE_REG_SLAVE(2)
+
+//spi slave constants
+#define UE_SPI_SS_AD9522    (1 << 3)
+#define UE_SPI_SS_AD9862    (1 << 2)
+#define UE_SPI_SS_TX_DB     (1 << 1)
+#define UE_SPI_SS_RX_DB     (1 << 0)
+
+////////////////////////////////////////////////
+// Slave 3 -- I2C Core
+//   This should be accessed through the IOCTL
+//   Users should not touch directly
+
+#define UE_REG_I2C_BASE UE_REG_SLAVE(3)
+
+
+////////////////////////////////////////////////
+// Slave 4 -- GPIO
+
+#define UE_REG_GPIO_BASE UE_REG_SLAVE(4)
+
+#define UE_REG_GPIO_RX_IO      UE_REG_GPIO_BASE + 0
+#define UE_REG_GPIO_TX_IO      UE_REG_GPIO_BASE + 2
+#define UE_REG_GPIO_RX_DDR     UE_REG_GPIO_BASE + 4
+#define UE_REG_GPIO_TX_DDR     UE_REG_GPIO_BASE + 6
+#define UE_REG_GPIO_RX_SEL     UE_REG_GPIO_BASE + 8
+#define UE_REG_GPIO_TX_SEL     UE_REG_GPIO_BASE + 10
+#define UE_REG_GPIO_RX_DBG     UE_REG_GPIO_BASE + 12
+#define UE_REG_GPIO_TX_DBG     UE_REG_GPIO_BASE + 14
+
+//possible bit values for sel when dbg is 0:
+#define GPIO_SEL_SW    0 // if pin is an output, set by software in the io reg
+#define GPIO_SEL_ATR   1 // if pin is an output, set by ATR logic
+
+//possible bit values for sel when dbg is 1:
+#define GPIO_SEL_DEBUG_0   0 // if pin is an output, debug lines from FPGA fabric
+#define GPIO_SEL_DEBUG_1   1 // if pin is an output, debug lines from FPGA fabric
+
+
+////////////////////////////////////////////////////
+// Slave 5 -- Settings Bus
+//
+// Output-only, no readback, 32 registers total
+//  Each register must be written 32 bits at a time
+//  First the address xxx_xx00 and then xxx_xx10
+
+#define UE_REG_SETTINGS_BASE UE_REG_SLAVE(5)
+
+///////////////////////////////////////////////////
+// Slave 6 -- ATR Controller
+//   16 regs
+
+#define UE_REG_ATR_BASE  UE_REG_SLAVE(6)
+
+#define	UE_REG_ATR_IDLE_RXSIDE  UE_REG_ATR_BASE + 0
+#define	UE_REG_ATR_IDLE_TXSIDE  UE_REG_ATR_BASE + 2
+#define UE_REG_ATR_INTX_RXSIDE  UE_REG_ATR_BASE + 4
+#define UE_REG_ATR_INTX_TXSIDE  UE_REG_ATR_BASE + 6
+#define	UE_REG_ATR_INRX_RXSIDE  UE_REG_ATR_BASE + 8
+#define	UE_REG_ATR_INRX_TXSIDE  UE_REG_ATR_BASE + 10
+#define	UE_REG_ATR_FULL_RXSIDE  UE_REG_ATR_BASE + 12
+#define	UE_REG_ATR_FULL_TXSIDE  UE_REG_ATR_BASE + 14
+
+/////////////////////////////////////////////////
+// DSP RX Regs
+////////////////////////////////////////////////
+#define UE_REG_DSP_RX_FREQ         UE_REG_SR_ADDR(0)
+#define UE_REG_DSP_RX_SCALE_IQ     UE_REG_SR_ADDR(1)  // {scale_i,scale_q}
+#define UE_REG_DSP_RX_DECIM_RATE   UE_REG_SR_ADDR(2)  // hb and decim rate
+#define UE_REG_DSP_RX_DCOFFSET_I   UE_REG_SR_ADDR(3) // Bit 31 high sets fixed offset mode, using lower 14 bits, // otherwise it is automatic
+#define UE_REG_DSP_RX_DCOFFSET_Q   UE_REG_SR_ADDR(4) // Bit 31 high sets fixed offset mode, using lower 14 bits
+#define UE_REG_DSP_RX_MUX          UE_REG_SR_ADDR(5)
+
+///////////////////////////////////////////////////
+// VITA RX CTRL regs
+///////////////////////////////////////////////////
+// The following 3 are logically a single command register.
+// They are clocked into the underlying fifo when time_ticks is written.
+#define UE_REG_CTRL_RX_STREAM_CMD        UE_REG_SR_ADDR(8) // {now, chain, num_samples(30)
+#define UE_REG_CTRL_RX_TIME_SECS         UE_REG_SR_ADDR(9)
+#define UE_REG_CTRL_RX_TIME_TICKS        UE_REG_SR_ADDR(10)
+#define UE_REG_CTRL_RX_CLEAR_OVERRUN     UE_REG_SR_ADDR(11) // write anything to clear overrun
+#define UE_REG_CTRL_RX_VRT_HEADER        UE_REG_SR_ADDR(12) // word 0 of packet.  FPGA fills in packet counter
+#define UE_REG_CTRL_RX_VRT_STREAM_ID     UE_REG_SR_ADDR(13) // word 1 of packet.
+#define UE_REG_CTRL_RX_VRT_TRAILER       UE_REG_SR_ADDR(14)
+#define UE_REG_CTRL_RX_NSAMPS_PER_PKT    UE_REG_SR_ADDR(15)
+#define UE_REG_CTRL_RX_NCHANNELS         UE_REG_SR_ADDR(16) // 1 in basic case, up to 4 for vector sources
+
+/////////////////////////////////////////////////
+// DSP TX Regs
+////////////////////////////////////////////////
+#define UE_REG_DSP_TX_FREQ         UE_REG_SR_ADDR(17)
+#define UE_REG_DSP_TX_SCALE_IQ     UE_REG_SR_ADDR(18) // {scale_i,scale_q}
+#define UE_REG_DSP_TX_INTERP_RATE  UE_REG_SR_ADDR(19)
+#define UE_REG_DSP_TX_UNUSED       UE_REG_SR_ADDR(20)
+#define UE_REG_DSP_TX_MUX          UE_REG_SR_ADDR(21)
+
+/////////////////////////////////////////////////
+// VITA TX CTRL regs
+////////////////////////////////////////////////
+#define UE_REG_CTRL_TX_NCHANNELS         UE_REG_SR_ADDR(24)
+#define UE_REG_CTRL_TX_CLEAR_UNDERRUN    UE_REG_SR_ADDR(25)
+#define UE_REG_CTRL_TX_REPORT_SID        UE_REG_SR_ADDR(26)
+#define UE_REG_CTRL_TX_POLICY            UE_REG_SR_ADDR(27)
+
+#define UE_FLAG_CTRL_TX_POLICY_WAIT          (0x1 << 0)
+#define UE_FLAG_CTRL_TX_POLICY_NEXT_PACKET   (0x1 << 1)
+#define UE_FLAG_CTRL_TX_POLICY_NEXT_BURST    (0x1 << 2)
+
+/////////////////////////////////////////////////
+// VITA49 64 bit time (write only)
+////////////////////////////////////////////////
+  /*!
+   * \brief Time 64 flags
+   *
+   * <pre>
+   *
+   *    3                   2                   1
+   *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   * +-----------------------------------------------------------+-+-+
+   * |                                                           |S|P|
+   * +-----------------------------------------------------------+-+-+
+   *
+   * P - PPS edge selection (0=negedge, 1=posedge, default=0)
+   * S - Source (0=sma, 1=mimo, 0=default)
+   *
+   * </pre>
+   */
+#define UE_REG_TIME64_SECS  UE_REG_SR_ADDR(28)  // value to set absolute secs to on next PPS
+#define UE_REG_TIME64_TICKS UE_REG_SR_ADDR(29)  // value to set absolute ticks to on next PPS
+#define UE_REG_TIME64_FLAGS UE_REG_SR_ADDR(30)  // flags - see chart above
+#define UE_REG_TIME64_IMM   UE_REG_SR_ADDR(31)  // set immediate (0=latch on next pps, 1=latch immediate, default=0)
+#define UE_REG_TIME64_TPS   UE_REG_SR_ADDR(31)  // clock ticks per second (counter rollover)
+
+//pps flags (see above)
+#define UE_FLAG_TIME64_PPS_NEGEDGE (0 << 0)
+#define UE_FLAG_TIME64_PPS_POSEDGE (1 << 0)
+#define UE_FLAG_TIME64_PPS_SMA     (0 << 1)
+#define UE_FLAG_TIME64_PPS_MIMO    (1 << 1)
+
+#define UE_FLAG_TIME64_LATCH_NOW 1
+#define UE_FLAG_TIME64_LATCH_NEXT_PPS 0
+
+#endif
+
diff --git a/images/Makefile b/images/Makefile
index 79e7b3362..34943cc59 100644
--- a/images/Makefile
+++ b/images/Makefile
@@ -114,18 +114,18 @@ $(_usrp2_fpga_bin):
 endif
 
 ########################################################################
-# USRP2 fpga
+# USRP-E100 fpga
 ########################################################################
 ifdef HAS_XTCLSH
 
-_usrp2p_fpga_dir = $(TOP_FPGA_DIR)/usrp2/top/u2plus
-_usrp2p_fpga_bin = $(BUILT_IMAGES_DIR)/usrp2p_fpga.bin
-IMAGES_LIST += $(_usrp2p_fpga_bin)
+_usrp_e100_fpga_dir = $(TOP_FPGA_DIR)/usrp2/top/u1e
+_usrp_e100_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_e100_fpga.bin
+IMAGES_LIST += $(_usrp_e100_fpga_bin)
 
-$(_usrp2p_fpga_bin):
-	cd $(_usrp2p_fpga_dir) && make -f Makefile.udp clean
-	cd $(_usrp2p_fpga_dir) && make -f Makefile.udp bin
-	cp $(_usrp2p_fpga_dir)/build-ISE12/u2plus.bin $@
+$(_usrp_e100_fpga_bin):
+	cd $(_usrp_e100_fpga_dir) && make clean
+	cd $(_usrp_e100_fpga_dir) && make bin
+	cp $(_usrp_e100_fpga_dir)/build/u1e.bin $@
 
 endif