From 2faaa1e36257c9909415f142e165e5ad74495a4e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 9 Feb 2010 18:26:47 -0800 Subject: skeletons that don't work yet --- usrp2/top/safe_u1e/Makefile | 245 ++++++++++++++++++++++++++++ usrp2/top/safe_u1e/safe_u1e.v | 362 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 607 insertions(+) create mode 100644 usrp2/top/safe_u1e/Makefile create mode 100644 usrp2/top/safe_u1e/safe_u1e.v diff --git a/usrp2/top/safe_u1e/Makefile b/usrp2/top/safe_u1e/Makefile new file mode 100644 index 000000000..8fe77d554 --- /dev/null +++ b/usrp2/top/safe_u1e/Makefile @@ -0,0 +1,245 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := safe_u1e +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +control_lib/CRC16_D16.v \ +control_lib/atr_controller.v \ +control_lib/bin2gray.v \ +control_lib/dcache.v \ +control_lib/decoder_3_8.v \ +control_lib/dpram32.v \ +control_lib/gray2bin.v \ +control_lib/gray_send.v \ +control_lib/icache.v \ +control_lib/mux4.v \ +control_lib/mux8.v \ +control_lib/nsgpio.v \ +control_lib/ram_2port.v \ +control_lib/ram_harv_cache.v \ +control_lib/ram_loader.v \ +control_lib/setting_reg.v \ +control_lib/settings_bus.v \ +control_lib/srl.v \ +control_lib/system_control.v \ +control_lib/wb_1master.v \ +control_lib/wb_readback_mux.v \ +control_lib/simple_uart.v \ +control_lib/simple_uart_tx.v \ +control_lib/simple_uart_rx.v \ +control_lib/oneshot_2clk.v \ +control_lib/sd_spi.v \ +control_lib/sd_spi_wb.v \ +control_lib/wb_bridge_16_32.v \ +control_lib/reset_sync.v \ +simple_gemac/simple_gemac_wrapper.v \ +simple_gemac/simple_gemac.v \ +simple_gemac/simple_gemac_wb.v \ +simple_gemac/simple_gemac_tx.v \ +simple_gemac/simple_gemac_rx.v \ +simple_gemac/crc.v \ +simple_gemac/delay_line.v \ +simple_gemac/flow_ctrl_tx.v \ +simple_gemac/flow_ctrl_rx.v \ +simple_gemac/address_filter.v \ +simple_gemac/ll8_to_txmac.v \ +simple_gemac/rxmac_to_ll8.v \ +simple_gemac/miim/eth_miim.v \ +simple_gemac/miim/eth_clockgen.v \ +simple_gemac/miim/eth_outputcontrol.v \ +simple_gemac/miim/eth_shiftreg.v \ +control_lib/newfifo/buffer_int.v \ +control_lib/newfifo/buffer_pool.v \ +control_lib/newfifo/fifo_2clock.v \ +control_lib/newfifo/fifo_2clock_cascade.v \ +control_lib/newfifo/ll8_shortfifo.v \ +control_lib/newfifo/ll8_to_fifo36.v \ +control_lib/newfifo/fifo_short.v \ +control_lib/newfifo/fifo_long.v \ +control_lib/newfifo/fifo_cascade.v \ +control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/longfifo.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ +coregen/fifo_xlnx_2Kx36_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.xco \ +coregen/fifo_xlnx_512x36_2clk.v \ +coregen/fifo_xlnx_512x36_2clk.xco \ +coregen/fifo_xlnx_64x36_2clk.v \ +coregen/fifo_xlnx_64x36_2clk.xco \ +extram/wb_zbt16_b.v \ +opencores/8b10b/decode_8b10b.v \ +opencores/8b10b/encode_8b10b.v \ +opencores/aemb/rtl/verilog/aeMB_bpcu.v \ +opencores/aemb/rtl/verilog/aeMB_core_BE.v \ +opencores/aemb/rtl/verilog/aeMB_ctrl.v \ +opencores/aemb/rtl/verilog/aeMB_edk32.v \ +opencores/aemb/rtl/verilog/aeMB_ibuf.v \ +opencores/aemb/rtl/verilog/aeMB_regf.v \ +opencores/aemb/rtl/verilog/aeMB_xecu.v \ +opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_defines.v \ +opencores/i2c/rtl/verilog/i2c_master_top.v \ +opencores/i2c/rtl/verilog/timescale.v \ +opencores/simple_pic/rtl/simple_pic.v \ +opencores/spi/rtl/verilog/spi_clgen.v \ +opencores/spi/rtl/verilog/spi_defines.v \ +opencores/spi/rtl/verilog/spi_shift.v \ +opencores/spi/rtl/verilog/spi_top.v \ +opencores/spi/rtl/verilog/timescale.v \ +sdr_lib/acc.v \ +sdr_lib/add2.v \ +sdr_lib/add2_and_round.v \ +sdr_lib/add2_and_round_reg.v \ +sdr_lib/add2_reg.v \ +sdr_lib/cic_dec_shifter.v \ +sdr_lib/cic_decim.v \ +sdr_lib/cic_int_shifter.v \ +sdr_lib/cic_interp.v \ +sdr_lib/cic_strober.v \ +sdr_lib/clip.v \ +sdr_lib/clip_reg.v \ +sdr_lib/cordic.v \ +sdr_lib/cordic_z24.v \ +sdr_lib/cordic_stage.v \ +sdr_lib/dsp_core_rx.v \ +sdr_lib/dsp_core_tx.v \ +sdr_lib/hb_dec.v \ +sdr_lib/hb_interp.v \ +sdr_lib/round.v \ +sdr_lib/round_reg.v \ +sdr_lib/rx_control.v \ +sdr_lib/rx_dcoffset.v \ +sdr_lib/sign_extend.v \ +sdr_lib/small_hb_dec.v \ +sdr_lib/small_hb_int.v \ +sdr_lib/tx_control.v \ +serdes/serdes.v \ +serdes/serdes_fc_rx.v \ +serdes/serdes_fc_tx.v \ +serdes/serdes_rx.v \ +serdes/serdes_tx.v \ +timing/time_receiver.v \ +timing/time_sender.v \ +timing/time_sync.v \ +timing/timer.v \ +top/u2_core/u2_core.v \ +top/safe_u1e/u1e.ucf \ +top/safe_u1e/safe_u1e.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +clean: + rm -rf $(BUILD_DIR) + + diff --git a/usrp2/top/safe_u1e/safe_u1e.v b/usrp2/top/safe_u1e/safe_u1e.v new file mode 100644 index 000000000..c880a9e55 --- /dev/null +++ b/usrp2/top/safe_u1e/safe_u1e.v @@ -0,0 +1,362 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module safe_u1e + ( + input CLK_FPGA_P, input CLK_FPGA_N, // Diff + + // ADC + //input ADC_clkout_p, //input ADC_clkout_n, + //input ADCA_12_p, //input ADCA_12_n, + //input ADCA_10_p, //input ADCA_10_n, + //input ADCA_8_p, //input ADCA_8_n, + //input ADCA_6_p, //input ADCA_6_n, + //input ADCA_4_p, //input ADCA_4_n, + //input ADCA_2_p, //input ADCA_2_n, + //input ADCA_0_p, //input ADCA_0_n, + //input ADCB_12_p, //input ADCB_12_n, + //input ADCB_10_p, //input ADCB_10_n, + //input ADCB_8_p, //input ADCB_8_n, + //input ADCB_6_p, //input ADCB_6_n, + //input ADCB_4_p, //input ADCB_4_n, + //input ADCB_2_p, //input ADCB_2_n, + //input ADCB_0_p, //input ADCB_0_n, + + // DAC + //output [15:0] DACA, + //output [15:0] DACB, + //input DAC_LOCK, // unused for now + + // DB IO Pins + //inout [15:0] io_tx, + //inout [15:0] io_rx, + + // Misc, debug + output [5:1] leds, // LED4 is shared w/INIT_B + //input FPGA_RESET, + //output [1:0] debug_clk, + //output [31:0] debug, + //output [3:1] TXD, //input [3:1] RXD, // UARTs + ////input [3:0] dipsw, // Forgot DIP Switches... + + // Clock Gen Control + //output [1:0] clk_en, + //output [1:0] clk_sel, + //input CLK_FUNC, // FIXME is an //input to control the 9510 + //input CLK_STATUS, + + //inout SCL, //inout SDA, // I2C + + // PPS + //input PPS_IN, //input PPS2_IN, + + // SPI + //output SEN_CLK, //output SCLK_CLK, //output MOSI_CLK, //input MISO_CLK, + //output SEN_DAC, //output SCLK_DAC, //output MOSI_DAC, //input MISO_DAC, + //output SEN_ADC, //output SCLK_ADC, //output MOSI_ADC, + //output SEN_TX_DB, //output SCLK_TX_DB, //output MOSI_TX_DB, //input MISO_TX_DB, + //output SEN_TX_DAC, //output SCLK_TX_DAC, //output MOSI_TX_DAC, + //output SEN_TX_ADC, //output SCLK_TX_ADC, //output MOSI_TX_ADC, //input MISO_TX_ADC, + //output SEN_RX_DB, //output SCLK_RX_DB, //output MOSI_RX_DB, //input MISO_RX_DB, + //output SEN_RX_DAC, //output SCLK_RX_DAC, //output MOSI_RX_DAC, + //output SEN_RX_ADC, //output SCLK_RX_ADC, //output MOSI_RX_ADC, //input MISO_RX_ADC, + + // GigE PHY + //input CLK_TO_MAC, + + //output reg [7:0] GMII_TXD, + //output reg GMII_TX_EN, + //output reg GMII_TX_ER, + //output GMII_GTX_CLK, + //input GMII_TX_CLK, // 100mbps clk + + //input GMII_RX_CLK, + //input [7:0] GMII_RXD, + //input GMII_RX_DV, + //input GMII_RX_ER, + //input GMII_COL, + //input GMII_CRS, + + //input PHY_INTn, // open drain + //inout MDIO, + //output MDC, + //output PHY_RESETn, + output ETH_LED + + //input POR, + + // Expansion + //input exp_time_in_p, //input exp_time_in_n, // Diff + //output exp_time_out_p, //output exp_time_out_n, // Diff + //input exp_user_in_p, //input exp_user_in_n, // Diff + //output exp_user_out_p, //output exp_user_out_n, // Diff + + // SERDES + //output ser_enable, + //output ser_prbsen, + //output ser_loopen, + //output ser_rx_en, + + //output ser_tx_clk, + //output reg [15:0] ser_t, + //output reg ser_tklsb, + //output reg ser_tkmsb, + + //input ser_rx_clk, + //input [15:0] ser_r, + //input ser_rklsb, + //input ser_rkmsb, + + // SRAM + //inout [35:0] RAM_D, + //output [20:0] RAM_A, + //output [3:0] RAM_BWn, + //output RAM_ZZ, + //output RAM_LDn, + //output RAM_OEn, + //output RAM_WEn, + //output RAM_CENn, + //output RAM_CLK, + + // SPI Flash + //output flash_cs, + //output flash_clk, + //output flash_mosi, + //input flash_miso + ); + + // FPGA-specific pins connections + wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; + + IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; + + reg [31:0] ctr; + + always @(posedge clk_fpga) + ctr <= ctr + 1; + + assign {leds,ETH_LED} = ~ctr[29:24]; + + +/* + wire exp_time_in; + IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); + defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; + + wire exp_time_out; + OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); + defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; + + wire dcm_rst = 0; + + wire [13:0] adc_a, adc_b; + + capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds + (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), + .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p}, + {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), + .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n}, + {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), + .out({adc_a,adc_b})); + + // Handle Clocks + DCM DCM_INST (.CLKFB(dsp_clk), + .CLKIN(clk_fpga), + .DSSEN(0), + .PSCLK(0), + .PSEN(0), + .PSINCDEC(0), + .RST(dcm_rst), + .CLKDV(clk_div), + .CLKFX(), + .CLKFX180(), + .CLK0(dcm_out), + .CLK2X(), + .CLK2X180(), + .CLK90(), + .CLK180(), + .CLK270(), + .LOCKED(LOCKED_OUT), + .PSDONE(), + .STATUS()); + defparam DCM_INST.CLK_FEEDBACK = "1X"; + defparam DCM_INST.CLKDV_DIVIDE = 2.0; + defparam DCM_INST.CLKFX_DIVIDE = 1; + defparam DCM_INST.CLKFX_MULTIPLY = 4; + defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; + defparam DCM_INST.CLKIN_PERIOD = 10.000; + defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; + defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; + defparam DCM_INST.FACTORY_JF = 16'h8080; + defparam DCM_INST.PHASE_SHIFT = 0; + defparam DCM_INST.STARTUP_WAIT = "FALSE"; + + BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // LEDs are active low outputs + wire [4:0] leds_int; + assign leds = ~leds_int; // drive low to turn on leds + + // SPI + wire miso, mosi, sclk; + + assign {SCLK_CLK,MOSI_CLK} = ~SEN_CLK ? {sclk,mosi} : 2'B0; + assign {SCLK_DAC,MOSI_DAC} = ~SEN_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_ADC,MOSI_ADC} = ~SEN_ADC ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_DAC,MOSI_TX_DAC} = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_TX_ADC,MOSI_TX_ADC} = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_DAC,MOSI_RX_DAC} = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0; + assign {SCLK_RX_ADC,MOSI_RX_ADC} = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0; + + assign miso = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) | + (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) | + (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC); + + wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; + wire [7:0] GMII_TXD_unreg; + wire GMII_GTX_CLK_int; + + always @(posedge GMII_GTX_CLK_int) + begin + GMII_TX_EN <= GMII_TX_EN_unreg; + GMII_TX_ER <= GMII_TX_ER_unreg; + GMII_TXD <= GMII_TXD_unreg; + end + + OFDDRRSE OFDDRRSE_gmii_inst + (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) + .C0(GMII_GTX_CLK_int), // 0 degree clock input + .C1(~GMII_GTX_CLK_int), // 180 degree clock input + .CE(1), // Clock enable input + .D0(0), // Posedge data input + .D1(1), // Negedge data input + .R(0), // Synchronous reset input + .S(0) // Synchronous preset input + ); + + wire ser_tklsb_unreg, ser_tkmsb_unreg; + wire [15:0] ser_t_unreg; + wire ser_tx_clk_int; + + always @(posedge ser_tx_clk_int) + begin + ser_tklsb <= ser_tklsb_unreg; + ser_tkmsb <= ser_tkmsb_unreg; + ser_t <= ser_t_unreg; + end + + assign ser_tx_clk = clk_fpga; + + reg [15:0] ser_r_int; + reg ser_rklsb_int, ser_rkmsb_int; + + always @(posedge ser_rx_clk) + begin + ser_r_int <= ser_r; + ser_rklsb_int <= ser_rklsb; + ser_rkmsb_int <= ser_rkmsb; + end + + u2_core u2_core(.dsp_clk (dsp_clk), + .wb_clk (wb_clk), + .clock_ready (clock_ready), + .clk_to_mac (clk_to_mac), + .pps_in (pps_in), + .leds (leds_int), + .debug (debug[31:0]), + .debug_clk (debug_clk[1:0]), + .exp_pps_in (exp_time_in), + .exp_pps_out (exp_time_out), + .GMII_COL (GMII_COL), + .GMII_CRS (GMII_CRS), + .GMII_TXD (GMII_TXD_unreg[7:0]), + .GMII_TX_EN (GMII_TX_EN_unreg), + .GMII_TX_ER (GMII_TX_ER_unreg), + .GMII_GTX_CLK (GMII_GTX_CLK_int), + .GMII_TX_CLK (GMII_TX_CLK), + .GMII_RXD (GMII_RXD[7:0]), + .GMII_RX_CLK (GMII_RX_CLK), + .GMII_RX_DV (GMII_RX_DV), + .GMII_RX_ER (GMII_RX_ER), + .MDIO (MDIO), + .MDC (MDC), + .PHY_INTn (PHY_INTn), + .PHY_RESETn (PHY_RESETn), + .ser_enable (ser_enable), + .ser_prbsen (ser_prbsen), + .ser_loopen (ser_loopen), + .ser_rx_en (ser_rx_en), + .ser_tx_clk (ser_tx_clk_int), + .ser_t (ser_t_unreg[15:0]), + .ser_tklsb (ser_tklsb_unreg), + .ser_tkmsb (ser_tkmsb_unreg), + .ser_rx_clk (ser_rx_clk), + .ser_r (ser_r_int[15:0]), + .ser_rklsb (ser_rklsb_int), + .ser_rkmsb (ser_rkmsb_int), + .cpld_start (cpld_start), + .cpld_mode (cpld_mode), + .cpld_done (cpld_done), + .cpld_din (cpld_din), + .cpld_clk (cpld_clk), + .cpld_detached (cpld_detached), + .adc_a (adc_a[13:0]), + .adc_ovf_a (adc_ovf_a), + .adc_on_a (adc_on_a), + .adc_oe_a (adc_oe_a), + .adc_b (adc_b[13:0]), + .adc_ovf_b (adc_ovf_b), + .adc_on_b (adc_on_b), + .adc_oe_b (adc_oe_b), + .dac_a (DACA[15:0]), + .dac_b (DACB[15:0]), + .scl_pad_i (scl_pad_i), + .scl_pad_o (scl_pad_o), + .scl_pad_oen_o (scl_pad_oen_o), + .sda_pad_i (sda_pad_i), + .sda_pad_o (sda_pad_o), + .sda_pad_oen_o (sda_pad_oen_o), + .clk_en (clk_en[1:0]), + .clk_sel (clk_sel[1:0]), + .clk_func (clk_func), + .clk_status (clk_status), + .sclk (sclk_int), + .mosi (mosi), + .miso (miso), + .sen_clk (sen_clk), + .sen_dac (sen_dac), + .sen_tx_db (sen_tx_db), + .sen_tx_adc (sen_tx_adc), + .sen_tx_dac (sen_tx_dac), + .sen_rx_db (sen_rx_db), + .sen_rx_adc (sen_rx_adc), + .sen_rx_dac (sen_rx_dac), + .io_tx (io_tx[15:0]), + .io_rx (io_rx[15:0]), + .RAM_D (RAM_D), + .RAM_A (RAM_A), + .RAM_CE1n (RAM_CE1n), + .RAM_CENn (RAM_CENn), + .RAM_CLK (RAM_CLK), + .RAM_WEn (RAM_WEn), + .RAM_OEn (RAM_OEn), + .RAM_LDn (RAM_LDn), + .uart_tx_o (uart_tx_o), + .uart_rx_i (uart_rx_i), + .uart_baud_o (), + .sim_mode (1'b0), + .clock_divider (2) + ); +*/ +endmodule // safe_u2plus -- cgit v1.2.3 From 3f2e589f639c6ec16e62b337568ebca96e241ae2 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 9 Feb 2010 18:41:22 -0800 Subject: first cut at blinking leds --- usrp2/top/safe_u1e/.gitignore | 2 + usrp2/top/safe_u1e/Makefile | 2 +- usrp2/top/safe_u1e/safe_u1e.ucf | 228 ++++++++++++++++++++++++++ usrp2/top/safe_u1e/safe_u1e.v | 350 +--------------------------------------- 4 files changed, 237 insertions(+), 345 deletions(-) create mode 100644 usrp2/top/safe_u1e/.gitignore create mode 100644 usrp2/top/safe_u1e/safe_u1e.ucf diff --git a/usrp2/top/safe_u1e/.gitignore b/usrp2/top/safe_u1e/.gitignore new file mode 100644 index 000000000..bdc5af040 --- /dev/null +++ b/usrp2/top/safe_u1e/.gitignore @@ -0,0 +1,2 @@ +*~ +build diff --git a/usrp2/top/safe_u1e/Makefile b/usrp2/top/safe_u1e/Makefile index 8fe77d554..664835187 100644 --- a/usrp2/top/safe_u1e/Makefile +++ b/usrp2/top/safe_u1e/Makefile @@ -175,7 +175,7 @@ timing/time_sender.v \ timing/time_sync.v \ timing/timer.v \ top/u2_core/u2_core.v \ -top/safe_u1e/u1e.ucf \ +top/safe_u1e/safe_u1e.ucf \ top/safe_u1e/safe_u1e.v ################################################## diff --git a/usrp2/top/safe_u1e/safe_u1e.ucf b/usrp2/top/safe_u1e/safe_u1e.ucf new file mode 100644 index 000000000..83dbeca54 --- /dev/null +++ b/usrp2/top/safe_u1e/safe_u1e.ucf @@ -0,0 +1,228 @@ +#NET "EM_CLK" LOC = "F11" ; +#NET "overo_gpio23" LOC = "B3" ; +#NET "overo_gpio22" LOC = "A3" ; +#NET "overo_gpio21" LOC = "D5" ; +#NET "overo_gpio14" LOC = "C4" ; +#NET "overo_gpio176" LOC = "B4" ; +#NET "overo_gpio64" LOC = "A4" ; +#NET "overo_gpio65" LOC = "F8" ; +#NET "overo_gpio170" LOC = "E8" ; +#NET "overo_gpio145" LOC = "C7" ; +#NET "overo_gpio163" LOC = "D7" ; +#NET "overo_gpio146" LOC = "A6" ; +#NET "overo_gpio144" LOC = "A5" ; +#NET "overo_gpio147" LOC = "B6" ; +#NET "overo_gpio128" LOC = "G8" ; +#NET "overo_gpio0" LOC = "F9" ; +#NET "overo_gpio127" LOC = "C8" ; +#NET "overo_txd1" LOC = "C6" ; +#NET "overo_rxd1" LOC = "D6" ; +#NET "EM_WAIT0" LOC = "F14" ; +#NET "EM_NWP" LOC = "F13" ; +#NET "EM_NBE1" LOC = "D14" ; +#NET "EM_NBE0" LOC = "A13" ; +#NET "EM_NWE" LOC = "B13" ; +#NET "EM_NOE" LOC = "A14" ; +#NET "EM_NADV_ALE" LOC = "B15" ; +#NET "EM_D15" LOC = "D13" ; +#NET "EM_D14" LOC = "D15" ; +#NET "EM_D13" LOC = "C16" ; +#NET "EM_D12" LOC = "B20" ; +#NET "EM_D11" LOC = "A19" ; +#NET "EM_D10" LOC = "A17" ; +#NET "EM_D9" LOC = "E15" ; +#NET "EM_D8" LOC = "F15" ; +#NET "EM_D7" LOC = "E16" ; +#NET "EM_D6" LOC = "F16" ; +#NET "EM_D5" LOC = "B17" ; +#NET "EM_D4" LOC = "C17" ; +#NET "EM_D3" LOC = "B19" ; +#NET "EM_D2" LOC = "D19" ; +#NET "EM_D1" LOC = "C19" ; +#NET "EM_D0" LOC = "A20" ; +#NET "SYSEN" LOC = "C11" ; +#NET "EM_NCS6" LOC = "E17" ; +#NET "EM_NCS5" LOC = "E10" ; +#NET "EM_NCS4" LOC = "E6" ; +#NET "EM_NCS1" LOC = "D18" ; +#NET "EM_NCS0" LOC = "D17" ; +#NET "EM_A10" LOC = "C14" ; +#NET "EM_A9" LOC = "C10" ; +#NET "EM_A8" LOC = "C5" ; +#NET "EM_A7" LOC = "A18" ; +#NET "EM_A6" LOC = "A15" ; +#NET "EM_A5" LOC = "A12" ; +#NET "EM_A4" LOC = "A10" ; +#NET "EM_A3" LOC = "E7" ; +#NET "EM_A2" LOC = "A7" ; +#NET "EM_A1" LOC = "C15" ; +#NET "db_scl" LOC = "U4" ; +#NET "db_sda" LOC = "U5" ; +#NET "db_sclk_rx" LOC = "W3" ; +#NET "db_miso_rx" LOC = "W2" ; +#NET "db_mosi_rx" LOC = "V4" ; +#NET "db_sen_rx" LOC = "V3" ; +#NET "db_sclk_tx" LOC = "Y1" ; +#NET "db_miso_tx" LOC = "W1" ; +#NET "db_mosi_tx" LOC = "R3" ; +#NET "db_sen_tx" LOC = "T4" ; +#NET "cgen_miso" LOC = "U2" ; +#NET "cgen_mosi" LOC = "V1" ; +#NET "cgen_sclk" LOC = "R5" ; +#NET "cgen_sen_b" LOC = "T1" ; +#NET "FPGA_TXD" LOC = "U1" ; +#NET "FPGA_RXD" LOC = "T6" ; +#NET "debug_00" LOC = "P6" ; +#NET "debug_01" LOC = "R6" ; +#NET "debug_02" LOC = "P1" ; +#NET "debug_03" LOC = "P2" ; +#NET "debug_04" LOC = "N6" ; +#NET "debug_05" LOC = "N5" ; +#NET "debug_06" LOC = "N1" ; +#NET "debug_07" LOC = "K2" ; +#NET "debug_08" LOC = "K3" ; +#NET "debug_09" LOC = "K6" ; +#NET "debug_10" LOC = "L5" ; +#NET "debug_11" LOC = "H2" ; +#NET "debug_12" LOC = "K4" ; +#NET "debug_13" LOC = "K5" ; +#NET "debug_14" LOC = "G1" ; +#NET "debug_15" LOC = "H1" ; +#NET "debug_16" LOC = "H5" ; +#NET "debug_17" LOC = "H6" ; +#NET "debug_18" LOC = "E3" ; +#NET "debug_19" LOC = "E4" ; +#NET "debug_20" LOC = "G5" ; +#NET "debug_21" LOC = "G6" ; +#NET "debug_22" LOC = "F2" ; +#NET "debug_23" LOC = "F1" ; +#NET "debug_24" LOC = "H3" ; +#NET "debug_25" LOC = "H4" ; +#NET "debug_26" LOC = "F4" ; +#NET "debug_27" LOC = "F5" ; +#NET "debug_28" LOC = "C2" ; +#NET "debug_29" LOC = "C1" ; +#NET "debug_30" LOC = "F3" ; +#NET "debug_31" LOC = "G3" ; +#NET "debug_pb2" LOC = "Y2" ; +#NET "debug_pb1" LOC = "AA1" ; +#NET "debug_pb0" LOC = "N3" ; +#NET "dip_sw_7" LOC = "T3" ; +#NET "dip_sw_6" LOC = "U3" ; +#NET "dip_sw_5" LOC = "M3" ; +#NET "dip_sw_4" LOC = "N4" ; +#NET "dip_sw_3" LOC = "J3" ; +#NET "dip_sw_2" LOC = "J4" ; +#NET "dip_sw_1" LOC = "J6" ; +#NET "dip_sw_0" LOC = "J7" ; +#NET "cgen_st_status" LOC = "D4" ; +#NET "cgen_st_ld" LOC = "D1" ; +#NET "cgen_st_refmon" LOC = "E1" ; +#NET "cgen_sync_b" LOC = "M1" ; +#NET "cgen_ref_sel" LOC = "J1" ; +#NET "debug_clk0" LOC = "L6" ; +#NET "debug_clk1" LOC = "M5" ; +#NET "unnamed_net37" LOC = "B1" ; +#NET "unnamed_net36" LOC = "B22" ; +#NET "unnamed_net35" LOC = "D2" ; +#NET "unnamed_net34" LOC = "A21" ; +#NET "GND" LOC = "V19" ; +#NET "fpga_cfg_prog_b" LOC = "A2" ; +#NET "fpga_cfg_done" LOC = "AB21" ; +#NET "unnamed_net45" LOC = "F7" ; +#NET "fpga_cfg_din" LOC = "W17" ; +#NET "fpga_cfg_cclk" LOC = "V17" ; +#NET "fpga_cfg_init_b" LOC = "W15" ; +#NET "unnamed_net44" LOC = "V6" ; +#NET "unnamed_net43" LOC = "AA3" ; +#NET "unnamed_net42" LOC = "AB3" ; +#NET "aux_sdi_codec" LOC = "F19" ; +#NET "aux_sdo_codec" LOC = "F18" ; +#NET "aux_sclk_codec" LOC = "D21" ; +#NET "reset_codec" LOC = "D22" ; +#NET "sen_codec" LOC = "D20" ; +#NET "mosi_codec" LOC = "E19" ; +#NET "miso_codec" LOC = "F21" ; +#NET "sclk_codec" LOC = "E20" ; +#NET "RXSYNC" LOC = "F22" ; +#NET "DB11" LOC = "E22" ; +#NET "DB10" LOC = "J19" ; +#NET "DB09" LOC = "H20" ; +#NET "DB08" LOC = "G19" ; +#NET "DB07" LOC = "F20" ; +#NET "DB06" LOC = "K16" ; +#NET "DB05" LOC = "J17" ; +#NET "DB04" LOC = "H22" ; +#NET "DB03" LOC = "G22" ; +#NET "DB02" LOC = "H17" ; +#NET "DB01" LOC = "H18" ; +#NET "DB00" LOC = "K20" ; +#NET "DA11" LOC = "J20" ; +#NET "DA10" LOC = "K19" ; +#NET "DA09" LOC = "K18" ; +#NET "DA08" LOC = "L22" ; +#NET "DA07" LOC = "K22" ; +#NET "DA06" LOC = "N22" ; +#NET "DA05" LOC = "M22" ; +#NET "DA04" LOC = "N20" ; +#NET "DA03" LOC = "N19" ; +#NET "DA02" LOC = "R22" ; +#NET "DA01" LOC = "P22" ; +#NET "DA00" LOC = "N17" ; +#NET "TX13" LOC = "P19" ; +#NET "TX12" LOC = "R18" ; +#NET "TX11" LOC = "U20" ; +#NET "TX10" LOC = "T20" ; +#NET "TX09" LOC = "R19" ; +#NET "TX08" LOC = "R20" ; +#NET "TX07" LOC = "W22" ; +#NET "TX06" LOC = "Y22" ; +#NET "TX05" LOC = "T18" ; +#NET "TX04" LOC = "T17" ; +#NET "TX03" LOC = "W19" ; +#NET "TX02" LOC = "V20" ; +#NET "TX01" LOC = "Y21" ; +#NET "TX00" LOC = "AA22" ; +#NET "TXSYNC" LOC = "U18" ; +#NET "TXBLANK" LOC = "U19" ; +#NET "PPS_IN" LOC = "M17" ; +#NET "io_tx_00" LOC = "AB20" ; +#NET "io_tx_01" LOC = "Y17" ; +#NET "io_tx_02" LOC = "Y16" ; +#NET "io_tx_03" LOC = "U16" ; +#NET "io_tx_04" LOC = "V16" ; +#NET "io_tx_05" LOC = "AB19" ; +#NET "io_tx_06" LOC = "AA19" ; +#NET "io_tx_07" LOC = "U14" ; +#NET "io_tx_08" LOC = "U15" ; +#NET "io_tx_09" LOC = "AB17" ; +#NET "io_tx_10" LOC = "AB18" ; +#NET "io_tx_11" LOC = "Y13" ; +#NET "io_tx_12" LOC = "W14" ; +#NET "io_tx_13" LOC = "U13" ; +#NET "io_tx_14" LOC = "AA15" ; +#NET "io_tx_15" LOC = "AB14" ; +#NET "io_rx_00" LOC = "Y8" ; +#NET "io_rx_01" LOC = "Y9" ; +#NET "io_rx_02" LOC = "V7" ; +#NET "io_rx_03" LOC = "U8" ; +#NET "io_rx_04" LOC = "V10" ; +#NET "io_rx_05" LOC = "U9" ; +#NET "io_rx_06" LOC = "AB7" ; +#NET "io_rx_07" LOC = "AA8" ; +#NET "io_rx_08" LOC = "W8" ; +#NET "io_rx_09" LOC = "V8" ; +#NET "io_rx_10" LOC = "AB5" ; +#NET "io_rx_11" LOC = "AB6" ; +#NET "io_rx_12" LOC = "AB4" ; +#NET "io_rx_13" LOC = "AA4" ; +#NET "io_rx_14" LOC = "W5" ; +#NET "io_rx_15" LOC = "Y4" ; +#NET "CLKOUT2_CODEC" LOC = "U12" ; +#NET "CLKOUT1_CODEC" LOC = "V12" ; + +NET "CLK_FPGA_P" LOC = "Y11" ; +NET "CLK_FPGA_N" LOC = "Y10" ; +NET "debug_led<2>" LOC = "T5" ; +NET "debug_led<1>" LOC = "R2" ; +NET "debug_led<0>" LOC = "R1" ; diff --git a/usrp2/top/safe_u1e/safe_u1e.v b/usrp2/top/safe_u1e/safe_u1e.v index c880a9e55..79aaac6cd 100644 --- a/usrp2/top/safe_u1e/safe_u1e.v +++ b/usrp2/top/safe_u1e/safe_u1e.v @@ -4,131 +4,14 @@ module safe_u1e ( input CLK_FPGA_P, input CLK_FPGA_N, // Diff - - // ADC - //input ADC_clkout_p, //input ADC_clkout_n, - //input ADCA_12_p, //input ADCA_12_n, - //input ADCA_10_p, //input ADCA_10_n, - //input ADCA_8_p, //input ADCA_8_n, - //input ADCA_6_p, //input ADCA_6_n, - //input ADCA_4_p, //input ADCA_4_n, - //input ADCA_2_p, //input ADCA_2_n, - //input ADCA_0_p, //input ADCA_0_n, - //input ADCB_12_p, //input ADCB_12_n, - //input ADCB_10_p, //input ADCB_10_n, - //input ADCB_8_p, //input ADCB_8_n, - //input ADCB_6_p, //input ADCB_6_n, - //input ADCB_4_p, //input ADCB_4_n, - //input ADCB_2_p, //input ADCB_2_n, - //input ADCB_0_p, //input ADCB_0_n, - - // DAC - //output [15:0] DACA, - //output [15:0] DACB, - //input DAC_LOCK, // unused for now - - // DB IO Pins - //inout [15:0] io_tx, - //inout [15:0] io_rx, - - // Misc, debug - output [5:1] leds, // LED4 is shared w/INIT_B - //input FPGA_RESET, - //output [1:0] debug_clk, - //output [31:0] debug, - //output [3:1] TXD, //input [3:1] RXD, // UARTs - ////input [3:0] dipsw, // Forgot DIP Switches... - - // Clock Gen Control - //output [1:0] clk_en, - //output [1:0] clk_sel, - //input CLK_FUNC, // FIXME is an //input to control the 9510 - //input CLK_STATUS, - - //inout SCL, //inout SDA, // I2C - - // PPS - //input PPS_IN, //input PPS2_IN, - - // SPI - //output SEN_CLK, //output SCLK_CLK, //output MOSI_CLK, //input MISO_CLK, - //output SEN_DAC, //output SCLK_DAC, //output MOSI_DAC, //input MISO_DAC, - //output SEN_ADC, //output SCLK_ADC, //output MOSI_ADC, - //output SEN_TX_DB, //output SCLK_TX_DB, //output MOSI_TX_DB, //input MISO_TX_DB, - //output SEN_TX_DAC, //output SCLK_TX_DAC, //output MOSI_TX_DAC, - //output SEN_TX_ADC, //output SCLK_TX_ADC, //output MOSI_TX_ADC, //input MISO_TX_ADC, - //output SEN_RX_DB, //output SCLK_RX_DB, //output MOSI_RX_DB, //input MISO_RX_DB, - //output SEN_RX_DAC, //output SCLK_RX_DAC, //output MOSI_RX_DAC, - //output SEN_RX_ADC, //output SCLK_RX_ADC, //output MOSI_RX_ADC, //input MISO_RX_ADC, - - // GigE PHY - //input CLK_TO_MAC, - - //output reg [7:0] GMII_TXD, - //output reg GMII_TX_EN, - //output reg GMII_TX_ER, - //output GMII_GTX_CLK, - //input GMII_TX_CLK, // 100mbps clk - - //input GMII_RX_CLK, - //input [7:0] GMII_RXD, - //input GMII_RX_DV, - //input GMII_RX_ER, - //input GMII_COL, - //input GMII_CRS, - - //input PHY_INTn, // open drain - //inout MDIO, - //output MDC, - //output PHY_RESETn, - output ETH_LED - - //input POR, - - // Expansion - //input exp_time_in_p, //input exp_time_in_n, // Diff - //output exp_time_out_p, //output exp_time_out_n, // Diff - //input exp_user_in_p, //input exp_user_in_n, // Diff - //output exp_user_out_p, //output exp_user_out_n, // Diff - - // SERDES - //output ser_enable, - //output ser_prbsen, - //output ser_loopen, - //output ser_rx_en, - - //output ser_tx_clk, - //output reg [15:0] ser_t, - //output reg ser_tklsb, - //output reg ser_tkmsb, - - //input ser_rx_clk, - //input [15:0] ser_r, - //input ser_rklsb, - //input ser_rkmsb, - - // SRAM - //inout [35:0] RAM_D, - //output [20:0] RAM_A, - //output [3:0] RAM_BWn, - //output RAM_ZZ, - //output RAM_LDn, - //output RAM_OEn, - //output RAM_WEn, - //output RAM_CENn, - //output RAM_CLK, - - // SPI Flash - //output flash_cs, - //output flash_clk, - //output flash_mosi, - //input flash_miso + output [2:0] debug_led ); // FPGA-specific pins connections - wire clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready; - - IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + wire clk_fpga; + + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) + clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; reg [31:0] ctr; @@ -136,227 +19,6 @@ module safe_u1e always @(posedge clk_fpga) ctr <= ctr + 1; - assign {leds,ETH_LED} = ~ctr[29:24]; - - -/* - wire exp_time_in; - IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n)); - defparam exp_time_in_pin.IOSTANDARD = "LVDS_25"; - - wire exp_time_out; - OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out)); - defparam exp_time_out_pin.IOSTANDARD = "LVDS_25"; - - wire dcm_rst = 0; - - wire [13:0] adc_a, adc_b; - - capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds - (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), - .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p}, - {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), - .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n}, - {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), - .out({adc_a,adc_b})); - - // Handle Clocks - DCM DCM_INST (.CLKFB(dsp_clk), - .CLKIN(clk_fpga), - .DSSEN(0), - .PSCLK(0), - .PSEN(0), - .PSINCDEC(0), - .RST(dcm_rst), - .CLKDV(clk_div), - .CLKFX(), - .CLKFX180(), - .CLK0(dcm_out), - .CLK2X(), - .CLK2X180(), - .CLK90(), - .CLK180(), - .CLK270(), - .LOCKED(LOCKED_OUT), - .PSDONE(), - .STATUS()); - defparam DCM_INST.CLK_FEEDBACK = "1X"; - defparam DCM_INST.CLKDV_DIVIDE = 2.0; - defparam DCM_INST.CLKFX_DIVIDE = 1; - defparam DCM_INST.CLKFX_MULTIPLY = 4; - defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE"; - defparam DCM_INST.CLKIN_PERIOD = 10.000; - defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE"; - defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW"; - defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE"; - defparam DCM_INST.FACTORY_JF = 16'h8080; - defparam DCM_INST.PHASE_SHIFT = 0; - defparam DCM_INST.STARTUP_WAIT = "FALSE"; - - BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); - BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); - - // I2C -- Don't use external transistors for open drain, the FPGA implements this - IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o)); - IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o)); - - // LEDs are active low outputs - wire [4:0] leds_int; - assign leds = ~leds_int; // drive low to turn on leds - - // SPI - wire miso, mosi, sclk; + assign debug_led = ctr[27:25]; - assign {SCLK_CLK,MOSI_CLK} = ~SEN_CLK ? {sclk,mosi} : 2'B0; - assign {SCLK_DAC,MOSI_DAC} = ~SEN_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_ADC,MOSI_ADC} = ~SEN_ADC ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_DB,MOSI_TX_DB} = ~SEN_TX_DB ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_DAC,MOSI_TX_DAC} = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_TX_ADC,MOSI_TX_ADC} = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_DB,MOSI_RX_DB} = ~SEN_RX_DB ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_DAC,MOSI_RX_DAC} = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0; - assign {SCLK_RX_ADC,MOSI_RX_ADC} = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0; - - assign miso = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) | - (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) | - (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC); - - wire GMII_TX_EN_unreg, GMII_TX_ER_unreg; - wire [7:0] GMII_TXD_unreg; - wire GMII_GTX_CLK_int; - - always @(posedge GMII_GTX_CLK_int) - begin - GMII_TX_EN <= GMII_TX_EN_unreg; - GMII_TX_ER <= GMII_TX_ER_unreg; - GMII_TXD <= GMII_TXD_unreg; - end - - OFDDRRSE OFDDRRSE_gmii_inst - (.Q(GMII_GTX_CLK), // Data output (connect directly to top-level port) - .C0(GMII_GTX_CLK_int), // 0 degree clock input - .C1(~GMII_GTX_CLK_int), // 180 degree clock input - .CE(1), // Clock enable input - .D0(0), // Posedge data input - .D1(1), // Negedge data input - .R(0), // Synchronous reset input - .S(0) // Synchronous preset input - ); - - wire ser_tklsb_unreg, ser_tkmsb_unreg; - wire [15:0] ser_t_unreg; - wire ser_tx_clk_int; - - always @(posedge ser_tx_clk_int) - begin - ser_tklsb <= ser_tklsb_unreg; - ser_tkmsb <= ser_tkmsb_unreg; - ser_t <= ser_t_unreg; - end - - assign ser_tx_clk = clk_fpga; - - reg [15:0] ser_r_int; - reg ser_rklsb_int, ser_rkmsb_int; - - always @(posedge ser_rx_clk) - begin - ser_r_int <= ser_r; - ser_rklsb_int <= ser_rklsb; - ser_rkmsb_int <= ser_rkmsb; - end - - u2_core u2_core(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), - .leds (leds_int), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_time_in), - .exp_pps_out (exp_time_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD_unreg[7:0]), - .GMII_TX_EN (GMII_TX_EN_unreg), - .GMII_TX_ER (GMII_TX_ER_unreg), - .GMII_GTX_CLK (GMII_GTX_CLK_int), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk_int), - .ser_t (ser_t_unreg[15:0]), - .ser_tklsb (ser_tklsb_unreg), - .ser_tkmsb (ser_tkmsb_unreg), - .ser_rx_clk (ser_rx_clk), - .ser_r (ser_r_int[15:0]), - .ser_rklsb (ser_rklsb_int), - .ser_rkmsb (ser_rkmsb_int), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .adc_a (adc_a[13:0]), - .adc_ovf_a (adc_ovf_a), - .adc_on_a (adc_on_a), - .adc_oe_a (adc_oe_a), - .adc_b (adc_b[13:0]), - .adc_ovf_b (adc_ovf_b), - .adc_on_b (adc_on_b), - .adc_oe_b (adc_oe_b), - .dac_a (DACA[15:0]), - .dac_b (DACB[15:0]), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk_int), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0]), - .RAM_D (RAM_D), - .RAM_A (RAM_A), - .RAM_CE1n (RAM_CE1n), - .RAM_CENn (RAM_CENn), - .RAM_CLK (RAM_CLK), - .RAM_WEn (RAM_WEn), - .RAM_OEn (RAM_OEn), - .RAM_LDn (RAM_LDn), - .uart_tx_o (uart_tx_o), - .uart_rx_i (uart_rx_i), - .uart_baud_o (), - .sim_mode (1'b0), - .clock_divider (2) - ); -*/ endmodule // safe_u2plus -- cgit v1.2.3 From 36138857e9d64a129840814aed79c00cc6f505e9 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 9 Feb 2010 19:04:26 -0800 Subject: builds a successful led blinker --- usrp2/top/safe_u1e/.gitignore | 2 ++ usrp2/top/safe_u1e/Makefile | 3 ++- usrp2/top/safe_u1e/safe_u1e.v | 1 - 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/usrp2/top/safe_u1e/.gitignore b/usrp2/top/safe_u1e/.gitignore index bdc5af040..f8b57ea21 100644 --- a/usrp2/top/safe_u1e/.gitignore +++ b/usrp2/top/safe_u1e/.gitignore @@ -1,2 +1,4 @@ *~ build +*.log +*.cmd diff --git a/usrp2/top/safe_u1e/Makefile b/usrp2/top/safe_u1e/Makefile index 664835187..d28cc2b89 100644 --- a/usrp2/top/safe_u1e/Makefile +++ b/usrp2/top/safe_u1e/Makefile @@ -217,7 +217,8 @@ export GEN_PROG_FILE_PROPERTIES := \ "Create Binary Configuration File" TRUE \ "Done (Output Events)" 5 \ "Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" export SIM_MODEL_PROPERTIES := "" diff --git a/usrp2/top/safe_u1e/safe_u1e.v b/usrp2/top/safe_u1e/safe_u1e.v index 79aaac6cd..1b81bab5a 100644 --- a/usrp2/top/safe_u1e/safe_u1e.v +++ b/usrp2/top/safe_u1e/safe_u1e.v @@ -12,7 +12,6 @@ module safe_u1e IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; reg [31:0] ctr; -- cgit v1.2.3 From 44d8aeb6bdbe598d6d453c4530015892959cb765 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 9 Feb 2010 21:09:56 -0800 Subject: organized the pins in the ucf by function --- usrp2/top/safe_u1e/safe_u1e.ucf | 128 ++++++++++++++++++++++------------------ 1 file changed, 72 insertions(+), 56 deletions(-) diff --git a/usrp2/top/safe_u1e/safe_u1e.ucf b/usrp2/top/safe_u1e/safe_u1e.ucf index 83dbeca54..16265c203 100644 --- a/usrp2/top/safe_u1e/safe_u1e.ucf +++ b/usrp2/top/safe_u1e/safe_u1e.ucf @@ -1,3 +1,8 @@ + +NET "CLK_FPGA_P" LOC = "Y11" ; +NET "CLK_FPGA_N" LOC = "Y10" ; + +## GPMC #NET "EM_CLK" LOC = "F11" ; #NET "overo_gpio23" LOC = "B3" ; #NET "overo_gpio22" LOC = "A3" ; @@ -56,6 +61,7 @@ #NET "EM_A3" LOC = "E7" ; #NET "EM_A2" LOC = "A7" ; #NET "EM_A1" LOC = "C15" ; + #NET "db_scl" LOC = "U4" ; #NET "db_sda" LOC = "U5" ; #NET "db_sclk_rx" LOC = "W3" ; @@ -72,49 +78,57 @@ #NET "cgen_sen_b" LOC = "T1" ; #NET "FPGA_TXD" LOC = "U1" ; #NET "FPGA_RXD" LOC = "T6" ; -#NET "debug_00" LOC = "P6" ; -#NET "debug_01" LOC = "R6" ; -#NET "debug_02" LOC = "P1" ; -#NET "debug_03" LOC = "P2" ; -#NET "debug_04" LOC = "N6" ; -#NET "debug_05" LOC = "N5" ; -#NET "debug_06" LOC = "N1" ; -#NET "debug_07" LOC = "K2" ; -#NET "debug_08" LOC = "K3" ; -#NET "debug_09" LOC = "K6" ; -#NET "debug_10" LOC = "L5" ; -#NET "debug_11" LOC = "H2" ; -#NET "debug_12" LOC = "K4" ; -#NET "debug_13" LOC = "K5" ; -#NET "debug_14" LOC = "G1" ; -#NET "debug_15" LOC = "H1" ; -#NET "debug_16" LOC = "H5" ; -#NET "debug_17" LOC = "H6" ; -#NET "debug_18" LOC = "E3" ; -#NET "debug_19" LOC = "E4" ; -#NET "debug_20" LOC = "G5" ; -#NET "debug_21" LOC = "G6" ; -#NET "debug_22" LOC = "F2" ; -#NET "debug_23" LOC = "F1" ; -#NET "debug_24" LOC = "H3" ; -#NET "debug_25" LOC = "H4" ; -#NET "debug_26" LOC = "F4" ; -#NET "debug_27" LOC = "F5" ; -#NET "debug_28" LOC = "C2" ; -#NET "debug_29" LOC = "C1" ; -#NET "debug_30" LOC = "F3" ; -#NET "debug_31" LOC = "G3" ; -#NET "debug_pb2" LOC = "Y2" ; -#NET "debug_pb1" LOC = "AA1" ; -#NET "debug_pb0" LOC = "N3" ; -#NET "dip_sw_7" LOC = "T3" ; -#NET "dip_sw_6" LOC = "U3" ; -#NET "dip_sw_5" LOC = "M3" ; -#NET "dip_sw_4" LOC = "N4" ; -#NET "dip_sw_3" LOC = "J3" ; -#NET "dip_sw_2" LOC = "J4" ; -#NET "dip_sw_1" LOC = "J6" ; -#NET "dip_sw_0" LOC = "J7" ; + +## Debug pins +NET "debug_led<2>" LOC = "T5" ; +NET "debug_led<1>" LOC = "R2" ; +NET "debug_led<0>" LOC = "R1" ; +#NET "debug<0>" LOC = "P6" ; +#NET "debug<1>" LOC = "R6" ; +#NET "debug<2>" LOC = "P1" ; +#NET "debug<3>" LOC = "P2" ; +#NET "debug<4>" LOC = "N6" ; +#NET "debug<5>" LOC = "N5" ; +#NET "debug<6>" LOC = "N1" ; +#NET "debug<7>" LOC = "K2" ; +#NET "debug<8>" LOC = "K3" ; +#NET "debug<9>" LOC = "K6" ; +#NET "debug<10>" LOC = "L5" ; +#NET "debug<11>" LOC = "H2" ; +#NET "debug<12>" LOC = "K4" ; +#NET "debug<13>" LOC = "K5" ; +#NET "debug<14>" LOC = "G1" ; +#NET "debug<15>" LOC = "H1" ; +#NET "debug<16>" LOC = "H5" ; +#NET "debug<17>" LOC = "H6" ; +#NET "debug<18>" LOC = "E3" ; +#NET "debug<19>" LOC = "E4" ; +#NET "debug<20>" LOC = "G5" ; +#NET "debug<21>" LOC = "G6" ; +#NET "debug<22>" LOC = "F2" ; +#NET "debug<23>" LOC = "F1" ; +#NET "debug<24>" LOC = "H3" ; +#NET "debug<25>" LOC = "H4" ; +#NET "debug<26>" LOC = "F4" ; +#NET "debug<27>" LOC = "F5" ; +#NET "debug<28>" LOC = "C2" ; +#NET "debug<29>" LOC = "C1" ; +#NET "debug<30>" LOC = "F3" ; +#NET "debug<31>" LOC = "G3" ; + +#NET "debug_pb<2>" LOC = "Y2" ; +#NET "debug_pb<1>" LOC = "AA1" ; +#NET "debug_pb<0>" LOC = "N3" ; + +#NET "dip_sw<7>" LOC = "T3" ; +#NET "dip_sw<6>" LOC = "U3" ; +#NET "dip_sw<5>" LOC = "M3" ; +#NET "dip_sw<4>" LOC = "N4" ; +#NET "dip_sw<3>" LOC = "J3" ; +#NET "dip_sw<2>" LOC = "J4" ; +#NET "dip_sw<1>" LOC = "J6" ; +#NET "dip_sw<0>" LOC = "J7" ; + #NET "cgen_st_status" LOC = "D4" ; #NET "cgen_st_ld" LOC = "D1" ; #NET "cgen_st_refmon" LOC = "E1" ; @@ -122,20 +136,12 @@ #NET "cgen_ref_sel" LOC = "J1" ; #NET "debug_clk0" LOC = "L6" ; #NET "debug_clk1" LOC = "M5" ; -#NET "unnamed_net37" LOC = "B1" ; -#NET "unnamed_net36" LOC = "B22" ; -#NET "unnamed_net35" LOC = "D2" ; -#NET "unnamed_net34" LOC = "A21" ; #NET "GND" LOC = "V19" ; #NET "fpga_cfg_prog_b" LOC = "A2" ; #NET "fpga_cfg_done" LOC = "AB21" ; -#NET "unnamed_net45" LOC = "F7" ; #NET "fpga_cfg_din" LOC = "W17" ; #NET "fpga_cfg_cclk" LOC = "V17" ; #NET "fpga_cfg_init_b" LOC = "W15" ; -#NET "unnamed_net44" LOC = "V6" ; -#NET "unnamed_net43" LOC = "AA3" ; -#NET "unnamed_net42" LOC = "AB3" ; #NET "aux_sdi_codec" LOC = "F19" ; #NET "aux_sdo_codec" LOC = "F18" ; #NET "aux_sclk_codec" LOC = "D21" ; @@ -144,7 +150,9 @@ #NET "mosi_codec" LOC = "E19" ; #NET "miso_codec" LOC = "F21" ; #NET "sclk_codec" LOC = "E20" ; + #NET "RXSYNC" LOC = "F22" ; + #NET "DB11" LOC = "E22" ; #NET "DB10" LOC = "J19" ; #NET "DB09" LOC = "H20" ; @@ -169,6 +177,7 @@ #NET "DA02" LOC = "R22" ; #NET "DA01" LOC = "P22" ; #NET "DA00" LOC = "N17" ; + #NET "TX13" LOC = "P19" ; #NET "TX12" LOC = "R18" ; #NET "TX11" LOC = "U20" ; @@ -185,7 +194,9 @@ #NET "TX00" LOC = "AA22" ; #NET "TXSYNC" LOC = "U18" ; #NET "TXBLANK" LOC = "U19" ; + #NET "PPS_IN" LOC = "M17" ; + #NET "io_tx_00" LOC = "AB20" ; #NET "io_tx_01" LOC = "Y17" ; #NET "io_tx_02" LOC = "Y16" ; @@ -218,11 +229,16 @@ #NET "io_rx_13" LOC = "AA4" ; #NET "io_rx_14" LOC = "W5" ; #NET "io_rx_15" LOC = "Y4" ; + #NET "CLKOUT2_CODEC" LOC = "U12" ; #NET "CLKOUT1_CODEC" LOC = "V12" ; -NET "CLK_FPGA_P" LOC = "Y11" ; -NET "CLK_FPGA_N" LOC = "Y10" ; -NET "debug_led<2>" LOC = "T5" ; -NET "debug_led<1>" LOC = "R2" ; -NET "debug_led<0>" LOC = "R1" ; +## Unnamed, need to figure out what they do +#NET "unnamed_net37" LOC = "B1" ; +#NET "unnamed_net36" LOC = "B22" ; +#NET "unnamed_net35" LOC = "D2" ; +#NET "unnamed_net34" LOC = "A21" ; +#NET "unnamed_net45" LOC = "F7" ; +#NET "unnamed_net44" LOC = "V6" ; +#NET "unnamed_net43" LOC = "AA3" ; +#NET "unnamed_net42" LOC = "AB3" ; -- cgit v1.2.3 From a6872631b33fca08bb39fd8b1329146470369b19 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 14 Feb 2010 17:07:24 -0800 Subject: connect GPMC pins to debug bus --- usrp2/top/safe_u1e/safe_u1e.ucf | 156 +++++++++++++++++++++------------------- usrp2/top/safe_u1e/safe_u1e.v | 14 +++- 2 files changed, 94 insertions(+), 76 deletions(-) diff --git a/usrp2/top/safe_u1e/safe_u1e.ucf b/usrp2/top/safe_u1e/safe_u1e.ucf index 16265c203..14389f299 100644 --- a/usrp2/top/safe_u1e/safe_u1e.ucf +++ b/usrp2/top/safe_u1e/safe_u1e.ucf @@ -3,7 +3,52 @@ NET "CLK_FPGA_P" LOC = "Y11" ; NET "CLK_FPGA_N" LOC = "Y10" ; ## GPMC -#NET "EM_CLK" LOC = "F11" ; +NET "EM_CLK" LOC = "F11" ; + +NET "EM_D<15>" LOC = "D13" ; +NET "EM_D<14>" LOC = "D15" ; +NET "EM_D<13>" LOC = "C16" ; +NET "EM_D<12>" LOC = "B20" ; +NET "EM_D<11>" LOC = "A19" ; +NET "EM_D<10>" LOC = "A17" ; +NET "EM_D<9>" LOC = "E15" ; +NET "EM_D<8>" LOC = "F15" ; +NET "EM_D<7>" LOC = "E16" ; +NET "EM_D<6>" LOC = "F16" ; +NET "EM_D<5>" LOC = "B17" ; +NET "EM_D<4>" LOC = "C17" ; +NET "EM_D<3>" LOC = "B19" ; +NET "EM_D<2>" LOC = "D19" ; +NET "EM_D<1>" LOC = "C19" ; +NET "EM_D<0>" LOC = "A20" ; + +NET "EM_A<10>" LOC = "C14" ; +NET "EM_A<9>" LOC = "C10" ; +NET "EM_A<8>" LOC = "C5" ; +NET "EM_A<7>" LOC = "A18" ; +NET "EM_A<6>" LOC = "A15" ; +NET "EM_A<5>" LOC = "A12" ; +NET "EM_A<4>" LOC = "A10" ; +NET "EM_A<3>" LOC = "E7" ; +NET "EM_A<2>" LOC = "A7" ; +NET "EM_A<1>" LOC = "C15" ; + +#NET "EM_NCS6" LOC = "E17" ; +#NET "EM_NCS5" LOC = "E10" ; +NET "EM_NCS4" LOC = "E6" ; +#NET "EM_NCS1" LOC = "D18" ; +#NET "EM_NCS0" LOC = "D17" ; + +NET "EM_WAIT0" LOC = "F14" ; +#NET "EM_NBE1" LOC = "D14" ; +#NET "EM_NBE0" LOC = "A13" ; +NET "EM_NWP" LOC = "F13" ; +NET "EM_NWE" LOC = "B13" ; +NET "EM_NOE" LOC = "A14" ; +NET "EM_NADV_ALE" LOC = "B15" ; + + +## Overo GPIO #NET "overo_gpio23" LOC = "B3" ; #NET "overo_gpio22" LOC = "A3" ; #NET "overo_gpio21" LOC = "D5" ; @@ -20,47 +65,12 @@ NET "CLK_FPGA_N" LOC = "Y10" ; #NET "overo_gpio128" LOC = "G8" ; #NET "overo_gpio0" LOC = "F9" ; #NET "overo_gpio127" LOC = "C8" ; + +## Overo UART #NET "overo_txd1" LOC = "C6" ; #NET "overo_rxd1" LOC = "D6" ; -#NET "EM_WAIT0" LOC = "F14" ; -#NET "EM_NWP" LOC = "F13" ; -#NET "EM_NBE1" LOC = "D14" ; -#NET "EM_NBE0" LOC = "A13" ; -#NET "EM_NWE" LOC = "B13" ; -#NET "EM_NOE" LOC = "A14" ; -#NET "EM_NADV_ALE" LOC = "B15" ; -#NET "EM_D15" LOC = "D13" ; -#NET "EM_D14" LOC = "D15" ; -#NET "EM_D13" LOC = "C16" ; -#NET "EM_D12" LOC = "B20" ; -#NET "EM_D11" LOC = "A19" ; -#NET "EM_D10" LOC = "A17" ; -#NET "EM_D9" LOC = "E15" ; -#NET "EM_D8" LOC = "F15" ; -#NET "EM_D7" LOC = "E16" ; -#NET "EM_D6" LOC = "F16" ; -#NET "EM_D5" LOC = "B17" ; -#NET "EM_D4" LOC = "C17" ; -#NET "EM_D3" LOC = "B19" ; -#NET "EM_D2" LOC = "D19" ; -#NET "EM_D1" LOC = "C19" ; -#NET "EM_D0" LOC = "A20" ; + #NET "SYSEN" LOC = "C11" ; -#NET "EM_NCS6" LOC = "E17" ; -#NET "EM_NCS5" LOC = "E10" ; -#NET "EM_NCS4" LOC = "E6" ; -#NET "EM_NCS1" LOC = "D18" ; -#NET "EM_NCS0" LOC = "D17" ; -#NET "EM_A10" LOC = "C14" ; -#NET "EM_A9" LOC = "C10" ; -#NET "EM_A8" LOC = "C5" ; -#NET "EM_A7" LOC = "A18" ; -#NET "EM_A6" LOC = "A15" ; -#NET "EM_A5" LOC = "A12" ; -#NET "EM_A4" LOC = "A10" ; -#NET "EM_A3" LOC = "E7" ; -#NET "EM_A2" LOC = "A7" ; -#NET "EM_A1" LOC = "C15" ; #NET "db_scl" LOC = "U4" ; #NET "db_sda" LOC = "U5" ; @@ -83,38 +93,40 @@ NET "CLK_FPGA_N" LOC = "Y10" ; NET "debug_led<2>" LOC = "T5" ; NET "debug_led<1>" LOC = "R2" ; NET "debug_led<0>" LOC = "R1" ; -#NET "debug<0>" LOC = "P6" ; -#NET "debug<1>" LOC = "R6" ; -#NET "debug<2>" LOC = "P1" ; -#NET "debug<3>" LOC = "P2" ; -#NET "debug<4>" LOC = "N6" ; -#NET "debug<5>" LOC = "N5" ; -#NET "debug<6>" LOC = "N1" ; -#NET "debug<7>" LOC = "K2" ; -#NET "debug<8>" LOC = "K3" ; -#NET "debug<9>" LOC = "K6" ; -#NET "debug<10>" LOC = "L5" ; -#NET "debug<11>" LOC = "H2" ; -#NET "debug<12>" LOC = "K4" ; -#NET "debug<13>" LOC = "K5" ; -#NET "debug<14>" LOC = "G1" ; -#NET "debug<15>" LOC = "H1" ; -#NET "debug<16>" LOC = "H5" ; -#NET "debug<17>" LOC = "H6" ; -#NET "debug<18>" LOC = "E3" ; -#NET "debug<19>" LOC = "E4" ; -#NET "debug<20>" LOC = "G5" ; -#NET "debug<21>" LOC = "G6" ; -#NET "debug<22>" LOC = "F2" ; -#NET "debug<23>" LOC = "F1" ; -#NET "debug<24>" LOC = "H3" ; -#NET "debug<25>" LOC = "H4" ; -#NET "debug<26>" LOC = "F4" ; -#NET "debug<27>" LOC = "F5" ; -#NET "debug<28>" LOC = "C2" ; -#NET "debug<29>" LOC = "C1" ; -#NET "debug<30>" LOC = "F3" ; -#NET "debug<31>" LOC = "G3" ; +NET "debug<0>" LOC = "P6" ; +NET "debug<1>" LOC = "R6" ; +NET "debug<2>" LOC = "P1" ; +NET "debug<3>" LOC = "P2" ; +NET "debug<4>" LOC = "N6" ; +NET "debug<5>" LOC = "N5" ; +NET "debug<6>" LOC = "N1" ; +NET "debug<7>" LOC = "K2" ; +NET "debug<8>" LOC = "K3" ; +NET "debug<9>" LOC = "K6" ; +NET "debug<10>" LOC = "L5" ; +NET "debug<11>" LOC = "H2" ; +NET "debug<12>" LOC = "K4" ; +NET "debug<13>" LOC = "K5" ; +NET "debug<14>" LOC = "G1" ; +NET "debug<15>" LOC = "H1" ; +NET "debug<16>" LOC = "H5" ; +NET "debug<17>" LOC = "H6" ; +NET "debug<18>" LOC = "E3" ; +NET "debug<19>" LOC = "E4" ; +NET "debug<20>" LOC = "G5" ; +NET "debug<21>" LOC = "G6" ; +NET "debug<22>" LOC = "F2" ; +NET "debug<23>" LOC = "F1" ; +NET "debug<24>" LOC = "H3" ; +NET "debug<25>" LOC = "H4" ; +NET "debug<26>" LOC = "F4" ; +NET "debug<27>" LOC = "F5" ; +NET "debug<28>" LOC = "C2" ; +NET "debug<29>" LOC = "C1" ; +NET "debug<30>" LOC = "F3" ; +NET "debug<31>" LOC = "G3" ; +NET "debug_clk<0>" LOC = "L6" ; +NET "debug_clk<1>" LOC = "M5" ; #NET "debug_pb<2>" LOC = "Y2" ; #NET "debug_pb<1>" LOC = "AA1" ; @@ -134,8 +146,6 @@ NET "debug_led<0>" LOC = "R1" ; #NET "cgen_st_refmon" LOC = "E1" ; #NET "cgen_sync_b" LOC = "M1" ; #NET "cgen_ref_sel" LOC = "J1" ; -#NET "debug_clk0" LOC = "L6" ; -#NET "debug_clk1" LOC = "M5" ; #NET "GND" LOC = "V19" ; #NET "fpga_cfg_prog_b" LOC = "A2" ; #NET "fpga_cfg_done" LOC = "AB21" ; diff --git a/usrp2/top/safe_u1e/safe_u1e.v b/usrp2/top/safe_u1e/safe_u1e.v index 1b81bab5a..3f16d941c 100644 --- a/usrp2/top/safe_u1e/safe_u1e.v +++ b/usrp2/top/safe_u1e/safe_u1e.v @@ -4,7 +4,11 @@ module safe_u1e ( input CLK_FPGA_P, input CLK_FPGA_N, // Diff - output [2:0] debug_led + output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + + // GPMC + input EM_CLK, input [15:0] EM_D, input [10:1] EM_A, + input EM_WAIT0, input EM_NCS4, input EM_NWP, input EM_NWE, input EM_NOE, input EM_NADV_ALE ); // FPGA-specific pins connections @@ -13,11 +17,15 @@ module safe_u1e IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + // Debug circuitry reg [31:0] ctr; - always @(posedge clk_fpga) ctr <= ctr + 1; + assign debug_led = ctr[27:25]; - + assign debug_clk = { EM_CLK, clk_fpga }; + assign debug = { { EM_WAIT0, EM_NADV_ALE, EM_NWP, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, + { EM_D } }; + endmodule // safe_u2plus -- cgit v1.2.3 From e091b4812ff4f7e6f959aabf48ac65bac5be86b7 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 14 Feb 2010 17:23:43 -0800 Subject: reorg pin defs --- usrp2/top/safe_u1e/safe_u1e.ucf | 196 +++++++++++++++++++++------------------- 1 file changed, 102 insertions(+), 94 deletions(-) diff --git a/usrp2/top/safe_u1e/safe_u1e.ucf b/usrp2/top/safe_u1e/safe_u1e.ucf index 14389f299..cb6d6372e 100644 --- a/usrp2/top/safe_u1e/safe_u1e.ucf +++ b/usrp2/top/safe_u1e/safe_u1e.ucf @@ -49,27 +49,30 @@ NET "EM_NADV_ALE" LOC = "B15" ; ## Overo GPIO -#NET "overo_gpio23" LOC = "B3" ; -#NET "overo_gpio22" LOC = "A3" ; -#NET "overo_gpio21" LOC = "D5" ; +#NET "overo_gpio0" LOC = "F9" ; #NET "overo_gpio14" LOC = "C4" ; -#NET "overo_gpio176" LOC = "B4" ; +#NET "overo_gpio21" LOC = "D5" ; +#NET "overo_gpio22" LOC = "A3" ; +#NET "overo_gpio23" LOC = "B3" ; #NET "overo_gpio64" LOC = "A4" ; #NET "overo_gpio65" LOC = "F8" ; -#NET "overo_gpio170" LOC = "E8" ; +#NET "overo_gpio127" LOC = "C8" ; +#NET "overo_gpio128" LOC = "G8" ; +#NET "overo_gpio144" LOC = "A5" ; #NET "overo_gpio145" LOC = "C7" ; -#NET "overo_gpio163" LOC = "D7" ; #NET "overo_gpio146" LOC = "A6" ; -#NET "overo_gpio144" LOC = "A5" ; #NET "overo_gpio147" LOC = "B6" ; -#NET "overo_gpio128" LOC = "G8" ; -#NET "overo_gpio0" LOC = "F9" ; -#NET "overo_gpio127" LOC = "C8" ; +#NET "overo_gpio163" LOC = "D7" ; +#NET "overo_gpio170" LOC = "E8" ; +#NET "overo_gpio176" LOC = "B4" ; ## Overo UART #NET "overo_txd1" LOC = "C6" ; #NET "overo_rxd1" LOC = "D6" ; +#NET "FPGA_TXD" LOC = "U1" ; +#NET "FPGA_RXD" LOC = "T6" ; + #NET "SYSEN" LOC = "C11" ; #NET "db_scl" LOC = "U4" ; @@ -82,12 +85,17 @@ NET "EM_NADV_ALE" LOC = "B15" ; #NET "db_miso_tx" LOC = "W1" ; #NET "db_mosi_tx" LOC = "R3" ; #NET "db_sen_tx" LOC = "T4" ; + +## Clock Gen #NET "cgen_miso" LOC = "U2" ; #NET "cgen_mosi" LOC = "V1" ; #NET "cgen_sclk" LOC = "R5" ; #NET "cgen_sen_b" LOC = "T1" ; -#NET "FPGA_TXD" LOC = "U1" ; -#NET "FPGA_RXD" LOC = "T6" ; +#NET "cgen_st_status" LOC = "D4" ; +#NET "cgen_st_ld" LOC = "D1" ; +#NET "cgen_st_refmon" LOC = "E1" ; +#NET "cgen_sync_b" LOC = "M1" ; +#NET "cgen_ref_sel" LOC = "J1" ; ## Debug pins NET "debug_led<2>" LOC = "T5" ; @@ -141,17 +149,7 @@ NET "debug_clk<1>" LOC = "M5" ; #NET "dip_sw<1>" LOC = "J6" ; #NET "dip_sw<0>" LOC = "J7" ; -#NET "cgen_st_status" LOC = "D4" ; -#NET "cgen_st_ld" LOC = "D1" ; -#NET "cgen_st_refmon" LOC = "E1" ; -#NET "cgen_sync_b" LOC = "M1" ; -#NET "cgen_ref_sel" LOC = "J1" ; -#NET "GND" LOC = "V19" ; -#NET "fpga_cfg_prog_b" LOC = "A2" ; -#NET "fpga_cfg_done" LOC = "AB21" ; -#NET "fpga_cfg_din" LOC = "W17" ; -#NET "fpga_cfg_cclk" LOC = "V17" ; -#NET "fpga_cfg_init_b" LOC = "W15" ; +## AD9862 Interface #NET "aux_sdi_codec" LOC = "F19" ; #NET "aux_sdo_codec" LOC = "F18" ; #NET "aux_sclk_codec" LOC = "D21" ; @@ -163,86 +161,94 @@ NET "debug_clk<1>" LOC = "M5" ; #NET "RXSYNC" LOC = "F22" ; -#NET "DB11" LOC = "E22" ; -#NET "DB10" LOC = "J19" ; -#NET "DB09" LOC = "H20" ; -#NET "DB08" LOC = "G19" ; -#NET "DB07" LOC = "F20" ; -#NET "DB06" LOC = "K16" ; -#NET "DB05" LOC = "J17" ; -#NET "DB04" LOC = "H22" ; -#NET "DB03" LOC = "G22" ; -#NET "DB02" LOC = "H17" ; -#NET "DB01" LOC = "H18" ; -#NET "DB00" LOC = "K20" ; -#NET "DA11" LOC = "J20" ; -#NET "DA10" LOC = "K19" ; -#NET "DA09" LOC = "K18" ; -#NET "DA08" LOC = "L22" ; -#NET "DA07" LOC = "K22" ; -#NET "DA06" LOC = "N22" ; -#NET "DA05" LOC = "M22" ; -#NET "DA04" LOC = "N20" ; -#NET "DA03" LOC = "N19" ; -#NET "DA02" LOC = "R22" ; -#NET "DA01" LOC = "P22" ; -#NET "DA00" LOC = "N17" ; - -#NET "TX13" LOC = "P19" ; -#NET "TX12" LOC = "R18" ; -#NET "TX11" LOC = "U20" ; -#NET "TX10" LOC = "T20" ; -#NET "TX09" LOC = "R19" ; -#NET "TX08" LOC = "R20" ; -#NET "TX07" LOC = "W22" ; -#NET "TX06" LOC = "Y22" ; -#NET "TX05" LOC = "T18" ; -#NET "TX04" LOC = "T17" ; -#NET "TX03" LOC = "W19" ; -#NET "TX02" LOC = "V20" ; -#NET "TX01" LOC = "Y21" ; -#NET "TX00" LOC = "AA22" ; +#NET "DB<11>" LOC = "E22" ; +#NET "DB<10>" LOC = "J19" ; +#NET "DB<9>" LOC = "H20" ; +#NET "DB<8>" LOC = "G19" ; +#NET "DB<7>" LOC = "F20" ; +#NET "DB<6>" LOC = "K16" ; +#NET "DB<5>" LOC = "J17" ; +#NET "DB<4>" LOC = "H22" ; +#NET "DB<3>" LOC = "G22" ; +#NET "DB<2>" LOC = "H17" ; +#NET "DB<1>" LOC = "H18" ; +#NET "DB<0>" LOC = "K20" ; +#NET "DA<11>" LOC = "J20" ; +#NET "DA<10>" LOC = "K19" ; +#NET "DA<9>" LOC = "K18" ; +#NET "DA<8>" LOC = "L22" ; +#NET "DA<7>" LOC = "K22" ; +#NET "DA<6>" LOC = "N22" ; +#NET "DA<5>" LOC = "M22" ; +#NET "DA<4>" LOC = "N20" ; +#NET "DA<3>" LOC = "N19" ; +#NET "DA<2>" LOC = "R22" ; +#NET "DA<1>" LOC = "P22" ; +#NET "DA<0>" LOC = "N17" ; + +#NET "TX<13>" LOC = "P19" ; +#NET "TX<12>" LOC = "R18" ; +#NET "TX<11>" LOC = "U20" ; +#NET "TX<10>" LOC = "T20" ; +#NET "TX<9>" LOC = "R19" ; +#NET "TX<8>" LOC = "R20" ; +#NET "TX<7>" LOC = "W22" ; +#NET "TX<6>" LOC = "Y22" ; +#NET "TX<5>" LOC = "T18" ; +#NET "TX<4>" LOC = "T17" ; +#NET "TX<3>" LOC = "W19" ; +#NET "TX<2>" LOC = "V20" ; +#NET "TX<1>" LOC = "Y21" ; +#NET "TX<0>" LOC = "AA22" ; #NET "TXSYNC" LOC = "U18" ; #NET "TXBLANK" LOC = "U19" ; #NET "PPS_IN" LOC = "M17" ; -#NET "io_tx_00" LOC = "AB20" ; -#NET "io_tx_01" LOC = "Y17" ; -#NET "io_tx_02" LOC = "Y16" ; -#NET "io_tx_03" LOC = "U16" ; -#NET "io_tx_04" LOC = "V16" ; -#NET "io_tx_05" LOC = "AB19" ; -#NET "io_tx_06" LOC = "AA19" ; -#NET "io_tx_07" LOC = "U14" ; -#NET "io_tx_08" LOC = "U15" ; -#NET "io_tx_09" LOC = "AB17" ; -#NET "io_tx_10" LOC = "AB18" ; -#NET "io_tx_11" LOC = "Y13" ; -#NET "io_tx_12" LOC = "W14" ; -#NET "io_tx_13" LOC = "U13" ; -#NET "io_tx_14" LOC = "AA15" ; -#NET "io_tx_15" LOC = "AB14" ; -#NET "io_rx_00" LOC = "Y8" ; -#NET "io_rx_01" LOC = "Y9" ; -#NET "io_rx_02" LOC = "V7" ; -#NET "io_rx_03" LOC = "U8" ; -#NET "io_rx_04" LOC = "V10" ; -#NET "io_rx_05" LOC = "U9" ; -#NET "io_rx_06" LOC = "AB7" ; -#NET "io_rx_07" LOC = "AA8" ; -#NET "io_rx_08" LOC = "W8" ; -#NET "io_rx_09" LOC = "V8" ; -#NET "io_rx_10" LOC = "AB5" ; -#NET "io_rx_11" LOC = "AB6" ; -#NET "io_rx_12" LOC = "AB4" ; -#NET "io_rx_13" LOC = "AA4" ; -#NET "io_rx_14" LOC = "W5" ; -#NET "io_rx_15" LOC = "Y4" ; +#NET "io_tx<0>" LOC = "AB20" ; +#NET "io_tx<1>" LOC = "Y17" ; +#NET "io_tx<2>" LOC = "Y16" ; +#NET "io_tx<3>" LOC = "U16" ; +#NET "io_tx<4>" LOC = "V16" ; +#NET "io_tx<5>" LOC = "AB19" ; +#NET "io_tx<6>" LOC = "AA19" ; +#NET "io_tx<7>" LOC = "U14" ; +#NET "io_tx<8>" LOC = "U15" ; +#NET "io_tx<9>" LOC = "AB17" ; +#NET "io_tx<10>" LOC = "AB18" ; +#NET "io_tx<11>" LOC = "Y13" ; +#NET "io_tx<12>" LOC = "W14" ; +#NET "io_tx<13>" LOC = "U13" ; +#NET "io_tx<14>" LOC = "AA15" ; +#NET "io_tx<15>" LOC = "AB14" ; + +#NET "io_rx<0>" LOC = "Y8" ; +#NET "io_rx<1>" LOC = "Y9" ; +#NET "io_rx<2>" LOC = "V7" ; +#NET "io_rx<3>" LOC = "U8" ; +#NET "io_rx<4>" LOC = "V10" ; +#NET "io_rx<5>" LOC = "U9" ; +#NET "io_rx<6>" LOC = "AB7" ; +#NET "io_rx<7>" LOC = "AA8" ; +#NET "io_rx<8>" LOC = "W8" ; +#NET "io_rx<9>" LOC = "V8" ; +#NET "io_rx<10>" LOC = "AB5" ; +#NET "io_rx<11>" LOC = "AB6" ; +#NET "io_rx<12>" LOC = "AB4" ; +#NET "io_rx<13>" LOC = "AA4" ; +#NET "io_rx<14>" LOC = "W5" ; +#NET "io_rx<15>" LOC = "Y4" ; #NET "CLKOUT2_CODEC" LOC = "U12" ; #NET "CLKOUT1_CODEC" LOC = "V12" ; +## FPGA Config Pins +#NET "fpga_cfg_prog_b" LOC = "A2" ; +#NET "fpga_cfg_done" LOC = "AB21" ; +#NET "fpga_cfg_din" LOC = "W17" ; +#NET "fpga_cfg_cclk" LOC = "V17" ; +#NET "fpga_cfg_init_b" LOC = "W15" ; + ## Unnamed, need to figure out what they do #NET "unnamed_net37" LOC = "B1" ; #NET "unnamed_net36" LOC = "B22" ; @@ -252,3 +258,5 @@ NET "debug_clk<1>" LOC = "M5" ; #NET "unnamed_net44" LOC = "V6" ; #NET "unnamed_net43" LOC = "AA3" ; #NET "unnamed_net42" LOC = "AB3" ; + +#NET "GND" LOC = "V19" ; -- cgit v1.2.3 From 034eeacfe8d35b0e9733dd9183f1a9dbed78f347 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 16 Feb 2010 10:24:18 -0800 Subject: basic read support for the GPMC, responds with 16'hBEEF --- usrp2/top/safe_u1e/safe_u1e.v | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/usrp2/top/safe_u1e/safe_u1e.v b/usrp2/top/safe_u1e/safe_u1e.v index 3f16d941c..ddd203cf9 100644 --- a/usrp2/top/safe_u1e/safe_u1e.v +++ b/usrp2/top/safe_u1e/safe_u1e.v @@ -7,7 +7,7 @@ module safe_u1e output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, // GPMC - input EM_CLK, input [15:0] EM_D, input [10:1] EM_A, + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input EM_WAIT0, input EM_NCS4, input EM_NWP, input EM_NWE, input EM_NOE, input EM_NADV_ALE ); @@ -27,5 +27,11 @@ module safe_u1e assign debug_clk = { EM_CLK, clk_fpga }; assign debug = { { EM_WAIT0, EM_NADV_ALE, EM_NWP, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, { EM_D } }; - + + wire EM_output_enable = (~EM_NOE & ~EM_NCS4); + wire [15:0] EM_D_out = 16'hBEEF; + wire [15:0] EM_D_in = EM_D; + + assign EM_D = EM_output_enable ? EM_D_out : 16'bz; + endmodule // safe_u2plus -- cgit v1.2.3 From 8e76952016272c9898776b6beb7a69f476d4707e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 16 Feb 2010 16:21:00 -0800 Subject: block ram interface to GPMC --- usrp2/top/safe_u1e/safe_u1e.v | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/usrp2/top/safe_u1e/safe_u1e.v b/usrp2/top/safe_u1e/safe_u1e.v index ddd203cf9..dee9c6067 100644 --- a/usrp2/top/safe_u1e/safe_u1e.v +++ b/usrp2/top/safe_u1e/safe_u1e.v @@ -29,9 +29,13 @@ module safe_u1e { EM_D } }; wire EM_output_enable = (~EM_NOE & ~EM_NCS4); - wire [15:0] EM_D_out = 16'hBEEF; - wire [15:0] EM_D_in = EM_D; + wire [15:0] EM_D_out; assign EM_D = EM_output_enable ? EM_D_out : 16'bz; + + ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port + (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_out), + .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob()); + endmodule // safe_u2plus -- cgit v1.2.3 From c1ddc5c082c053eaa46c8bc87064d3e3e56b0d9e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 16 Feb 2010 16:29:44 -0800 Subject: copied over from safe_u1e --- usrp2/top/u1e/.gitignore | 4 + usrp2/top/u1e/Makefile | 246 ++++++++++++++++++++++++++++++++++++++++++++ usrp2/top/u1e/u1e.ucf | 262 +++++++++++++++++++++++++++++++++++++++++++++++ usrp2/top/u1e/u1e.v | 41 ++++++++ 4 files changed, 553 insertions(+) create mode 100644 usrp2/top/u1e/.gitignore create mode 100644 usrp2/top/u1e/Makefile create mode 100644 usrp2/top/u1e/u1e.ucf create mode 100644 usrp2/top/u1e/u1e.v diff --git a/usrp2/top/u1e/.gitignore b/usrp2/top/u1e/.gitignore new file mode 100644 index 000000000..f8b57ea21 --- /dev/null +++ b/usrp2/top/u1e/.gitignore @@ -0,0 +1,4 @@ +*~ +build +*.log +*.cmd diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile new file mode 100644 index 000000000..e9c101226 --- /dev/null +++ b/usrp2/top/u1e/Makefile @@ -0,0 +1,246 @@ +# +# Copyright 2008 Ettus Research LLC +# +# This file is part of GNU Radio +# +# GNU Radio is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GNU Radio is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GNU Radio; see the file COPYING. If not, write to +# the Free Software Foundation, Inc., 51 Franklin Street, +# Boston, MA 02110-1301, USA. +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := u1e +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +control_lib/CRC16_D16.v \ +control_lib/atr_controller.v \ +control_lib/bin2gray.v \ +control_lib/dcache.v \ +control_lib/decoder_3_8.v \ +control_lib/dpram32.v \ +control_lib/gray2bin.v \ +control_lib/gray_send.v \ +control_lib/icache.v \ +control_lib/mux4.v \ +control_lib/mux8.v \ +control_lib/nsgpio.v \ +control_lib/ram_2port.v \ +control_lib/ram_harv_cache.v \ +control_lib/ram_loader.v \ +control_lib/setting_reg.v \ +control_lib/settings_bus.v \ +control_lib/srl.v \ +control_lib/system_control.v \ +control_lib/wb_1master.v \ +control_lib/wb_readback_mux.v \ +control_lib/simple_uart.v \ +control_lib/simple_uart_tx.v \ +control_lib/simple_uart_rx.v \ +control_lib/oneshot_2clk.v \ +control_lib/sd_spi.v \ +control_lib/sd_spi_wb.v \ +control_lib/wb_bridge_16_32.v \ +control_lib/reset_sync.v \ +simple_gemac/simple_gemac_wrapper.v \ +simple_gemac/simple_gemac.v \ +simple_gemac/simple_gemac_wb.v \ +simple_gemac/simple_gemac_tx.v \ +simple_gemac/simple_gemac_rx.v \ +simple_gemac/crc.v \ +simple_gemac/delay_line.v \ +simple_gemac/flow_ctrl_tx.v \ +simple_gemac/flow_ctrl_rx.v \ +simple_gemac/address_filter.v \ +simple_gemac/ll8_to_txmac.v \ +simple_gemac/rxmac_to_ll8.v \ +simple_gemac/miim/eth_miim.v \ +simple_gemac/miim/eth_clockgen.v \ +simple_gemac/miim/eth_outputcontrol.v \ +simple_gemac/miim/eth_shiftreg.v \ +control_lib/newfifo/buffer_int.v \ +control_lib/newfifo/buffer_pool.v \ +control_lib/newfifo/fifo_2clock.v \ +control_lib/newfifo/fifo_2clock_cascade.v \ +control_lib/newfifo/ll8_shortfifo.v \ +control_lib/newfifo/ll8_to_fifo36.v \ +control_lib/newfifo/fifo_short.v \ +control_lib/newfifo/fifo_long.v \ +control_lib/newfifo/fifo_cascade.v \ +control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/longfifo.v \ +control_lib/shortfifo.v \ +control_lib/medfifo.v \ +coregen/fifo_xlnx_2Kx36_2clk.v \ +coregen/fifo_xlnx_2Kx36_2clk.xco \ +coregen/fifo_xlnx_512x36_2clk.v \ +coregen/fifo_xlnx_512x36_2clk.xco \ +coregen/fifo_xlnx_64x36_2clk.v \ +coregen/fifo_xlnx_64x36_2clk.xco \ +extram/wb_zbt16_b.v \ +opencores/8b10b/decode_8b10b.v \ +opencores/8b10b/encode_8b10b.v \ +opencores/aemb/rtl/verilog/aeMB_bpcu.v \ +opencores/aemb/rtl/verilog/aeMB_core_BE.v \ +opencores/aemb/rtl/verilog/aeMB_ctrl.v \ +opencores/aemb/rtl/verilog/aeMB_edk32.v \ +opencores/aemb/rtl/verilog/aeMB_ibuf.v \ +opencores/aemb/rtl/verilog/aeMB_regf.v \ +opencores/aemb/rtl/verilog/aeMB_xecu.v \ +opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ +opencores/i2c/rtl/verilog/i2c_master_defines.v \ +opencores/i2c/rtl/verilog/i2c_master_top.v \ +opencores/i2c/rtl/verilog/timescale.v \ +opencores/simple_pic/rtl/simple_pic.v \ +opencores/spi/rtl/verilog/spi_clgen.v \ +opencores/spi/rtl/verilog/spi_defines.v \ +opencores/spi/rtl/verilog/spi_shift.v \ +opencores/spi/rtl/verilog/spi_top.v \ +opencores/spi/rtl/verilog/timescale.v \ +sdr_lib/acc.v \ +sdr_lib/add2.v \ +sdr_lib/add2_and_round.v \ +sdr_lib/add2_and_round_reg.v \ +sdr_lib/add2_reg.v \ +sdr_lib/cic_dec_shifter.v \ +sdr_lib/cic_decim.v \ +sdr_lib/cic_int_shifter.v \ +sdr_lib/cic_interp.v \ +sdr_lib/cic_strober.v \ +sdr_lib/clip.v \ +sdr_lib/clip_reg.v \ +sdr_lib/cordic.v \ +sdr_lib/cordic_z24.v \ +sdr_lib/cordic_stage.v \ +sdr_lib/dsp_core_rx.v \ +sdr_lib/dsp_core_tx.v \ +sdr_lib/hb_dec.v \ +sdr_lib/hb_interp.v \ +sdr_lib/round.v \ +sdr_lib/round_reg.v \ +sdr_lib/rx_control.v \ +sdr_lib/rx_dcoffset.v \ +sdr_lib/sign_extend.v \ +sdr_lib/small_hb_dec.v \ +sdr_lib/small_hb_int.v \ +sdr_lib/tx_control.v \ +serdes/serdes.v \ +serdes/serdes_fc_rx.v \ +serdes/serdes_fc_tx.v \ +serdes/serdes_rx.v \ +serdes/serdes_tx.v \ +timing/time_receiver.v \ +timing/time_sender.v \ +timing/time_sync.v \ +timing/timer.v \ +top/u2_core/u2_core.v \ +top/u1e/u1e.ucf \ +top/u1e/u1e.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +clean: + rm -rf $(BUILD_DIR) + + diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf new file mode 100644 index 000000000..cb6d6372e --- /dev/null +++ b/usrp2/top/u1e/u1e.ucf @@ -0,0 +1,262 @@ + +NET "CLK_FPGA_P" LOC = "Y11" ; +NET "CLK_FPGA_N" LOC = "Y10" ; + +## GPMC +NET "EM_CLK" LOC = "F11" ; + +NET "EM_D<15>" LOC = "D13" ; +NET "EM_D<14>" LOC = "D15" ; +NET "EM_D<13>" LOC = "C16" ; +NET "EM_D<12>" LOC = "B20" ; +NET "EM_D<11>" LOC = "A19" ; +NET "EM_D<10>" LOC = "A17" ; +NET "EM_D<9>" LOC = "E15" ; +NET "EM_D<8>" LOC = "F15" ; +NET "EM_D<7>" LOC = "E16" ; +NET "EM_D<6>" LOC = "F16" ; +NET "EM_D<5>" LOC = "B17" ; +NET "EM_D<4>" LOC = "C17" ; +NET "EM_D<3>" LOC = "B19" ; +NET "EM_D<2>" LOC = "D19" ; +NET "EM_D<1>" LOC = "C19" ; +NET "EM_D<0>" LOC = "A20" ; + +NET "EM_A<10>" LOC = "C14" ; +NET "EM_A<9>" LOC = "C10" ; +NET "EM_A<8>" LOC = "C5" ; +NET "EM_A<7>" LOC = "A18" ; +NET "EM_A<6>" LOC = "A15" ; +NET "EM_A<5>" LOC = "A12" ; +NET "EM_A<4>" LOC = "A10" ; +NET "EM_A<3>" LOC = "E7" ; +NET "EM_A<2>" LOC = "A7" ; +NET "EM_A<1>" LOC = "C15" ; + +#NET "EM_NCS6" LOC = "E17" ; +#NET "EM_NCS5" LOC = "E10" ; +NET "EM_NCS4" LOC = "E6" ; +#NET "EM_NCS1" LOC = "D18" ; +#NET "EM_NCS0" LOC = "D17" ; + +NET "EM_WAIT0" LOC = "F14" ; +#NET "EM_NBE1" LOC = "D14" ; +#NET "EM_NBE0" LOC = "A13" ; +NET "EM_NWP" LOC = "F13" ; +NET "EM_NWE" LOC = "B13" ; +NET "EM_NOE" LOC = "A14" ; +NET "EM_NADV_ALE" LOC = "B15" ; + + +## Overo GPIO +#NET "overo_gpio0" LOC = "F9" ; +#NET "overo_gpio14" LOC = "C4" ; +#NET "overo_gpio21" LOC = "D5" ; +#NET "overo_gpio22" LOC = "A3" ; +#NET "overo_gpio23" LOC = "B3" ; +#NET "overo_gpio64" LOC = "A4" ; +#NET "overo_gpio65" LOC = "F8" ; +#NET "overo_gpio127" LOC = "C8" ; +#NET "overo_gpio128" LOC = "G8" ; +#NET "overo_gpio144" LOC = "A5" ; +#NET "overo_gpio145" LOC = "C7" ; +#NET "overo_gpio146" LOC = "A6" ; +#NET "overo_gpio147" LOC = "B6" ; +#NET "overo_gpio163" LOC = "D7" ; +#NET "overo_gpio170" LOC = "E8" ; +#NET "overo_gpio176" LOC = "B4" ; + +## Overo UART +#NET "overo_txd1" LOC = "C6" ; +#NET "overo_rxd1" LOC = "D6" ; + +#NET "FPGA_TXD" LOC = "U1" ; +#NET "FPGA_RXD" LOC = "T6" ; + +#NET "SYSEN" LOC = "C11" ; + +#NET "db_scl" LOC = "U4" ; +#NET "db_sda" LOC = "U5" ; +#NET "db_sclk_rx" LOC = "W3" ; +#NET "db_miso_rx" LOC = "W2" ; +#NET "db_mosi_rx" LOC = "V4" ; +#NET "db_sen_rx" LOC = "V3" ; +#NET "db_sclk_tx" LOC = "Y1" ; +#NET "db_miso_tx" LOC = "W1" ; +#NET "db_mosi_tx" LOC = "R3" ; +#NET "db_sen_tx" LOC = "T4" ; + +## Clock Gen +#NET "cgen_miso" LOC = "U2" ; +#NET "cgen_mosi" LOC = "V1" ; +#NET "cgen_sclk" LOC = "R5" ; +#NET "cgen_sen_b" LOC = "T1" ; +#NET "cgen_st_status" LOC = "D4" ; +#NET "cgen_st_ld" LOC = "D1" ; +#NET "cgen_st_refmon" LOC = "E1" ; +#NET "cgen_sync_b" LOC = "M1" ; +#NET "cgen_ref_sel" LOC = "J1" ; + +## Debug pins +NET "debug_led<2>" LOC = "T5" ; +NET "debug_led<1>" LOC = "R2" ; +NET "debug_led<0>" LOC = "R1" ; +NET "debug<0>" LOC = "P6" ; +NET "debug<1>" LOC = "R6" ; +NET "debug<2>" LOC = "P1" ; +NET "debug<3>" LOC = "P2" ; +NET "debug<4>" LOC = "N6" ; +NET "debug<5>" LOC = "N5" ; +NET "debug<6>" LOC = "N1" ; +NET "debug<7>" LOC = "K2" ; +NET "debug<8>" LOC = "K3" ; +NET "debug<9>" LOC = "K6" ; +NET "debug<10>" LOC = "L5" ; +NET "debug<11>" LOC = "H2" ; +NET "debug<12>" LOC = "K4" ; +NET "debug<13>" LOC = "K5" ; +NET "debug<14>" LOC = "G1" ; +NET "debug<15>" LOC = "H1" ; +NET "debug<16>" LOC = "H5" ; +NET "debug<17>" LOC = "H6" ; +NET "debug<18>" LOC = "E3" ; +NET "debug<19>" LOC = "E4" ; +NET "debug<20>" LOC = "G5" ; +NET "debug<21>" LOC = "G6" ; +NET "debug<22>" LOC = "F2" ; +NET "debug<23>" LOC = "F1" ; +NET "debug<24>" LOC = "H3" ; +NET "debug<25>" LOC = "H4" ; +NET "debug<26>" LOC = "F4" ; +NET "debug<27>" LOC = "F5" ; +NET "debug<28>" LOC = "C2" ; +NET "debug<29>" LOC = "C1" ; +NET "debug<30>" LOC = "F3" ; +NET "debug<31>" LOC = "G3" ; +NET "debug_clk<0>" LOC = "L6" ; +NET "debug_clk<1>" LOC = "M5" ; + +#NET "debug_pb<2>" LOC = "Y2" ; +#NET "debug_pb<1>" LOC = "AA1" ; +#NET "debug_pb<0>" LOC = "N3" ; + +#NET "dip_sw<7>" LOC = "T3" ; +#NET "dip_sw<6>" LOC = "U3" ; +#NET "dip_sw<5>" LOC = "M3" ; +#NET "dip_sw<4>" LOC = "N4" ; +#NET "dip_sw<3>" LOC = "J3" ; +#NET "dip_sw<2>" LOC = "J4" ; +#NET "dip_sw<1>" LOC = "J6" ; +#NET "dip_sw<0>" LOC = "J7" ; + +## AD9862 Interface +#NET "aux_sdi_codec" LOC = "F19" ; +#NET "aux_sdo_codec" LOC = "F18" ; +#NET "aux_sclk_codec" LOC = "D21" ; +#NET "reset_codec" LOC = "D22" ; +#NET "sen_codec" LOC = "D20" ; +#NET "mosi_codec" LOC = "E19" ; +#NET "miso_codec" LOC = "F21" ; +#NET "sclk_codec" LOC = "E20" ; + +#NET "RXSYNC" LOC = "F22" ; + +#NET "DB<11>" LOC = "E22" ; +#NET "DB<10>" LOC = "J19" ; +#NET "DB<9>" LOC = "H20" ; +#NET "DB<8>" LOC = "G19" ; +#NET "DB<7>" LOC = "F20" ; +#NET "DB<6>" LOC = "K16" ; +#NET "DB<5>" LOC = "J17" ; +#NET "DB<4>" LOC = "H22" ; +#NET "DB<3>" LOC = "G22" ; +#NET "DB<2>" LOC = "H17" ; +#NET "DB<1>" LOC = "H18" ; +#NET "DB<0>" LOC = "K20" ; +#NET "DA<11>" LOC = "J20" ; +#NET "DA<10>" LOC = "K19" ; +#NET "DA<9>" LOC = "K18" ; +#NET "DA<8>" LOC = "L22" ; +#NET "DA<7>" LOC = "K22" ; +#NET "DA<6>" LOC = "N22" ; +#NET "DA<5>" LOC = "M22" ; +#NET "DA<4>" LOC = "N20" ; +#NET "DA<3>" LOC = "N19" ; +#NET "DA<2>" LOC = "R22" ; +#NET "DA<1>" LOC = "P22" ; +#NET "DA<0>" LOC = "N17" ; + +#NET "TX<13>" LOC = "P19" ; +#NET "TX<12>" LOC = "R18" ; +#NET "TX<11>" LOC = "U20" ; +#NET "TX<10>" LOC = "T20" ; +#NET "TX<9>" LOC = "R19" ; +#NET "TX<8>" LOC = "R20" ; +#NET "TX<7>" LOC = "W22" ; +#NET "TX<6>" LOC = "Y22" ; +#NET "TX<5>" LOC = "T18" ; +#NET "TX<4>" LOC = "T17" ; +#NET "TX<3>" LOC = "W19" ; +#NET "TX<2>" LOC = "V20" ; +#NET "TX<1>" LOC = "Y21" ; +#NET "TX<0>" LOC = "AA22" ; +#NET "TXSYNC" LOC = "U18" ; +#NET "TXBLANK" LOC = "U19" ; + +#NET "PPS_IN" LOC = "M17" ; + +#NET "io_tx<0>" LOC = "AB20" ; +#NET "io_tx<1>" LOC = "Y17" ; +#NET "io_tx<2>" LOC = "Y16" ; +#NET "io_tx<3>" LOC = "U16" ; +#NET "io_tx<4>" LOC = "V16" ; +#NET "io_tx<5>" LOC = "AB19" ; +#NET "io_tx<6>" LOC = "AA19" ; +#NET "io_tx<7>" LOC = "U14" ; +#NET "io_tx<8>" LOC = "U15" ; +#NET "io_tx<9>" LOC = "AB17" ; +#NET "io_tx<10>" LOC = "AB18" ; +#NET "io_tx<11>" LOC = "Y13" ; +#NET "io_tx<12>" LOC = "W14" ; +#NET "io_tx<13>" LOC = "U13" ; +#NET "io_tx<14>" LOC = "AA15" ; +#NET "io_tx<15>" LOC = "AB14" ; + +#NET "io_rx<0>" LOC = "Y8" ; +#NET "io_rx<1>" LOC = "Y9" ; +#NET "io_rx<2>" LOC = "V7" ; +#NET "io_rx<3>" LOC = "U8" ; +#NET "io_rx<4>" LOC = "V10" ; +#NET "io_rx<5>" LOC = "U9" ; +#NET "io_rx<6>" LOC = "AB7" ; +#NET "io_rx<7>" LOC = "AA8" ; +#NET "io_rx<8>" LOC = "W8" ; +#NET "io_rx<9>" LOC = "V8" ; +#NET "io_rx<10>" LOC = "AB5" ; +#NET "io_rx<11>" LOC = "AB6" ; +#NET "io_rx<12>" LOC = "AB4" ; +#NET "io_rx<13>" LOC = "AA4" ; +#NET "io_rx<14>" LOC = "W5" ; +#NET "io_rx<15>" LOC = "Y4" ; + +#NET "CLKOUT2_CODEC" LOC = "U12" ; +#NET "CLKOUT1_CODEC" LOC = "V12" ; + +## FPGA Config Pins +#NET "fpga_cfg_prog_b" LOC = "A2" ; +#NET "fpga_cfg_done" LOC = "AB21" ; +#NET "fpga_cfg_din" LOC = "W17" ; +#NET "fpga_cfg_cclk" LOC = "V17" ; +#NET "fpga_cfg_init_b" LOC = "W15" ; + +## Unnamed, need to figure out what they do +#NET "unnamed_net37" LOC = "B1" ; +#NET "unnamed_net36" LOC = "B22" ; +#NET "unnamed_net35" LOC = "D2" ; +#NET "unnamed_net34" LOC = "A21" ; +#NET "unnamed_net45" LOC = "F7" ; +#NET "unnamed_net44" LOC = "V6" ; +#NET "unnamed_net43" LOC = "AA3" ; +#NET "unnamed_net42" LOC = "AB3" ; + +#NET "GND" LOC = "V19" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v new file mode 100644 index 000000000..e28a6a582 --- /dev/null +++ b/usrp2/top/u1e/u1e.v @@ -0,0 +1,41 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u1e + ( + input CLK_FPGA_P, input CLK_FPGA_N, // Diff + output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + + // GPMC + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, + input EM_WAIT0, input EM_NCS4, input EM_NWP, input EM_NWE, input EM_NOE, input EM_NADV_ALE + ); + + // FPGA-specific pins connections + wire clk_fpga; + + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) + clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + + // Debug circuitry + reg [31:0] ctr; + always @(posedge clk_fpga) + ctr <= ctr + 1; + + + assign debug_led = ctr[27:25]; + assign debug_clk = { EM_CLK, clk_fpga }; + assign debug = { { EM_WAIT0, EM_NADV_ALE, EM_NWP, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, + { EM_D } }; + + wire EM_output_enable = (~EM_NOE & ~EM_NCS4); + wire [15:0] EM_D_out; + + assign EM_D = EM_output_enable ? EM_D_out : 16'bz; + + ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port + (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_out), + .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob()); + + +endmodule // u2plus -- cgit v1.2.3 From b115e4d7661d64c6d20f0421908622b56a91e950 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 16 Feb 2010 18:47:22 -0800 Subject: first cut at gpmc <-> wb bridge, split u1e into core, top, and tb --- .gitignore | 1 + usrp2/gpmc/gpmc.v | 66 ++++++++++++++++++++++++++++++++++++++++++++++++ usrp2/top/u1e/Makefile | 3 ++- usrp2/top/u1e/tb_u1e.v | 25 ++++++++++++++++++ usrp2/top/u1e/u1e.ucf | 14 +++++----- usrp2/top/u1e/u1e.v | 33 ++++++------------------ usrp2/top/u1e/u1e_core.v | 52 ++++++++++++++++++++++++++++++++++++++ 7 files changed, 160 insertions(+), 34 deletions(-) create mode 100644 .gitignore create mode 100644 usrp2/gpmc/gpmc.v create mode 100644 usrp2/top/u1e/tb_u1e.v create mode 100644 usrp2/top/u1e/u1e_core.v diff --git a/.gitignore b/.gitignore new file mode 100644 index 000000000..b25c15b81 --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +*~ diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v new file mode 100644 index 000000000..96ee139fd --- /dev/null +++ b/usrp2/gpmc/gpmc.v @@ -0,0 +1,66 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module gpmc + (input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + + input wb_clk, input wb_rst, + output reg [10:0] wb_adr_o, output reg [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output reg [1:0] wb_sel_o, output wb_cyc_o, output reg wb_stb_o, output reg wb_we_o, input wb_ack_i + ); + + wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); + wire [15:0] EM_D_ram; + reg [15:0] EM_D_wb; + + assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_ram : EM_D_wb; + + // CS4 is RAM_2PORT for high-speed data + ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port + (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_ram), + .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob()); + + // CS6 is Control, Wishbone bus bridge (wb master) + // Sync version + reg [1:0] cs_del, we_del, oe_del; + + // Synchronize the async control signals + always @(posedge wb_clk) + begin + cs_del <= { cs_del[0], EM_NCS6 }; + we_del <= { we_del[0], EM_NWE }; + oe_del <= { oe_del[0], EM_NOE }; + end + + always @(posedge wb_clk) + if(cs_del == 2'b10) // Falling Edge + wb_adr_o <= { EM_A, 1'b0 }; + + always @(posedge wb_clk) + if(we_del == 2'b10) // Falling Edge + begin + wb_dat_mosi <= EM_D; + wb_sel_o <= ~EM_NBE; + end + + always @(posedge wb_clk) + if(wb_ack_i) + EM_D_wb <= wb_dat_miso; + + // stb, oe_del, we_del + assign wb_cyc_o = wb_stb_o; + + always @(posedge wb_clk) + if( ~cs_del[0] & (we_del == 2'b10) ) + wb_we_o <= 1; + else if(wb_ack_i) // Turn off we when done. Could also use we_del[0], others... + wb_we_o <= 0; + + always @(posedge wb_clk) + if( ~cs_del[0] & ((we_del == 2'b10) | (oe_del == 2'b10))) + wb_stb_o <= 1; + else if(wb_ack_i) + wb_stb_o <= 0; + +endmodule // gpmc diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index e9c101226..cdbdf995e 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -174,7 +174,8 @@ timing/time_receiver.v \ timing/time_sender.v \ timing/time_sync.v \ timing/timer.v \ -top/u2_core/u2_core.v \ +gpmc/gpmc.v \ +top/u1e/u1e_core.v \ top/u1e/u1e.ucf \ top/u1e/u1e.v diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v new file mode 100644 index 000000000..6e0c60e17 --- /dev/null +++ b/usrp2/top/u1e/tb_u1e.v @@ -0,0 +1,25 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module tb_u1e(); + + wire [2:0] debug_led; + wire [31:0] debug; + wire [1:0] debug_clk; + + + // GPMC + wire EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE; + wire [15:0] EM_D; + wire [10:1] EM_A; + wire [1:0] EM_NBE; + + reg clk_fpga = 0; + always #100 clk_fpga = ~clk_fpga; + + u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); + +endmodule // u1e diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index cb6d6372e..3b524a6ea 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -3,8 +3,6 @@ NET "CLK_FPGA_P" LOC = "Y11" ; NET "CLK_FPGA_N" LOC = "Y10" ; ## GPMC -NET "EM_CLK" LOC = "F11" ; - NET "EM_D<15>" LOC = "D13" ; NET "EM_D<14>" LOC = "D15" ; NET "EM_D<13>" LOC = "C16" ; @@ -33,20 +31,20 @@ NET "EM_A<3>" LOC = "E7" ; NET "EM_A<2>" LOC = "A7" ; NET "EM_A<1>" LOC = "C15" ; -#NET "EM_NCS6" LOC = "E17" ; +NET "EM_NCS6" LOC = "E17" ; #NET "EM_NCS5" LOC = "E10" ; NET "EM_NCS4" LOC = "E6" ; #NET "EM_NCS1" LOC = "D18" ; #NET "EM_NCS0" LOC = "D17" ; +NET "EM_CLK" LOC = "F11" ; NET "EM_WAIT0" LOC = "F14" ; -#NET "EM_NBE1" LOC = "D14" ; -#NET "EM_NBE0" LOC = "A13" ; -NET "EM_NWP" LOC = "F13" ; +NET "EM_NBE<1>" LOC = "D14" ; +NET "EM_NBE<0>" LOC = "A13" ; NET "EM_NWE" LOC = "B13" ; NET "EM_NOE" LOC = "A14" ; -NET "EM_NADV_ALE" LOC = "B15" ; - +#NET "EM_NADV_ALE" LOC = "B15" ; +#NET "EM_NWP" LOC = "F13" ; ## Overo GPIO #NET "overo_gpio0" LOC = "F9" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index e28a6a582..8832d6e11 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -2,13 +2,12 @@ ////////////////////////////////////////////////////////////////////////////////// module u1e - ( - input CLK_FPGA_P, input CLK_FPGA_N, // Diff + (input CLK_FPGA_P, input CLK_FPGA_N, // Diff output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, // GPMC - input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, - input EM_WAIT0, input EM_NCS4, input EM_NWP, input EM_NWE, input EM_NOE, input EM_NADV_ALE + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE ); // FPGA-specific pins connections @@ -17,25 +16,9 @@ module u1e IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - // Debug circuitry - reg [31:0] ctr; - always @(posedge clk_fpga) - ctr <= ctr + 1; - - - assign debug_led = ctr[27:25]; - assign debug_clk = { EM_CLK, clk_fpga }; - assign debug = { { EM_WAIT0, EM_NADV_ALE, EM_NWP, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, - { EM_D } }; - - wire EM_output_enable = (~EM_NOE & ~EM_NCS4); - wire [15:0] EM_D_out; - - assign EM_D = EM_output_enable ? EM_D_out : 16'bz; - - ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port - (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_out), - .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob()); + u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); - -endmodule // u2plus +endmodule // u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v new file mode 100644 index 000000000..2481549b2 --- /dev/null +++ b/usrp2/top/u1e/u1e_core.v @@ -0,0 +1,52 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u1e_core + (input clk_fpga, output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + + // GPMC + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE + ); + + // Debug circuitry + reg [31:0] ctr; + always @(posedge clk_fpga) + ctr <= ctr + 1; + + assign debug_led = ctr[27:25]; + assign debug_clk = { EM_CLK, clk_fpga }; + assign debug = { { 1'b0, EM_WAIT0, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, + { EM_D } }; + + wire wb_clk, wb_rst; + wire wb_cyc, wb_stb, wb_we, wb_ack; + wire [1:0] wb_sel; + wire [10:0] wb_adr; + wire [15:0] wb_dat_mosi, wb_dat_miso; + + gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), + .EM_NOE(EM_NOE), + + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(wb_adr), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), + .wb_sel_o(wb_sel), .wb_cyc_o(wb_cyc), .wb_stb_o(wb_stb), .wb_we_o(wb_we), + .wb_ack_i(wb_ack)); + + assign wb_clk = clk_fpga; + reg [15:0] reg_fast, reg_slow; + + localparam [10:0] WB_ADR_REG_FAST = 36; + localparam [10:0] WB_ADR_REG_SLOW = 38; + + always @(posedge wb_clk) + if(wb_cyc & wb_stb & wb_we & (wb_adr == WB_ADR_REG_FAST)) + reg_fast <= wb_dat_mosi; + + assign wb_dat_miso = (wb_adr == WB_ADR_REG_FAST) ? reg_fast : 16'bx; + + assign wb_ack = wb_stb & wb_cyc; + + +endmodule // u2plus -- cgit v1.2.3 From d4649caee02a1c76802dc4f8d7d76bb31b14ce09 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 16 Feb 2010 22:49:02 -0800 Subject: wishbone bridge now with minimal functionality. Need to check timing and handle wait states. --- usrp2/gpmc/gpmc.v | 4 +-- usrp2/models/gpmc_model.v | 70 +++++++++++++++++++++++++++++++++++++++++++++++ usrp2/top/u1e/.gitignore | 2 ++ usrp2/top/u1e/README | 4 +++ usrp2/top/u1e/cmdfile | 19 +++++++++++++ usrp2/top/u1e/make.sim | 7 +++++ usrp2/top/u1e/tb_u1e.v | 17 +++++++++--- usrp2/top/u1e/u1e_core.v | 9 +++--- 8 files changed, 121 insertions(+), 11 deletions(-) create mode 100644 usrp2/models/gpmc_model.v create mode 100644 usrp2/top/u1e/README create mode 100644 usrp2/top/u1e/cmdfile create mode 100644 usrp2/top/u1e/make.sim diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v index 96ee139fd..1963af6e6 100644 --- a/usrp2/gpmc/gpmc.v +++ b/usrp2/gpmc/gpmc.v @@ -18,8 +18,8 @@ module gpmc // CS4 is RAM_2PORT for high-speed data ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port - (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_ram), - .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob()); + (.clka(wb_clk), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_ram), + .clkb(wb_clk), .enb(0), .web(0), .addrb(0), .dib(0), .dob()); // CS6 is Control, Wishbone bus bridge (wb master) // Sync version diff --git a/usrp2/models/gpmc_model.v b/usrp2/models/gpmc_model.v new file mode 100644 index 000000000..ce3acaacf --- /dev/null +++ b/usrp2/models/gpmc_model.v @@ -0,0 +1,70 @@ + + +module gpmc_model + (output EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE, + output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, + output reg EM_NWE, output reg EM_NOE ); + + assign EM_CLK = 0; + reg [15:0] EM_D_int; + assign EM_D = EM_D_int; + + initial + begin + EM_A <= 10'bz; + EM_NBE <= 2'b11; + EM_NWE <= 1; + EM_NOE <= 1; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + EM_D_int <= 16'bz; + EM_WAIT0 <= 0; // FIXME this is actually an input + end + + task GPMC_Write; + input [10:0] addr; + input [15:0] data; + begin + #2; + EM_A <= addr[10:1]; + EM_D_int <= data; + #4; + EM_NCS6 <= 0; + #5; + EM_NWE <= 0; + #41; + EM_NWE <= 1; + EM_NCS6 <= 1; + EM_A <= 10'bz; + EM_D_int <= 16'bz; + end + endtask // GPMC_Write + + task GPMC_Read; + input [10:0] addr; + begin + #2; + EM_A <= addr[10:1]; + #4; + EM_NCS6 <= 0; + #5; + EM_NOE <= 0; + #41; + EM_NOE <= 1; + EM_NCS6 <= 1; + EM_A <= 10'bz; + $display("Data Read from GPMC: %X",EM_D); + end + endtask // GPMC_Read + + initial + begin + #1000; + GPMC_Write(36,16'hBEEF); + #1000; + GPMC_Read(36); + #1000; + $finish; + end + +endmodule // gpmc_model diff --git a/usrp2/top/u1e/.gitignore b/usrp2/top/u1e/.gitignore index f8b57ea21..8d872713e 100644 --- a/usrp2/top/u1e/.gitignore +++ b/usrp2/top/u1e/.gitignore @@ -2,3 +2,5 @@ build *.log *.cmd +tb_u1e +*.lxt diff --git a/usrp2/top/u1e/README b/usrp2/top/u1e/README new file mode 100644 index 000000000..14c7a4955 --- /dev/null +++ b/usrp2/top/u1e/README @@ -0,0 +1,4 @@ + +make clean +make sim +./tb_u1e -lxt2 diff --git a/usrp2/top/u1e/cmdfile b/usrp2/top/u1e/cmdfile new file mode 100644 index 000000000..5e4db5c65 --- /dev/null +++ b/usrp2/top/u1e/cmdfile @@ -0,0 +1,19 @@ + +# My stuff +-y . +-y ../../control_lib +-y ../../control_lib/newfifo +-y ../../sdr_lib +-y ../../timing +-y ../../coregen +-y ../../gpmc + +# Models +-y ../../models + +# Open Cores +-y ../opencores/spi/rtl/verilog ++incdir+../opencores/spi/rtl/verilog +-y ../opencores/i2c/rtl/verilog ++incdir+../opencores/i2c/rtl/verilog + diff --git a/usrp2/top/u1e/make.sim b/usrp2/top/u1e/make.sim new file mode 100644 index 000000000..1c163884c --- /dev/null +++ b/usrp2/top/u1e/make.sim @@ -0,0 +1,7 @@ +all: sim + +sim: + iverilog -Wimplicit -Wportbind -c cmdfile tb_u1e.v -o tb_u1e + +clean: + rm -f tb_u1e *.vcd *.lxt a.out diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v index 6e0c60e17..85d2b49f0 100644 --- a/usrp2/top/u1e/tb_u1e.v +++ b/usrp2/top/u1e/tb_u1e.v @@ -6,8 +6,12 @@ module tb_u1e(); wire [2:0] debug_led; wire [31:0] debug; wire [1:0] debug_clk; - - + + initial begin + $dumpfile("tb_u1e.lxt"); + $dumpvars(0,tb_u1e); + end + // GPMC wire EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE; wire [15:0] EM_D; @@ -15,11 +19,16 @@ module tb_u1e(); wire [1:0] EM_NBE; reg clk_fpga = 0; - always #100 clk_fpga = ~clk_fpga; + always #15.625 clk_fpga = ~clk_fpga; u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); + + gpmc_model gpmc_model + (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); -endmodule // u1e +endmodule // tb_u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 2481549b2..b0edbb9b6 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -10,7 +10,7 @@ module u1e_core ); // Debug circuitry - reg [31:0] ctr; + reg [31:0] ctr=0; always @(posedge clk_fpga) ctr <= ctr + 1; @@ -37,7 +37,7 @@ module u1e_core assign wb_clk = clk_fpga; reg [15:0] reg_fast, reg_slow; - localparam [10:0] WB_ADR_REG_FAST = 36; + localparam [10:0] WB_ADR_REG_FAST = 11'd36; localparam [10:0] WB_ADR_REG_SLOW = 38; always @(posedge wb_clk) @@ -47,6 +47,5 @@ module u1e_core assign wb_dat_miso = (wb_adr == WB_ADR_REG_FAST) ? reg_fast : 16'bx; assign wb_ack = wb_stb & wb_cyc; - - -endmodule // u2plus + +endmodule // u1e_core -- cgit v1.2.3 From 1912ff60acd490a24204a7596e373e9aef9276cd Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 17 Feb 2010 15:00:41 -0800 Subject: speed up the presentation of registered wb data to the gpmc --- usrp2/gpmc/gpmc.v | 7 +++++-- usrp2/models/gpmc_model.v | 26 +++++++++++++++----------- 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v index 1963af6e6..56f879abc 100644 --- a/usrp2/gpmc/gpmc.v +++ b/usrp2/gpmc/gpmc.v @@ -12,7 +12,7 @@ module gpmc wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); wire [15:0] EM_D_ram; - reg [15:0] EM_D_wb; + wire [15:0] EM_D_wb; assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_ram : EM_D_wb; @@ -44,10 +44,13 @@ module gpmc wb_sel_o <= ~EM_NBE; end + reg [15:0] EM_D_wb_reg; always @(posedge wb_clk) if(wb_ack_i) - EM_D_wb <= wb_dat_miso; + EM_D_wb_reg <= wb_dat_miso; + assign EM_D_wb = wb_ack_i ? wb_dat_miso : EM_D_wb_reg; + // stb, oe_del, we_del assign wb_cyc_o = wb_stb_o; diff --git a/usrp2/models/gpmc_model.v b/usrp2/models/gpmc_model.v index ce3acaacf..38dde1fa5 100644 --- a/usrp2/models/gpmc_model.v +++ b/usrp2/models/gpmc_model.v @@ -25,16 +25,18 @@ module gpmc_model input [10:0] addr; input [15:0] data; begin - #2; + #2.3; EM_A <= addr[10:1]; EM_D_int <= data; - #4; + #2.01; EM_NCS6 <= 0; - #5; + #14; EM_NWE <= 0; - #41; - EM_NWE <= 1; + #77.5; EM_NCS6 <= 1; + //#1.5; + EM_NWE <= 1; + #6; EM_A <= 10'bz; EM_D_int <= 16'bz; end @@ -43,17 +45,19 @@ module gpmc_model task GPMC_Read; input [10:0] addr; begin - #2; + #1.3; EM_A <= addr[10:1]; - #4; + #3; EM_NCS6 <= 0; - #5; + #14; EM_NOE <= 0; - #41; - EM_NOE <= 1; + #77.5; EM_NCS6 <= 1; - EM_A <= 10'bz; + //#1.5; $display("Data Read from GPMC: %X",EM_D); + EM_NOE <= 1; + #254; + EM_A <= 10'bz; end endtask // GPMC_Read -- cgit v1.2.3 From e56b4767451dcdca41512faba634b812e44d2e1d Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 18 Feb 2010 18:03:26 -0800 Subject: Fixed paths to help icarus find opencores and xilinx models. Added Xilinx global set and reset module. --- usrp2/top/u1e/cmdfile | 9 +++++---- usrp2/top/u1e/tb_u1e.v | 2 ++ 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/usrp2/top/u1e/cmdfile b/usrp2/top/u1e/cmdfile index 5e4db5c65..291c723b8 100644 --- a/usrp2/top/u1e/cmdfile +++ b/usrp2/top/u1e/cmdfile @@ -10,10 +10,11 @@ # Models -y ../../models +-y /opt/Xilinx/10.1/ISE/verilog/src/unisims # Open Cores --y ../opencores/spi/rtl/verilog -+incdir+../opencores/spi/rtl/verilog --y ../opencores/i2c/rtl/verilog -+incdir+../opencores/i2c/rtl/verilog +-y ../../opencores/spi/rtl/verilog ++incdir+../../opencores/spi/rtl/verilog +-y ../../opencores/i2c/rtl/verilog ++incdir+../../opencores/i2c/rtl/verilog diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v index 85d2b49f0..319645af6 100644 --- a/usrp2/top/u1e/tb_u1e.v +++ b/usrp2/top/u1e/tb_u1e.v @@ -7,6 +7,8 @@ module tb_u1e(); wire [31:0] debug; wire [1:0] debug_clk; + xlnx_glbl glbl (.GSR(),.GTS()); + initial begin $dumpfile("tb_u1e.lxt"); $dumpvars(0,tb_u1e); -- cgit v1.2.3 From 7c31f8d25d563b9f2795914f8ea0f3e49b214c56 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 18 Feb 2010 18:04:24 -0800 Subject: allow default uart clock divider --- usrp2/control_lib/simple_uart.v | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/usrp2/control_lib/simple_uart.v b/usrp2/control_lib/simple_uart.v index 22f0e70a2..0dd58b5f5 100644 --- a/usrp2/control_lib/simple_uart.v +++ b/usrp2/control_lib/simple_uart.v @@ -1,11 +1,12 @@ module simple_uart #(parameter TXDEPTH = 1, - parameter RXDEPTH = 1) - (input clk_i, input rst_i, - input we_i, input stb_i, input cyc_i, output reg ack_o, - input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o, - output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o); + parameter RXDEPTH = 1, + parameter CLKDIV_DEFAULT = 16'd0) + (input clk_i, input rst_i, + input we_i, input stb_i, input cyc_i, output reg ack_o, + input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o, + output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o); // Register Map localparam SUART_CLKDIV = 0; @@ -30,7 +31,7 @@ module simple_uart always @(posedge clk_i) if (rst_i) - clkdiv <= 0; + clkdiv <= CLKDIV_DEFAULT; else if (wb_wr) case(adr_i) SUART_CLKDIV : clkdiv <= dat_i[15:0]; -- cgit v1.2.3 From f3c61700fbeba30f420ef939a1cabdc42bd15fb7 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 18 Feb 2010 18:05:42 -0800 Subject: Added I2C, UART, debug pins, misc wishbone stuff --- usrp2/top/u1e/u1e.ucf | 38 +++++----- usrp2/top/u1e/u1e.v | 12 ++- usrp2/top/u1e/u1e_core.v | 185 ++++++++++++++++++++++++++++++++++++++++------- 3 files changed, 187 insertions(+), 48 deletions(-) diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 3b524a6ea..40d458034 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -56,10 +56,10 @@ NET "EM_NOE" LOC = "A14" ; #NET "overo_gpio65" LOC = "F8" ; #NET "overo_gpio127" LOC = "C8" ; #NET "overo_gpio128" LOC = "G8" ; -#NET "overo_gpio144" LOC = "A5" ; -#NET "overo_gpio145" LOC = "C7" ; -#NET "overo_gpio146" LOC = "A6" ; -#NET "overo_gpio147" LOC = "B6" ; +NET "overo_gpio144" LOC = "A5" ; # tx_have_space +NET "overo_gpio145" LOC = "C7" ; # tx_underrun +NET "overo_gpio146" LOC = "A6" ; # rx_have_data +NET "overo_gpio147" LOC = "B6" ; # rx_overrun #NET "overo_gpio163" LOC = "D7" ; #NET "overo_gpio170" LOC = "E8" ; #NET "overo_gpio176" LOC = "B4" ; @@ -68,13 +68,13 @@ NET "EM_NOE" LOC = "A14" ; #NET "overo_txd1" LOC = "C6" ; #NET "overo_rxd1" LOC = "D6" ; -#NET "FPGA_TXD" LOC = "U1" ; -#NET "FPGA_RXD" LOC = "T6" ; +NET "FPGA_TXD" LOC = "U1" ; +NET "FPGA_RXD" LOC = "T6" ; #NET "SYSEN" LOC = "C11" ; -#NET "db_scl" LOC = "U4" ; -#NET "db_sda" LOC = "U5" ; +NET "db_scl" LOC = "U4" ; +NET "db_sda" LOC = "U5" ; #NET "db_sclk_rx" LOC = "W3" ; #NET "db_miso_rx" LOC = "W2" ; #NET "db_mosi_rx" LOC = "V4" ; @@ -134,18 +134,18 @@ NET "debug<31>" LOC = "G3" ; NET "debug_clk<0>" LOC = "L6" ; NET "debug_clk<1>" LOC = "M5" ; -#NET "debug_pb<2>" LOC = "Y2" ; -#NET "debug_pb<1>" LOC = "AA1" ; -#NET "debug_pb<0>" LOC = "N3" ; +NET "debug_pb<2>" LOC = "Y2" ; +NET "debug_pb<1>" LOC = "AA1" ; +NET "debug_pb<0>" LOC = "N3" ; -#NET "dip_sw<7>" LOC = "T3" ; -#NET "dip_sw<6>" LOC = "U3" ; -#NET "dip_sw<5>" LOC = "M3" ; -#NET "dip_sw<4>" LOC = "N4" ; -#NET "dip_sw<3>" LOC = "J3" ; -#NET "dip_sw<2>" LOC = "J4" ; -#NET "dip_sw<1>" LOC = "J6" ; -#NET "dip_sw<0>" LOC = "J7" ; +NET "dip_sw<7>" LOC = "T3" ; +NET "dip_sw<6>" LOC = "U3" ; +NET "dip_sw<5>" LOC = "M3" ; +NET "dip_sw<4>" LOC = "N4" ; +NET "dip_sw<3>" LOC = "J3" ; +NET "dip_sw<2>" LOC = "J4" ; +NET "dip_sw<1>" LOC = "J6" ; +NET "dip_sw<0>" LOC = "J7" ; ## AD9862 Interface #NET "aux_sdi_codec" LOC = "F19" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 8832d6e11..4ca9b5580 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -4,10 +4,14 @@ module u1e (input CLK_FPGA_P, input CLK_FPGA_N, // Diff output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + input [2:0] debug_pb, input [7:0] dip_sw, output FPGA_TXD, input FPGA_RXD, // GPMC input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, - input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + + inout db_sda, inout db_scl, // I2C + output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147 // Fifo controls ); // FPGA-specific pins connections @@ -17,8 +21,12 @@ module u1e clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .debug_pb(debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), - .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); + .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), + .db_sda(db_sda), .db_scl(db_scl), + .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), + .rx_have_data(overo_gpio_146), .rx_overrun(overo_gpio147) ); endmodule // u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index b0edbb9b6..cad697858 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -3,49 +3,180 @@ module u1e_core (input clk_fpga, output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - + input [2:0] debug_pb, input [7:0] dip_sw, output debug_txd, input debug_rxd, + // GPMC input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, - input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE - ); - - // Debug circuitry - reg [31:0] ctr=0; - always @(posedge clk_fpga) - ctr <= ctr + 1; + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, - assign debug_led = ctr[27:25]; - assign debug_clk = { EM_CLK, clk_fpga }; - assign debug = { { 1'b0, EM_WAIT0, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, - { EM_D } }; + inout db_sda, inout db_scl, + output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun + ); wire wb_clk, wb_rst; - wire wb_cyc, wb_stb, wb_we, wb_ack; - wire [1:0] wb_sel; - wire [10:0] wb_adr; - wire [15:0] wb_dat_mosi, wb_dat_miso; + + assign tx_have_space = 0; + assign tx_underrun = 0; + assign rx_have_data = 0; + assign rx_overrun = 0; + + // ///////////////////////////////////////////////////////////////////////////////////// + // GPMC Slave to Wishbone Master + localparam dw = 16; + localparam aw = 11; + localparam sw = 2; + + wire [dw-1:0] m0_dat_mosi, m0_dat_miso; + wire [aw-1:0] m0_adr; + wire [sw-1:0] m0_sel; + wire m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty; gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .wb_clk(wb_clk), .wb_rst(wb_rst), - .wb_adr_o(wb_adr), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), - .wb_sel_o(wb_sel), .wb_cyc_o(wb_cyc), .wb_stb_o(wb_stb), .wb_we_o(wb_we), - .wb_ack_i(wb_ack)); + .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), + .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), + .wb_ack_i(m0_ack)); assign wb_clk = clk_fpga; - reg [15:0] reg_fast, reg_slow; - localparam [10:0] WB_ADR_REG_FAST = 11'd36; - localparam [10:0] WB_ADR_REG_SLOW = 38; + // ///////////////////////////////////////////////////////////////////////////////////// + // Wishbone Intercon, single master + wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, + s4_dat_mosi, s5_dat_mosi, s4_dat_miso, s5_dat_miso, s6_dat_mosi, s7_dat_mosi, s6_dat_miso, s7_dat_miso, + s8_dat_mosi, s9_dat_mosi, s8_dat_miso, s9_dat_miso, sa_dat_mosi, sb_dat_mosi, sa_dat_miso, sb_dat_miso, + sc_dat_mosi, sd_dat_mosi, sc_dat_miso, sd_dat_miso, se_dat_mosi, sf_dat_mosi, se_dat_miso, sf_dat_miso; + wire [aw-1:0] s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr; + wire [aw-1:0] s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; + wire [sw-1:0] s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel; + wire [sw-1:0] s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; + wire s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack; + wire s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; + wire s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb; + wire s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; + wire s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc; + wire s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; + wire s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we; + wire s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we, sf_we; + + wb_1master #(.dw(dw), .aw(aw), .sw(sw), .decode_w(4), + .s0_addr(4'h0), .s0_mask(4'hF), .s1_addr(4'h1), .s1_mask(4'hF), + .s2_addr(4'h2), .s2_mask(4'hF), .s3_addr(4'h3), .s3_mask(4'hF), + .s4_addr(4'h4), .s4_mask(4'hF), .s5_addr(4'h5), .s5_mask(4'hF), + .s6_addr(4'h6), .s6_mask(4'hF), .s7_addr(4'h7), .s7_mask(4'hF), + .s8_addr(4'h8), .s8_mask(4'hF), .s9_addr(4'h9), .s9_mask(4'hF), + .sa_addr(4'ha), .sa_mask(4'hF), .sb_addr(4'hb), .sb_mask(4'hF), + .sc_addr(4'hc), .sc_mask(4'hF), .sd_addr(4'hd), .sd_mask(4'hF), + .se_addr(4'he), .se_mask(4'hF), .sf_addr(4'hf), .sf_mask(4'hF)) + wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_miso),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_mosi), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_mosi),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_miso),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_mosi),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_miso),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_mosi),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_miso),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_mosi),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_miso),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_mosi),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_miso),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_mosi),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_miso),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_mosi),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_miso),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_mosi),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_miso),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_mosi),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_miso),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_mosi),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_miso),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_mosi),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_miso),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_mosi),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_miso),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_mosi),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_miso),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_mosi),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_miso),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_mosi),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_miso),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), + .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); + + assign s4_ack = 0; assign s5_ack = 0; assign s6_ack = 0; assign s7_ack = 0; + assign s8_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; + assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 0, LEDs and Switches + + reg [15:0] reg_fast, reg_slow; + localparam REG_FAST = 7'd4; + localparam REG_SWITCHES = 7'd5; always @(posedge wb_clk) - if(wb_cyc & wb_stb & wb_we & (wb_adr == WB_ADR_REG_FAST)) - reg_fast <= wb_dat_mosi; + if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_FAST)) + reg_fast <= s0_dat_mosi; - assign wb_dat_miso = (wb_adr == WB_ADR_REG_FAST) ? reg_fast : 16'bx; + assign s0_dat_miso = (s0_adr[6:0] == REG_FAST) ? reg_fast : + (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : + 16'hBEEF; + assign s0_ack = s0_stb & s0_cyc; - assign wb_ack = wb_stb & wb_cyc; - + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 1, UART + // depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack), + .adr_i(s1_adr[4:2]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso), + .rx_int_o(),.tx_int_o(), + .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o()); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 2, SPI + + /* + spi_top shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), + .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), + .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), + .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); + */ + + // ///////////////////////////////////////////////////////////////////////// + // Slave 3, I2C + + wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o; + i2c_master_top #(.ARST_LVL(1)) i2c + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_miso[15:8] = 8'd0; + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Debug Pins + + // Debug circuitry + assign debug_clk = { EM_CLK, clk_fpga }; + assign debug = { { 1'b0, EM_WAIT0, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, + { EM_D } }; + + assign { debug_led[2],debug_led[0],debug_led[1] } = reg_fast; // LEDs are arranged funny on board + endmodule // u1e_core -- cgit v1.2.3 From bc3c1fb34afba5fb4358f1b7eaaf3832360cc375 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 18 Feb 2010 19:13:10 -0800 Subject: added gpio control to the wishbone --- usrp2/top/u1e/u1e.v | 2 +- usrp2/top/u1e/u1e_core.v | 23 +++++++++++++---------- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 4ca9b5580..326476b21 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -27,6 +27,6 @@ module u1e .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .db_sda(db_sda), .db_scl(db_scl), .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), - .rx_have_data(overo_gpio_146), .rx_overrun(overo_gpio147) ); + .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147) ); endmodule // u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index cad697858..257156d4b 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -12,20 +12,15 @@ module u1e_core inout db_sda, inout db_scl, output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun ); - - wire wb_clk, wb_rst; - - assign tx_have_space = 0; - assign tx_underrun = 0; - assign rx_have_data = 0; - assign rx_overrun = 0; + + wire wb_clk, wb_rst; // ///////////////////////////////////////////////////////////////////////////////////// // GPMC Slave to Wishbone Master localparam dw = 16; localparam aw = 11; localparam sw = 2; - + wire [dw-1:0] m0_dat_mosi, m0_dat_miso; wire [aw-1:0] m0_adr; wire [sw-1:0] m0_sel; @@ -114,19 +109,27 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////////////////// // Slave 0, LEDs and Switches - reg [15:0] reg_fast, reg_slow; + reg [15:0] reg_fast, reg_slow; localparam REG_FAST = 7'd4; - localparam REG_SWITCHES = 7'd5; + localparam REG_SWITCHES = 7'd6; + localparam REG_GPIOS = 7'd8; + + reg [3:0] reg_gpios; always @(posedge wb_clk) if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_FAST)) reg_fast <= s0_dat_mosi; + always @(posedge wb_clk) + if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_GPIOS)) + reg_gpios <= s0_dat_mosi; + assign s0_dat_miso = (s0_adr[6:0] == REG_FAST) ? reg_fast : (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : 16'hBEEF; assign s0_ack = s0_stb & s0_cyc; + assign { rx_overrun, rx_have_data, tx_underrun, tx_have_space } = reg_gpios; // ///////////////////////////////////////////////////////////////////////////////////// // Slave 1, UART -- cgit v1.2.3 From 2e4d962021334109b268c9080e5a5903b99be217 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 22 Feb 2010 12:30:22 -0800 Subject: GPIOs now on the wishbone interface --- usrp2/top/u1e/Makefile | 2 +- usrp2/top/u1e/u1e.ucf | 64 ++++++++++++++++++++++++------------------------ usrp2/top/u1e/u1e.v | 6 +++-- usrp2/top/u1e/u1e_core.v | 19 ++++++++++++-- 4 files changed, 54 insertions(+), 37 deletions(-) diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index cdbdf995e..9381789a7 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -64,7 +64,7 @@ control_lib/gray_send.v \ control_lib/icache.v \ control_lib/mux4.v \ control_lib/mux8.v \ -control_lib/nsgpio.v \ +control_lib/nsgpio16LE.v \ control_lib/ram_2port.v \ control_lib/ram_harv_cache.v \ control_lib/ram_loader.v \ diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 40d458034..f237eb60c 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -203,39 +203,39 @@ NET "dip_sw<0>" LOC = "J7" ; #NET "PPS_IN" LOC = "M17" ; -#NET "io_tx<0>" LOC = "AB20" ; -#NET "io_tx<1>" LOC = "Y17" ; -#NET "io_tx<2>" LOC = "Y16" ; -#NET "io_tx<3>" LOC = "U16" ; -#NET "io_tx<4>" LOC = "V16" ; -#NET "io_tx<5>" LOC = "AB19" ; -#NET "io_tx<6>" LOC = "AA19" ; -#NET "io_tx<7>" LOC = "U14" ; -#NET "io_tx<8>" LOC = "U15" ; -#NET "io_tx<9>" LOC = "AB17" ; -#NET "io_tx<10>" LOC = "AB18" ; -#NET "io_tx<11>" LOC = "Y13" ; -#NET "io_tx<12>" LOC = "W14" ; -#NET "io_tx<13>" LOC = "U13" ; -#NET "io_tx<14>" LOC = "AA15" ; -#NET "io_tx<15>" LOC = "AB14" ; +NET "io_tx<0>" LOC = "AB20" ; +NET "io_tx<1>" LOC = "Y17" ; +NET "io_tx<2>" LOC = "Y16" ; +NET "io_tx<3>" LOC = "U16" ; +NET "io_tx<4>" LOC = "V16" ; +NET "io_tx<5>" LOC = "AB19" ; +NET "io_tx<6>" LOC = "AA19" ; +NET "io_tx<7>" LOC = "U14" ; +NET "io_tx<8>" LOC = "U15" ; +NET "io_tx<9>" LOC = "AB17" ; +NET "io_tx<10>" LOC = "AB18" ; +NET "io_tx<11>" LOC = "Y13" ; +NET "io_tx<12>" LOC = "W14" ; +NET "io_tx<13>" LOC = "U13" ; +NET "io_tx<14>" LOC = "AA15" ; +NET "io_tx<15>" LOC = "AB14" ; -#NET "io_rx<0>" LOC = "Y8" ; -#NET "io_rx<1>" LOC = "Y9" ; -#NET "io_rx<2>" LOC = "V7" ; -#NET "io_rx<3>" LOC = "U8" ; -#NET "io_rx<4>" LOC = "V10" ; -#NET "io_rx<5>" LOC = "U9" ; -#NET "io_rx<6>" LOC = "AB7" ; -#NET "io_rx<7>" LOC = "AA8" ; -#NET "io_rx<8>" LOC = "W8" ; -#NET "io_rx<9>" LOC = "V8" ; -#NET "io_rx<10>" LOC = "AB5" ; -#NET "io_rx<11>" LOC = "AB6" ; -#NET "io_rx<12>" LOC = "AB4" ; -#NET "io_rx<13>" LOC = "AA4" ; -#NET "io_rx<14>" LOC = "W5" ; -#NET "io_rx<15>" LOC = "Y4" ; +NET "io_rx<0>" LOC = "Y8" ; +NET "io_rx<1>" LOC = "Y9" ; +NET "io_rx<2>" LOC = "V7" ; +NET "io_rx<3>" LOC = "U8" ; +NET "io_rx<4>" LOC = "V10" ; +NET "io_rx<5>" LOC = "U9" ; +NET "io_rx<6>" LOC = "AB7" ; +NET "io_rx<7>" LOC = "AA8" ; +NET "io_rx<8>" LOC = "W8" ; +NET "io_rx<9>" LOC = "V8" ; +NET "io_rx<10>" LOC = "AB5" ; +NET "io_rx<11>" LOC = "AB6" ; +NET "io_rx<12>" LOC = "AB4" ; +NET "io_rx<13>" LOC = "AA4" ; +NET "io_rx<14>" LOC = "W5" ; +NET "io_rx<15>" LOC = "Y4" ; #NET "CLKOUT2_CODEC" LOC = "U12" ; #NET "CLKOUT1_CODEC" LOC = "V12" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 326476b21..667372434 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -11,7 +11,8 @@ module u1e input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, inout db_sda, inout db_scl, // I2C - output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147 // Fifo controls + output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls + inout [15:0] io_tx, inout [15:0] io_rx ); // FPGA-specific pins connections @@ -27,6 +28,7 @@ module u1e .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .db_sda(db_sda), .db_scl(db_scl), .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), - .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147) ); + .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), + .io_tx(io_tx), .io_rx(io_rx) ); endmodule // u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 257156d4b..ad3234b56 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -10,7 +10,8 @@ module u1e_core input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, inout db_sda, inout db_scl, - output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun + output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, + inout [15:0] io_tx, inout [15:0] io_rx ); wire wb_clk, wb_rst; @@ -102,7 +103,7 @@ module u1e_core .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); - assign s4_ack = 0; assign s5_ack = 0; assign s6_ack = 0; assign s7_ack = 0; + assign s5_ack = 0; assign s6_ack = 0; assign s7_ack = 0; assign s8_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; @@ -172,6 +173,20 @@ module u1e_core IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o)); IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o)); + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + + wire [31:0] atr_lines; + wire [31:0] debug_gpio_0, debug_gpio_1; + + nsgpio16LE + nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio( {io_tx,io_rx} ) ); + + // ///////////////////////////////////////////////////////////////////////////////////// // Debug Pins -- cgit v1.2.3 From 7043c21bcef95879c58c9101f8bd16f216aa277a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 22 Feb 2010 12:30:55 -0800 Subject: Modified nsgpio.v to support 16 bit little endian bus interface. --- usrp2/control_lib/nsgpio16LE.v | 124 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 usrp2/control_lib/nsgpio16LE.v diff --git a/usrp2/control_lib/nsgpio16LE.v b/usrp2/control_lib/nsgpio16LE.v new file mode 100644 index 000000000..6847bb4a9 --- /dev/null +++ b/usrp2/control_lib/nsgpio16LE.v @@ -0,0 +1,124 @@ +// Modified from code originally by Richard Herveille, his copyright is below + +///////////////////////////////////////////////////////////////////// +//// //// +//// OpenCores Simple General Purpose IO core //// +//// //// +//// Author: Richard Herveille //// +//// richard@asics.ws //// +//// www.asics.ws //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + + +module nsgpio16LE + (input clk_i, input rst_i, + input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [15:0] dat_i, + output reg [15:0] dat_o, output reg ack_o, + input [31:0] atr, input [31:0] debug_0, input [31:0] debug_1, + inout [31:0] gpio + ); + + reg [63:0] ctrl; + reg [31:0] line; + reg [31:0] lgpio; // LatchedGPIO pins + reg [31:0] ddr; + + wire wb_acc = cyc_i & stb_i; // WISHBONE access + wire wb_wr = wb_acc & we_i; // WISHBONE write access + + always @(posedge clk_i or posedge rst_i) + if (rst_i) + begin + ctrl <= 64'h0; + line <= 0; + end + else if (wb_wr) + case( adr_i[3:1] ) + 3'b000 : + line[15:0] <= dat_i; + 3'b001 : + line[31:16] <= dat_i; + 3'b010 : + ddr[15:0] <= dat_i; + 3'b011 : + ddr[31:16] <= dat_i; + 3'b100 : + ctrl[15:0] <= dat_i; + 3'b101 : + ctrl[31:16] <= dat_i; + 3'b110 : + ctrl[47:32] <= dat_i; + 3'b111 : + ctrl[63:48] <= dat_i; + endcase // case ( adr_i[3:1] ) + + always @(posedge clk_i) + case (adr_i[3:1]) + 3'b000 : + dat_o <= lgpio[15:0]; + 3'b001 : + dat_o <= lgpio[31:16]; + 3'b010 : + dat_o <= ddr[15:0]; + 3'b011 : + dat_o <= ddr[31:16]; + 3'b100 : + dat_o <= ctrl[15:0]; + 3'b101 : + dat_o <= ctrl[31:16]; + 3'b110 : + dat_o <= ctrl[47:32]; + 3'b111 : + dat_o <= ctrl[63:48]; + endcase // case (adr_i[3:1]) + + + always @(posedge clk_i or posedge rst_i) + if (rst_i) + ack_o <= 1'b0; + else + ack_o <= wb_acc & !ack_o; + + // latch GPIO input pins + always @(posedge clk_i) + lgpio <= gpio; + + // assign GPIO outputs + integer n; + reg [31:0] igpio; // temporary internal signal + + always @(ctrl or line or debug_1 or debug_0 or atr) + for(n=0;n<32;n=n+1) + igpio[n] <= ddr[n] ? (ctrl[2*n+1] ? (ctrl[2*n] ? debug_1[n] : debug_0[n]) : + (ctrl[2*n] ? atr[n] : line[n]) ) + : 1'bz; + + assign gpio = igpio; + +endmodule + -- cgit v1.2.3 From ba97786f44d66c634f289e9a23021e8e13548326 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 22 Feb 2010 12:33:13 -0800 Subject: remove the #1 delay in all the regs. They just slow down sims. --- usrp2/opencores/spi/rtl/verilog/spi_clgen.v | 20 +++--- usrp2/opencores/spi/rtl/verilog/spi_defines.v | 8 +-- usrp2/opencores/spi/rtl/verilog/spi_shift.v | 90 +++++++++++++-------------- usrp2/opencores/spi/rtl/verilog/spi_top.v | 68 ++++++++++---------- 4 files changed, 90 insertions(+), 96 deletions(-) diff --git a/usrp2/opencores/spi/rtl/verilog/spi_clgen.v b/usrp2/opencores/spi/rtl/verilog/spi_clgen.v index 7bc4f6e5e..3f29f6d7f 100644 --- a/usrp2/opencores/spi/rtl/verilog/spi_clgen.v +++ b/usrp2/opencores/spi/rtl/verilog/spi_clgen.v @@ -43,8 +43,6 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge); - parameter Tp = 1; - input clk_in; // input clock (system clock) input rst; // reset input enable; // clock enable @@ -71,13 +69,13 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, always @(posedge clk_in or posedge rst) begin if(rst) - cnt <= #Tp {`SPI_DIVIDER_LEN{1'b1}}; + cnt <= {`SPI_DIVIDER_LEN{1'b1}}; else begin if(!enable || cnt_zero) - cnt <= #Tp divider; + cnt <= divider; else - cnt <= #Tp cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1}; + cnt <= cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1}; end end @@ -85,9 +83,9 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, always @(posedge clk_in or posedge rst) begin if(rst) - clk_out <= #Tp 1'b0; + clk_out <= 1'b0; else - clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out; + clk_out <= (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out; end // Pos and neg edge signals @@ -95,13 +93,13 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, begin if(rst) begin - pos_edge <= #Tp 1'b0; - neg_edge <= #Tp 1'b0; + pos_edge <= 1'b0; + neg_edge <= 1'b0; end else begin - pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable); - neg_edge <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable); + pos_edge <= (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable); + neg_edge <= (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable); end end endmodule diff --git a/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/usrp2/opencores/spi/rtl/verilog/spi_defines.v index a6925918e..01de2584d 100644 --- a/usrp2/opencores/spi/rtl/verilog/spi_defines.v +++ b/usrp2/opencores/spi/rtl/verilog/spi_defines.v @@ -43,8 +43,8 @@ // low frequency of system clock this can be reduced. // Use SPI_DIVIDER_LEN for fine tuning theexact number. // -//`define SPI_DIVIDER_LEN_8 -`define SPI_DIVIDER_LEN_16 +`define SPI_DIVIDER_LEN_8 +//`define SPI_DIVIDER_LEN_16 //`define SPI_DIVIDER_LEN_24 //`define SPI_DIVIDER_LEN_32 @@ -66,9 +66,9 @@ // Use SPI_MAX_CHAR for fine tuning the exact number, when using // SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8. // -`define SPI_MAX_CHAR_128 +//`define SPI_MAX_CHAR_128 //`define SPI_MAX_CHAR_64 -//`define SPI_MAX_CHAR_32 +`define SPI_MAX_CHAR_32 //`define SPI_MAX_CHAR_24 //`define SPI_MAX_CHAR_16 //`define SPI_MAX_CHAR_8 diff --git a/usrp2/opencores/spi/rtl/verilog/spi_shift.v b/usrp2/opencores/spi/rtl/verilog/spi_shift.v index b17ac8b1f..c8c73706b 100644 --- a/usrp2/opencores/spi/rtl/verilog/spi_shift.v +++ b/usrp2/opencores/spi/rtl/verilog/spi_shift.v @@ -46,8 +46,6 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, tip, last, p_in, p_out, s_clk, s_in, s_out); - parameter Tp = 1; - input clk; // system clock input rst; // reset input [3:0] latch; // latch signal for storing the data in shift register @@ -92,13 +90,13 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, always @(posedge clk or posedge rst) begin if(rst) - cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}}; + cnt <= {`SPI_CHAR_LEN_BITS+1{1'b0}}; else begin if(tip) - cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt; + cnt <= pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt; else - cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len}; + cnt <= !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len}; end end @@ -106,132 +104,132 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, always @(posedge clk or posedge rst) begin if(rst) - tip <= #Tp 1'b0; + tip <= 1'b0; else if(go && ~tip) - tip <= #Tp 1'b1; + tip <= 1'b1; else if(tip && last && pos_edge) - tip <= #Tp 1'b0; + tip <= 1'b0; end // Sending bits to the line always @(posedge clk or posedge rst) begin if (rst) - s_out <= #Tp 1'b0; + s_out <= 1'b0; else - s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out; + s_out <= (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out; end // Receiving bits from the line always @(posedge clk or posedge rst) begin if (rst) - data <= #Tp {`SPI_MAX_CHAR{1'b0}}; + data <= {`SPI_MAX_CHAR{1'b0}}; `ifdef SPI_MAX_CHAR_128 else if (latch[0] && !tip) begin if (byte_sel[3]) - data[31:24] <= #Tp p_in[31:24]; + data[31:24] <= p_in[31:24]; if (byte_sel[2]) - data[23:16] <= #Tp p_in[23:16]; + data[23:16] <= p_in[23:16]; if (byte_sel[1]) - data[15:8] <= #Tp p_in[15:8]; + data[15:8] <= p_in[15:8]; if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; + data[7:0] <= p_in[7:0]; end else if (latch[1] && !tip) begin if (byte_sel[3]) - data[63:56] <= #Tp p_in[31:24]; + data[63:56] <= p_in[31:24]; if (byte_sel[2]) - data[55:48] <= #Tp p_in[23:16]; + data[55:48] <= p_in[23:16]; if (byte_sel[1]) - data[47:40] <= #Tp p_in[15:8]; + data[47:40] <= p_in[15:8]; if (byte_sel[0]) - data[39:32] <= #Tp p_in[7:0]; + data[39:32] <= p_in[7:0]; end else if (latch[2] && !tip) begin if (byte_sel[3]) - data[95:88] <= #Tp p_in[31:24]; + data[95:88] <= p_in[31:24]; if (byte_sel[2]) - data[87:80] <= #Tp p_in[23:16]; + data[87:80] <= p_in[23:16]; if (byte_sel[1]) - data[79:72] <= #Tp p_in[15:8]; + data[79:72] <= p_in[15:8]; if (byte_sel[0]) - data[71:64] <= #Tp p_in[7:0]; + data[71:64] <= p_in[7:0]; end else if (latch[3] && !tip) begin if (byte_sel[3]) - data[127:120] <= #Tp p_in[31:24]; + data[127:120] <= p_in[31:24]; if (byte_sel[2]) - data[119:112] <= #Tp p_in[23:16]; + data[119:112] <= p_in[23:16]; if (byte_sel[1]) - data[111:104] <= #Tp p_in[15:8]; + data[111:104] <= p_in[15:8]; if (byte_sel[0]) - data[103:96] <= #Tp p_in[7:0]; + data[103:96] <= p_in[7:0]; end `else `ifdef SPI_MAX_CHAR_64 else if (latch[0] && !tip) begin if (byte_sel[3]) - data[31:24] <= #Tp p_in[31:24]; + data[31:24] <= p_in[31:24]; if (byte_sel[2]) - data[23:16] <= #Tp p_in[23:16]; + data[23:16] <= p_in[23:16]; if (byte_sel[1]) - data[15:8] <= #Tp p_in[15:8]; + data[15:8] <= p_in[15:8]; if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; + data[7:0] <= p_in[7:0]; end else if (latch[1] && !tip) begin if (byte_sel[3]) - data[63:56] <= #Tp p_in[31:24]; + data[63:56] <= p_in[31:24]; if (byte_sel[2]) - data[55:48] <= #Tp p_in[23:16]; + data[55:48] <= p_in[23:16]; if (byte_sel[1]) - data[47:40] <= #Tp p_in[15:8]; + data[47:40] <= p_in[15:8]; if (byte_sel[0]) - data[39:32] <= #Tp p_in[7:0]; + data[39:32] <= p_in[7:0]; end `else else if (latch[0] && !tip) begin `ifdef SPI_MAX_CHAR_8 if (byte_sel[0]) - data[`SPI_MAX_CHAR-1:0] <= #Tp p_in[`SPI_MAX_CHAR-1:0]; + data[`SPI_MAX_CHAR-1:0] <= p_in[`SPI_MAX_CHAR-1:0]; `endif `ifdef SPI_MAX_CHAR_16 if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; + data[7:0] <= p_in[7:0]; if (byte_sel[1]) - data[`SPI_MAX_CHAR-1:8] <= #Tp p_in[`SPI_MAX_CHAR-1:8]; + data[`SPI_MAX_CHAR-1:8] <= p_in[`SPI_MAX_CHAR-1:8]; `endif `ifdef SPI_MAX_CHAR_24 if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; + data[7:0] <= p_in[7:0]; if (byte_sel[1]) - data[15:8] <= #Tp p_in[15:8]; + data[15:8] <= p_in[15:8]; if (byte_sel[2]) - data[`SPI_MAX_CHAR-1:16] <= #Tp p_in[`SPI_MAX_CHAR-1:16]; + data[`SPI_MAX_CHAR-1:16] <= p_in[`SPI_MAX_CHAR-1:16]; `endif `ifdef SPI_MAX_CHAR_32 if (byte_sel[0]) - data[7:0] <= #Tp p_in[7:0]; + data[7:0] <= p_in[7:0]; if (byte_sel[1]) - data[15:8] <= #Tp p_in[15:8]; + data[15:8] <= p_in[15:8]; if (byte_sel[2]) - data[23:16] <= #Tp p_in[23:16]; + data[23:16] <= p_in[23:16]; if (byte_sel[3]) - data[`SPI_MAX_CHAR-1:24] <= #Tp p_in[`SPI_MAX_CHAR-1:24]; + data[`SPI_MAX_CHAR-1:24] <= p_in[`SPI_MAX_CHAR-1:24]; `endif end `endif `endif else - data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]]; + data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]]; end endmodule diff --git a/usrp2/opencores/spi/rtl/verilog/spi_top.v b/usrp2/opencores/spi/rtl/verilog/spi_top.v index 09b2e50e1..071aeefca 100644 --- a/usrp2/opencores/spi/rtl/verilog/spi_top.v +++ b/usrp2/opencores/spi/rtl/verilog/spi_top.v @@ -52,8 +52,6 @@ module spi_top ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i ); - parameter Tp = 1; - // Wishbone signals input wb_clk_i; // master clock input input wb_rst_i; // synchronous active high reset @@ -142,18 +140,18 @@ module spi_top always @(posedge wb_clk_i or posedge wb_rst_i) begin if (wb_rst_i) - wb_dat_o <= #Tp 32'b0; + wb_dat_o <= 32'b0; else - wb_dat_o <= #Tp wb_dat; + wb_dat_o <= wb_dat; end // Wb acknowledge always @(posedge wb_clk_i or posedge wb_rst_i) begin if (wb_rst_i) - wb_ack_o <= #Tp 1'b0; + wb_ack_o <= 1'b0; else - wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o; + wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o; end // Wb error @@ -163,47 +161,47 @@ module spi_top always @(posedge wb_clk_i or posedge wb_rst_i) begin if (wb_rst_i) - wb_int_o <= #Tp 1'b0; + wb_int_o <= 1'b0; else if (ie && tip && last_bit && pos_edge) - wb_int_o <= #Tp 1'b1; + wb_int_o <= 1'b1; else if (wb_ack_o) - wb_int_o <= #Tp 1'b0; + wb_int_o <= 1'b0; end // Divider register always @(posedge wb_clk_i or posedge wb_rst_i) begin if (wb_rst_i) - divider <= #Tp {`SPI_DIVIDER_LEN{1'b0}}; + divider <= {`SPI_DIVIDER_LEN{1'b0}}; else if (spi_divider_sel && wb_we_i && !tip) begin `ifdef SPI_DIVIDER_LEN_8 if (wb_sel_i[0]) - divider <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:0]; + divider <= wb_dat_i[`SPI_DIVIDER_LEN-1:0]; `endif `ifdef SPI_DIVIDER_LEN_16 if (wb_sel_i[0]) - divider[7:0] <= #Tp wb_dat_i[7:0]; + divider[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - divider[`SPI_DIVIDER_LEN-1:8] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:8]; + divider[`SPI_DIVIDER_LEN-1:8] <= wb_dat_i[`SPI_DIVIDER_LEN-1:8]; `endif `ifdef SPI_DIVIDER_LEN_24 if (wb_sel_i[0]) - divider[7:0] <= #Tp wb_dat_i[7:0]; + divider[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - divider[15:8] <= #Tp wb_dat_i[15:8]; + divider[15:8] <= wb_dat_i[15:8]; if (wb_sel_i[2]) - divider[`SPI_DIVIDER_LEN-1:16] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:16]; + divider[`SPI_DIVIDER_LEN-1:16] <= wb_dat_i[`SPI_DIVIDER_LEN-1:16]; `endif `ifdef SPI_DIVIDER_LEN_32 if (wb_sel_i[0]) - divider[7:0] <= #Tp wb_dat_i[7:0]; + divider[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - divider[15:8] <= #Tp wb_dat_i[15:8]; + divider[15:8] <= wb_dat_i[15:8]; if (wb_sel_i[2]) - divider[23:16] <= #Tp wb_dat_i[23:16]; + divider[23:16] <= wb_dat_i[23:16]; if (wb_sel_i[3]) - divider[`SPI_DIVIDER_LEN-1:24] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:24]; + divider[`SPI_DIVIDER_LEN-1:24] <= wb_dat_i[`SPI_DIVIDER_LEN-1:24]; `endif end end @@ -212,16 +210,16 @@ module spi_top always @(posedge wb_clk_i or posedge wb_rst_i) begin if (wb_rst_i) - ctrl <= #Tp {`SPI_CTRL_BIT_NB{1'b0}}; + ctrl <= {`SPI_CTRL_BIT_NB{1'b0}}; else if(spi_ctrl_sel && wb_we_i && !tip) begin if (wb_sel_i[0]) - ctrl[7:0] <= #Tp wb_dat_i[7:0] | {7'b0, ctrl[0]}; + ctrl[7:0] <= wb_dat_i[7:0] | {7'b0, ctrl[0]}; if (wb_sel_i[1]) - ctrl[`SPI_CTRL_BIT_NB-1:8] <= #Tp wb_dat_i[`SPI_CTRL_BIT_NB-1:8]; + ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8]; end else if(tip && last_bit && pos_edge) - ctrl[`SPI_CTRL_GO] <= #Tp 1'b0; + ctrl[`SPI_CTRL_GO] <= 1'b0; end assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE]; @@ -236,36 +234,36 @@ module spi_top always @(posedge wb_clk_i or posedge wb_rst_i) begin if (wb_rst_i) - ss <= #Tp {`SPI_SS_NB{1'b0}}; + ss <= {`SPI_SS_NB{1'b0}}; else if(spi_ss_sel && wb_we_i && !tip) begin `ifdef SPI_SS_NB_8 if (wb_sel_i[0]) - ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0]; + ss <= wb_dat_i[`SPI_SS_NB-1:0]; `endif `ifdef SPI_SS_NB_16 if (wb_sel_i[0]) - ss[7:0] <= #Tp wb_dat_i[7:0]; + ss[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - ss[`SPI_SS_NB-1:8] <= #Tp wb_dat_i[`SPI_SS_NB-1:8]; + ss[`SPI_SS_NB-1:8] <= wb_dat_i[`SPI_SS_NB-1:8]; `endif `ifdef SPI_SS_NB_24 if (wb_sel_i[0]) - ss[7:0] <= #Tp wb_dat_i[7:0]; + ss[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - ss[15:8] <= #Tp wb_dat_i[15:8]; + ss[15:8] <= wb_dat_i[15:8]; if (wb_sel_i[2]) - ss[`SPI_SS_NB-1:16] <= #Tp wb_dat_i[`SPI_SS_NB-1:16]; + ss[`SPI_SS_NB-1:16] <= wb_dat_i[`SPI_SS_NB-1:16]; `endif `ifdef SPI_SS_NB_32 if (wb_sel_i[0]) - ss[7:0] <= #Tp wb_dat_i[7:0]; + ss[7:0] <= wb_dat_i[7:0]; if (wb_sel_i[1]) - ss[15:8] <= #Tp wb_dat_i[15:8]; + ss[15:8] <= wb_dat_i[15:8]; if (wb_sel_i[2]) - ss[23:16] <= #Tp wb_dat_i[23:16]; + ss[23:16] <= wb_dat_i[23:16]; if (wb_sel_i[3]) - ss[`SPI_SS_NB-1:24] <= #Tp wb_dat_i[`SPI_SS_NB-1:24]; + ss[`SPI_SS_NB-1:24] <= wb_dat_i[`SPI_SS_NB-1:24]; `endif end end -- cgit v1.2.3 From 035440ab7dce5c13655539db606de531606bad59 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 22 Feb 2010 15:39:53 -0800 Subject: settings bus with 16 bit wishbone interface, put on the main wishbone in u1e --- usrp2/control_lib/settings_bus_16LE.v | 54 +++++++++++++++++++++++++++++++++++ usrp2/top/u1e/Makefile | 2 +- usrp2/top/u1e/u1e_core.v | 15 ++++++++-- 3 files changed, 68 insertions(+), 3 deletions(-) create mode 100644 usrp2/control_lib/settings_bus_16LE.v diff --git a/usrp2/control_lib/settings_bus_16LE.v b/usrp2/control_lib/settings_bus_16LE.v new file mode 100644 index 000000000..fbef9b1c9 --- /dev/null +++ b/usrp2/control_lib/settings_bus_16LE.v @@ -0,0 +1,54 @@ + +// Grab settings off the wishbone bus, send them out to settings bus +// 16 bits little endian, but all registers need to be written 32 bits at a time. +// This means that you write the low 16 bits first and then the high 16 bits. +// The setting regs are strobed when the high 16 bits are written + +module settings_bus_16LE + #(parameter AWIDTH=16) + (input wb_clk, + input wb_rst, + input [AWIDTH-1:0] wb_adr_i, + input [15:0] wb_dat_i, + input wb_stb_i, + input wb_we_i, + output reg wb_ack_o, + output strobe, + output reg [7:0] addr, + output reg [31:0] data); + + reg stb_int; + + always @(posedge wb_clk) + if(wb_rst) + begin + stb_int <= 1'b0; + addr <= 8'd0; + data <= 32'd0; + end + else if(wb_we_i & wb_stb_i) + begin + addr <= wb_adr_i[9:2]; + if(wb_adr_i[1]) + begin + stb_int <= 1'b1; // We now have both halves + data[31:16] <= wb_dat_i; + end + else + begin + stb_int <= 1'b0; // Don't strobe, we need other half + data[15:0] <= wb_dat_i; + end + end + else + stb_int <= 1'b0; + + always @(posedge wb_clk) + if(wb_rst) + wb_ack_o <= 0; + else + wb_ack_o <= wb_stb_i & ~wb_ack_o; + + assign strobe = stb_int & wb_ack_o; + +endmodule // settings_bus_16LE diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 9381789a7..bcd80df6a 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -69,7 +69,7 @@ control_lib/ram_2port.v \ control_lib/ram_harv_cache.v \ control_lib/ram_loader.v \ control_lib/setting_reg.v \ -control_lib/settings_bus.v \ +control_lib/settings_bus_16LE.v \ control_lib/srl.v \ control_lib/system_control.v \ control_lib/wb_1master.v \ diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index ad3234b56..7ac4c8f86 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -103,7 +103,7 @@ module u1e_core .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); - assign s5_ack = 0; assign s6_ack = 0; assign s7_ack = 0; + assign s6_ack = 0; assign s7_ack = 0; assign s8_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; @@ -182,10 +182,21 @@ module u1e_core nsgpio16LE nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst), .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), - .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), + .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), .gpio( {io_tx,io_rx} ) ); + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #5 + + wire [7:0] set_addr; + wire [31:0] set_data; + wire set_stb; + + settings_bus_16LE settings_bus_16LE + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s5_adr),.wb_dat_i(s5_dat_mosi), + .wb_stb_i(s5_stb),.wb_we_i(s5_we),.wb_ack_o(s5_ack), + .strobe(set_stb),.addr(set_addr),.data(set_data) ); // ///////////////////////////////////////////////////////////////////////////////////// // Debug Pins -- cgit v1.2.3 From be576635cbba32bec56974fc24f5ae859f6722da Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 22 Feb 2010 16:44:15 -0800 Subject: place to put omap tools --- host/apps/omap_debug/README | 1 + 1 file changed, 1 insertion(+) create mode 100644 host/apps/omap_debug/README diff --git a/host/apps/omap_debug/README b/host/apps/omap_debug/README new file mode 100644 index 000000000..bbe0c2cc4 --- /dev/null +++ b/host/apps/omap_debug/README @@ -0,0 +1 @@ +OMAP development tools go here -- cgit v1.2.3 From fa35b710c09d7cb4a410313fd24d0ea2aa4172a3 Mon Sep 17 00:00:00 2001 From: root Date: Tue, 23 Feb 2010 02:06:59 +0000 Subject: Initial checkin of u1e testing code. Some of these may not be really useful anymore. --- host/apps/omap_debug/fpga-downloader.cc | 251 ++++++++++++++++++++++++++++++++ host/apps/omap_debug/test.c | 34 +++++ host/apps/omap_debug/u1e-read-stream.c | 21 +++ host/apps/omap_debug/usrp1-e-ctl.c | 52 +++++++ host/apps/omap_debug/usrp1-e-ram.c | 25 ++++ host/apps/omap_debug/usrp1-e-read.c | 18 +++ host/apps/omap_debug/usrp1-e-write.c | 21 +++ 7 files changed, 422 insertions(+) create mode 100644 host/apps/omap_debug/fpga-downloader.cc create mode 100644 host/apps/omap_debug/test.c create mode 100644 host/apps/omap_debug/u1e-read-stream.c create mode 100644 host/apps/omap_debug/usrp1-e-ctl.c create mode 100644 host/apps/omap_debug/usrp1-e-ram.c create mode 100644 host/apps/omap_debug/usrp1-e-read.c create mode 100644 host/apps/omap_debug/usrp1-e-write.c diff --git a/host/apps/omap_debug/fpga-downloader.cc b/host/apps/omap_debug/fpga-downloader.cc new file mode 100644 index 000000000..fb96b64a3 --- /dev/null +++ b/host/apps/omap_debug/fpga-downloader.cc @@ -0,0 +1,251 @@ +/* -*- c++ -*- */ +/* + * Copyright 2003,2004,2008,2009 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. +*/ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +/* + * Configuration connections + * + * CCK - MCSPI1_CLK + * DIN - MCSPI1_MOSI + * PROG_B - GPIO_175 - output (change mux) + * DONE - GPIO_173 - input (change mux) + * INIT_B - GPIO_114 - input (change mux) + * +*/ + +const unsigned int PROG_B = 175; +const unsigned int DONE = 173; +const unsigned int INIT_B = 114; + +static std::string bit_file = "safe_u1e.bin"; + +const int BUF_SIZE = 4096; + +enum gpio_direction {IN, OUT}; + +class gpio { + public: + + gpio(unsigned int gpio_num, gpio_direction pin_direction); + + bool get_value(); + void set_value(bool state); + + private: + + std::stringstream base_path; + std::fstream value_file; +}; + +class spidev { + public: + + spidev(std::string dev_name); + ~spidev(); + + void send(char *wbuf, char *rbuf, unsigned int nbytes); + + private: + + int fd; + +}; + +gpio::gpio(unsigned int gpio_num, gpio_direction pin_direction) +{ + std::fstream export_file; + + export_file.open("/sys/class/gpio/export", std::ios::out); + if (!export_file.is_open()) ///\todo Poor error handling + std::cout << "Failed to open gpio export file." << std::endl; + + export_file << gpio_num << std::endl; + + base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush; + + std::fstream direction_file; + std::string direction_file_name; + + direction_file_name = base_path.str() + "/direction"; + + direction_file.open(direction_file_name.c_str()); + if (!direction_file.is_open()) + std::cout << "Failed to open direction file." << std::endl; + if (pin_direction == OUT) + direction_file << "out" << std::endl; + else + direction_file << "in" << std::endl; + + std::string value_file_name; + + value_file_name = base_path.str() + "/value"; + + value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out); + if (!value_file.is_open()) + std::cout << "Failed to open value file." << std::endl; +} + +bool gpio::get_value() +{ + + std::string val; + + std::getline(value_file, val); + value_file.seekg(0); + + if (val == "0") + return false; + else if (val == "1") + return true; + else + std::cout << "Data read from value file|" << val << "|" << std::endl; + + return false; +} + +void gpio::set_value(bool state) +{ + + if (state) + value_file << "1" << std::endl; + else + value_file << "0" << std::endl; +} + +static void prepare_fpga_for_configuration(gpio &prog, gpio &init) +{ + + prog.set_value(true); + prog.set_value(false); + prog.set_value(true); + +#if 0 + bool ready_to_program(false); + unsigned int count(0); + do { + ready_to_program = init.get_value(); + count++; + + sleep(1); + } while (count < 10 && !ready_to_program); + + if (count == 10) { + std::cout << "FPGA not ready for programming." << std::endl; + exit(-1); + } +#endif +} + +spidev::spidev(std::string fname) +{ + int ret; + int mode = 0; + int speed = 12000000; + int bits = 8; + + fd = open(fname.c_str(), O_RDWR); + + ret = ioctl(fd, SPI_IOC_WR_MODE, &mode); + ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed); + ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits); +} + + +spidev::~spidev() +{ + close(fd); +} + +void spidev::send(char *buf, char *rbuf, unsigned int nbytes) +{ + int ret; + + struct spi_ioc_transfer tr; + tr.tx_buf = (unsigned long) buf; + tr.rx_buf = (unsigned long) rbuf; + tr.len = nbytes; + tr.delay_usecs = 0; + tr.speed_hz = 48000000; + tr.bits_per_word = 8; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + +} + +static void send_file_to_fpga(std::string &file_name, gpio &error, gpio &done) +{ + std::ifstream bitstream; + + std::cout << "File name - " << file_name.c_str() << std::endl; + + bitstream.open(file_name.c_str(), std::ios::binary); + if (!bitstream.is_open()) + std::cout << "File " << file_name << " not opened succesfully." << std::endl; + + spidev spi("/dev/spidev1.0"); + char buf[BUF_SIZE]; + char rbuf[BUF_SIZE]; + + do { + bitstream.read(buf, BUF_SIZE); + spi.send(buf, rbuf, bitstream.gcount()); + + if (error.get_value()) + std::cout << "INIT_B went high, error occured." << std::endl; + + if (!done.get_value()) + std::cout << "Configuration complete." << std::endl; + + } while (bitstream.gcount() == BUF_SIZE); +} + +int main(int argc, char *argv[]) +{ + + gpio gpio_prog_b(PROG_B, OUT); + gpio gpio_init_b(INIT_B, IN); + gpio gpio_done (DONE, IN); + + if (argc == 2) + bit_file = argv[1]; + + std::cout << "FPGA config file: " << bit_file << std::endl; + + prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b); + + std::cout << "Done = " << gpio_done.get_value() << std::endl; + + send_file_to_fpga(bit_file, gpio_init_b, gpio_done); +} + diff --git a/host/apps/omap_debug/test.c b/host/apps/omap_debug/test.c new file mode 100644 index 000000000..36f4d700a --- /dev/null +++ b/host/apps/omap_debug/test.c @@ -0,0 +1,34 @@ +#include + +void +main() +{ + int x; + char *y; + long long z; + + x = 0x01020304; + z = 0x0102030405060708LL; + + printf("%x\n",x); + y = (char *)&x; + printf("%x\n",y[0]); + printf("%x\n",y[1]); + printf("%x\n",y[2]); + printf("%x\n",y[3]); + + printf("Printing z ...\n"); + printf("%llx\n",z); + printf("Printing z done\n"); + + y = (char *)&z; + printf("%x\n",y[0]); + printf("%x\n",y[1]); + printf("%x\n",y[2]); + printf("%x\n",y[3]); + printf("%x\n",y[4]); + printf("%x\n",y[5]); + printf("%x\n",y[6]); + printf("%x\n",y[7]); +} + diff --git a/host/apps/omap_debug/u1e-read-stream.c b/host/apps/omap_debug/u1e-read-stream.c new file mode 100644 index 000000000..4e4c21d9e --- /dev/null +++ b/host/apps/omap_debug/u1e-read-stream.c @@ -0,0 +1,21 @@ +#include +#include +#include + +int main(int rgc, char *argv[]) +{ + int fp, cnt, n; + short buf[1024]; + + n = 0; + + fp = open("/dev/usrp1_e0", O_RDONLY); + printf("fp = %d\n", fp); + + do { + cnt = read(fp, buf, 2048); + n++; +// printf("Bytes read - %d\n", cnt); + } while(n < 10*512); + printf("Data - %hX\n", buf[0]); +} diff --git a/host/apps/omap_debug/usrp1-e-ctl.c b/host/apps/omap_debug/usrp1-e-ctl.c new file mode 100644 index 000000000..045e7ce19 --- /dev/null +++ b/host/apps/omap_debug/usrp1-e-ctl.c @@ -0,0 +1,52 @@ +#include +#include +#include +#include +#include + +#include "usrp1_e.h" + +// Usage: usrp1_e_ctl w|r offset number_of_values val1 val2 .... + +int main(int argc, char *argv[]) +{ + int fp, i, cnt, ret; + struct usrp1_e_ctl *ctl_data; + + if (argc < 4) { + printf("Usage: usrp1_e_ctl w|r offset number_of_values val1 val2 ....\n"); + exit(-1); + } + + cnt = atoi(argv[3]); + + ctl_data = malloc(sizeof(struct usrp1_e_ctl) + cnt*2); + + ctl_data->offset = atoi(argv[2]); + ctl_data->count = cnt; + + printf("Sizeof usrp1_e_ctl struct = %d\n", sizeof(struct usrp1_e_ctl)); + + fp = open("/dev/usrp1_e0", O_RDWR); + printf("fp = %d\n", fp); + + if (*argv[1] == 'w') { + for (i=0; ibuf[i] = atoi(argv[4+i]); + + ret = ioctl(fp, USRP1_E_WRITE_CTL, ctl_data); + printf("Return value from write ioctl = %d\n", ret); + } + + if (*argv[1] == 'r') { + ret = ioctl(fp, USRP1_E_READ_CTL, ctl_data); + printf("Return value from write ioctl = %d\n", ret); + + for (i=0; icount; i++) { + if (!(i%8)) + printf("\nData at %4d :", i); + printf(" %5d", ctl_data->buf[i]); + } + printf("\n"); + } +} diff --git a/host/apps/omap_debug/usrp1-e-ram.c b/host/apps/omap_debug/usrp1-e-ram.c new file mode 100644 index 000000000..d548f7ccd --- /dev/null +++ b/host/apps/omap_debug/usrp1-e-ram.c @@ -0,0 +1,25 @@ +#include +#include +#include + +int main(int rgc, char *argv[]) +{ + int fp, i, cnt; + unsigned short buf[1024]; + unsigned short buf_rb[1024]; + + fp = open("/dev/usrp1_e0", O_RDWR); + printf("fp = %d\n", fp); + + for (i=0; i<1024; i++) + buf[i] = i*256; + write(fp, buf, 2048); + read(fp, buf_rb, 2048); + + printf("Read back %hX %hX\n", buf_rb[0], buf_rb[1]); + + for (i=0; i<1024; i++) { + if (buf[i] != buf_rb[i]) + printf("Read - %hX, expected - %hX\n", buf_rb[i], buf[i]); + } +} diff --git a/host/apps/omap_debug/usrp1-e-read.c b/host/apps/omap_debug/usrp1-e-read.c new file mode 100644 index 000000000..c28f018d5 --- /dev/null +++ b/host/apps/omap_debug/usrp1-e-read.c @@ -0,0 +1,18 @@ +#include +#include +#include + +int main(int rgc, char *argv[]) +{ + int fp, cnt; + short buf[1024]; + + fp = open("/dev/usrp1_e0", O_RDONLY); + printf("fp = %d\n", fp); + + do { + cnt = read(fp, buf, 2048); +// printf("Bytes read - %d\n", cnt); + } while(1); + printf("Data - %hX\n", buf[0]); +} diff --git a/host/apps/omap_debug/usrp1-e-write.c b/host/apps/omap_debug/usrp1-e-write.c new file mode 100644 index 000000000..f29cc7032 --- /dev/null +++ b/host/apps/omap_debug/usrp1-e-write.c @@ -0,0 +1,21 @@ +#include +#include +#include + +int main(int rgc, char *argv[]) +{ + int fp, i, cnt; + short buf[1024]; + + fp = open("/dev/usrp1_e0", O_WRONLY); + printf("fp = %d\n", fp); + + for (i=0; i<1024; i++) { + buf[i] = i; + } + + do { + cnt = write(fp, buf, 2048); + printf("Bytes written - %d\n", cnt); + } while (1); +} -- cgit v1.2.3 From 1e49264f713701a89fb2bc079344273df5a94c06 Mon Sep 17 00:00:00 2001 From: root Date: Tue, 23 Feb 2010 02:09:51 +0000 Subject: Initial checkin of useful shell scripts. --- host/apps/omap_debug/fetch-bin.sh | 1 + host/apps/omap_debug/fetch-kernel.sh | 2 ++ host/apps/omap_debug/fetch-module.sh | 1 + 3 files changed, 4 insertions(+) create mode 100755 host/apps/omap_debug/fetch-bin.sh create mode 100755 host/apps/omap_debug/fetch-kernel.sh create mode 100755 host/apps/omap_debug/fetch-module.sh diff --git a/host/apps/omap_debug/fetch-bin.sh b/host/apps/omap_debug/fetch-bin.sh new file mode 100755 index 000000000..9fb09a10d --- /dev/null +++ b/host/apps/omap_debug/fetch-bin.sh @@ -0,0 +1 @@ +scp balister@192.168.1.182:Download/u1e.bin . diff --git a/host/apps/omap_debug/fetch-kernel.sh b/host/apps/omap_debug/fetch-kernel.sh new file mode 100755 index 000000000..e3bc1b0ad --- /dev/null +++ b/host/apps/omap_debug/fetch-kernel.sh @@ -0,0 +1,2 @@ +scp balister@192.168.1.182:src/git/kernel_usrp/arch/arm/boot/uImage /media/mmcblk0p1/uImage + diff --git a/host/apps/omap_debug/fetch-module.sh b/host/apps/omap_debug/fetch-module.sh new file mode 100755 index 000000000..95140df15 --- /dev/null +++ b/host/apps/omap_debug/fetch-module.sh @@ -0,0 +1 @@ +scp balister@192.168.1.182:src/git/kernel_usrp/drivers/misc/usrp1_e.ko /lib/modules/2.6.33-rc3/kernel/drivers/misc -- cgit v1.2.3 From ba0bbdb3ca3815ca45766cc5f2d06a4d12810f0f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 22 Feb 2010 18:37:29 -0800 Subject: first cut at automatically setting the debug pins --- host/apps/omap_debug/set_debug_pins.py | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100755 host/apps/omap_debug/set_debug_pins.py diff --git a/host/apps/omap_debug/set_debug_pins.py b/host/apps/omap_debug/set_debug_pins.py new file mode 100755 index 000000000..982c290ef --- /dev/null +++ b/host/apps/omap_debug/set_debug_pins.py @@ -0,0 +1,34 @@ +#!/usr/bin/python + +import os + +# Memory Map +misc_base = 0 +uart_base = 1 +spi_base = 2 +i2c_base = 3 +gpio_base = 4 +settings_base = 5 + +# GPIO offset +gpio_pins = 0 +gpio_ddr = 4 +gpio_ctrl_lo = 8 +gpio_ctrl_hi = 12 + +def set_reg(reg, val): + os.system("usrp1-e-ctl w %d 1 %d" % (reg,val)) + +def get_reg(reg): + fin,fout = os.popen4("usrp1-e-ctl r %d 1" % (reg,)) + print fout.read() + +# Set DDRs to output +set_reg(gpio_base+gpio_ddr, 0xFFFF) +set_reg(gpio_base+gpio_ddr+2, 0xFFFF) + +# Set CTRL to Debug #0 ( A is for debug 0, F is for debug 1 ) +set_reg(gpio_base+ctrl_lo, 0xAAAA) +set_reg(gpio_base+ctrl_lo+2, 0xAAAA) +set_reg(gpio_base+ctrl_hi, 0xAAAA) +set_reg(gpio_base+ctrl_hi+2, 0xAAAA) -- cgit v1.2.3 From 3cd7bc9be6420623eb7803e490b39ecc75d83ed9 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 22 Feb 2010 18:43:16 -0800 Subject: full neame --- host/apps/omap_debug/set_debug_pins.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/host/apps/omap_debug/set_debug_pins.py b/host/apps/omap_debug/set_debug_pins.py index 982c290ef..d67cc3e58 100755 --- a/host/apps/omap_debug/set_debug_pins.py +++ b/host/apps/omap_debug/set_debug_pins.py @@ -28,7 +28,7 @@ set_reg(gpio_base+gpio_ddr, 0xFFFF) set_reg(gpio_base+gpio_ddr+2, 0xFFFF) # Set CTRL to Debug #0 ( A is for debug 0, F is for debug 1 ) -set_reg(gpio_base+ctrl_lo, 0xAAAA) -set_reg(gpio_base+ctrl_lo+2, 0xAAAA) -set_reg(gpio_base+ctrl_hi, 0xAAAA) -set_reg(gpio_base+ctrl_hi+2, 0xAAAA) +set_reg(gpio_base+gpio_ctrl_lo, 0xAAAA) +set_reg(gpio_base+gpio_ctrl_lo+2, 0xAAAA) +set_reg(gpio_base+gpio_ctrl_hi, 0xAAAA) +set_reg(gpio_base+gpio_ctrl_hi+2, 0xAAAA) -- cgit v1.2.3 From 89fc3946d6fa590dd8047984ed8718a6ffa4ab77 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 23 Feb 2010 16:35:06 -0800 Subject: use our fancy new debug ports --- usrp2/top/u1e/u1e_core.v | 3 +++ 1 file changed, 3 insertions(+) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 7ac4c8f86..12c566b6c 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -206,6 +206,9 @@ module u1e_core assign debug = { { 1'b0, EM_WAIT0, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, { EM_D } }; + assign debug_gpio_0 = { m0_we, m0_stb, m0_ack, s1_stb, s0_stb, m0_adr[10:0], m0_dat_mosi[15:0] }; + assign debug_gpio_1 = { debug_txd, debug_rxd }; + assign { debug_led[2],debug_led[0],debug_led[1] } = reg_fast; // LEDs are arranged funny on board endmodule // u1e_core -- cgit v1.2.3 From f6ec1e45117f5794facd1cd8e11cbfacabdeb166 Mon Sep 17 00:00:00 2001 From: root Date: Wed, 24 Feb 2010 02:18:54 +0000 Subject: Commit wip. Programs that fetch OS code sync now. --- host/apps/omap_debug/fetch-bin.sh | 1 + host/apps/omap_debug/fetch-kernel.sh | 1 + host/apps/omap_debug/fetch-module.sh | 1 + host/apps/omap_debug/set_debug_pins.py | 4 ++-- 4 files changed, 5 insertions(+), 2 deletions(-) diff --git a/host/apps/omap_debug/fetch-bin.sh b/host/apps/omap_debug/fetch-bin.sh index 9fb09a10d..1ceec4fd2 100755 --- a/host/apps/omap_debug/fetch-bin.sh +++ b/host/apps/omap_debug/fetch-bin.sh @@ -1 +1,2 @@ scp balister@192.168.1.182:Download/u1e.bin . +sync diff --git a/host/apps/omap_debug/fetch-kernel.sh b/host/apps/omap_debug/fetch-kernel.sh index e3bc1b0ad..08b470e9b 100755 --- a/host/apps/omap_debug/fetch-kernel.sh +++ b/host/apps/omap_debug/fetch-kernel.sh @@ -1,2 +1,3 @@ scp balister@192.168.1.182:src/git/kernel_usrp/arch/arm/boot/uImage /media/mmcblk0p1/uImage +sync diff --git a/host/apps/omap_debug/fetch-module.sh b/host/apps/omap_debug/fetch-module.sh index 95140df15..6511958f9 100755 --- a/host/apps/omap_debug/fetch-module.sh +++ b/host/apps/omap_debug/fetch-module.sh @@ -1 +1,2 @@ scp balister@192.168.1.182:src/git/kernel_usrp/drivers/misc/usrp1_e.ko /lib/modules/2.6.33-rc3/kernel/drivers/misc +sync diff --git a/host/apps/omap_debug/set_debug_pins.py b/host/apps/omap_debug/set_debug_pins.py index d67cc3e58..bedabc20c 100755 --- a/host/apps/omap_debug/set_debug_pins.py +++ b/host/apps/omap_debug/set_debug_pins.py @@ -17,10 +17,10 @@ gpio_ctrl_lo = 8 gpio_ctrl_hi = 12 def set_reg(reg, val): - os.system("usrp1-e-ctl w %d 1 %d" % (reg,val)) + os.system("./usrp1-e-ctl w %d 1 %d" % (reg,val)) def get_reg(reg): - fin,fout = os.popen4("usrp1-e-ctl r %d 1" % (reg,)) + fin,fout = os.popen4("./usrp1-e-ctl r %d 1" % (reg,)) print fout.read() # Set DDRs to output -- cgit v1.2.3 From 702c87c3bae259f038d2c10fe32903f391e95de1 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 23 Feb 2010 19:54:54 -0800 Subject: first cut at making a bidirectional 2 port ram for the gpmc data interface ISE chokes on the unequal size ram --- usrp2/control_lib/ram_2port_mixed_width.v | 44 +++++++++++++++++++++++++++++++ usrp2/gpmc/gpmc.v | 24 ++++++++++++----- usrp2/top/u1e/Makefile | 1 + 3 files changed, 63 insertions(+), 6 deletions(-) create mode 100644 usrp2/control_lib/ram_2port_mixed_width.v diff --git a/usrp2/control_lib/ram_2port_mixed_width.v b/usrp2/control_lib/ram_2port_mixed_width.v new file mode 100644 index 000000000..3fa43114f --- /dev/null +++ b/usrp2/control_lib/ram_2port_mixed_width.v @@ -0,0 +1,44 @@ + + +module ram_2port_mixed_width + #(parameter AWIDTH=9) + (input clk16, + input en16, + input we16, + input [10:0] addr16, + input [15:0] di16, + output reg [15:0] do16, + + input clk32, + input en32, + input we32, + input [9:0] addr32, + input [31:0] di32, + output reg [31:0] do32); + + reg [31:0] ram [(1< Date: Thu, 25 Feb 2010 18:26:00 +0000 Subject: added usrp1e conditional compilation, and checking of device node (aka file for now) --- host/lib/CMakeLists.txt | 14 ++++++-- host/lib/usrp/usrp1e/usrp1e_impl.cpp | 69 ++++++++++++++++++++++++++++++++++++ host/lib/usrp/usrp1e/usrp1e_impl.hpp | 23 ++++++++++++ host/lib/usrp/usrp2/usrp2_impl.cpp | 1 - 4 files changed, 103 insertions(+), 4 deletions(-) create mode 100644 host/lib/usrp/usrp1e/usrp1e_impl.cpp create mode 100644 host/lib/usrp/usrp1e/usrp1e_impl.hpp diff --git a/host/lib/CMakeLists.txt b/host/lib/CMakeLists.txt index edfefa127..96fba6e53 100644 --- a/host/lib/CMakeLists.txt +++ b/host/lib/CMakeLists.txt @@ -41,9 +41,17 @@ SET(libuhd_sources ######################################################################## # Conditionally add the usrp1e sources ######################################################################## -LIST(APPEND libuhd_sources - usrp/usrp1e/usrp1e_none.cpp -) +INCLUDE(CheckIncludeFile) +CHECK_INCLUDE_FILE("linux/ioctl.h" HAS_LINUX_IOCTL_H) +IF(HAS_LINUX_IOCTL_H) + LIST(APPEND libuhd_sources + usrp/usrp1e/usrp1e_impl.cpp + ) +ELSE(HAS_LINUX_IOCTL_H) + LIST(APPEND libuhd_sources + usrp/usrp1e/usrp1e_none.cpp + ) +ENDIF(HAS_LINUX_IOCTL_H) ######################################################################## # Setup libuhd library diff --git a/host/lib/usrp/usrp1e/usrp1e_impl.cpp b/host/lib/usrp/usrp1e/usrp1e_impl.cpp new file mode 100644 index 000000000..93265ab17 --- /dev/null +++ b/host/lib/usrp/usrp1e/usrp1e_impl.cpp @@ -0,0 +1,69 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include +#include "usrp1e_impl.hpp" + +using namespace uhd; +using namespace uhd::usrp; + +/*********************************************************************** + * Helper Functions + **********************************************************************/ +static bool file_exists(const std::string &file_path){ + return access(file_path.c_str(), F_OK) == 0; +} + +/*********************************************************************** + * Discovery + **********************************************************************/ +device_addrs_t usrp1e::discover(const device_addr_t &device_addr){ + device_addrs_t usrp1e_addrs; + + //if a node was provided, use it and only it + if (device_addr.has_key("node")){ + if (not file_exists(device_addr["node"])) return usrp1e_addrs; + device_addr_t new_addr; + new_addr["name"] = "USRP1E"; + new_addr["type"] = "usrp1e"; + new_addr["node"] = device_addr["node"]; + usrp1e_addrs.push_back(new_addr); + } + + //otherwise look for a few nodes at small indexes + else{ + for(size_t i = 0; i < 5; i++){ + std::string node = str(boost::format("/dev/usrp1_e%d") % i); + if (not file_exists(node)) continue; + device_addr_t new_addr; + new_addr["name"] = "USRP1E"; + new_addr["type"] = "usrp1e"; + new_addr["node"] = node; + usrp1e_addrs.push_back(new_addr); + } + } + + return usrp1e_addrs; +} + +/*********************************************************************** + * Make + **********************************************************************/ +device::sptr usrp1e::make(const device_addr_t &){ + throw std::runtime_error("not implemented yet"); +} diff --git a/host/lib/usrp/usrp1e/usrp1e_impl.hpp b/host/lib/usrp/usrp1e/usrp1e_impl.hpp new file mode 100644 index 000000000..3f5f89ec6 --- /dev/null +++ b/host/lib/usrp/usrp1e/usrp1e_impl.hpp @@ -0,0 +1,23 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include + +#ifndef INCLUDED_USRP1E_IMPL_HPP +#define INCLUDED_USRP1E_IMPL_HPP + +#endif /* INCLUDED_USRP1E_IMPL_HPP */ diff --git a/host/lib/usrp/usrp2/usrp2_impl.cpp b/host/lib/usrp/usrp2/usrp2_impl.cpp index 06876d241..5aa5d6e8d 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.cpp +++ b/host/lib/usrp/usrp2/usrp2_impl.cpp @@ -62,7 +62,6 @@ uhd::device_addrs_t usrp2::discover(const device_addr_t &hint){ device_addr_t new_addr; new_addr["name"] = "USRP2"; new_addr["type"] = "usrp2"; - new_addr["transport"] = "udp"; new_addr["addr"] = ip_addr.to_string(); usrp2_addrs.push_back(new_addr); break; -- cgit v1.2.3 From 778a41b393b7d517463950c4ac014d3a2eb8eceb Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 25 Feb 2010 19:43:20 +0000 Subject: added usrp1e fpga loader --- host/include/uhd/usrp/usrp1e.hpp | 6 + host/lib/CMakeLists.txt | 21 ++- host/lib/usrp/usrp1e/fpga-downloader.cc | 262 ++++++++++++++++++++++++++++++++ host/lib/usrp/usrp1e/usrp1e_none.cpp | 4 + 4 files changed, 288 insertions(+), 5 deletions(-) create mode 100644 host/lib/usrp/usrp1e/fpga-downloader.cc diff --git a/host/include/uhd/usrp/usrp1e.hpp b/host/include/uhd/usrp/usrp1e.hpp index 00748e55f..60a6a191a 100644 --- a/host/include/uhd/usrp/usrp1e.hpp +++ b/host/include/uhd/usrp/usrp1e.hpp @@ -41,6 +41,12 @@ public: * \return a device sptr to a new usrp1e */ static device::sptr make(const device_addr_t &addr); + + /*! + * Load the FPGA with an image file. + * \param bin_file the name of the fpga image file + */ + static void load_fpga(const std::string &bin_file); }; }} //namespace diff --git a/host/lib/CMakeLists.txt b/host/lib/CMakeLists.txt index 96fba6e53..33314e729 100644 --- a/host/lib/CMakeLists.txt +++ b/host/lib/CMakeLists.txt @@ -41,17 +41,28 @@ SET(libuhd_sources ######################################################################## # Conditionally add the usrp1e sources ######################################################################## -INCLUDE(CheckIncludeFile) -CHECK_INCLUDE_FILE("linux/ioctl.h" HAS_LINUX_IOCTL_H) -IF(HAS_LINUX_IOCTL_H) +INCLUDE(CheckIncludeFiles) +SET(usrp1e_required_headers + linux/ioctl.h + linux/spi/spidev.h +) +CHECK_INCLUDE_FILES( + "${usrp1e_required_headers}" + HAS_USRP1E_REQUIRED_HEADERS +) + +IF(HAS_USRP1E_REQUIRED_HEADERS) + MESSAGE(STATUS "Building usrp1e support...") LIST(APPEND libuhd_sources + usrp/usrp1e/fpga-downloader.cc usrp/usrp1e/usrp1e_impl.cpp ) -ELSE(HAS_LINUX_IOCTL_H) +ELSE(HAS_USRP1E_REQUIRED_HEADERS) + MESSAGE(STATUS "Skipping usrp1e support...") LIST(APPEND libuhd_sources usrp/usrp1e/usrp1e_none.cpp ) -ENDIF(HAS_LINUX_IOCTL_H) +ENDIF(HAS_USRP1E_REQUIRED_HEADERS) ######################################################################## # Setup libuhd library diff --git a/host/lib/usrp/usrp1e/fpga-downloader.cc b/host/lib/usrp/usrp1e/fpga-downloader.cc new file mode 100644 index 000000000..15023d945 --- /dev/null +++ b/host/lib/usrp/usrp1e/fpga-downloader.cc @@ -0,0 +1,262 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +/* + * Configuration connections + * + * CCK - MCSPI1_CLK + * DIN - MCSPI1_MOSI + * PROG_B - GPIO_175 - output (change mux) + * DONE - GPIO_173 - input (change mux) + * INIT_B - GPIO_114 - input (change mux) + * +*/ + +const unsigned int PROG_B = 175; +const unsigned int DONE = 173; +const unsigned int INIT_B = 114; + +static std::string bit_file = "safe_u1e.bin"; + +const int BUF_SIZE = 4096; + +enum gpio_direction {IN, OUT}; + +class gpio { + public: + + gpio(unsigned int gpio_num, gpio_direction pin_direction); + + bool get_value(); + void set_value(bool state); + + private: + + std::stringstream base_path; + std::fstream value_file; +}; + +class spidev { + public: + + spidev(std::string dev_name); + ~spidev(); + + void send(char *wbuf, char *rbuf, unsigned int nbytes); + + private: + + int fd; + +}; + +gpio::gpio(unsigned int gpio_num, gpio_direction pin_direction) +{ + std::fstream export_file; + + export_file.open("/sys/class/gpio/export", std::ios::out); + if (!export_file.is_open()) ///\todo Poor error handling + std::cout << "Failed to open gpio export file." << std::endl; + + export_file << gpio_num << std::endl; + + base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush; + + std::fstream direction_file; + std::string direction_file_name; + + direction_file_name = base_path.str() + "/direction"; + + direction_file.open(direction_file_name.c_str()); + if (!direction_file.is_open()) + std::cout << "Failed to open direction file." << std::endl; + if (pin_direction == OUT) + direction_file << "out" << std::endl; + else + direction_file << "in" << std::endl; + + std::string value_file_name; + + value_file_name = base_path.str() + "/value"; + + value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out); + if (!value_file.is_open()) + std::cout << "Failed to open value file." << std::endl; +} + +bool gpio::get_value() +{ + + std::string val; + + std::getline(value_file, val); + value_file.seekg(0); + + if (val == "0") + return false; + else if (val == "1") + return true; + else + std::cout << "Data read from value file|" << val << "|" << std::endl; + + return false; +} + +void gpio::set_value(bool state) +{ + + if (state) + value_file << "1" << std::endl; + else + value_file << "0" << std::endl; +} + +static void prepare_fpga_for_configuration(gpio &prog, gpio &)//init) +{ + + prog.set_value(true); + prog.set_value(false); + prog.set_value(true); + +#if 0 + bool ready_to_program(false); + unsigned int count(0); + do { + ready_to_program = init.get_value(); + count++; + + sleep(1); + } while (count < 10 && !ready_to_program); + + if (count == 10) { + std::cout << "FPGA not ready for programming." << std::endl; + exit(-1); + } +#endif +} + +spidev::spidev(std::string fname) +{ + int ret; + int mode = 0; + int speed = 12000000; + int bits = 8; + + fd = open(fname.c_str(), O_RDWR); + + ret = ioctl(fd, SPI_IOC_WR_MODE, &mode); + ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed); + ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits); +} + + +spidev::~spidev() +{ + close(fd); +} + +void spidev::send(char *buf, char *rbuf, unsigned int nbytes) +{ + int ret; + + struct spi_ioc_transfer tr; + tr.tx_buf = (unsigned long) buf; + tr.rx_buf = (unsigned long) rbuf; + tr.len = nbytes; + tr.delay_usecs = 0; + tr.speed_hz = 48000000; + tr.bits_per_word = 8; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + +} + +static void send_file_to_fpga(std::string &file_name, gpio &error, gpio &done) +{ + std::ifstream bitstream; + + std::cout << "File name - " << file_name.c_str() << std::endl; + + bitstream.open(file_name.c_str(), std::ios::binary); + if (!bitstream.is_open()) + std::cout << "File " << file_name << " not opened succesfully." << std::endl; + + spidev spi("/dev/spidev1.0"); + char buf[BUF_SIZE]; + char rbuf[BUF_SIZE]; + + do { + bitstream.read(buf, BUF_SIZE); + spi.send(buf, rbuf, bitstream.gcount()); + + if (error.get_value()) + std::cout << "INIT_B went high, error occured." << std::endl; + + if (!done.get_value()) + std::cout << "Configuration complete." << std::endl; + + } while (bitstream.gcount() == BUF_SIZE); +} + +/* +int main(int argc, char *argv[]) +{ + + gpio gpio_prog_b(PROG_B, OUT); + gpio gpio_init_b(INIT_B, IN); + gpio gpio_done (DONE, IN); + + if (argc == 2) + bit_file = argv[1]; + + std::cout << "FPGA config file: " << bit_file << std::endl; + + prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b); + + std::cout << "Done = " << gpio_done.get_value() << std::endl; + + send_file_to_fpga(bit_file, gpio_init_b, gpio_done); +} +*/ + +#include +void uhd::usrp::usrp1e::load_fpga(const std::string &bin_file){ + gpio gpio_prog_b(PROG_B, OUT); + gpio gpio_init_b(INIT_B, IN); + gpio gpio_done (DONE, IN); + + std::cout << "FPGA config file: " << bin_file << std::endl; + + prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b); + + std::cout << "Done = " << gpio_done.get_value() << std::endl; + + send_file_to_fpga(bit_file, gpio_init_b, gpio_done); +} diff --git a/host/lib/usrp/usrp1e/usrp1e_none.cpp b/host/lib/usrp/usrp1e/usrp1e_none.cpp index 1c8cf9a5b..ac0b12a75 100644 --- a/host/lib/usrp/usrp1e/usrp1e_none.cpp +++ b/host/lib/usrp/usrp1e/usrp1e_none.cpp @@ -32,3 +32,7 @@ device_addrs_t usrp1e::discover(const device_addr_t &){ device::sptr usrp1e::make(const device_addr_t &){ throw std::runtime_error("this build has no usrp1e support"); } + +void usrp1e::load_fpga(const std::string &){ + throw std::runtime_error("this build has no usrp1e support"); +} -- cgit v1.2.3 From 030f6a21539207c058b982ffade384ec7a937ec2 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Feb 2010 16:50:09 -0800 Subject: First cut at passing data buffers around on GPMC bus --- usrp2/gpmc/dbsm.v | 88 +++++++++++++++++++++++++++++++++++++++++++++++ usrp2/gpmc/gpmc.v | 45 ++++++++++++++++++------ usrp2/models/gpmc_model.v | 23 ++++++++++--- usrp2/top/u1e/tb_u1e.v | 11 ++++-- usrp2/top/u1e/u1e.v | 3 +- usrp2/top/u1e/u1e_core.v | 20 +++++++---- 6 files changed, 165 insertions(+), 25 deletions(-) create mode 100644 usrp2/gpmc/dbsm.v diff --git a/usrp2/gpmc/dbsm.v b/usrp2/gpmc/dbsm.v new file mode 100644 index 000000000..0f27be46a --- /dev/null +++ b/usrp2/gpmc/dbsm.v @@ -0,0 +1,88 @@ + +module bsm + (input clk, input reset, input clear, + input write_done, + input read_done, + output readable, + output writeable); + + reg state; + localparam ST_WRITEABLE = 0; + localparam ST_READABLE = 1; + + always @(posedge clk) + if(reset | clear) + state <= ST_WRITEABLE; + else + case(state) + ST_WRITEABLE : + if(write_done) + state <= ST_READABLE; + ST_READABLE : + if(read_done) + state <= ST_WRITEABLE; + endcase // case (state) + + assign readable = (state == ST_READABLE); + assign writeable = (state == ST_WRITEABLE); + +endmodule // bsm + +module dbsm + (input clk, input reset, input clear, + output reg read_sel, output read_ready, input read_done, + output reg write_sel, output write_ready, input write_done); + + localparam NUM_BUFS = 2; + + wire [NUM_BUFS-1:0] readable, writeable, read_done_buf, write_done_buf; + + // Two of these buffer state machines + genvar i; + for(i=0;i Date: Thu, 25 Feb 2010 16:50:29 -0800 Subject: ISE chokes on the pure verilog version so we use the macro --- usrp2/control_lib/ram_2port_mixed_width.v | 53 ++++++++++++++++++++++++++++--- 1 file changed, 49 insertions(+), 4 deletions(-) diff --git a/usrp2/control_lib/ram_2port_mixed_width.v b/usrp2/control_lib/ram_2port_mixed_width.v index 3fa43114f..e10321959 100644 --- a/usrp2/control_lib/ram_2port_mixed_width.v +++ b/usrp2/control_lib/ram_2port_mixed_width.v @@ -1,5 +1,3 @@ - - module ram_2port_mixed_width #(parameter AWIDTH=9) (input clk16, @@ -7,14 +5,58 @@ module ram_2port_mixed_width input we16, input [10:0] addr16, input [15:0] di16, - output reg [15:0] do16, + output [15:0] do16, input clk32, input en32, input we32, input [9:0] addr32, input [31:0] di32, - output reg [31:0] do32); + output [31:0] do32); + + RAMB16BWER #(.DATA_WIDTH_A(18), // Valid values are 0, 1, 2, 4, 9, 18, or 36 + .DATA_WIDTH_B(36), // Valid values are 0, 1, 2, 4, 9, 18, or 36 + .DOA_REG(0), // Specifies to enable=1/disable=0 port A output registers + .DOB_REG(0), // Specifies to enable=1/disable=0 port B output registers + .INIT_A(36'h000000000), // Initial values on A output port + .INIT_B(36'h000000000), // Initial values on B output port + .RSTTYPE("SYNC"), // Specifes reset type to be "SYNC" or "ASYNC" + .SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY", + // "GENERATE_X_ONLY" or "NONE" + .SRVAL_A(36'h000000000), // Set/Reset value for A port output + .SRVAL_B(36'h000000000), // Set/Reset value for B port output + .WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE" + .WRITE_MODE_B("WRITE_FIRST")) // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE" + RAMB16BWER_inst (.DOA(do16), // 32-bit A port data output + .DOB(do32), // 32-bit B port data output + .DOPA(), // 4-bit A port parity data output + .DOPB(), // 4-bit B port parity data output + .ADDRA(addr16), // 14-bit A port address input + .ADDRB(addr32), // 14-bit B port address input + .CLKA(clk16), // 1-bit A port clock input + .CLKB(clk32), // 1-bit B port clock input + .DIA(di16), // 32-bit A port data input + .DIB(di32), // 32-bit B port data input + .DIPA(0), // 4-bit A port parity data input + .DIPB(0), // 4-bit B port parity data input + .ENA(en16), // 1-bit A port enable input + .ENB(en32), // 1-bit B port enable input + .REGCEA(0), // 1-bit A port output register enable input + .REGCEB(0), // 1-bit B port output register enable input + .RSTA(0), // 1-bit A port reset input + .RSTB(0), // 1-bit B port reset input + .WEA({2{we16}}), // 4-bit A port write enable input + .WEB({4{we32}}) // 4-bit B port write enable input + ); + +endmodule // ram_2port_mixed_width + + + + +// ISE 10.1.03 chokes on the following + +/* reg [31:0] ram [(1< Date: Thu, 25 Feb 2010 18:37:25 -0800 Subject: Switched xilinx primitives because they order the bits funny in the other one --- usrp2/control_lib/ram_2port_mixed_width.v | 127 +++++++++++++++++++----------- 1 file changed, 79 insertions(+), 48 deletions(-) diff --git a/usrp2/control_lib/ram_2port_mixed_width.v b/usrp2/control_lib/ram_2port_mixed_width.v index e10321959..e84b0da02 100644 --- a/usrp2/control_lib/ram_2port_mixed_width.v +++ b/usrp2/control_lib/ram_2port_mixed_width.v @@ -1,54 +1,85 @@ + module ram_2port_mixed_width - #(parameter AWIDTH=9) - (input clk16, - input en16, - input we16, - input [10:0] addr16, - input [15:0] di16, - output [15:0] do16, - - input clk32, - input en32, - input we32, - input [9:0] addr32, - input [31:0] di32, - output [31:0] do32); + (input clk16, + input en16, + input we16, + input [10:0] addr16, + input [15:0] di16, + output [15:0] do16, + input clk32, + input en32, + input we32, + input [9:0] addr32, + input [31:0] di32, + output [31:0] do32); + + wire en32a = en32 & ~addr32[9]; + wire en32b = en32 & addr32[9]; + wire en16a = en16 & ~addr16[9]; + wire en16b = en16 & addr16[9]; - RAMB16BWER #(.DATA_WIDTH_A(18), // Valid values are 0, 1, 2, 4, 9, 18, or 36 - .DATA_WIDTH_B(36), // Valid values are 0, 1, 2, 4, 9, 18, or 36 - .DOA_REG(0), // Specifies to enable=1/disable=0 port A output registers - .DOB_REG(0), // Specifies to enable=1/disable=0 port B output registers - .INIT_A(36'h000000000), // Initial values on A output port - .INIT_B(36'h000000000), // Initial values on B output port - .RSTTYPE("SYNC"), // Specifes reset type to be "SYNC" or "ASYNC" - .SIM_COLLISION_CHECK("ALL"), // Collision check enable "ALL", "WARNING_ONLY", - // "GENERATE_X_ONLY" or "NONE" - .SRVAL_A(36'h000000000), // Set/Reset value for A port output - .SRVAL_B(36'h000000000), // Set/Reset value for B port output - .WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE" - .WRITE_MODE_B("WRITE_FIRST")) // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE" - RAMB16BWER_inst (.DOA(do16), // 32-bit A port data output - .DOB(do32), // 32-bit B port data output - .DOPA(), // 4-bit A port parity data output - .DOPB(), // 4-bit B port parity data output - .ADDRA(addr16), // 14-bit A port address input - .ADDRB(addr32), // 14-bit B port address input - .CLKA(clk16), // 1-bit A port clock input - .CLKB(clk32), // 1-bit B port clock input - .DIA(di16), // 32-bit A port data input - .DIB(di32), // 32-bit B port data input - .DIPA(0), // 4-bit A port parity data input - .DIPB(0), // 4-bit B port parity data input - .ENA(en16), // 1-bit A port enable input - .ENB(en32), // 1-bit B port enable input - .REGCEA(0), // 1-bit A port output register enable input - .REGCEB(0), // 1-bit B port output register enable input - .RSTA(0), // 1-bit A port reset input - .RSTB(0), // 1-bit B port reset input - .WEA({2{we16}}), // 4-bit A port write enable input - .WEB({4{we32}}) // 4-bit B port write enable input - ); + wire [31:0] do32a, do32b; + wire [15:0] do16a, do16b; + + assign do32 = addr32[9] ? do32b : do32a; + assign do16 = addr16[10] ? do16b : do16a; + RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000), + .INIT_B(18'h00000), + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(18'h00000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE + ) + RAMB16BWE_S36_S18_0 (.DOA(do32a), // Port A 32-bit Data Output + .DOB(do16a), // Port B 16-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .DOPB(), // Port B 2-bit Parity Output + .ADDRA(addr32[8:0]), // Port A 9-bit Address Input + .ADDRB(addr16[9:0]), // Port B 10-bit Address Input + .CLKA(clk32), // Port A 1-bit Clock + .CLKB(clk16), // Port B 1-bit Clock + .DIA(di32), // Port A 32-bit Data Input + .DIB(di16), // Port B 16-bit Data Input + .DIPA(0), // Port A 4-bit parity Input + .DIPB(0), // Port-B 2-bit parity Input + .ENA(en32a), // Port A 1-bit RAM Enable Input + .ENB(en16a), // Port B 1-bit RAM Enable Input + .SSRA(0), // Port A 1-bit Synchronous Set/Reset Input + .SSRB(0), // Port B 1-bit Synchronous Set/Reset Input + .WEA({4{we32}}), // Port A 4-bit Write Enable Input + .WEB({2{we16}}) // Port B 2-bit Write Enable Input + ); + + RAMB16BWE_S36_S18 #(.INIT_A(36'h000000000), + .INIT_B(18'h00000), + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(18'h00000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST") // WRITE_FIRST, READ_FIRST or NO_CHANGE + ) + RAMB16BWE_S36_S18_1 (.DOA(do32b), // Port A 32-bit Data Output + .DOB(do16b), // Port B 16-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .DOPB(), // Port B 2-bit Parity Output + .ADDRA(addr32[8:0]), // Port A 9-bit Address Input + .ADDRB(addr16[9:0]), // Port B 10-bit Address Input + .CLKA(clk32), // Port A 1-bit Clock + .CLKB(clk16), // Port B 1-bit Clock + .DIA(di32), // Port A 32-bit Data Input + .DIB(di16), // Port B 16-bit Data Input + .DIPA(0), // Port A 4-bit parity Input + .DIPB(0), // Port-B 2-bit parity Input + .ENA(en32b), // Port A 1-bit RAM Enable Input + .ENB(en16b), // Port B 1-bit RAM Enable Input + .SSRA(0), // Port A 1-bit Synchronous Set/Reset Input + .SSRB(0), // Port B 1-bit Synchronous Set/Reset Input + .WEA({4{we32}}), // Port A 4-bit Write Enable Input + .WEB({2{we16}}) // Port B 2-bit Write Enable Input + ); + endmodule // ram_2port_mixed_width -- cgit v1.2.3 From 2f9b93f32ed8e561a0e92e2e32af03707475011c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Feb 2010 18:38:07 -0800 Subject: edge sync on done signals so we only fill/empty one buffer --- usrp2/gpmc/edge_sync.v | 22 ++++++++++++++++++++++ usrp2/gpmc/gpmc.v | 12 ++++++++++-- 2 files changed, 32 insertions(+), 2 deletions(-) create mode 100644 usrp2/gpmc/edge_sync.v diff --git a/usrp2/gpmc/edge_sync.v b/usrp2/gpmc/edge_sync.v new file mode 100644 index 000000000..5d9417c08 --- /dev/null +++ b/usrp2/gpmc/edge_sync.v @@ -0,0 +1,22 @@ + + +module edge_sync + #(parameter POSEDGE = 1) + (input clk, + input rst, + input sig, + output trig); + + reg [1:0] delay; + + always @(posedge clk) + if(rst) + delay <= 2'b00; + else + delay <= {delay[0],sig}; + + assign trig = POSEDGE ? (delay==2'b01) : (delay==2'b10); + +endmodule // edge_sync + + diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v index 91d02bfec..831df3b4c 100644 --- a/usrp2/gpmc/gpmc.v +++ b/usrp2/gpmc/gpmc.v @@ -32,7 +32,11 @@ module gpmc // //////////////////////////////////////////// // Write path wire read_sel_in, write_sel_in, clear_in; - wire write_done_in = ~EM_NCS4 & ~EM_NWE & (EM_A == 10'h3FF); + wire write_done_in; + + edge_sync #(.POSEDGE(0)) + edge_sync_wdi(.clk(wb_clk), .rst(wb_rst), + .sig(~EM_NCS4 & ~EM_NWE & (EM_A == 10'h3FF)), .trig(write_done_in)); ram_2port_mixed_width buffer_in (.clk16(wb_clk), .en16(~EM_NCS4), .we16(~EM_NWE), .addr16({write_sel_in,EM_A}), .di16(EM_D), .do16(), @@ -47,7 +51,11 @@ module gpmc // //////////////////////////////////////////// // Read path wire read_sel_out, write_sel_out, clear_out; - wire read_done_out = ~EM_NCS4 & ~EM_NOE & (EM_A == 10'h3FF); + wire read_done_out; + + edge_sync #(.POSEDGE(0)) + edge_sync_rdo(.clk(wb_clk), .rst(wb_rst), + .sig(~EM_NCS4 & ~EM_NOE & (EM_A == 10'h3FF)), .trig(read_done_out)); ram_2port_mixed_width buffer_out (.clk16(wb_clk), .en16(~EM_NCS4), .we16(0), .addr16({read_sel_out,EM_A}), .di16(0), .do16(EM_D_ram), -- cgit v1.2.3 From d808829fee0c93f22c2ff3b34d0772d7cb91df5c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Feb 2010 18:38:35 -0800 Subject: corrected logic --- usrp2/gpmc/dbsm.v | 24 +++++++----------------- 1 file changed, 7 insertions(+), 17 deletions(-) diff --git a/usrp2/gpmc/dbsm.v b/usrp2/gpmc/dbsm.v index 0f27be46a..ff61859ec 100644 --- a/usrp2/gpmc/dbsm.v +++ b/usrp2/gpmc/dbsm.v @@ -56,28 +56,18 @@ module dbsm full <= 0; end else - if(write_done) - if(writeable[write_sel]==(NUM_BUFS-1)) - begin - write_sel <= 0; - if(read_sel == 0) - full <= 1; - end + if(write_done & writeable[write_sel]) + if(write_sel ==(NUM_BUFS-1)) + write_sel <= 0; else - begin - write_sel <= write_sel + 1; - if(read_sel == write_sel + 1) - full <= 1; - end // else: !if(writeable[write_sel]==(NUM_BUFS-1)) - else if(read_done) - full <= 0; - + write_sel <= write_sel + 1; + always @(posedge clk) if(reset | clear) read_sel <= 0; else - if(read_done) - if(readable[read_sel]==(NUM_BUFS-1)) + if(read_done & readable[read_sel]) + if(read_sel==(NUM_BUFS-1)) read_sel <= 0; else read_sel <= read_sel + 1; -- cgit v1.2.3 From c8e869b2e685cb8a5c012498b7f47aaadf39698a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Feb 2010 18:38:48 -0800 Subject: loopback and test --- usrp2/models/gpmc_model.v | 11 ++++++----- usrp2/top/u1e/u1e_core.v | 34 ++++++++++++++++++++++++++++++++-- 2 files changed, 38 insertions(+), 7 deletions(-) diff --git a/usrp2/models/gpmc_model.v b/usrp2/models/gpmc_model.v index 1e7dcdde5..3424671bd 100644 --- a/usrp2/models/gpmc_model.v +++ b/usrp2/models/gpmc_model.v @@ -78,11 +78,12 @@ module gpmc_model #1000; GPMC_Read(1,36); #1000; - GPMC_Write(0,36,16'hF00D); - GPMC_Write(0,38,16'hF00D); - GPMC_Write(0,40,16'hF00D); - GPMC_Write(0,11'h7FFE,16'hF00D); - #1000; + GPMC_Write(0,36,16'h1234); + GPMC_Write(0,38,16'h5678); + GPMC_Write(0,40,16'h9abc); + GPMC_Write(0,11'h2F4,16'hF00D); + GPMC_Write(0,11'h7FE,16'hF00D); + #100000; $finish; end diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 7feafeda8..e14152f33 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -26,6 +26,13 @@ module u1e_core wire [aw-1:0] m0_adr; wire [sw-1:0] m0_sel; wire m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty; + + // FIFO buffers + wire [31:0] read_data, write_data; + wire [8:0] read_addr, write_addr; + reg [8:0] addr; + + wire read_done, write_done, read_en, write_en, read_ready, write_ready; gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), @@ -43,9 +50,32 @@ module u1e_core .read_ready(read_ready), .read_done(read_done), .write_en(write_en), .write_addr(write_addr), .write_data(write_data), .write_ready(write_ready), .write_done(write_done) ); + + // Loopback + assign write_data = read_data; + + reg [10:0] counter; + assign write_addr = counter[10:2]; + assign read_addr = counter[10:2]; - assign wb_clk = clk_fpga; - + assign read_done = (counter == 11'h7FF); + assign write_done = (counter == 11'h7FF); + + always @(posedge wb_clk) + if(wb_rst) + counter <= 0; + else + if(counter == 0) + counter <= write_ready & read_ready; + else if(counter == 11'h7FF) + counter <= 0; + else + counter <= counter + 1; + + assign read_en = (counter[1:0] == 1); + assign write_en = (counter[1:0] == 2); + + // ///////////////////////////////////////////////////////////////////////////////////// // Wishbone Intercon, single master wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, -- cgit v1.2.3 From bcf582bab2544a1d519f84c659322c4c4adc59a1 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Feb 2010 18:48:51 -0800 Subject: fix syntax error which icarus allowed (filed a bug with them) --- usrp2/gpmc/dbsm.v | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/usrp2/gpmc/dbsm.v b/usrp2/gpmc/dbsm.v index ff61859ec..530af7205 100644 --- a/usrp2/gpmc/dbsm.v +++ b/usrp2/gpmc/dbsm.v @@ -39,13 +39,15 @@ module dbsm // Two of these buffer state machines genvar i; - for(i=0;i Date: Thu, 25 Feb 2010 18:49:20 -0800 Subject: point to the new files --- usrp2/top/u1e/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 306ab5bae..3412e227d 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -176,6 +176,8 @@ timing/time_sender.v \ timing/time_sync.v \ timing/timer.v \ gpmc/gpmc.v \ +gpmc/edge_sync.v \ +gpmc/dbsm.v \ top/u1e/u1e_core.v \ top/u1e/u1e.ucf \ top/u1e/u1e.v -- cgit v1.2.3 From 67dd6732b70c1cd35a7134f4830b09b893255935 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Feb 2010 19:43:01 -0800 Subject: gpmc debug pins --- usrp2/gpmc/gpmc.v | 9 ++++++++- usrp2/top/u1e/u1e_core.v | 9 ++++++--- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v index 831df3b4c..cf1357232 100644 --- a/usrp2/gpmc/gpmc.v +++ b/usrp2/gpmc/gpmc.v @@ -16,7 +16,8 @@ module gpmc // RAM Interface signals input ram_clk, input read_en, input [8:0] read_addr, output [31:0] read_data, output read_ready, input read_done, - input write_en, input [8:0] write_addr, input [31:0] write_data, output write_ready, input write_done + input write_en, input [8:0] write_addr, input [31:0] write_data, output write_ready, input write_done, + output [31:0] debug ); wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); @@ -65,6 +66,12 @@ module gpmc .read_sel(read_sel_out), .read_ready(rx_have_data), .read_done(read_done_out), .write_sel(write_sel_out), .write_ready(write_ready), .write_done(write_done)); + + assign debug = { { 2'b00, write_done_in, write_sel_in, read_en, read_sel_in, read_ready, read_done}, + { 2'b00, read_sel_out, write_en, write_sel_out, read_done_out, write_ready, write_done }, + { 8'd0 }, + { 8'd0 } }; + // CS6 is Control, Wishbone bus bridge (wb master) // Sync version reg [1:0] cs_del, we_del, oe_del; diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index e14152f33..6706d4aac 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -33,6 +33,8 @@ module u1e_core reg [8:0] addr; wire read_done, write_done, read_en, write_en, read_ready, write_ready; + + wire [31:0] debug_gpmc; gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), @@ -49,7 +51,8 @@ module u1e_core .read_en(read_en), .read_addr(read_addr), .read_data(read_data), .read_ready(read_ready), .read_done(read_done), .write_en(write_en), .write_addr(write_addr), .write_data(write_data), - .write_ready(write_ready), .write_done(write_done) ); + .write_ready(write_ready), .write_done(write_done), + .debug(debug_gpmc)); // Loopback assign write_data = read_data; @@ -241,10 +244,10 @@ module u1e_core // Debug circuitry assign debug_clk = { EM_CLK, clk_fpga }; - assign debug = { { 1'b0, EM_WAIT0, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, + assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, { EM_D } }; - assign debug_gpio_0 = { m0_we, m0_stb, m0_ack, s1_stb, s0_stb, m0_adr[10:0], m0_dat_mosi[15:0] }; + assign debug_gpio_0 = { debug_gpmc }; assign debug_gpio_1 = { debug_txd, debug_rxd }; assign { debug_led[2],debug_led[0],debug_led[1] } = reg_fast; // LEDs are arranged funny on board -- cgit v1.2.3 From e775ce6c17d1e43865cdd3f9472157d0d2d26b92 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Feb 2010 21:09:34 -0800 Subject: invert the pushbuttons since they are active low --- usrp2/top/u1e/u1e.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 066d02ca4..329d61aa9 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -21,9 +21,9 @@ module u1e IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(debug_pb[2]), + u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb[2]), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), - .debug_pb(debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), + .debug_pb(~debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), -- cgit v1.2.3 From db60b00d7a1bafe4f3f49e1ec2367897fc8c71ab Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Feb 2010 21:10:26 -0800 Subject: enable was on the wrong address pin, needs to be the highest order one --- usrp2/control_lib/ram_2port_mixed_width.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/control_lib/ram_2port_mixed_width.v b/usrp2/control_lib/ram_2port_mixed_width.v index e84b0da02..fae7d8de3 100644 --- a/usrp2/control_lib/ram_2port_mixed_width.v +++ b/usrp2/control_lib/ram_2port_mixed_width.v @@ -15,8 +15,8 @@ module ram_2port_mixed_width wire en32a = en32 & ~addr32[9]; wire en32b = en32 & addr32[9]; - wire en16a = en16 & ~addr16[9]; - wire en16b = en16 & addr16[9]; + wire en16a = en16 & ~addr16[10]; + wire en16b = en16 & addr16[10]; wire [31:0] do32a, do32b; wire [15:0] do16a, do16b; -- cgit v1.2.3 From 4288c956b45143f3cab7b798758ff41ffb43aa4a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Feb 2010 21:55:13 -0800 Subject: debug pins --- usrp2/top/u1e/u1e_core.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 6706d4aac..2645225a0 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -216,7 +216,7 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////// // GPIOs -- Slave #4 - +/* wire [31:0] atr_lines; wire [31:0] debug_gpio_0, debug_gpio_1; @@ -226,7 +226,7 @@ module u1e_core .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), .gpio( {io_tx,io_rx} ) ); - +*/ // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #5 @@ -247,6 +247,7 @@ module u1e_core assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, { EM_D } }; + assign {io_tx,io_rx} = debug_gpmc; assign debug_gpio_0 = { debug_gpmc }; assign debug_gpio_1 = { debug_txd, debug_rxd }; -- cgit v1.2.3 From 1b965831ae7588c7879d84de4e5fbd78ca614761 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 26 Feb 2010 11:01:19 +0000 Subject: made app to load usrp1e fpga images, and tested it to be working --- host/apps/CMakeLists.txt | 4 ++- host/apps/usrp1e_load_fpga.cpp | 47 +++++++++++++++++++++++++++++++++ host/lib/usrp/usrp1e/fpga-downloader.cc | 6 ++--- 3 files changed, 53 insertions(+), 4 deletions(-) create mode 100644 host/apps/usrp1e_load_fpga.cpp diff --git a/host/apps/CMakeLists.txt b/host/apps/CMakeLists.txt index f4428f958..a7068e5a4 100644 --- a/host/apps/CMakeLists.txt +++ b/host/apps/CMakeLists.txt @@ -16,7 +16,9 @@ # ADD_EXECUTABLE(discover_usrps discover_usrps.cpp) - TARGET_LINK_LIBRARIES(discover_usrps uhd) +ADD_EXECUTABLE(usrp1e_load_fpga usrp1e_load_fpga.cpp) +TARGET_LINK_LIBRARIES(usrp1e_load_fpga uhd) + INSTALL(TARGETS discover_usrps RUNTIME DESTINATION ${RUNTIME_DIR}) diff --git a/host/apps/usrp1e_load_fpga.cpp b/host/apps/usrp1e_load_fpga.cpp new file mode 100644 index 000000000..d5960b391 --- /dev/null +++ b/host/apps/usrp1e_load_fpga.cpp @@ -0,0 +1,47 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include +#include +#include + +namespace po = boost::program_options; + +int main(int argc, char *argv[]){ + po::options_description desc("Allowed options"); + desc.add_options() + ("help", "help message") + ("file", po::value(), "path to fpga bin file") + ; + + po::variables_map vm; + po::store(po::parse_command_line(argc, argv, desc), vm); + po::notify(vm); + + //print the help message + if (vm.count("help") or vm.count("file") == 0){ + std::cout << boost::format("USRP1E Load FPGA %s") % desc << std::endl; + return ~0; + } + + //load the fpga + std::string file = vm["file"].as(); + uhd::usrp::usrp1e::load_fpga(file); + + return 0; +} diff --git a/host/lib/usrp/usrp1e/fpga-downloader.cc b/host/lib/usrp/usrp1e/fpga-downloader.cc index 15023d945..f7c78b875 100644 --- a/host/lib/usrp/usrp1e/fpga-downloader.cc +++ b/host/lib/usrp/usrp1e/fpga-downloader.cc @@ -43,7 +43,7 @@ const unsigned int PROG_B = 175; const unsigned int DONE = 173; const unsigned int INIT_B = 114; -static std::string bit_file = "safe_u1e.bin"; +//static std::string bit_file = "safe_u1e.bin"; const int BUF_SIZE = 4096; @@ -198,7 +198,7 @@ void spidev::send(char *buf, char *rbuf, unsigned int nbytes) } -static void send_file_to_fpga(std::string &file_name, gpio &error, gpio &done) +static void send_file_to_fpga(const std::string &file_name, gpio &error, gpio &done) { std::ifstream bitstream; @@ -258,5 +258,5 @@ void uhd::usrp::usrp1e::load_fpga(const std::string &bin_file){ std::cout << "Done = " << gpio_done.get_value() << std::endl; - send_file_to_fpga(bit_file, gpio_init_b, gpio_done); + send_file_to_fpga(bin_file, gpio_init_b, gpio_done); } -- cgit v1.2.3 From e273ea92d83d46ca350ac07e3d836a4d99b106c2 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 8 Mar 2010 16:13:06 -0800 Subject: proper flags bits --- host/apps/omap_debug/set_debug_pins.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/host/apps/omap_debug/set_debug_pins.py b/host/apps/omap_debug/set_debug_pins.py index d67cc3e58..20071db6b 100755 --- a/host/apps/omap_debug/set_debug_pins.py +++ b/host/apps/omap_debug/set_debug_pins.py @@ -3,12 +3,12 @@ import os # Memory Map -misc_base = 0 -uart_base = 1 -spi_base = 2 -i2c_base = 3 -gpio_base = 4 -settings_base = 5 +misc_base = 0 << 7 +uart_base = 1 << 7 +spi_base = 2 << 7 +i2c_base = 3 << 7 +gpio_base = 4 << 7 +settings_base = 5 << 7 # GPIO offset gpio_pins = 0 -- cgit v1.2.3 From 10ee8022dd22f13f942d8bfeeca3b380224fff52 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 18 Mar 2010 19:38:06 +0000 Subject: added usrp1e implementation skeleton, began filling it in... --- host/include/uhd/usrp/dboard_id.hpp | 3 +- host/lib/CMakeLists.txt | 4 + host/lib/usrp/usrp1e/dboard_impl.cpp | 76 +++++++++++++++++ host/lib/usrp/usrp1e/dboard_interface.cpp | 135 ++++++++++++++++++++++++++++++ host/lib/usrp/usrp1e/dsp_impl.cpp | 63 ++++++++++++++ host/lib/usrp/usrp1e/mboard_impl.cpp | 42 ++++++++++ host/lib/usrp/usrp1e/usrp1e_impl.cpp | 33 ++++++++ host/lib/usrp/usrp1e/usrp1e_impl.hpp | 97 +++++++++++++++++++++ 8 files changed, 452 insertions(+), 1 deletion(-) create mode 100644 host/lib/usrp/usrp1e/dboard_impl.cpp create mode 100644 host/lib/usrp/usrp1e/dboard_interface.cpp create mode 100644 host/lib/usrp/usrp1e/dsp_impl.cpp create mode 100644 host/lib/usrp/usrp1e/mboard_impl.cpp diff --git a/host/include/uhd/usrp/dboard_id.hpp b/host/include/uhd/usrp/dboard_id.hpp index 62c61661c..370cd1fbb 100644 --- a/host/include/uhd/usrp/dboard_id.hpp +++ b/host/include/uhd/usrp/dboard_id.hpp @@ -25,9 +25,10 @@ namespace uhd{ namespace usrp{ typedef boost::uint16_t dboard_id_t; -static const dboard_id_t ID_NONE = 0xffff; +static const dboard_id_t ID_NONE = 0xffff; //TODO: REMOVE ME namespace dboard_id{ + static const dboard_id_t NONE = 0xffff; std::string to_string(const dboard_id_t &id); } diff --git a/host/lib/CMakeLists.txt b/host/lib/CMakeLists.txt index 7d7fcbea9..e547fef85 100644 --- a/host/lib/CMakeLists.txt +++ b/host/lib/CMakeLists.txt @@ -63,7 +63,11 @@ CHECK_INCLUDE_FILES( IF(HAS_USRP1E_REQUIRED_HEADERS) MESSAGE(STATUS "Building usrp1e support...") LIST(APPEND libuhd_sources + usrp/usrp1e/dboard_impl.cpp + usrp/usrp1e/dboard_interface.cpp + usrp/usrp1e/dsp_impl.cpp usrp/usrp1e/fpga-downloader.cc + usrp/usrp1e/mboard_impl.cpp usrp/usrp1e/usrp1e_impl.cpp ) ELSE(HAS_USRP1E_REQUIRED_HEADERS) diff --git a/host/lib/usrp/usrp1e/dboard_impl.cpp b/host/lib/usrp/usrp1e/dboard_impl.cpp new file mode 100644 index 000000000..7d46366bc --- /dev/null +++ b/host/lib/usrp/usrp1e/dboard_impl.cpp @@ -0,0 +1,76 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include +#include "usrp1e_impl.hpp" + +using namespace uhd::usrp; + +/*********************************************************************** + * Dboard Initialization + **********************************************************************/ +void usrp1e_impl::dboard_init(void){ + dboard_id_t rx_dboard_id = dboard_id::NONE; //TODO get these from the eeprom + dboard_id_t tx_dboard_id = dboard_id::NONE; + + //create a new dboard interface and manager + dboard_interface::sptr dboard_interface( + make_usrp1e_dboard_interface(this) + ); + _dboard_manager = dboard_manager::make( + rx_dboard_id, tx_dboard_id, dboard_interface + ); + + //setup the dboard proxies + _rx_dboard_proxy = wax_obj_proxy( + boost::bind(&usrp1e_impl::rx_dboard_get, this, _1, _2), + boost::bind(&usrp1e_impl::rx_dboard_set, this, _1, _2) + ); + _tx_dboard_proxy = wax_obj_proxy( + boost::bind(&usrp1e_impl::tx_dboard_get, this, _1, _2), + boost::bind(&usrp1e_impl::tx_dboard_set, this, _1, _2) + ); +} + +/*********************************************************************** + * RX Dboard Get + **********************************************************************/ +void usrp1e_impl::rx_dboard_get(const wax::obj &, wax::obj &){ + +} + +/*********************************************************************** + * RX Dboard Set + **********************************************************************/ +void usrp1e_impl::rx_dboard_set(const wax::obj &, const wax::obj &){ + +} + +/*********************************************************************** + * TX Dboard Get + **********************************************************************/ +void usrp1e_impl::tx_dboard_get(const wax::obj &, wax::obj &){ + +} + +/*********************************************************************** + * TX Dboard Set + **********************************************************************/ +void usrp1e_impl::tx_dboard_set(const wax::obj &, const wax::obj &){ + +} diff --git a/host/lib/usrp/usrp1e/dboard_interface.cpp b/host/lib/usrp/usrp1e/dboard_interface.cpp new file mode 100644 index 000000000..b3e06f7be --- /dev/null +++ b/host/lib/usrp/usrp1e/dboard_interface.cpp @@ -0,0 +1,135 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include "usrp1e_impl.hpp" + +using namespace uhd::usrp; + +class usrp1e_dboard_interface : public dboard_interface{ +public: + usrp1e_dboard_interface(usrp1e_impl *impl); + ~usrp1e_dboard_interface(void); + + void write_aux_dac(unit_type_t, int, int); + int read_aux_adc(unit_type_t, int); + + void set_atr_reg(gpio_bank_t, boost::uint16_t, boost::uint16_t, boost::uint16_t); + void set_gpio_ddr(gpio_bank_t, boost::uint16_t, boost::uint16_t); + void write_gpio(gpio_bank_t, boost::uint16_t, boost::uint16_t); + boost::uint16_t read_gpio(gpio_bank_t); + + void write_i2c(int, const byte_vector_t &); + byte_vector_t read_i2c(int, size_t); + + double get_rx_clock_rate(void); + double get_tx_clock_rate(void); + +private: + byte_vector_t transact_spi( + spi_dev_t dev, + spi_latch_t latch, + spi_push_t push, + const byte_vector_t &buf, + bool readback + ); + + usrp1e_impl *_impl; +}; + +/*********************************************************************** + * Make Function + **********************************************************************/ +dboard_interface::sptr make_usrp1e_dboard_interface(usrp1e_impl *impl){ + return dboard_interface::sptr(new usrp1e_dboard_interface(impl)); +} + +/*********************************************************************** + * Structors + **********************************************************************/ +usrp1e_dboard_interface::usrp1e_dboard_interface(usrp1e_impl *impl){ + _impl = impl; +} + +usrp1e_dboard_interface::~usrp1e_dboard_interface(void){ + /* NOP */ +} + +/*********************************************************************** + * Clock Rates + **********************************************************************/ +double usrp1e_dboard_interface::get_rx_clock_rate(void){ + throw std::runtime_error("not implemented"); +} + +double usrp1e_dboard_interface::get_tx_clock_rate(void){ + throw std::runtime_error("not implemented"); +} + +/*********************************************************************** + * GPIO + **********************************************************************/ +void usrp1e_dboard_interface::set_gpio_ddr(gpio_bank_t bank, boost::uint16_t value, boost::uint16_t mask){ + throw std::runtime_error("not implemented"); +} + +void usrp1e_dboard_interface::write_gpio(gpio_bank_t bank, boost::uint16_t value, boost::uint16_t mask){ + throw std::runtime_error("not implemented"); +} + +boost::uint16_t usrp1e_dboard_interface::read_gpio(gpio_bank_t bank){ + throw std::runtime_error("not implemented"); +} + +void usrp1e_dboard_interface::set_atr_reg(gpio_bank_t bank, boost::uint16_t tx_value, boost::uint16_t rx_value, boost::uint16_t mask){ + throw std::runtime_error("not implemented"); +} + +/*********************************************************************** + * SPI + **********************************************************************/ +dboard_interface::byte_vector_t usrp1e_dboard_interface::transact_spi( + spi_dev_t dev, + spi_latch_t latch, + spi_push_t push, + const byte_vector_t &buf, + bool readback +){ + throw std::runtime_error("not implemented"); +} + +/*********************************************************************** + * I2C + **********************************************************************/ +void usrp1e_dboard_interface::write_i2c(int i2c_addr, const byte_vector_t &buf){ + throw std::runtime_error("not implemented"); +} + +dboard_interface::byte_vector_t usrp1e_dboard_interface::read_i2c(int i2c_addr, size_t num_bytes){ + throw std::runtime_error("not implemented"); +} + +/*********************************************************************** + * Aux DAX/ADC + **********************************************************************/ +void usrp1e_dboard_interface::write_aux_dac(dboard_interface::unit_type_t unit, int which, int value){ + throw std::runtime_error("not implemented"); +} + +int usrp1e_dboard_interface::read_aux_adc(dboard_interface::unit_type_t unit, int which){ + throw std::runtime_error("not implemented"); +} diff --git a/host/lib/usrp/usrp1e/dsp_impl.cpp b/host/lib/usrp/usrp1e/dsp_impl.cpp new file mode 100644 index 000000000..b6076ef97 --- /dev/null +++ b/host/lib/usrp/usrp1e/dsp_impl.cpp @@ -0,0 +1,63 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include "usrp1e_impl.hpp" + +using namespace uhd::usrp; + +/*********************************************************************** + * RX DDC Initialization + **********************************************************************/ +void usrp1e_impl::rx_ddc_init(void){ + +} + +/*********************************************************************** + * RX DDC Get + **********************************************************************/ +void usrp1e_impl::rx_ddc_get(const wax::obj &, wax::obj &){ + +} + +/*********************************************************************** + * RX DDC Set + **********************************************************************/ +void usrp1e_impl::rx_ddc_set(const wax::obj &, const wax::obj &){ + +} + +/*********************************************************************** + * TX DUC Initialization + **********************************************************************/ +void usrp1e_impl::tx_duc_init(void){ + +} + +/*********************************************************************** + * TX DUC Get + **********************************************************************/ +void usrp1e_impl::tx_duc_get(const wax::obj &, wax::obj &){ + +} + +/*********************************************************************** + * TX DUC Set + **********************************************************************/ +void usrp1e_impl::tx_duc_set(const wax::obj &, const wax::obj &){ + +} diff --git a/host/lib/usrp/usrp1e/mboard_impl.cpp b/host/lib/usrp/usrp1e/mboard_impl.cpp new file mode 100644 index 000000000..c79ed1820 --- /dev/null +++ b/host/lib/usrp/usrp1e/mboard_impl.cpp @@ -0,0 +1,42 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include "usrp1e_impl.hpp" + +using namespace uhd::usrp; + +/*********************************************************************** + * Mboard Initialization + **********************************************************************/ +void usrp1e_impl::mboard_init(void){ + +} + +/*********************************************************************** + * Mboard Get + **********************************************************************/ +void usrp1e_impl::mboard_get(const wax::obj &, wax::obj &){ + +} + +/*********************************************************************** + * Mboard Set + **********************************************************************/ +void usrp1e_impl::mboard_set(const wax::obj &, const wax::obj &){ + +} diff --git a/host/lib/usrp/usrp1e/usrp1e_impl.cpp b/host/lib/usrp/usrp1e/usrp1e_impl.cpp index 441f6d060..14c4b7278 100644 --- a/host/lib/usrp/usrp1e/usrp1e_impl.cpp +++ b/host/lib/usrp/usrp1e/usrp1e_impl.cpp @@ -70,3 +70,36 @@ device_addrs_t usrp1e::discover(const device_addr_t &device_addr){ device::sptr usrp1e::make(const device_addr_t &){ throw std::runtime_error("not implemented yet"); } + +/*********************************************************************** + * Structors + **********************************************************************/ +usrp1e_impl::usrp1e_impl(void){ + //initialize the mboard + mboard_init(); + + //initialize the dboards + dboard_init(); + + //initialize the dsps + rx_ddc_init(); + tx_duc_init(); +} + +usrp1e_impl::~usrp1e_impl(void){ + /* NOP */ +} + +/*********************************************************************** + * Device Get + **********************************************************************/ +void usrp1e_impl::get(const wax::obj &, wax::obj &){ + +} + +/*********************************************************************** + * Device Set + **********************************************************************/ +void usrp1e_impl::set(const wax::obj &, const wax::obj &){ + +} diff --git a/host/lib/usrp/usrp1e/usrp1e_impl.hpp b/host/lib/usrp/usrp1e/usrp1e_impl.hpp index 3f5f89ec6..3b2fcdd57 100644 --- a/host/lib/usrp/usrp1e/usrp1e_impl.hpp +++ b/host/lib/usrp/usrp1e/usrp1e_impl.hpp @@ -16,8 +16,105 @@ // #include +#include #ifndef INCLUDED_USRP1E_IMPL_HPP #define INCLUDED_USRP1E_IMPL_HPP +class usrp1e_impl; // dummy class declaration + +/*! + * Make a usrp1e dboard interface. + * \param impl a pointer to the usrp1e impl object + * \return a sptr to a new dboard interface + */ +uhd::usrp::dboard_interface::sptr make_usrp1e_dboard_interface(usrp1e_impl *impl); + +/*! + * Simple wax obj proxy class: + * Provides a wax obj interface for a set and a get function. + * This allows us to create nested properties structures + * while maintaining flattened code within the implementation. + */ +class wax_obj_proxy : public wax::obj{ +public: + typedef boost::function get_t; + typedef boost::function set_t; + + wax_obj_proxy(void){ + /* NOP */ + } + + wax_obj_proxy(const get_t &get, const set_t &set){ + _get = get; + _set = set; + }; + + ~wax_obj_proxy(void){ + /* NOP */ + } + + void get(const wax::obj &key, wax::obj &val){ + return _get(key, val); + } + + void set(const wax::obj &key, const wax::obj &val){ + return _set(key, val); + } + +private: + get_t _get; + set_t _set; +}; + +/*! + * USRP1E implementation guts: + * The implementation details are encapsulated here. + * Handles properties on the mboard, dboard, dsps... + */ +class usrp1e_impl : public uhd::device{ +public: + typedef boost::shared_ptr sptr; + + usrp1e_impl(void); + ~usrp1e_impl(void); + +private: + //device functions and settings + void get(const wax::obj &, wax::obj &); + void set(const wax::obj &, const wax::obj &); + + //mboard functions and settings + void mboard_init(void); + void mboard_get(const wax::obj &, wax::obj &); + void mboard_set(const wax::obj &, const wax::obj &); + wax_obj_proxy _mboard_proxy; + + //xx dboard functions and settings + void dboard_init(void); + uhd::usrp::dboard_manager::sptr _dboard_manager; + + //rx dboard functions and settings + void rx_dboard_get(const wax::obj &, wax::obj &); + void rx_dboard_set(const wax::obj &, const wax::obj &); + wax_obj_proxy _rx_dboard_proxy; + + //tx dboard functions and settings + void tx_dboard_get(const wax::obj &, wax::obj &); + void tx_dboard_set(const wax::obj &, const wax::obj &); + wax_obj_proxy _tx_dboard_proxy; + + //rx ddc functions and settings + void rx_ddc_init(void); + void rx_ddc_get(const wax::obj &, wax::obj &); + void rx_ddc_set(const wax::obj &, const wax::obj &); + wax_obj_proxy _rx_ddc_proxy; + + //tx duc functions and settings + void tx_duc_init(void); + void tx_duc_get(const wax::obj &, wax::obj &); + void tx_duc_set(const wax::obj &, const wax::obj &); + wax_obj_proxy _tx_duc_proxy; +}; + #endif /* INCLUDED_USRP1E_IMPL_HPP */ -- cgit v1.2.3 From a31761cb0c37b61f7243836d6dd8c40cbf49efc0 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 22 Mar 2010 13:12:03 +0000 Subject: filled in more skeleton code, filled in dboard interface spi and i2c with ioctls, added file descriptor opening, and checking for usrp1 kernel header --- host/lib/CMakeLists.txt | 1 + host/lib/usrp/usrp1e/dboard_impl.cpp | 4 +- host/lib/usrp/usrp1e/dboard_interface.cpp | 60 +++++++++++++++++++++-- host/lib/usrp/usrp1e/dsp_impl.cpp | 11 ++++- host/lib/usrp/usrp1e/mboard_impl.cpp | 6 ++- host/lib/usrp/usrp1e/usrp1e_impl.cpp | 79 ++++++++++++++++++++++++++----- host/lib/usrp/usrp1e/usrp1e_impl.hpp | 48 ++++++++++++------- host/lib/usrp/usrp2/usrp2_impl.hpp | 2 - 8 files changed, 172 insertions(+), 39 deletions(-) diff --git a/host/lib/CMakeLists.txt b/host/lib/CMakeLists.txt index a7dded86b..46cce729e 100644 --- a/host/lib/CMakeLists.txt +++ b/host/lib/CMakeLists.txt @@ -56,6 +56,7 @@ INCLUDE(CheckIncludeFiles) SET(usrp1e_required_headers linux/ioctl.h linux/spi/spidev.h + linux/usrp1_e.h ) CHECK_INCLUDE_FILES( "${usrp1e_required_headers}" diff --git a/host/lib/usrp/usrp1e/dboard_impl.cpp b/host/lib/usrp/usrp1e/dboard_impl.cpp index 7d46366bc..a2798dce3 100644 --- a/host/lib/usrp/usrp1e/dboard_impl.cpp +++ b/host/lib/usrp/usrp1e/dboard_impl.cpp @@ -37,11 +37,11 @@ void usrp1e_impl::dboard_init(void){ ); //setup the dboard proxies - _rx_dboard_proxy = wax_obj_proxy( + _rx_dboard_proxy = wax_obj_proxy::make( boost::bind(&usrp1e_impl::rx_dboard_get, this, _1, _2), boost::bind(&usrp1e_impl::rx_dboard_set, this, _1, _2) ); - _tx_dboard_proxy = wax_obj_proxy( + _tx_dboard_proxy = wax_obj_proxy::make( boost::bind(&usrp1e_impl::tx_dboard_get, this, _1, _2), boost::bind(&usrp1e_impl::tx_dboard_set, this, _1, _2) ); diff --git a/host/lib/usrp/usrp1e/dboard_interface.cpp b/host/lib/usrp/usrp1e/dboard_interface.cpp index b3e06f7be..ef91014ac 100644 --- a/host/lib/usrp/usrp1e/dboard_interface.cpp +++ b/host/lib/usrp/usrp1e/dboard_interface.cpp @@ -16,7 +16,9 @@ // #include +#include //std::copy #include "usrp1e_impl.hpp" +#include using namespace uhd::usrp; @@ -109,18 +111,70 @@ dboard_interface::byte_vector_t usrp1e_dboard_interface::transact_spi( const byte_vector_t &buf, bool readback ){ - throw std::runtime_error("not implemented"); + //load data struct + usrp_e_spi data; + data.readback = (readback)? UE_SPI_TXRX : UE_SPI_TXONLY; + data.slave = (dev == SPI_RX_DEV)? UE_SPI_CTRL_RXNEG : UE_SPI_CTRL_TXNEG; + data.length = buf.size() * 8; //bytes to bits + boost::uint8_t *data_bytes = reinterpret_cast(&data.data); + + //load the data + ASSERT_THROW(buf.size() <= sizeof(data.data)); + std::copy(buf.begin(), buf.end(), data_bytes); + + //load the flags + data.flags = 0; + data.flags |= (latch == SPI_LATCH_RISE)? UE_SPI_LATCH_RISE : UE_SPI_LATCH_FALL; + data.flags |= (push == SPI_PUSH_RISE)? UE_SPI_PUSH_RISE : UE_SPI_PUSH_FALL; + + //call the spi ioctl + _impl->ioctl(USRP_E_SPI, &data); + + //unload the data + byte_vector_t ret(data.length/8); //bits to bytes + ASSERT_THROW(ret.size() <= sizeof(data.data)); + std::copy(data_bytes, data_bytes+ret.size(), ret.begin()); + return ret; } /*********************************************************************** * I2C **********************************************************************/ +static const size_t max_i2c_data_bytes = 10; + void usrp1e_dboard_interface::write_i2c(int i2c_addr, const byte_vector_t &buf){ - throw std::runtime_error("not implemented"); + //allocate some memory for this transaction + ASSERT_THROW(buf.size() <= max_i2c_data_bytes); + boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; + + //load the data struct + usrp_e_i2c &data = reinterpret_cast(mem); + data.addr = i2c_addr; + data.len = buf.size(); + std::copy(buf.begin(), buf.end(), data.data); + + //call the spi ioctl + _impl->ioctl(USRP_E_I2C_WRITE, &data); } dboard_interface::byte_vector_t usrp1e_dboard_interface::read_i2c(int i2c_addr, size_t num_bytes){ - throw std::runtime_error("not implemented"); + //allocate some memory for this transaction + ASSERT_THROW(num_bytes <= max_i2c_data_bytes); + boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; + + //load the data struct + usrp_e_i2c &data = reinterpret_cast(mem); + data.addr = i2c_addr; + data.len = num_bytes; + + //call the spi ioctl + _impl->ioctl(USRP_E_I2C_READ, &data); + + //unload the data + byte_vector_t ret(data.len); + ASSERT_THROW(ret.size() == num_bytes); + std::copy(data.data, data.data+ret.size(), ret.begin()); + return ret; } /*********************************************************************** diff --git a/host/lib/usrp/usrp1e/dsp_impl.cpp b/host/lib/usrp/usrp1e/dsp_impl.cpp index b6076ef97..862b89184 100644 --- a/host/lib/usrp/usrp1e/dsp_impl.cpp +++ b/host/lib/usrp/usrp1e/dsp_impl.cpp @@ -15,6 +15,7 @@ // along with this program. If not, see . // +#include #include #include "usrp1e_impl.hpp" @@ -24,7 +25,10 @@ using namespace uhd::usrp; * RX DDC Initialization **********************************************************************/ void usrp1e_impl::rx_ddc_init(void){ - + _rx_ddc_proxy = wax_obj_proxy::make( + boost::bind(&usrp1e_impl::rx_ddc_get, this, _1, _2), + boost::bind(&usrp1e_impl::rx_ddc_set, this, _1, _2) + ); } /*********************************************************************** @@ -45,7 +49,10 @@ void usrp1e_impl::rx_ddc_set(const wax::obj &, const wax::obj &){ * TX DUC Initialization **********************************************************************/ void usrp1e_impl::tx_duc_init(void){ - + _tx_duc_proxy = wax_obj_proxy::make( + boost::bind(&usrp1e_impl::tx_duc_get, this, _1, _2), + boost::bind(&usrp1e_impl::tx_duc_set, this, _1, _2) + ); } /*********************************************************************** diff --git a/host/lib/usrp/usrp1e/mboard_impl.cpp b/host/lib/usrp/usrp1e/mboard_impl.cpp index c79ed1820..b480f7616 100644 --- a/host/lib/usrp/usrp1e/mboard_impl.cpp +++ b/host/lib/usrp/usrp1e/mboard_impl.cpp @@ -15,6 +15,7 @@ // along with this program. If not, see . // +#include #include #include "usrp1e_impl.hpp" @@ -24,7 +25,10 @@ using namespace uhd::usrp; * Mboard Initialization **********************************************************************/ void usrp1e_impl::mboard_init(void){ - + _mboard_proxy = wax_obj_proxy::make( + boost::bind(&usrp1e_impl::mboard_get, this, _1, _2), + boost::bind(&usrp1e_impl::mboard_set, this, _1, _2) + ); } /*********************************************************************** diff --git a/host/lib/usrp/usrp1e/usrp1e_impl.cpp b/host/lib/usrp/usrp1e/usrp1e_impl.cpp index 14c4b7278..d3b0264a7 100644 --- a/host/lib/usrp/usrp1e/usrp1e_impl.cpp +++ b/host/lib/usrp/usrp1e/usrp1e_impl.cpp @@ -19,9 +19,12 @@ #include #include #include "usrp1e_impl.hpp" +#include //open +#include //ioctl using namespace uhd; using namespace uhd::usrp; +namespace fs = boost::filesystem; STATIC_BLOCK(register_usrp1e_device){ device::register_device(&usrp1e::discover, &usrp1e::make); @@ -30,8 +33,8 @@ STATIC_BLOCK(register_usrp1e_device){ /*********************************************************************** * Helper Functions **********************************************************************/ -static bool file_exists(const std::string &file_path){ - return boost::filesystem::exists(file_path); +static std::string abs_path(const std::string &file_path){ + return fs::system_complete(fs::path(file_path)).file_string(); } /*********************************************************************** @@ -42,10 +45,10 @@ device_addrs_t usrp1e::discover(const device_addr_t &device_addr){ //if a node was provided, use it and only it if (device_addr.has_key("node")){ - if (not file_exists(device_addr["node"])) return usrp1e_addrs; + if (not fs::exists(device_addr["node"])) return usrp1e_addrs; device_addr_t new_addr; new_addr["name"] = "USRP1E"; - new_addr["node"] = device_addr["node"]; + new_addr["node"] = abs_path(device_addr["node"]); usrp1e_addrs.push_back(new_addr); } @@ -53,10 +56,10 @@ device_addrs_t usrp1e::discover(const device_addr_t &device_addr){ else{ for(size_t i = 0; i < 5; i++){ std::string node = str(boost::format("/dev/usrp1_e%d") % i); - if (not file_exists(node)) continue; + if (not fs::exists(node)) continue; device_addr_t new_addr; new_addr["name"] = "USRP1E"; - new_addr["node"] = node; + new_addr["node"] = abs_path(node); usrp1e_addrs.push_back(new_addr); } } @@ -67,14 +70,23 @@ device_addrs_t usrp1e::discover(const device_addr_t &device_addr){ /*********************************************************************** * Make **********************************************************************/ -device::sptr usrp1e::make(const device_addr_t &){ - throw std::runtime_error("not implemented yet"); +device::sptr usrp1e::make(const device_addr_t &device_addr){ + std::string node = device_addr["node"]; + int node_fd = open(node.c_str(), 0); + if (node_fd < 0){ + throw std::runtime_error(str( + boost::format("Failed to open %s") % node + )); + } + return sptr(new usrp1e_impl(node_fd)); } /*********************************************************************** * Structors **********************************************************************/ -usrp1e_impl::usrp1e_impl(void){ +usrp1e_impl::usrp1e_impl(int node_fd){ + _node_fd = node_fd; + //initialize the mboard mboard_init(); @@ -90,16 +102,59 @@ usrp1e_impl::~usrp1e_impl(void){ /* NOP */ } +/*********************************************************************** + * Misc Methods + **********************************************************************/ +void usrp1e_impl::ioctl(int request, void *mem){ + if (::ioctl(_node_fd, request, mem) < 0){ + throw std::runtime_error(str( + boost::format("ioctl failed with request %d") % request + )); + } +} + /*********************************************************************** * Device Get **********************************************************************/ -void usrp1e_impl::get(const wax::obj &, wax::obj &){ - +void usrp1e_impl::get(const wax::obj &key_, wax::obj &val){ + wax::obj key; std::string name; + boost::tie(key, name) = extract_named_prop(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case DEVICE_PROP_NAME: + val = std::string("usrp1e device"); + return; + + case DEVICE_PROP_MBOARD: + ASSERT_THROW(name == ""); + val = _mboard_proxy->get_link(); + return; + + case DEVICE_PROP_MBOARD_NAMES: + val = prop_names_t(1, ""); //vector of size 1 with empty string + return; + + case DEVICE_PROP_MAX_RX_SAMPLES: + val = size_t(0); //TODO + return; + + case DEVICE_PROP_MAX_TX_SAMPLES: + val = size_t(0); //TODO + return; + + } } /*********************************************************************** * Device Set **********************************************************************/ void usrp1e_impl::set(const wax::obj &, const wax::obj &){ - + throw std::runtime_error("Cannot set in usrp1e device"); } + +/*********************************************************************** + * Device IO (TODO) + **********************************************************************/ +size_t usrp1e_impl::send(const boost::asio::const_buffer &, const uhd::tx_metadata_t &, const std::string &){return 0;} +size_t usrp1e_impl::recv(const boost::asio::mutable_buffer &, uhd::rx_metadata_t &, const std::string &){return 0;} diff --git a/host/lib/usrp/usrp1e/usrp1e_impl.hpp b/host/lib/usrp/usrp1e/usrp1e_impl.hpp index 3b2fcdd57..7a09254ec 100644 --- a/host/lib/usrp/usrp1e/usrp1e_impl.hpp +++ b/host/lib/usrp/usrp1e/usrp1e_impl.hpp @@ -40,20 +40,25 @@ class wax_obj_proxy : public wax::obj{ public: typedef boost::function get_t; typedef boost::function set_t; + typedef boost::shared_ptr sptr; - wax_obj_proxy(void){ + static sptr make(const get_t &get, const set_t &set){ + return sptr(new wax_obj_proxy(get, set)); + } + + ~wax_obj_proxy(void){ /* NOP */ } +private: + get_t _get; + set_t _set; + wax_obj_proxy(const get_t &get, const set_t &set){ _get = get; _set = set; }; - ~wax_obj_proxy(void){ - /* NOP */ - } - void get(const wax::obj &key, wax::obj &val){ return _get(key, val); } @@ -61,10 +66,6 @@ public: void set(const wax::obj &key, const wax::obj &val){ return _set(key, val); } - -private: - get_t _get; - set_t _set; }; /*! @@ -74,12 +75,25 @@ private: */ class usrp1e_impl : public uhd::device{ public: - typedef boost::shared_ptr sptr; - - usrp1e_impl(void); + //structors + usrp1e_impl(int node_fd); ~usrp1e_impl(void); + //the io interface + size_t send(const boost::asio::const_buffer &, const uhd::tx_metadata_t &, const std::string &); + size_t recv(const boost::asio::mutable_buffer &, uhd::rx_metadata_t &, const std::string &); + + /*! + * Perform an ioctl call on the device node file descriptor. + * This will throw when the internal ioctl call fails. + * \param request the control word + * \param mem pointer to some memory + */ + void ioctl(int request, void *mem); + private: + int _node_fd; + //device functions and settings void get(const wax::obj &, wax::obj &); void set(const wax::obj &, const wax::obj &); @@ -88,7 +102,7 @@ private: void mboard_init(void); void mboard_get(const wax::obj &, wax::obj &); void mboard_set(const wax::obj &, const wax::obj &); - wax_obj_proxy _mboard_proxy; + wax_obj_proxy::sptr _mboard_proxy; //xx dboard functions and settings void dboard_init(void); @@ -97,24 +111,24 @@ private: //rx dboard functions and settings void rx_dboard_get(const wax::obj &, wax::obj &); void rx_dboard_set(const wax::obj &, const wax::obj &); - wax_obj_proxy _rx_dboard_proxy; + wax_obj_proxy::sptr _rx_dboard_proxy; //tx dboard functions and settings void tx_dboard_get(const wax::obj &, wax::obj &); void tx_dboard_set(const wax::obj &, const wax::obj &); - wax_obj_proxy _tx_dboard_proxy; + wax_obj_proxy::sptr _tx_dboard_proxy; //rx ddc functions and settings void rx_ddc_init(void); void rx_ddc_get(const wax::obj &, wax::obj &); void rx_ddc_set(const wax::obj &, const wax::obj &); - wax_obj_proxy _rx_ddc_proxy; + wax_obj_proxy::sptr _rx_ddc_proxy; //tx duc functions and settings void tx_duc_init(void); void tx_duc_get(const wax::obj &, wax::obj &); void tx_duc_set(const wax::obj &, const wax::obj &); - wax_obj_proxy _tx_duc_proxy; + wax_obj_proxy::sptr _tx_duc_proxy; }; #endif /* INCLUDED_USRP1E_IMPL_HPP */ diff --git a/host/lib/usrp/usrp2/usrp2_impl.hpp b/host/lib/usrp/usrp2/usrp2_impl.hpp index 70420fd49..55ac0b192 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.hpp +++ b/host/lib/usrp/usrp2/usrp2_impl.hpp @@ -86,8 +86,6 @@ private: */ class usrp2_impl : public uhd::device{ public: - typedef boost::shared_ptr sptr; - /*! * Create a new usrp2 impl base. * \param ctrl_transport the udp transport for control -- cgit v1.2.3 From 09a21dd6d4bc5b7f032e07cfabcba9f55d25b0f6 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 22 Mar 2010 15:31:16 +0000 Subject: bit of io work --- host/lib/usrp/usrp1e/usrp1e_impl.cpp | 48 +++++++++++++++++++++++++----------- host/lib/usrp/usrp1e/usrp1e_impl.hpp | 3 ++- 2 files changed, 35 insertions(+), 16 deletions(-) diff --git a/host/lib/usrp/usrp1e/usrp1e_impl.cpp b/host/lib/usrp/usrp1e/usrp1e_impl.cpp index d3b0264a7..8230cc8e4 100644 --- a/host/lib/usrp/usrp1e/usrp1e_impl.cpp +++ b/host/lib/usrp/usrp1e/usrp1e_impl.cpp @@ -71,21 +71,19 @@ device_addrs_t usrp1e::discover(const device_addr_t &device_addr){ * Make **********************************************************************/ device::sptr usrp1e::make(const device_addr_t &device_addr){ - std::string node = device_addr["node"]; - int node_fd = open(node.c_str(), 0); - if (node_fd < 0){ - throw std::runtime_error(str( - boost::format("Failed to open %s") % node - )); - } - return sptr(new usrp1e_impl(node_fd)); + return sptr(new usrp1e_impl(device_addr["node"])); } /*********************************************************************** * Structors **********************************************************************/ -usrp1e_impl::usrp1e_impl(int node_fd){ - _node_fd = node_fd; +usrp1e_impl::usrp1e_impl(const std::string &node){ + //open the device node and check file descriptor + if ((_node_fd = ::open(node.c_str(), O_RDWR)) < 0){ + throw std::runtime_error(str( + boost::format("Failed to open %s") % node + )); + } //initialize the mboard mboard_init(); @@ -99,7 +97,8 @@ usrp1e_impl::usrp1e_impl(int node_fd){ } usrp1e_impl::~usrp1e_impl(void){ - /* NOP */ + //close the device node file descriptor + ::close(_node_fd); } /*********************************************************************** @@ -136,11 +135,11 @@ void usrp1e_impl::get(const wax::obj &key_, wax::obj &val){ return; case DEVICE_PROP_MAX_RX_SAMPLES: - val = size_t(0); //TODO + val = size_t(_max_num_samples); return; case DEVICE_PROP_MAX_TX_SAMPLES: - val = size_t(0); //TODO + val = size_t(_max_num_samples); return; } @@ -156,5 +155,24 @@ void usrp1e_impl::set(const wax::obj &, const wax::obj &){ /*********************************************************************** * Device IO (TODO) **********************************************************************/ -size_t usrp1e_impl::send(const boost::asio::const_buffer &, const uhd::tx_metadata_t &, const std::string &){return 0;} -size_t usrp1e_impl::recv(const boost::asio::mutable_buffer &, uhd::rx_metadata_t &, const std::string &){return 0;} +size_t usrp1e_impl::send( + const boost::asio::const_buffer &, + const uhd::tx_metadata_t &, + const std::string &type +){ + if (type != "16sc"){ + throw std::runtime_error(str(boost::format("usrp1e send: cannot handle type \"%s\"") % type)); + } + return 0; +} + +size_t usrp1e_impl::recv( + const boost::asio::mutable_buffer &, + uhd::rx_metadata_t &, + const std::string &type +){ + if (type != "16sc"){ + throw std::runtime_error(str(boost::format("usrp1e recv: cannot handle type \"%s\"") % type)); + } + return 0; +} diff --git a/host/lib/usrp/usrp1e/usrp1e_impl.hpp b/host/lib/usrp/usrp1e/usrp1e_impl.hpp index 7a09254ec..c199a0465 100644 --- a/host/lib/usrp/usrp1e/usrp1e_impl.hpp +++ b/host/lib/usrp/usrp1e/usrp1e_impl.hpp @@ -76,7 +76,7 @@ private: class usrp1e_impl : public uhd::device{ public: //structors - usrp1e_impl(int node_fd); + usrp1e_impl(const std::string &node); ~usrp1e_impl(void); //the io interface @@ -92,6 +92,7 @@ public: void ioctl(int request, void *mem); private: + static const size_t _max_num_samples = 2048/sizeof(boost::uint32_t); int _node_fd; //device functions and settings -- cgit v1.2.3 From 3137e2ca001176c4ffc12e091530fe23c82974b6 Mon Sep 17 00:00:00 2001 From: root Date: Tue, 23 Mar 2010 13:38:46 +0000 Subject: Commit random test code. Unfiltered commit of test code I am accumlating on my ewewoneee. Most of this should go away before release. --- host/apps/omap_debug/fetch-bin.sh | 2 +- host/apps/omap_debug/fetch-kernel.sh | 2 +- host/apps/omap_debug/fetch-module.sh | 3 +- host/apps/omap_debug/fetch-u-boot.sh | 3 ++ host/apps/omap_debug/usrp1-e-rw.c | 97 ++++++++++++++++++++++++++++++++++++ host/apps/omap_debug/usrp1-e-spi.c | 40 +++++++++++++++ host/apps/omap_debug/usrp1-e-write.c | 4 +- host/apps/omap_debug/usrp1_e.h | 56 +++++++++++++++++++++ host/apps/omap_debug/write-eeprom.sh | 92 ++++++++++++++++++++++++++++++++++ 9 files changed, 294 insertions(+), 5 deletions(-) create mode 100755 host/apps/omap_debug/fetch-u-boot.sh create mode 100644 host/apps/omap_debug/usrp1-e-rw.c create mode 100644 host/apps/omap_debug/usrp1-e-spi.c create mode 100644 host/apps/omap_debug/usrp1_e.h create mode 100755 host/apps/omap_debug/write-eeprom.sh diff --git a/host/apps/omap_debug/fetch-bin.sh b/host/apps/omap_debug/fetch-bin.sh index 1ceec4fd2..beff7ffcd 100755 --- a/host/apps/omap_debug/fetch-bin.sh +++ b/host/apps/omap_debug/fetch-bin.sh @@ -1,2 +1,2 @@ -scp balister@192.168.1.182:Download/u1e.bin . +scp balister@astro:/workspace/usrp1-e-dev/u1e.bin . sync diff --git a/host/apps/omap_debug/fetch-kernel.sh b/host/apps/omap_debug/fetch-kernel.sh index 08b470e9b..7023f5d28 100755 --- a/host/apps/omap_debug/fetch-kernel.sh +++ b/host/apps/omap_debug/fetch-kernel.sh @@ -1,3 +1,3 @@ -scp balister@192.168.1.182:src/git/kernel_usrp/arch/arm/boot/uImage /media/mmcblk0p1/uImage +scp balister@192.168.1.167:src/git/kernel_usrp/arch/arm/boot/uImage /media/mmcblk0p1/uImage sync diff --git a/host/apps/omap_debug/fetch-module.sh b/host/apps/omap_debug/fetch-module.sh index 6511958f9..101ea9aef 100755 --- a/host/apps/omap_debug/fetch-module.sh +++ b/host/apps/omap_debug/fetch-module.sh @@ -1,2 +1,3 @@ -scp balister@192.168.1.182:src/git/kernel_usrp/drivers/misc/usrp1_e.ko /lib/modules/2.6.33-rc3/kernel/drivers/misc +scp balister@192.168.1.167:src/git/kernel_usrp/drivers/misc/usrp1_e.ko /lib/modules/2.6.33-rc3/kernel/drivers/misc +scp balister@192.168.1.167:src/git/kernel_usrp/include/linux/usrp1_e.h . sync diff --git a/host/apps/omap_debug/fetch-u-boot.sh b/host/apps/omap_debug/fetch-u-boot.sh new file mode 100755 index 000000000..63d4edcf2 --- /dev/null +++ b/host/apps/omap_debug/fetch-u-boot.sh @@ -0,0 +1,3 @@ +scp balister@astro:/workspace/usrp1-e-dev/u-boot-overo/u-boot.bin /media/mmcblk0p1/ +sync + diff --git a/host/apps/omap_debug/usrp1-e-rw.c b/host/apps/omap_debug/usrp1-e-rw.c new file mode 100644 index 000000000..cd7fbe4dd --- /dev/null +++ b/host/apps/omap_debug/usrp1-e-rw.c @@ -0,0 +1,97 @@ +#include +#include +#include +#include +#include + +struct pkt { + int checksum; + int seq_num; + short data[1020]; +}; + +static int fp; + +static int calc_checksum(struct pkt *p) +{ + int i, sum; + + i = 0; + sum = 0; + + for (i=0; i<1020; i++) + sum += p->data[i]; + + sum += p->seq_num; + + return sum; +} + +static void *read_thread(void *threadid) +{ + int cnt, prev_seq_num; + struct pkt rx_data; + + printf("Greetings from the reading thread!\n"); + + prev_seq_num = 0; + + while (1) { + cnt = read(fp, &rx_data, 2048); + + if (rx_data.seq_num != prev_seq_num + 1) + printf("Sequence number fail, current = %d, previous = %d\n", + rx_data.seq_num, prev_seq_num); + prev_seq_num = rx_data.seq_num; + + if (calc_checksum(&rx_data) != rx_data.checksum) + printf("Checksum fail packet = %d, expected = %d\n", + calc_checksum(&rx_data), rx_data.checksum); + } + +} + +static void *write_thread(void *threadid) +{ + int seq_number, i, cnt; + struct pkt tx_data; + + printf("Greetings from the write thread!\n"); + + for (i=0; i<1020; i++) + tx_data.data[i] = random() >> 16; + + + seq_number = 1; + + while (1) { + tx_data.seq_num = seq_number++; + tx_data.checksum = calc_checksum(&tx_data); + cnt = write(fp, &tx_data, 2048); + } +} + + +int main(int argc, char *argv[]) +{ + int ret; + pthread_t tx, rx; + long int t; + + fp = open("/dev/usrp1_e0", O_RDWR); + printf("fp = %d\n", fp); + + if (pthread_create(&rx, NULL, read_thread, (void *) t)) { + printf("Failed to create rx thread\n"); + exit(-1); + } + + if (pthread_create(&tx, NULL, write_thread, (void *) t)) { + printf("Failed to create tx thread\n"); + exit(-1); + } + + sleep(10000); + + printf("Done sleeping\n"); +} diff --git a/host/apps/omap_debug/usrp1-e-spi.c b/host/apps/omap_debug/usrp1-e-spi.c new file mode 100644 index 000000000..a79d74b18 --- /dev/null +++ b/host/apps/omap_debug/usrp1-e-spi.c @@ -0,0 +1,40 @@ +#include +#include +#include +#include +#include + +#include "usrp1_e.h" + +// Usage: usrp1_e_spi w|rb slave data + +int main(int argc, char *argv[]) +{ + int fp, slave, data, ret; + struct usrp_e_spi spi_dat; + + if (argc < 4) { + printf("Usage: usrp1_e_spi w|rb slave data\n"); + exit(-1); + } + + slave = atoi(argv[2]); + data = atoi(argv[3]); + + fp = open("/dev/usrp1_e0", O_RDWR); + printf("fp = %d\n", fp); + + spi_dat.slave = slave; + spi_dat.data = data; + spi_dat.length = 2; + spi_dat.flags = 0; + + if (*argv[1] == 'r') { + spi_dat.readback = 1; + ret = ioctl(fp, USRP_E_SPI, &spi_dat); + printf("Data returned = %d\n", ret); + } else { + spi_dat.readback = 0; + ioctl(fp, USRP_E_SPI, &spi_dat); + } +} diff --git a/host/apps/omap_debug/usrp1-e-write.c b/host/apps/omap_debug/usrp1-e-write.c index f29cc7032..903c0071f 100644 --- a/host/apps/omap_debug/usrp1-e-write.c +++ b/host/apps/omap_debug/usrp1-e-write.c @@ -14,8 +14,8 @@ int main(int rgc, char *argv[]) buf[i] = i; } - do { +// do { cnt = write(fp, buf, 2048); printf("Bytes written - %d\n", cnt); - } while (1); +// } while (1); } diff --git a/host/apps/omap_debug/usrp1_e.h b/host/apps/omap_debug/usrp1_e.h new file mode 100644 index 000000000..b49b526dc --- /dev/null +++ b/host/apps/omap_debug/usrp1_e.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2010 Ettus Research, LLC + * + * Written by Philip Balister + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __USRP_E_H +#define __USRP_E_H + +#include +#include + +struct usrp1_e_ctl { + __u32 offset; + __u32 count; + __u16 buf[]; +}; + +// SPI interface + +#define UE_SPI_TXONLY 0 +#define UE_SPI_TXRX 1 + +// Defines for spi ctrl register +#define UE_SPI_CTRL_ASS (1<<13) +#define UE_SPI_CTRL_IE (1<<12) +#define UE_SPI_CTRL_LSB (1<<11) +#define UE_SPI_CTRL_TXNEG (1<<10) +#define UE_SPI_CTRL_RXNEG (1<<9) +#define UE_SPI_CTRL_GO_BSY (1<<8) +#define UE_SPI_CTRL_CHAR_LEN_MASK 0x7f + +#define UE_SPI_PUSH_RISE 0 +#define UE_SPI_PUSH_FALL UE_SPI_CTRL_TXNEG +#define UE_SPI_LATCH_RISE 0 +#define UE_SPI_LATCH_FALL UE_SPI_CTRL_RXNEG + +struct usrp_e_spi { + __u8 readback; + __u32 slave; + __u32 data; + __u32 length; + __u32 flags; +}; + +#define USRP_E_IOC_MAGIC 'u' +#define USRP_E_WRITE_CTL _IOW(USRP_E_IOC_MAGIC, 0x20, struct usrp1_e_ctl) +#define USRP_E_READ_CTL _IOWR(USRP_E_IOC_MAGIC, 0x21, struct usrp1_e_ctl) +#define USRP_E_SPI _IOW(USRP_E_IOC_MAGIC, 0x22, struct usrp_e_spi) + +#endif diff --git a/host/apps/omap_debug/write-eeprom.sh b/host/apps/omap_debug/write-eeprom.sh new file mode 100755 index 000000000..301b06f07 --- /dev/null +++ b/host/apps/omap_debug/write-eeprom.sh @@ -0,0 +1,92 @@ +#!/bin/bash + +if [ $# -ne 3 ] && [ $# -ne 5 ]; +then + echo "Usage:" + echo "" + echo "writeprom.sh deviceid rev fab_rev [envvar envsetting]" + echo + echo " deviceid - expansion board device number from table:" + echo + echo " Summit 0x01" + echo " Tobi 0x02" + echo " Tobi Duo 0x03" + echo " Palo35 0x04" + echo " Palo43 0x05" + echo " Chestnut43 0x06" + echo " Pinto 0x07" + echo + echo " rev - board revision (e.g. 0x00)" + echo " fab_rev - revision marking from pcb (e.g. R2411)" + echo " envvar - optional u-boot env variable name" + echo " (e.g. dvimode)" + echo " envsetting - optional u-boot env variable setting" + echo " (e.g. 1024x768MR-16@60)" + exit 1 +fi + +fabrevision=$3 +if [ ${#fabrevision} -ge 8 ]; then + echo "Error: fab revision string must less than 8 characters" + exit 1 +fi + +envvar=$4 +if [ ${#envar} -ge 16 ]; then + echo "Error: environment variable name string must less than 16 characters" + exit 1 +fi + +envsetting=$5 +if [ ${#ensetting} -ge 64 ]; then + echo "Error: environment setting string must less than 64 characters" + exit 1 +fi + +bus=3 +device=0x51 +vendorid=0x03 + +i2cset -y $bus $device 0x00 0x00 +i2cset -y $bus $device 0x01 $vendorid +i2cset -y $bus $device 0x02 0x00 +i2cset -y $bus $device 0x03 $1 +i2cset -y $bus $device 0x04 $2 +i2cset -y $bus $device 0x05 00 + +let i=6 +hexdumpargs="'${#fabrevision}/1 \"0x%02x \"'" +command="echo -n \"$fabrevision\" | hexdump -e $hexdumpargs" +hex=$(eval $command) +for character in $hex; do + i2cset -y $bus $device $i $character + let i=$i+1 +done +i2cset -y $bus $device $i 0x00 + +if [ $# -eq 5 ] +then + i2cset -y $bus $device 0x05 0x01 + + let i=14 + hexdumpargs="'${#envvar}/1 \"0x%02x \"'" + command="echo -n \"$envvar\" | hexdump -e $hexdumpargs" + hex=$(eval $command) + for character in $hex; do + i2cset -y $bus $device $i $character + let i=$i+1 + done + i2cset -y $bus $device $i 0x00 + + let i=30 + hexdumpargs="'${#envsetting}/1 \"0x%02x \"'" + command="echo -n \"$envsetting\" | hexdump -e $hexdumpargs" + hex=$(eval $command) + for character in $hex; do + i2cset -y $bus $device $i $character + let i=$i+1 + done + i2cset -y $bus $device $i 0x00 +fi + + -- cgit v1.2.3 From 4e5429b2839115235c7be778fe334479b833f128 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 24 Mar 2010 11:33:02 -0400 Subject: Start renaming stuff in line with product name USRP Embedded. --- host/apps/omap_debug/usrp-e-ctl.c | 52 +++++++++++++++++++ host/apps/omap_debug/usrp-e-ram.c | 25 ++++++++++ host/apps/omap_debug/usrp-e-read.c | 18 +++++++ host/apps/omap_debug/usrp-e-rw.c | 97 ++++++++++++++++++++++++++++++++++++ host/apps/omap_debug/usrp-e-spi.c | 40 +++++++++++++++ host/apps/omap_debug/usrp-e-write.c | 21 ++++++++ host/apps/omap_debug/usrp1-e-ctl.c | 52 ------------------- host/apps/omap_debug/usrp1-e-ram.c | 25 ---------- host/apps/omap_debug/usrp1-e-read.c | 18 ------- host/apps/omap_debug/usrp1-e-rw.c | 97 ------------------------------------ host/apps/omap_debug/usrp1-e-spi.c | 40 --------------- host/apps/omap_debug/usrp1-e-write.c | 21 -------- 12 files changed, 253 insertions(+), 253 deletions(-) create mode 100644 host/apps/omap_debug/usrp-e-ctl.c create mode 100644 host/apps/omap_debug/usrp-e-ram.c create mode 100644 host/apps/omap_debug/usrp-e-read.c create mode 100644 host/apps/omap_debug/usrp-e-rw.c create mode 100644 host/apps/omap_debug/usrp-e-spi.c create mode 100644 host/apps/omap_debug/usrp-e-write.c delete mode 100644 host/apps/omap_debug/usrp1-e-ctl.c delete mode 100644 host/apps/omap_debug/usrp1-e-ram.c delete mode 100644 host/apps/omap_debug/usrp1-e-read.c delete mode 100644 host/apps/omap_debug/usrp1-e-rw.c delete mode 100644 host/apps/omap_debug/usrp1-e-spi.c delete mode 100644 host/apps/omap_debug/usrp1-e-write.c diff --git a/host/apps/omap_debug/usrp-e-ctl.c b/host/apps/omap_debug/usrp-e-ctl.c new file mode 100644 index 000000000..045e7ce19 --- /dev/null +++ b/host/apps/omap_debug/usrp-e-ctl.c @@ -0,0 +1,52 @@ +#include +#include +#include +#include +#include + +#include "usrp1_e.h" + +// Usage: usrp1_e_ctl w|r offset number_of_values val1 val2 .... + +int main(int argc, char *argv[]) +{ + int fp, i, cnt, ret; + struct usrp1_e_ctl *ctl_data; + + if (argc < 4) { + printf("Usage: usrp1_e_ctl w|r offset number_of_values val1 val2 ....\n"); + exit(-1); + } + + cnt = atoi(argv[3]); + + ctl_data = malloc(sizeof(struct usrp1_e_ctl) + cnt*2); + + ctl_data->offset = atoi(argv[2]); + ctl_data->count = cnt; + + printf("Sizeof usrp1_e_ctl struct = %d\n", sizeof(struct usrp1_e_ctl)); + + fp = open("/dev/usrp1_e0", O_RDWR); + printf("fp = %d\n", fp); + + if (*argv[1] == 'w') { + for (i=0; ibuf[i] = atoi(argv[4+i]); + + ret = ioctl(fp, USRP1_E_WRITE_CTL, ctl_data); + printf("Return value from write ioctl = %d\n", ret); + } + + if (*argv[1] == 'r') { + ret = ioctl(fp, USRP1_E_READ_CTL, ctl_data); + printf("Return value from write ioctl = %d\n", ret); + + for (i=0; icount; i++) { + if (!(i%8)) + printf("\nData at %4d :", i); + printf(" %5d", ctl_data->buf[i]); + } + printf("\n"); + } +} diff --git a/host/apps/omap_debug/usrp-e-ram.c b/host/apps/omap_debug/usrp-e-ram.c new file mode 100644 index 000000000..d548f7ccd --- /dev/null +++ b/host/apps/omap_debug/usrp-e-ram.c @@ -0,0 +1,25 @@ +#include +#include +#include + +int main(int rgc, char *argv[]) +{ + int fp, i, cnt; + unsigned short buf[1024]; + unsigned short buf_rb[1024]; + + fp = open("/dev/usrp1_e0", O_RDWR); + printf("fp = %d\n", fp); + + for (i=0; i<1024; i++) + buf[i] = i*256; + write(fp, buf, 2048); + read(fp, buf_rb, 2048); + + printf("Read back %hX %hX\n", buf_rb[0], buf_rb[1]); + + for (i=0; i<1024; i++) { + if (buf[i] != buf_rb[i]) + printf("Read - %hX, expected - %hX\n", buf_rb[i], buf[i]); + } +} diff --git a/host/apps/omap_debug/usrp-e-read.c b/host/apps/omap_debug/usrp-e-read.c new file mode 100644 index 000000000..c28f018d5 --- /dev/null +++ b/host/apps/omap_debug/usrp-e-read.c @@ -0,0 +1,18 @@ +#include +#include +#include + +int main(int rgc, char *argv[]) +{ + int fp, cnt; + short buf[1024]; + + fp = open("/dev/usrp1_e0", O_RDONLY); + printf("fp = %d\n", fp); + + do { + cnt = read(fp, buf, 2048); +// printf("Bytes read - %d\n", cnt); + } while(1); + printf("Data - %hX\n", buf[0]); +} diff --git a/host/apps/omap_debug/usrp-e-rw.c b/host/apps/omap_debug/usrp-e-rw.c new file mode 100644 index 000000000..cd7fbe4dd --- /dev/null +++ b/host/apps/omap_debug/usrp-e-rw.c @@ -0,0 +1,97 @@ +#include +#include +#include +#include +#include + +struct pkt { + int checksum; + int seq_num; + short data[1020]; +}; + +static int fp; + +static int calc_checksum(struct pkt *p) +{ + int i, sum; + + i = 0; + sum = 0; + + for (i=0; i<1020; i++) + sum += p->data[i]; + + sum += p->seq_num; + + return sum; +} + +static void *read_thread(void *threadid) +{ + int cnt, prev_seq_num; + struct pkt rx_data; + + printf("Greetings from the reading thread!\n"); + + prev_seq_num = 0; + + while (1) { + cnt = read(fp, &rx_data, 2048); + + if (rx_data.seq_num != prev_seq_num + 1) + printf("Sequence number fail, current = %d, previous = %d\n", + rx_data.seq_num, prev_seq_num); + prev_seq_num = rx_data.seq_num; + + if (calc_checksum(&rx_data) != rx_data.checksum) + printf("Checksum fail packet = %d, expected = %d\n", + calc_checksum(&rx_data), rx_data.checksum); + } + +} + +static void *write_thread(void *threadid) +{ + int seq_number, i, cnt; + struct pkt tx_data; + + printf("Greetings from the write thread!\n"); + + for (i=0; i<1020; i++) + tx_data.data[i] = random() >> 16; + + + seq_number = 1; + + while (1) { + tx_data.seq_num = seq_number++; + tx_data.checksum = calc_checksum(&tx_data); + cnt = write(fp, &tx_data, 2048); + } +} + + +int main(int argc, char *argv[]) +{ + int ret; + pthread_t tx, rx; + long int t; + + fp = open("/dev/usrp1_e0", O_RDWR); + printf("fp = %d\n", fp); + + if (pthread_create(&rx, NULL, read_thread, (void *) t)) { + printf("Failed to create rx thread\n"); + exit(-1); + } + + if (pthread_create(&tx, NULL, write_thread, (void *) t)) { + printf("Failed to create tx thread\n"); + exit(-1); + } + + sleep(10000); + + printf("Done sleeping\n"); +} diff --git a/host/apps/omap_debug/usrp-e-spi.c b/host/apps/omap_debug/usrp-e-spi.c new file mode 100644 index 000000000..a79d74b18 --- /dev/null +++ b/host/apps/omap_debug/usrp-e-spi.c @@ -0,0 +1,40 @@ +#include +#include +#include +#include +#include + +#include "usrp1_e.h" + +// Usage: usrp1_e_spi w|rb slave data + +int main(int argc, char *argv[]) +{ + int fp, slave, data, ret; + struct usrp_e_spi spi_dat; + + if (argc < 4) { + printf("Usage: usrp1_e_spi w|rb slave data\n"); + exit(-1); + } + + slave = atoi(argv[2]); + data = atoi(argv[3]); + + fp = open("/dev/usrp1_e0", O_RDWR); + printf("fp = %d\n", fp); + + spi_dat.slave = slave; + spi_dat.data = data; + spi_dat.length = 2; + spi_dat.flags = 0; + + if (*argv[1] == 'r') { + spi_dat.readback = 1; + ret = ioctl(fp, USRP_E_SPI, &spi_dat); + printf("Data returned = %d\n", ret); + } else { + spi_dat.readback = 0; + ioctl(fp, USRP_E_SPI, &spi_dat); + } +} diff --git a/host/apps/omap_debug/usrp-e-write.c b/host/apps/omap_debug/usrp-e-write.c new file mode 100644 index 000000000..903c0071f --- /dev/null +++ b/host/apps/omap_debug/usrp-e-write.c @@ -0,0 +1,21 @@ +#include +#include +#include + +int main(int rgc, char *argv[]) +{ + int fp, i, cnt; + short buf[1024]; + + fp = open("/dev/usrp1_e0", O_WRONLY); + printf("fp = %d\n", fp); + + for (i=0; i<1024; i++) { + buf[i] = i; + } + +// do { + cnt = write(fp, buf, 2048); + printf("Bytes written - %d\n", cnt); +// } while (1); +} diff --git a/host/apps/omap_debug/usrp1-e-ctl.c b/host/apps/omap_debug/usrp1-e-ctl.c deleted file mode 100644 index 045e7ce19..000000000 --- a/host/apps/omap_debug/usrp1-e-ctl.c +++ /dev/null @@ -1,52 +0,0 @@ -#include -#include -#include -#include -#include - -#include "usrp1_e.h" - -// Usage: usrp1_e_ctl w|r offset number_of_values val1 val2 .... - -int main(int argc, char *argv[]) -{ - int fp, i, cnt, ret; - struct usrp1_e_ctl *ctl_data; - - if (argc < 4) { - printf("Usage: usrp1_e_ctl w|r offset number_of_values val1 val2 ....\n"); - exit(-1); - } - - cnt = atoi(argv[3]); - - ctl_data = malloc(sizeof(struct usrp1_e_ctl) + cnt*2); - - ctl_data->offset = atoi(argv[2]); - ctl_data->count = cnt; - - printf("Sizeof usrp1_e_ctl struct = %d\n", sizeof(struct usrp1_e_ctl)); - - fp = open("/dev/usrp1_e0", O_RDWR); - printf("fp = %d\n", fp); - - if (*argv[1] == 'w') { - for (i=0; ibuf[i] = atoi(argv[4+i]); - - ret = ioctl(fp, USRP1_E_WRITE_CTL, ctl_data); - printf("Return value from write ioctl = %d\n", ret); - } - - if (*argv[1] == 'r') { - ret = ioctl(fp, USRP1_E_READ_CTL, ctl_data); - printf("Return value from write ioctl = %d\n", ret); - - for (i=0; icount; i++) { - if (!(i%8)) - printf("\nData at %4d :", i); - printf(" %5d", ctl_data->buf[i]); - } - printf("\n"); - } -} diff --git a/host/apps/omap_debug/usrp1-e-ram.c b/host/apps/omap_debug/usrp1-e-ram.c deleted file mode 100644 index d548f7ccd..000000000 --- a/host/apps/omap_debug/usrp1-e-ram.c +++ /dev/null @@ -1,25 +0,0 @@ -#include -#include -#include - -int main(int rgc, char *argv[]) -{ - int fp, i, cnt; - unsigned short buf[1024]; - unsigned short buf_rb[1024]; - - fp = open("/dev/usrp1_e0", O_RDWR); - printf("fp = %d\n", fp); - - for (i=0; i<1024; i++) - buf[i] = i*256; - write(fp, buf, 2048); - read(fp, buf_rb, 2048); - - printf("Read back %hX %hX\n", buf_rb[0], buf_rb[1]); - - for (i=0; i<1024; i++) { - if (buf[i] != buf_rb[i]) - printf("Read - %hX, expected - %hX\n", buf_rb[i], buf[i]); - } -} diff --git a/host/apps/omap_debug/usrp1-e-read.c b/host/apps/omap_debug/usrp1-e-read.c deleted file mode 100644 index c28f018d5..000000000 --- a/host/apps/omap_debug/usrp1-e-read.c +++ /dev/null @@ -1,18 +0,0 @@ -#include -#include -#include - -int main(int rgc, char *argv[]) -{ - int fp, cnt; - short buf[1024]; - - fp = open("/dev/usrp1_e0", O_RDONLY); - printf("fp = %d\n", fp); - - do { - cnt = read(fp, buf, 2048); -// printf("Bytes read - %d\n", cnt); - } while(1); - printf("Data - %hX\n", buf[0]); -} diff --git a/host/apps/omap_debug/usrp1-e-rw.c b/host/apps/omap_debug/usrp1-e-rw.c deleted file mode 100644 index cd7fbe4dd..000000000 --- a/host/apps/omap_debug/usrp1-e-rw.c +++ /dev/null @@ -1,97 +0,0 @@ -#include -#include -#include -#include -#include - -struct pkt { - int checksum; - int seq_num; - short data[1020]; -}; - -static int fp; - -static int calc_checksum(struct pkt *p) -{ - int i, sum; - - i = 0; - sum = 0; - - for (i=0; i<1020; i++) - sum += p->data[i]; - - sum += p->seq_num; - - return sum; -} - -static void *read_thread(void *threadid) -{ - int cnt, prev_seq_num; - struct pkt rx_data; - - printf("Greetings from the reading thread!\n"); - - prev_seq_num = 0; - - while (1) { - cnt = read(fp, &rx_data, 2048); - - if (rx_data.seq_num != prev_seq_num + 1) - printf("Sequence number fail, current = %d, previous = %d\n", - rx_data.seq_num, prev_seq_num); - prev_seq_num = rx_data.seq_num; - - if (calc_checksum(&rx_data) != rx_data.checksum) - printf("Checksum fail packet = %d, expected = %d\n", - calc_checksum(&rx_data), rx_data.checksum); - } - -} - -static void *write_thread(void *threadid) -{ - int seq_number, i, cnt; - struct pkt tx_data; - - printf("Greetings from the write thread!\n"); - - for (i=0; i<1020; i++) - tx_data.data[i] = random() >> 16; - - - seq_number = 1; - - while (1) { - tx_data.seq_num = seq_number++; - tx_data.checksum = calc_checksum(&tx_data); - cnt = write(fp, &tx_data, 2048); - } -} - - -int main(int argc, char *argv[]) -{ - int ret; - pthread_t tx, rx; - long int t; - - fp = open("/dev/usrp1_e0", O_RDWR); - printf("fp = %d\n", fp); - - if (pthread_create(&rx, NULL, read_thread, (void *) t)) { - printf("Failed to create rx thread\n"); - exit(-1); - } - - if (pthread_create(&tx, NULL, write_thread, (void *) t)) { - printf("Failed to create tx thread\n"); - exit(-1); - } - - sleep(10000); - - printf("Done sleeping\n"); -} diff --git a/host/apps/omap_debug/usrp1-e-spi.c b/host/apps/omap_debug/usrp1-e-spi.c deleted file mode 100644 index a79d74b18..000000000 --- a/host/apps/omap_debug/usrp1-e-spi.c +++ /dev/null @@ -1,40 +0,0 @@ -#include -#include -#include -#include -#include - -#include "usrp1_e.h" - -// Usage: usrp1_e_spi w|rb slave data - -int main(int argc, char *argv[]) -{ - int fp, slave, data, ret; - struct usrp_e_spi spi_dat; - - if (argc < 4) { - printf("Usage: usrp1_e_spi w|rb slave data\n"); - exit(-1); - } - - slave = atoi(argv[2]); - data = atoi(argv[3]); - - fp = open("/dev/usrp1_e0", O_RDWR); - printf("fp = %d\n", fp); - - spi_dat.slave = slave; - spi_dat.data = data; - spi_dat.length = 2; - spi_dat.flags = 0; - - if (*argv[1] == 'r') { - spi_dat.readback = 1; - ret = ioctl(fp, USRP_E_SPI, &spi_dat); - printf("Data returned = %d\n", ret); - } else { - spi_dat.readback = 0; - ioctl(fp, USRP_E_SPI, &spi_dat); - } -} diff --git a/host/apps/omap_debug/usrp1-e-write.c b/host/apps/omap_debug/usrp1-e-write.c deleted file mode 100644 index 903c0071f..000000000 --- a/host/apps/omap_debug/usrp1-e-write.c +++ /dev/null @@ -1,21 +0,0 @@ -#include -#include -#include - -int main(int rgc, char *argv[]) -{ - int fp, i, cnt; - short buf[1024]; - - fp = open("/dev/usrp1_e0", O_WRONLY); - printf("fp = %d\n", fp); - - for (i=0; i<1024; i++) { - buf[i] = i; - } - -// do { - cnt = write(fp, buf, 2048); - printf("Bytes written - %d\n", cnt); -// } while (1); -} -- cgit v1.2.3 From 5463912c324639791b354dea0d6af5e42c1eae77 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 24 Mar 2010 12:00:05 -0400 Subject: Start applying order through Makefile. --- host/apps/omap_debug/Makefile | 1 + 1 file changed, 1 insertion(+) create mode 100644 host/apps/omap_debug/Makefile diff --git a/host/apps/omap_debug/Makefile b/host/apps/omap_debug/Makefile new file mode 100644 index 000000000..5616a7355 --- /dev/null +++ b/host/apps/omap_debug/Makefile @@ -0,0 +1 @@ +usrp-e-spi : usrp-e-spi.c -- cgit v1.2.3 From 550bf3230aa1a5e7236d5bdb64a77c4ae1acea66 Mon Sep 17 00:00:00 2001 From: root Date: Wed, 24 Mar 2010 16:57:48 +0000 Subject: Update usrp1_e.h header file to match kernel driver. --- host/apps/omap_debug/usrp1_e.h | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/host/apps/omap_debug/usrp1_e.h b/host/apps/omap_debug/usrp1_e.h index b49b526dc..b34446b01 100644 --- a/host/apps/omap_debug/usrp1_e.h +++ b/host/apps/omap_debug/usrp1_e.h @@ -15,10 +15,16 @@ #include #include -struct usrp1_e_ctl { +struct usrp1_e_ctl16 { __u32 offset; __u32 count; - __u16 buf[]; + __u16 buf[20]; +}; + +struct usrp1_e_ctl32 { + __u32 offset; + __u32 count; + __u32 buf[10]; }; // SPI interface @@ -48,9 +54,19 @@ struct usrp_e_spi { __u32 flags; }; +struct usrp_e_i2c { + __u8 addr; + __u32 len; + __u8 data[]; +}; + #define USRP_E_IOC_MAGIC 'u' -#define USRP_E_WRITE_CTL _IOW(USRP_E_IOC_MAGIC, 0x20, struct usrp1_e_ctl) -#define USRP_E_READ_CTL _IOWR(USRP_E_IOC_MAGIC, 0x21, struct usrp1_e_ctl) -#define USRP_E_SPI _IOW(USRP_E_IOC_MAGIC, 0x22, struct usrp_e_spi) +#define USRP_E_WRITE_CTL16 _IOW(USRP_E_IOC_MAGIC, 0x20, struct usrp1_e_ctl16) +#define USRP_E_READ_CTL16 _IOWR(USRP_E_IOC_MAGIC, 0x21, struct usrp1_e_ctl16) +#define USRP_E_WRITE_CTL32 _IOW(USRP_E_IOC_MAGIC, 0x22, struct usrp1_e_ctl32) +#define USRP_E_READ_CTL32 _IOWR(USRP_E_IOC_MAGIC, 0x23, struct usrp1_e_ctl32) +#define USRP_E_SPI _IOW(USRP_E_IOC_MAGIC, 0x24, struct usrp_e_spi) +#define USRP_E_I2C_READ _IOR(USRP_E_IOC_MAGIC, 0x25, struct usrp_e_i2c) +#define USRP_E_I2C_WRITE _IOW(USRP_E_IOC_MAGIC, 0x26, struct usrp_e_i2c) #endif -- cgit v1.2.3 From 4f5cd64188c7e2b5490d910d5e86301c053960ea Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 24 Mar 2010 15:49:08 -0400 Subject: Makefile and usrp-e-spi edits, add i2c test program. --- host/apps/omap_debug/Makefile | 10 ++++++ host/apps/omap_debug/usrp-e-i2c.c | 71 +++++++++++++++++++++++++++++++++++++++ host/apps/omap_debug/usrp-e-spi.c | 4 ++- 3 files changed, 84 insertions(+), 1 deletion(-) create mode 100644 host/apps/omap_debug/usrp-e-i2c.c diff --git a/host/apps/omap_debug/Makefile b/host/apps/omap_debug/Makefile index 5616a7355..07545a639 100644 --- a/host/apps/omap_debug/Makefile +++ b/host/apps/omap_debug/Makefile @@ -1 +1,11 @@ +CFLAGS=-Wall + +all : usrp-e-spi usrp-e-i2c + usrp-e-spi : usrp-e-spi.c + +usrp-e-i2c : usrp-e-i2c.c + +clean : + rm -f usrp-e-spi + rm -f usrp-e-i2c diff --git a/host/apps/omap_debug/usrp-e-i2c.c b/host/apps/omap_debug/usrp-e-i2c.c new file mode 100644 index 000000000..dce1ae153 --- /dev/null +++ b/host/apps/omap_debug/usrp-e-i2c.c @@ -0,0 +1,71 @@ +#include +#include +#include +#include +#include +#include + +#include "usrp1_e.h" + +// Usage: usrp_e_i2c w address data0 data1 data 2 .... +// Usage: usrp_e_i2c r address count + +int main(int argc, char *argv[]) +{ + int fp, ret, i; + struct usrp_e_i2c *i2c_msg; + int direction, address, count; + + if (argc < 3) { + printf("Usage: usrp1_e_i2c w address data0 data1 data2 ...\n"); + printf("Usage: usrp1_e_i2c r address count\n"); + exit(-1); + } + + if (strcmp(argv[1], "r") == 0) { + direction = 0; + } else if (strcmp(argv[1], "w") == 0) { + direction = 1; + } else { + return -1; + } + + address = atoi(argv[2]); + + fp = open("/dev/usrp1_e0", O_RDWR); + printf("fp = %d\n", fp); + + if (direction) { + count = argc - 2; + } else { + count = atoi(argv[3]); + } + + i2c_msg = malloc(sizeof(i2c_msg) + count * sizeof(char)); + + i2c_msg->addr = address; + i2c_msg->len = count; + + if (direction) { + // Write + + for (i=0; idata[i] = atoi(argv[3+i]); + } + + ret = ioctl(fp, USRP_E_I2C_WRITE, i2c_msg); + printf("Return value from i2c_write ioctl: %d\n", ret); + } else { + // Read + + ret = ioctl(fp, USRP_E_I2C_READ, i2c_msg); + + printf("Ioctl: %d Data read :", ret); + for (i=0; idata[i]); + } + printf("/n"); + + } + return 0; +} diff --git a/host/apps/omap_debug/usrp-e-spi.c b/host/apps/omap_debug/usrp-e-spi.c index a79d74b18..e10e72b80 100644 --- a/host/apps/omap_debug/usrp-e-spi.c +++ b/host/apps/omap_debug/usrp-e-spi.c @@ -2,7 +2,7 @@ #include #include #include -#include +#include #include "usrp1_e.h" @@ -37,4 +37,6 @@ int main(int argc, char *argv[]) spi_dat.readback = 0; ioctl(fp, USRP_E_SPI, &spi_dat); } + + return 0; } -- cgit v1.2.3 From 28e5e0740a8fc3c7233a1bd5cc6bbc897c586da6 Mon Sep 17 00:00:00 2001 From: root Date: Thu, 25 Mar 2010 17:42:36 +0000 Subject: Updates for header file change from usrp1_e.h to usrp_e.h. --- host/apps/omap_debug/fetch-module.sh | 4 +- host/apps/omap_debug/usrp-e-i2c.c | 8 ++-- host/apps/omap_debug/usrp-e-spi.c | 8 ++-- host/apps/omap_debug/usrp1_e.h | 72 ------------------------------------ host/apps/omap_debug/usrp_e.h | 72 ++++++++++++++++++++++++++++++++++++ 5 files changed, 82 insertions(+), 82 deletions(-) delete mode 100644 host/apps/omap_debug/usrp1_e.h create mode 100644 host/apps/omap_debug/usrp_e.h diff --git a/host/apps/omap_debug/fetch-module.sh b/host/apps/omap_debug/fetch-module.sh index 101ea9aef..45cf1f052 100755 --- a/host/apps/omap_debug/fetch-module.sh +++ b/host/apps/omap_debug/fetch-module.sh @@ -1,3 +1,3 @@ -scp balister@192.168.1.167:src/git/kernel_usrp/drivers/misc/usrp1_e.ko /lib/modules/2.6.33-rc3/kernel/drivers/misc -scp balister@192.168.1.167:src/git/kernel_usrp/include/linux/usrp1_e.h . +scp balister@192.168.1.167:src/git/kernel_usrp/drivers/misc/usrp_e.ko /lib/modules/2.6.33-rc3/kernel/drivers/misc +scp balister@192.168.1.167:src/git/kernel_usrp/include/linux/usrp_e.h . sync diff --git a/host/apps/omap_debug/usrp-e-i2c.c b/host/apps/omap_debug/usrp-e-i2c.c index dce1ae153..417d6d580 100644 --- a/host/apps/omap_debug/usrp-e-i2c.c +++ b/host/apps/omap_debug/usrp-e-i2c.c @@ -5,7 +5,7 @@ #include #include -#include "usrp1_e.h" +#include "usrp_e.h" // Usage: usrp_e_i2c w address data0 data1 data 2 .... // Usage: usrp_e_i2c r address count @@ -17,8 +17,8 @@ int main(int argc, char *argv[]) int direction, address, count; if (argc < 3) { - printf("Usage: usrp1_e_i2c w address data0 data1 data2 ...\n"); - printf("Usage: usrp1_e_i2c r address count\n"); + printf("Usage: usrp_e_i2c w address data0 data1 data2 ...\n"); + printf("Usage: usrp_e_i2c r address count\n"); exit(-1); } @@ -32,7 +32,7 @@ int main(int argc, char *argv[]) address = atoi(argv[2]); - fp = open("/dev/usrp1_e0", O_RDWR); + fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); if (direction) { diff --git a/host/apps/omap_debug/usrp-e-spi.c b/host/apps/omap_debug/usrp-e-spi.c index e10e72b80..1af47b172 100644 --- a/host/apps/omap_debug/usrp-e-spi.c +++ b/host/apps/omap_debug/usrp-e-spi.c @@ -4,9 +4,9 @@ #include #include -#include "usrp1_e.h" +#include "usrp_e.h" -// Usage: usrp1_e_spi w|rb slave data +// Usage: usrp_e_spi w|rb slave data int main(int argc, char *argv[]) { @@ -14,14 +14,14 @@ int main(int argc, char *argv[]) struct usrp_e_spi spi_dat; if (argc < 4) { - printf("Usage: usrp1_e_spi w|rb slave data\n"); + printf("Usage: usrp_e_spi w|rb slave data\n"); exit(-1); } slave = atoi(argv[2]); data = atoi(argv[3]); - fp = open("/dev/usrp1_e0", O_RDWR); + fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); spi_dat.slave = slave; diff --git a/host/apps/omap_debug/usrp1_e.h b/host/apps/omap_debug/usrp1_e.h deleted file mode 100644 index b34446b01..000000000 --- a/host/apps/omap_debug/usrp1_e.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (C) 2010 Ettus Research, LLC - * - * Written by Philip Balister - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef __USRP_E_H -#define __USRP_E_H - -#include -#include - -struct usrp1_e_ctl16 { - __u32 offset; - __u32 count; - __u16 buf[20]; -}; - -struct usrp1_e_ctl32 { - __u32 offset; - __u32 count; - __u32 buf[10]; -}; - -// SPI interface - -#define UE_SPI_TXONLY 0 -#define UE_SPI_TXRX 1 - -// Defines for spi ctrl register -#define UE_SPI_CTRL_ASS (1<<13) -#define UE_SPI_CTRL_IE (1<<12) -#define UE_SPI_CTRL_LSB (1<<11) -#define UE_SPI_CTRL_TXNEG (1<<10) -#define UE_SPI_CTRL_RXNEG (1<<9) -#define UE_SPI_CTRL_GO_BSY (1<<8) -#define UE_SPI_CTRL_CHAR_LEN_MASK 0x7f - -#define UE_SPI_PUSH_RISE 0 -#define UE_SPI_PUSH_FALL UE_SPI_CTRL_TXNEG -#define UE_SPI_LATCH_RISE 0 -#define UE_SPI_LATCH_FALL UE_SPI_CTRL_RXNEG - -struct usrp_e_spi { - __u8 readback; - __u32 slave; - __u32 data; - __u32 length; - __u32 flags; -}; - -struct usrp_e_i2c { - __u8 addr; - __u32 len; - __u8 data[]; -}; - -#define USRP_E_IOC_MAGIC 'u' -#define USRP_E_WRITE_CTL16 _IOW(USRP_E_IOC_MAGIC, 0x20, struct usrp1_e_ctl16) -#define USRP_E_READ_CTL16 _IOWR(USRP_E_IOC_MAGIC, 0x21, struct usrp1_e_ctl16) -#define USRP_E_WRITE_CTL32 _IOW(USRP_E_IOC_MAGIC, 0x22, struct usrp1_e_ctl32) -#define USRP_E_READ_CTL32 _IOWR(USRP_E_IOC_MAGIC, 0x23, struct usrp1_e_ctl32) -#define USRP_E_SPI _IOW(USRP_E_IOC_MAGIC, 0x24, struct usrp_e_spi) -#define USRP_E_I2C_READ _IOR(USRP_E_IOC_MAGIC, 0x25, struct usrp_e_i2c) -#define USRP_E_I2C_WRITE _IOW(USRP_E_IOC_MAGIC, 0x26, struct usrp_e_i2c) - -#endif diff --git a/host/apps/omap_debug/usrp_e.h b/host/apps/omap_debug/usrp_e.h new file mode 100644 index 000000000..aa8ef3d57 --- /dev/null +++ b/host/apps/omap_debug/usrp_e.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2010 Ettus Research, LLC + * + * Written by Philip Balister + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __USRP_E_H +#define __USRP_E_H + +#include +#include + +struct usrp_e_ctl16 { + __u32 offset; + __u32 count; + __u16 buf[20]; +}; + +struct usrp_e_ctl32 { + __u32 offset; + __u32 count; + __u32 buf[10]; +}; + +// SPI interface + +#define UE_SPI_TXONLY 0 +#define UE_SPI_TXRX 1 + +// Defines for spi ctrl register +#define UE_SPI_CTRL_ASS (1<<13) +#define UE_SPI_CTRL_IE (1<<12) +#define UE_SPI_CTRL_LSB (1<<11) +#define UE_SPI_CTRL_TXNEG (1<<10) +#define UE_SPI_CTRL_RXNEG (1<<9) +#define UE_SPI_CTRL_GO_BSY (1<<8) +#define UE_SPI_CTRL_CHAR_LEN_MASK 0x7f + +#define UE_SPI_PUSH_RISE 0 +#define UE_SPI_PUSH_FALL UE_SPI_CTRL_TXNEG +#define UE_SPI_LATCH_RISE 0 +#define UE_SPI_LATCH_FALL UE_SPI_CTRL_RXNEG + +struct usrp_e_spi { + __u8 readback; + __u32 slave; + __u32 data; + __u32 length; + __u32 flags; +}; + +struct usrp_e_i2c { + __u8 addr; + __u32 len; + __u8 data[]; +}; + +#define USRP_E_IOC_MAGIC 'u' +#define USRP_E_WRITE_CTL16 _IOW(USRP_E_IOC_MAGIC, 0x20, struct usrp_e_ctl16) +#define USRP_E_READ_CTL16 _IOWR(USRP_E_IOC_MAGIC, 0x21, struct usrp_e_ctl16) +#define USRP_E_WRITE_CTL32 _IOW(USRP_E_IOC_MAGIC, 0x22, struct usrp_e_ctl32) +#define USRP_E_READ_CTL32 _IOWR(USRP_E_IOC_MAGIC, 0x23, struct usrp_e_ctl32) +#define USRP_E_SPI _IOW(USRP_E_IOC_MAGIC, 0x24, struct usrp_e_spi) +#define USRP_E_I2C_READ _IOR(USRP_E_IOC_MAGIC, 0x25, struct usrp_e_i2c) +#define USRP_E_I2C_WRITE _IOW(USRP_E_IOC_MAGIC, 0x26, struct usrp_e_i2c) + +#endif -- cgit v1.2.3 From 717a6acd2b0687348c492cbf2e0813ffd63d847a Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 25 Mar 2010 20:43:59 +0000 Subject: Update read/write test program to new header name and add to Makefile. --- host/apps/omap_debug/Makefile | 6 +++++- host/apps/omap_debug/usrp-e-rw.c | 4 ++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/host/apps/omap_debug/Makefile b/host/apps/omap_debug/Makefile index 07545a639..34446ccc3 100644 --- a/host/apps/omap_debug/Makefile +++ b/host/apps/omap_debug/Makefile @@ -1,11 +1,15 @@ CFLAGS=-Wall -all : usrp-e-spi usrp-e-i2c +all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-spi : usrp-e-spi.c usrp-e-i2c : usrp-e-i2c.c +usrp-e-rw : usrp-e-rw.c + gcc -o $@ $< -lpthread clean : rm -f usrp-e-spi rm -f usrp-e-i2c + rm -f usrp-e-rw + diff --git a/host/apps/omap_debug/usrp-e-rw.c b/host/apps/omap_debug/usrp-e-rw.c index cd7fbe4dd..5607166b0 100644 --- a/host/apps/omap_debug/usrp-e-rw.c +++ b/host/apps/omap_debug/usrp-e-rw.c @@ -3,6 +3,7 @@ #include #include #include +#include struct pkt { int checksum; @@ -74,11 +75,10 @@ static void *write_thread(void *threadid) int main(int argc, char *argv[]) { - int ret; pthread_t tx, rx; long int t; - fp = open("/dev/usrp1_e0", O_RDWR); + fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); if (pthread_create(&rx, NULL, read_thread, (void *) t)) { -- cgit v1.2.3 From b74388567c0ed3048e45158ac077e31def59fea1 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 25 Mar 2010 15:49:23 -0700 Subject: connected spi pins, but the spi core still needs to be redone for 16 bit interfaces Also reconnected GPIOs so you'll need to send commands in order to get debug pins on the GPIOs --- usrp2/top/u1e/u1e.ucf | 72 ++++++++++++++++++++++++++---------------------- usrp2/top/u1e/u1e.v | 16 +++++++++++ usrp2/top/u1e/u1e_core.v | 12 ++++---- 3 files changed, 60 insertions(+), 40 deletions(-) diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index f237eb60c..27f507c6b 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -68,27 +68,43 @@ NET "overo_gpio147" LOC = "B6" ; # rx_overrun #NET "overo_txd1" LOC = "C6" ; #NET "overo_rxd1" LOC = "D6" ; +## FTDI UART to USB converter NET "FPGA_TXD" LOC = "U1" ; NET "FPGA_RXD" LOC = "T6" ; #NET "SYSEN" LOC = "C11" ; +## I2C NET "db_scl" LOC = "U4" ; NET "db_sda" LOC = "U5" ; -#NET "db_sclk_rx" LOC = "W3" ; -#NET "db_miso_rx" LOC = "W2" ; -#NET "db_mosi_rx" LOC = "V4" ; -#NET "db_sen_rx" LOC = "V3" ; -#NET "db_sclk_tx" LOC = "Y1" ; -#NET "db_miso_tx" LOC = "W1" ; -#NET "db_mosi_tx" LOC = "R3" ; -#NET "db_sen_tx" LOC = "T4" ; -## Clock Gen -#NET "cgen_miso" LOC = "U2" ; -#NET "cgen_mosi" LOC = "V1" ; -#NET "cgen_sclk" LOC = "R5" ; -#NET "cgen_sen_b" LOC = "T1" ; +## SPI +### DBoard SPI +NET "db_sclk_rx" LOC = "W3" ; +NET "db_miso_rx" LOC = "W2" ; +NET "db_mosi_rx" LOC = "V4" ; +NET "db_sen_rx" LOC = "V3" ; +NET "db_sclk_tx" LOC = "Y1" ; +NET "db_miso_tx" LOC = "W1" ; +NET "db_mosi_tx" LOC = "R3" ; +NET "db_sen_tx" LOC = "T4" ; + +### AD9862 SPI and aux SPI Interfaces +#NET "aux_sdi_codec" LOC = "F19" ; +#NET "aux_sdo_codec" LOC = "F18" ; +#NET "aux_sclk_codec" LOC = "D21" ; +NET "sen_codec" LOC = "D20" ; +NET "mosi_codec" LOC = "E19" ; +NET "miso_codec" LOC = "F21" ; +NET "sclk_codec" LOC = "E20" ; + +### Clock Gen SPI +NET "cgen_miso" LOC = "U2" ; +NET "cgen_mosi" LOC = "V1" ; +NET "cgen_sclk" LOC = "R5" ; +NET "cgen_sen_b" LOC = "T1" ; + +## Clock gen control #NET "cgen_st_status" LOC = "D4" ; #NET "cgen_st_ld" LOC = "D1" ; #NET "cgen_st_refmon" LOC = "E1" ; @@ -147,17 +163,8 @@ NET "dip_sw<2>" LOC = "J4" ; NET "dip_sw<1>" LOC = "J6" ; NET "dip_sw<0>" LOC = "J7" ; -## AD9862 Interface -#NET "aux_sdi_codec" LOC = "F19" ; -#NET "aux_sdo_codec" LOC = "F18" ; -#NET "aux_sclk_codec" LOC = "D21" ; -#NET "reset_codec" LOC = "D22" ; -#NET "sen_codec" LOC = "D20" ; -#NET "mosi_codec" LOC = "E19" ; -#NET "miso_codec" LOC = "F21" ; -#NET "sclk_codec" LOC = "E20" ; - #NET "RXSYNC" LOC = "F22" ; +#NET "reset_codec" LOC = "D22" ; #NET "DB<11>" LOC = "E22" ; #NET "DB<10>" LOC = "J19" ; @@ -248,13 +255,12 @@ NET "io_rx<15>" LOC = "Y4" ; #NET "fpga_cfg_init_b" LOC = "W15" ; ## Unnamed, need to figure out what they do -#NET "unnamed_net37" LOC = "B1" ; -#NET "unnamed_net36" LOC = "B22" ; -#NET "unnamed_net35" LOC = "D2" ; -#NET "unnamed_net34" LOC = "A21" ; -#NET "unnamed_net45" LOC = "F7" ; -#NET "unnamed_net44" LOC = "V6" ; -#NET "unnamed_net43" LOC = "AA3" ; -#NET "unnamed_net42" LOC = "AB3" ; - -#NET "GND" LOC = "V19" ; +#NET "unnamed_net37" LOC = "B1" ; # TMS +#NET "unnamed_net36" LOC = "B22" ; # TDO +#NET "unnamed_net35" LOC = "D2" ; # TDI +#NET "unnamed_net34" LOC = "A21" ; # TCK +#NET "unnamed_net45" LOC = "F7" ; # PUDC_B +#NET "unnamed_net44" LOC = "V6" ; # M2 +#NET "unnamed_net43" LOC = "AA3" ; # M1 +#NET "unnamed_net42" LOC = "AB3" ; # M0 +#NET "GND" LOC = "V19" ; # Suspend, unused diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 329d61aa9..f1f491a97 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -11,6 +11,12 @@ module u1e input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, inout db_sda, inout db_scl, // I2C + + output db_sclk_tx, output db_sen_tx, output db_mosi_tx, input db_miso_tx, // DB TX SPI + output db_sclk_rx, output db_sen_rx, output db_mosi_rx, input db_miso_rx, // DB TX SPI + output sclk_codec, output sen_codec, output mosi_codec, input miso_codec, // AD9862 main SPI + output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso, // Clock gen SPI + output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls inout [15:0] io_tx, inout [15:0] io_rx ); @@ -21,6 +27,15 @@ module u1e IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + // SPI pins + wire mosi, sclk, miso; + assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0; + assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0; + assign { sclk_codec, mosi_codec } = ~sen_codec ? {sclk,mosi} : 2'b0; + assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0; + assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) | + (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso); + u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb[2]), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), .debug_pb(~debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), @@ -28,6 +43,7 @@ module u1e .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .db_sda(db_sda), .db_scl(db_scl), + .sclk(sclk), .sen({cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso), .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), .io_tx(io_tx), .io_rx(io_rx) ); diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 2645225a0..c74d385ee 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -9,6 +9,8 @@ module u1e_core input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, inout db_sda, inout db_scl, + output sclk, output [7:0] sen, output mosi, input miso, + output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, inout [15:0] io_tx, inout [15:0] io_rx ); @@ -187,14 +189,11 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////////////////// // Slave 2, SPI - /* spi_top shared_spi (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), - .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), - .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); - */ + .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) ); // ///////////////////////////////////////////////////////////////////////// // Slave 3, I2C @@ -216,7 +215,7 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////// // GPIOs -- Slave #4 -/* + wire [31:0] atr_lines; wire [31:0] debug_gpio_0, debug_gpio_1; @@ -226,7 +225,7 @@ module u1e_core .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), .gpio( {io_tx,io_rx} ) ); -*/ + // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #5 @@ -247,7 +246,6 @@ module u1e_core assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, { EM_D } }; - assign {io_tx,io_rx} = debug_gpmc; assign debug_gpio_0 = { debug_gpmc }; assign debug_gpio_1 = { debug_txd, debug_rxd }; -- cgit v1.2.3 From 84df070f371b989ef51b6f2d04c131b34308e5e9 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Fri, 26 Mar 2010 15:22:12 +0000 Subject: Add test program to send characters to the wishbone uart. --- host/apps/omap_debug/Makefile | 6 +++++- host/apps/omap_debug/usrp-e-uart.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 host/apps/omap_debug/usrp-e-uart.c diff --git a/host/apps/omap_debug/Makefile b/host/apps/omap_debug/Makefile index 34446ccc3..13b834e28 100644 --- a/host/apps/omap_debug/Makefile +++ b/host/apps/omap_debug/Makefile @@ -1,6 +1,6 @@ CFLAGS=-Wall -all : usrp-e-spi usrp-e-i2c usrp-e-rw +all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-spi : usrp-e-spi.c @@ -8,8 +8,12 @@ usrp-e-i2c : usrp-e-i2c.c usrp-e-rw : usrp-e-rw.c gcc -o $@ $< -lpthread + +usrp-e-uart : usrp-e-uart.c + clean : rm -f usrp-e-spi rm -f usrp-e-i2c rm -f usrp-e-rw + rm -f usrp-e-uart diff --git a/host/apps/omap_debug/usrp-e-uart.c b/host/apps/omap_debug/usrp-e-uart.c new file mode 100644 index 000000000..92f89f45c --- /dev/null +++ b/host/apps/omap_debug/usrp-e-uart.c @@ -0,0 +1,37 @@ +#include +#include +#include +#include +#include +#include + +#include "usrp_e.h" + +// Usage: usrp_e_uart + +#define UART_WRITE_ADDR ((1<<6) + 16) + +int main(int argc, char *argv[]) +{ + int fp, i, ret; + struct usrp_e_ctl16 d; + char *str = argv[1]; + + if (argc < 2) { + printf("Usage: usrp_e_uart n"); + exit(-1); + } + + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); + + for (i=0; i Date: Fri, 26 Mar 2010 11:30:13 -0700 Subject: connect 2 clock gen controls and 3 status pins to the wishbone so they can be read/controlled from SW --- usrp2/top/u1e/u1e.ucf | 10 +++++----- usrp2/top/u1e/u1e.v | 4 ++++ usrp2/top/u1e/u1e_core.v | 20 +++++++++++++++++--- 3 files changed, 26 insertions(+), 8 deletions(-) diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 27f507c6b..c39759d0b 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -105,11 +105,11 @@ NET "cgen_sclk" LOC = "R5" ; NET "cgen_sen_b" LOC = "T1" ; ## Clock gen control -#NET "cgen_st_status" LOC = "D4" ; -#NET "cgen_st_ld" LOC = "D1" ; -#NET "cgen_st_refmon" LOC = "E1" ; -#NET "cgen_sync_b" LOC = "M1" ; -#NET "cgen_ref_sel" LOC = "J1" ; +NET "cgen_st_status" LOC = "D4" ; +NET "cgen_st_ld" LOC = "D1" ; +NET "cgen_st_refmon" LOC = "E1" ; +NET "cgen_sync_b" LOC = "M1" ; +NET "cgen_ref_sel" LOC = "J1" ; ## Debug pins NET "debug_led<2>" LOC = "T5" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index f1f491a97..ab270879c 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -16,6 +16,8 @@ module u1e output db_sclk_rx, output db_sen_rx, output db_mosi_rx, input db_miso_rx, // DB TX SPI output sclk_codec, output sen_codec, output mosi_codec, input miso_codec, // AD9862 main SPI output cgen_sclk, output cgen_sen_b, output cgen_mosi, input cgen_miso, // Clock gen SPI + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls inout [15:0] io_tx, inout [15:0] io_rx @@ -44,6 +46,8 @@ module u1e .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .db_sda(db_sda), .db_scl(db_scl), .sclk(sclk), .sen({cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso), + .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), + .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel), .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), .io_tx(io_tx), .io_rx(io_rx) ); diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index c74d385ee..4f0227dfd 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -10,7 +10,8 @@ module u1e_core inout db_sda, inout db_scl, output sclk, output [7:0] sen, output mosi, input miso, - + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, inout [15:0] io_tx, inout [15:0] io_rx ); @@ -151,13 +152,15 @@ module u1e_core assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; // ///////////////////////////////////////////////////////////////////////////////////// - // Slave 0, LEDs and Switches + // Slave 0, Misc LEDs, Switches, controls reg [15:0] reg_fast, reg_slow; localparam REG_FAST = 7'd4; localparam REG_SWITCHES = 7'd6; localparam REG_GPIOS = 7'd8; - + localparam REG_CGEN_ST = 7'd9; + localparam REG_CGEN_CTRL = 7'd10; + reg [3:0] reg_gpios; always @(posedge wb_clk) @@ -168,8 +171,19 @@ module u1e_core if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_GPIOS)) reg_gpios <= s0_dat_mosi; + reg [1:0] reg_cgen_ctrls; + + always @(posedge wb_clk) + if(wb_rst) + reg_cgen_ctrls <= 2'b11; + else if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_CGEN_CTRL)) + reg_cgen_ctrls <= s0_dat_mosi; + + assign {cgen_sync_b, cgen_ref_sel} = reg_cgen_ctrls; + assign s0_dat_miso = (s0_adr[6:0] == REG_FAST) ? reg_fast : (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : + (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : 16'hBEEF; assign s0_ack = s0_stb & s0_cyc; -- cgit v1.2.3 From 29e88b3478aad89ff76363029395200a8601e667 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Fri, 26 Mar 2010 19:04:18 +0000 Subject: Working version. --- host/apps/omap_debug/usrp-e-uart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/host/apps/omap_debug/usrp-e-uart.c b/host/apps/omap_debug/usrp-e-uart.c index 92f89f45c..239df9444 100644 --- a/host/apps/omap_debug/usrp-e-uart.c +++ b/host/apps/omap_debug/usrp-e-uart.c @@ -9,7 +9,7 @@ // Usage: usrp_e_uart -#define UART_WRITE_ADDR ((1<<6) + 16) +#define UART_WRITE_ADDR (0x80 + 12) int main(int argc, char *argv[]) { -- cgit v1.2.3 From 806a2de4cdd9794f6fba915e32534fd2a0f31cb5 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 26 Mar 2010 14:04:22 -0700 Subject: remove timescale junk get rid of asynchronous resets fix spelling error corrected comment --- usrp2/opencores/spi/rtl/verilog/spi_clgen.v | 7 +++---- usrp2/opencores/spi/rtl/verilog/spi_defines.v | 2 +- usrp2/opencores/spi/rtl/verilog/spi_shift.v | 9 ++++----- usrp2/opencores/spi/rtl/verilog/spi_top.v | 20 +++++++++++--------- usrp2/opencores/spi/rtl/verilog/timescale.v | 2 -- 5 files changed, 19 insertions(+), 21 deletions(-) delete mode 100644 usrp2/opencores/spi/rtl/verilog/timescale.v diff --git a/usrp2/opencores/spi/rtl/verilog/spi_clgen.v b/usrp2/opencores/spi/rtl/verilog/spi_clgen.v index 3f29f6d7f..2d9c34f40 100644 --- a/usrp2/opencores/spi/rtl/verilog/spi_clgen.v +++ b/usrp2/opencores/spi/rtl/verilog/spi_clgen.v @@ -39,7 +39,6 @@ ////////////////////////////////////////////////////////////////////// `include "spi_defines.v" -`include "timescale.v" module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge); @@ -66,7 +65,7 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, assign cnt_one = cnt == {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1}; // Counter counts half period - always @(posedge clk_in or posedge rst) + always @(posedge clk_in) begin if(rst) cnt <= {`SPI_DIVIDER_LEN{1'b1}}; @@ -80,7 +79,7 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, end // clk_out is asserted every other half period - always @(posedge clk_in or posedge rst) + always @(posedge clk_in) begin if(rst) clk_out <= 1'b0; @@ -89,7 +88,7 @@ module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, end // Pos and neg edge signals - always @(posedge clk_in or posedge rst) + always @(posedge clk_in) begin if(rst) begin diff --git a/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/usrp2/opencores/spi/rtl/verilog/spi_defines.v index 01de2584d..963a680a8 100644 --- a/usrp2/opencores/spi/rtl/verilog/spi_defines.v +++ b/usrp2/opencores/spi/rtl/verilog/spi_defines.v @@ -137,7 +137,7 @@ `define SPI_TX_2 2 `define SPI_TX_3 3 `define SPI_CTRL 4 -`define SPI_DEVIDE 5 +`define SPI_DIVIDE 5 `define SPI_SS 6 // diff --git a/usrp2/opencores/spi/rtl/verilog/spi_shift.v b/usrp2/opencores/spi/rtl/verilog/spi_shift.v index c8c73706b..ac3bb3f48 100644 --- a/usrp2/opencores/spi/rtl/verilog/spi_shift.v +++ b/usrp2/opencores/spi/rtl/verilog/spi_shift.v @@ -39,7 +39,6 @@ ////////////////////////////////////////////////////////////////////// `include "spi_defines.v" -`include "timescale.v" module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, pos_edge, neg_edge, rx_negedge, tx_negedge, @@ -87,7 +86,7 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last; // Character bit counter - always @(posedge clk or posedge rst) + always @(posedge clk) begin if(rst) cnt <= {`SPI_CHAR_LEN_BITS+1{1'b0}}; @@ -101,7 +100,7 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, end // Transfer in progress - always @(posedge clk or posedge rst) + always @(posedge clk) begin if(rst) tip <= 1'b0; @@ -112,7 +111,7 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, end // Sending bits to the line - always @(posedge clk or posedge rst) + always @(posedge clk) begin if (rst) s_out <= 1'b0; @@ -121,7 +120,7 @@ module spi_shift (clk, rst, latch, byte_sel, len, lsb, go, end // Receiving bits from the line - always @(posedge clk or posedge rst) + always @(posedge clk) begin if (rst) data <= {`SPI_MAX_CHAR{1'b0}}; diff --git a/usrp2/opencores/spi/rtl/verilog/spi_top.v b/usrp2/opencores/spi/rtl/verilog/spi_top.v index 071aeefca..8289449a9 100644 --- a/usrp2/opencores/spi/rtl/verilog/spi_top.v +++ b/usrp2/opencores/spi/rtl/verilog/spi_top.v @@ -1,3 +1,6 @@ + +// Modified 2010 by Matt Ettus to remove old verilog style + ////////////////////////////////////////////////////////////////////// //// //// //// spi_top.v //// @@ -40,7 +43,6 @@ `include "spi_defines.v" -`include "timescale.v" module spi_top ( @@ -99,7 +101,7 @@ module spi_top wire last_bit; // marks last character bit // Address decoder - assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DEVIDE); + assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DIVIDE); assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL); assign spi_tx_sel[0] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0); assign spi_tx_sel[1] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_1); @@ -130,14 +132,14 @@ module spi_top `endif `endif `SPI_CTRL: wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl}; - `SPI_DEVIDE: wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider}; + `SPI_DIVIDE: wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider}; `SPI_SS: wb_dat = {{32-`SPI_SS_NB{1'b0}}, ss}; default: wb_dat = 32'bx; endcase end // Wb data out - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) wb_dat_o <= 32'b0; @@ -146,7 +148,7 @@ module spi_top end // Wb acknowledge - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) wb_ack_o <= 1'b0; @@ -158,7 +160,7 @@ module spi_top assign wb_err_o = 1'b0; // Interrupt - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) wb_int_o <= 1'b0; @@ -169,7 +171,7 @@ module spi_top end // Divider register - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) divider <= {`SPI_DIVIDER_LEN{1'b0}}; @@ -207,7 +209,7 @@ module spi_top end // Ctrl register - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) ctrl <= {`SPI_CTRL_BIT_NB{1'b0}}; @@ -231,7 +233,7 @@ module spi_top assign ass = ctrl[`SPI_CTRL_ASS]; // Slave select register - always @(posedge wb_clk_i or posedge wb_rst_i) + always @(posedge wb_clk_i) begin if (wb_rst_i) ss <= {`SPI_SS_NB{1'b0}}; diff --git a/usrp2/opencores/spi/rtl/verilog/timescale.v b/usrp2/opencores/spi/rtl/verilog/timescale.v deleted file mode 100644 index 60d4ecbd1..000000000 --- a/usrp2/opencores/spi/rtl/verilog/timescale.v +++ /dev/null @@ -1,2 +0,0 @@ -`timescale 1ns / 10ps - -- cgit v1.2.3 From b9e715983eaa625f65f1ac4d18c7fbc9e5ace4cd Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 26 Mar 2010 17:12:07 -0700 Subject: connect up the 16 bit spi core --- usrp2/top/u1e/Makefile | 3 +-- usrp2/top/u1e/u1e_core.v | 6 +++--- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 3412e227d..2b78b21bd 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -137,8 +137,7 @@ opencores/simple_pic/rtl/simple_pic.v \ opencores/spi/rtl/verilog/spi_clgen.v \ opencores/spi/rtl/verilog/spi_defines.v \ opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ +opencores/spi/rtl/verilog/spi_top16.v \ sdr_lib/acc.v \ sdr_lib/add2.v \ sdr_lib/add2_and_round.v \ diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 4f0227dfd..f2415d7e1 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -203,9 +203,9 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////////////////// // Slave 2, SPI - spi_top shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), - .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + spi_top16 shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_mosi), + .wb_dat_o(s2_dat_miso),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) ); -- cgit v1.2.3 From cce4104964c1e1930f85dbb0bb8b8f33086bd75e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sat, 27 Mar 2010 09:20:50 -0700 Subject: 16 bit wide spi core --- usrp2/opencores/spi/rtl/verilog/spi_top16.v | 182 ++++++++++++++++++++++++++++ 1 file changed, 182 insertions(+) create mode 100644 usrp2/opencores/spi/rtl/verilog/spi_top16.v diff --git a/usrp2/opencores/spi/rtl/verilog/spi_top16.v b/usrp2/opencores/spi/rtl/verilog/spi_top16.v new file mode 100644 index 000000000..ee808a8ab --- /dev/null +++ b/usrp2/opencores/spi/rtl/verilog/spi_top16.v @@ -0,0 +1,182 @@ + +// Modified 2010 by Matt Ettus to remove old verilog style and +// allow 16-bit operation + +////////////////////////////////////////////////////////////////////// +//// //// +//// spi_top.v //// +//// //// +//// This file is part of the SPI IP core project //// +//// http://www.opencores.org/projects/spi/ //// +//// //// +//// Author(s): //// +//// - Simon Srot (simons@opencores.org) //// +//// //// +//// All additional information is avaliable in the Readme.txt //// +//// file. //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2002 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + + +`include "spi_defines.v" + +module spi_top16 + (input wb_clk_i, input wb_rst_i, + input [4:0] wb_adr_i, + input [15:0] wb_dat_i, + output reg [15:0] wb_dat_o, + input [1:0] wb_sel_i, + input wb_we_i, input wb_stb_i, input wb_cyc_i, + output reg wb_ack_o, output wb_err_o, output reg wb_int_o, + + // SPI signals + output [15:0] ss_pad_o, output sclk_pad_o, output mosi_pad_o, input miso_pad_i); + + // Internal signals + reg [15:0] divider; // Divider register + reg [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register + reg [15:0] ss; // Slave select register + reg [31:0] wb_dat; // wb data out + wire [31:0] rx; // Rx register + wire rx_negedge; // miso is sampled on negative edge + wire tx_negedge; // mosi is driven on negative edge + wire [`SPI_CHAR_LEN_BITS-1:0] char_len; // char len + wire go; // go + wire lsb; // lsb first on line + wire ie; // interrupt enable + wire ass; // automatic slave select + wire spi_divider_sel; // divider register select + wire spi_ctrl_sel; // ctrl register select + wire [3:0] spi_tx_sel; // tx_l register select + wire spi_ss_sel; // ss register select + wire tip; // transfer in progress + wire pos_edge; // recognize posedge of sclk + wire neg_edge; // recognize negedge of sclk + wire last_bit; // marks last character bit + + // Address decoder + assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_DIVIDE); + assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_CTRL); + assign spi_tx_sel[0] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_0); + assign spi_tx_sel[1] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_1); + assign spi_tx_sel[2] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_2); + assign spi_tx_sel[3] = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_TX_3); + assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[4:2] == `SPI_SS); + + always @(wb_adr_i or rx or ctrl or divider or ss) + case (wb_adr_i[4:2]) + `SPI_RX_0: wb_dat = rx[31:0]; + `SPI_CTRL: wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl}; + `SPI_DIVIDE: wb_dat = {16'b0, divider}; + `SPI_SS: wb_dat = {16'b0, ss}; + default : wb_dat = 32'd0; + endcase // case (wb_adr_i[4:2]) + + always @(posedge wb_clk_i) + if (wb_rst_i) + wb_dat_o <= 32'b0; + else + wb_dat_o <= wb_adr_i[1] ? wb_dat[31:16] : wb_dat[15:0]; + + always @(posedge wb_clk_i) + if (wb_rst_i) + wb_ack_o <= 1'b0; + else + wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o; + + assign wb_err_o = 1'b0; + + // Interrupt + always @(posedge wb_clk_i) + if (wb_rst_i) + wb_int_o <= 1'b0; + else if (ie && tip && last_bit && pos_edge) + wb_int_o <= 1'b1; + else if (wb_ack_o) + wb_int_o <= 1'b0; + + // Divider register + always @(posedge wb_clk_i) + if (wb_rst_i) + divider <= 16'b0; + else if (spi_divider_sel && wb_we_i && !tip && ~wb_adr_i[1]) + divider <= wb_dat_i; + + // Ctrl register + always @(posedge wb_clk_i) + if (wb_rst_i) + ctrl <= {`SPI_CTRL_BIT_NB{1'b0}}; + else if(spi_ctrl_sel && wb_we_i && !tip && ~wb_adr_i[1]) + begin + if (wb_sel_i[0]) + ctrl[7:0] <= wb_dat_i[7:0] | {7'b0, ctrl[0]}; + if (wb_sel_i[1]) + ctrl[`SPI_CTRL_BIT_NB-1:8] <= wb_dat_i[`SPI_CTRL_BIT_NB-1:8]; + end + else if(tip && last_bit && pos_edge) + ctrl[`SPI_CTRL_GO] <= 1'b0; + + assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE]; + assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE]; + assign go = ctrl[`SPI_CTRL_GO]; + assign char_len = ctrl[`SPI_CTRL_CHAR_LEN]; + assign lsb = ctrl[`SPI_CTRL_LSB]; + assign ie = ctrl[`SPI_CTRL_IE]; + assign ass = ctrl[`SPI_CTRL_ASS]; + + // Slave select register + always @(posedge wb_clk_i) + if (wb_rst_i) + ss <= 16'b0; + else if(spi_ss_sel && wb_we_i && !tip & ~wb_adr_i[1]) + begin + if (wb_sel_i[0]) + ss[7:0] <= wb_dat_i[7:0]; + if (wb_sel_i[1]) + ss[15:8] <= wb_dat_i[15:8]; + end + + assign ss_pad_o = ~((ss & {16{tip & ass}}) | (ss & {16{!ass}})); + + spi_clgen clgen (.clk_in(wb_clk_i), .rst(wb_rst_i), .go(go), .enable(tip), .last_clk(last_bit), + .divider(divider[`SPI_DIVIDER_LEN-1:0]), .clk_out(sclk_pad_o), .pos_edge(pos_edge), + .neg_edge(neg_edge)); + + wire [3:0] new_sels = { (wb_adr_i[1] & wb_sel_i[1]), (wb_adr_i[1] & wb_sel_i[0]), + (~wb_adr_i[1] & wb_sel_i[1]), (~wb_adr_i[1] & wb_sel_i[0]) }; + + + spi_shift shift (.clk(wb_clk_i), .rst(wb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]), + .latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(new_sels), .lsb(lsb), + .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge), + .rx_negedge(rx_negedge), .tx_negedge(tx_negedge), + .tip(tip), .last(last_bit), + .p_in({wb_dat_i,wb_dat_i}), .p_out(rx), + .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o)); + +endmodule // spi_top16 -- cgit v1.2.3 From 930755fce1e5d22a5ede0459dccd6c9501fc642c Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Mon, 29 Mar 2010 13:30:17 +0000 Subject: Minor fixes. --- host/apps/omap_debug/usrp-e-i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-i2c.c b/host/apps/omap_debug/usrp-e-i2c.c index 417d6d580..19d64731b 100644 --- a/host/apps/omap_debug/usrp-e-i2c.c +++ b/host/apps/omap_debug/usrp-e-i2c.c @@ -36,7 +36,7 @@ int main(int argc, char *argv[]) printf("fp = %d\n", fp); if (direction) { - count = argc - 2; + count = argc - 3; } else { count = atoi(argv[3]); } @@ -64,7 +64,7 @@ int main(int argc, char *argv[]) for (i=0; idata[i]); } - printf("/n"); + printf("\n"); } return 0; -- cgit v1.2.3 From c81a975766a8831cab1e3123af94b4fe4a09d9bc Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 30 Mar 2010 14:12:11 +0000 Subject: compiling with master merge, renamed usrp1e to usrp_e --- host/apps/usrp1e_load_fpga.cpp | 47 ------ host/include/uhd/usrp/CMakeLists.txt | 2 +- host/include/uhd/usrp/usrp1e.hpp | 54 ------ host/include/uhd/usrp/usrp_e.hpp | 54 ++++++ host/lib/CMakeLists.txt | 20 ++- host/lib/usrp/usrp1e/dboard_impl.cpp | 76 --------- host/lib/usrp/usrp1e/dboard_interface.cpp | 189 --------------------- host/lib/usrp/usrp1e/dsp_impl.cpp | 70 -------- host/lib/usrp/usrp1e/fpga-downloader.cc | 262 ------------------------------ host/lib/usrp/usrp1e/mboard_impl.cpp | 46 ------ host/lib/usrp/usrp1e/usrp1e_impl.cpp | 178 -------------------- host/lib/usrp/usrp1e/usrp1e_impl.hpp | 135 --------------- host/lib/usrp/usrp1e/usrp1e_none.cpp | 38 ----- host/lib/usrp/usrp2/usrp2_impl.cpp | 2 +- host/lib/usrp/usrp_e/dboard_impl.cpp | 76 +++++++++ host/lib/usrp/usrp_e/dboard_interface.cpp | 189 +++++++++++++++++++++ host/lib/usrp/usrp_e/dsp_impl.cpp | 69 ++++++++ host/lib/usrp/usrp_e/fpga-downloader.cc | 262 ++++++++++++++++++++++++++++++ host/lib/usrp/usrp_e/mboard_impl.cpp | 45 +++++ host/lib/usrp/usrp_e/usrp_e_impl.cpp | 179 ++++++++++++++++++++ host/lib/usrp/usrp_e/usrp_e_impl.hpp | 135 +++++++++++++++ host/lib/usrp/usrp_e/usrp_e_none.cpp | 38 +++++ host/utils/CMakeLists.txt | 5 +- host/utils/usrp_e_load_fpga.cpp | 47 ++++++ 24 files changed, 1110 insertions(+), 1108 deletions(-) delete mode 100644 host/apps/usrp1e_load_fpga.cpp delete mode 100644 host/include/uhd/usrp/usrp1e.hpp create mode 100644 host/include/uhd/usrp/usrp_e.hpp delete mode 100644 host/lib/usrp/usrp1e/dboard_impl.cpp delete mode 100644 host/lib/usrp/usrp1e/dboard_interface.cpp delete mode 100644 host/lib/usrp/usrp1e/dsp_impl.cpp delete mode 100644 host/lib/usrp/usrp1e/fpga-downloader.cc delete mode 100644 host/lib/usrp/usrp1e/mboard_impl.cpp delete mode 100644 host/lib/usrp/usrp1e/usrp1e_impl.cpp delete mode 100644 host/lib/usrp/usrp1e/usrp1e_impl.hpp delete mode 100644 host/lib/usrp/usrp1e/usrp1e_none.cpp create mode 100644 host/lib/usrp/usrp_e/dboard_impl.cpp create mode 100644 host/lib/usrp/usrp_e/dboard_interface.cpp create mode 100644 host/lib/usrp/usrp_e/dsp_impl.cpp create mode 100644 host/lib/usrp/usrp_e/fpga-downloader.cc create mode 100644 host/lib/usrp/usrp_e/mboard_impl.cpp create mode 100644 host/lib/usrp/usrp_e/usrp_e_impl.cpp create mode 100644 host/lib/usrp/usrp_e/usrp_e_impl.hpp create mode 100644 host/lib/usrp/usrp_e/usrp_e_none.cpp create mode 100644 host/utils/usrp_e_load_fpga.cpp diff --git a/host/apps/usrp1e_load_fpga.cpp b/host/apps/usrp1e_load_fpga.cpp deleted file mode 100644 index d5960b391..000000000 --- a/host/apps/usrp1e_load_fpga.cpp +++ /dev/null @@ -1,47 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include -#include -#include -#include - -namespace po = boost::program_options; - -int main(int argc, char *argv[]){ - po::options_description desc("Allowed options"); - desc.add_options() - ("help", "help message") - ("file", po::value(), "path to fpga bin file") - ; - - po::variables_map vm; - po::store(po::parse_command_line(argc, argv, desc), vm); - po::notify(vm); - - //print the help message - if (vm.count("help") or vm.count("file") == 0){ - std::cout << boost::format("USRP1E Load FPGA %s") % desc << std::endl; - return ~0; - } - - //load the fpga - std::string file = vm["file"].as(); - uhd::usrp::usrp1e::load_fpga(file); - - return 0; -} diff --git a/host/include/uhd/usrp/CMakeLists.txt b/host/include/uhd/usrp/CMakeLists.txt index bab01fdeb..b9be370bd 100644 --- a/host/include/uhd/usrp/CMakeLists.txt +++ b/host/include/uhd/usrp/CMakeLists.txt @@ -21,7 +21,7 @@ INSTALL(FILES dboard_id.hpp dboard_interface.hpp dboard_manager.hpp - usrp1e.hpp + usrp_e.hpp usrp2.hpp DESTINATION ${INCLUDE_DIR}/uhd/usrp ) diff --git a/host/include/uhd/usrp/usrp1e.hpp b/host/include/uhd/usrp/usrp1e.hpp deleted file mode 100644 index 75da58453..000000000 --- a/host/include/uhd/usrp/usrp1e.hpp +++ /dev/null @@ -1,54 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#ifndef INCLUDED_UHD_USRP_USRP1E_HPP -#define INCLUDED_UHD_USRP_USRP1E_HPP - -#include -#include - -namespace uhd{ namespace usrp{ - -/*! - * The usrp1e device class. - */ -class UHD_API usrp1e : public device{ -public: - /*! - * Find usrp1e devices on the system via the device node. - * \param hint a device addr with the usrp1e address filled in - * \return a vector of device addresses for all usrp1es found - */ - static device_addrs_t find(const device_addr_t &hint); - - /*! - * Make a usrp1e from a device address. - * \param addr the device address - * \return a device sptr to a new usrp1e - */ - static device::sptr make(const device_addr_t &addr); - - /*! - * Load the FPGA with an image file. - * \param bin_file the name of the fpga image file - */ - static void load_fpga(const std::string &bin_file); -}; - -}} //namespace - -#endif /* INCLUDED_UHD_USRP_USRP1E_HPP */ diff --git a/host/include/uhd/usrp/usrp_e.hpp b/host/include/uhd/usrp/usrp_e.hpp new file mode 100644 index 000000000..557058261 --- /dev/null +++ b/host/include/uhd/usrp/usrp_e.hpp @@ -0,0 +1,54 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_UHD_USRP_USRP_E_HPP +#define INCLUDED_UHD_USRP_USRP_E_HPP + +#include +#include + +namespace uhd{ namespace usrp{ + +/*! + * The USRP-Embedded device class. + */ +class UHD_API usrp_e : public device{ +public: + /*! + * Find usrp_e devices on the system via the device node. + * \param hint a device addr with the usrp_e address filled in + * \return a vector of device addresses for all usrp-e's found + */ + static device_addrs_t find(const device_addr_t &hint); + + /*! + * Make a usrp_e from a device address. + * \param addr the device address + * \return a device sptr to a new usrp_e + */ + static device::sptr make(const device_addr_t &addr); + + /*! + * Load the FPGA with an image file. + * \param bin_file the name of the fpga image file + */ + static void load_fpga(const std::string &bin_file); +}; + +}} //namespace + +#endif /* INCLUDED_UHD_USRP_USRP_E_HPP */ diff --git a/host/lib/CMakeLists.txt b/host/lib/CMakeLists.txt index 323b69b14..db5e9d273 100644 --- a/host/lib/CMakeLists.txt +++ b/host/lib/CMakeLists.txt @@ -51,6 +51,8 @@ LIST(APPEND libuhd_sources ######################################################################## # Conditionally add the usrp1e sources ######################################################################## +MESSAGE(STATUS "Configuring usrp-e support...") + INCLUDE(CheckIncludeFiles) SET(usrp1e_required_headers linux/ioctl.h @@ -63,19 +65,19 @@ CHECK_INCLUDE_FILES( ) IF(HAS_USRP1E_REQUIRED_HEADERS) - MESSAGE(STATUS "Building usrp1e support...") + MESSAGE(STATUS " Building usrp1e support.") LIST(APPEND libuhd_sources - usrp/usrp1e/dboard_impl.cpp - usrp/usrp1e/dboard_interface.cpp - usrp/usrp1e/dsp_impl.cpp - usrp/usrp1e/fpga-downloader.cc - usrp/usrp1e/mboard_impl.cpp - usrp/usrp1e/usrp1e_impl.cpp + usrp/usrp_e/dboard_impl.cpp + usrp/usrp_e/dboard_interface.cpp + usrp/usrp_e/dsp_impl.cpp + usrp/usrp_e/fpga-downloader.cc + usrp/usrp_e/mboard_impl.cpp + usrp/usrp_e/usrp_e_impl.cpp ) ELSE(HAS_USRP1E_REQUIRED_HEADERS) - MESSAGE(STATUS "Skipping usrp1e support...") + MESSAGE(STATUS " Skipping usrp1e support.") LIST(APPEND libuhd_sources - usrp/usrp1e/usrp1e_none.cpp + usrp/usrp_e/usrp_e_none.cpp ) ENDIF(HAS_USRP1E_REQUIRED_HEADERS) diff --git a/host/lib/usrp/usrp1e/dboard_impl.cpp b/host/lib/usrp/usrp1e/dboard_impl.cpp deleted file mode 100644 index a2798dce3..000000000 --- a/host/lib/usrp/usrp1e/dboard_impl.cpp +++ /dev/null @@ -1,76 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include -#include -#include "usrp1e_impl.hpp" - -using namespace uhd::usrp; - -/*********************************************************************** - * Dboard Initialization - **********************************************************************/ -void usrp1e_impl::dboard_init(void){ - dboard_id_t rx_dboard_id = dboard_id::NONE; //TODO get these from the eeprom - dboard_id_t tx_dboard_id = dboard_id::NONE; - - //create a new dboard interface and manager - dboard_interface::sptr dboard_interface( - make_usrp1e_dboard_interface(this) - ); - _dboard_manager = dboard_manager::make( - rx_dboard_id, tx_dboard_id, dboard_interface - ); - - //setup the dboard proxies - _rx_dboard_proxy = wax_obj_proxy::make( - boost::bind(&usrp1e_impl::rx_dboard_get, this, _1, _2), - boost::bind(&usrp1e_impl::rx_dboard_set, this, _1, _2) - ); - _tx_dboard_proxy = wax_obj_proxy::make( - boost::bind(&usrp1e_impl::tx_dboard_get, this, _1, _2), - boost::bind(&usrp1e_impl::tx_dboard_set, this, _1, _2) - ); -} - -/*********************************************************************** - * RX Dboard Get - **********************************************************************/ -void usrp1e_impl::rx_dboard_get(const wax::obj &, wax::obj &){ - -} - -/*********************************************************************** - * RX Dboard Set - **********************************************************************/ -void usrp1e_impl::rx_dboard_set(const wax::obj &, const wax::obj &){ - -} - -/*********************************************************************** - * TX Dboard Get - **********************************************************************/ -void usrp1e_impl::tx_dboard_get(const wax::obj &, wax::obj &){ - -} - -/*********************************************************************** - * TX Dboard Set - **********************************************************************/ -void usrp1e_impl::tx_dboard_set(const wax::obj &, const wax::obj &){ - -} diff --git a/host/lib/usrp/usrp1e/dboard_interface.cpp b/host/lib/usrp/usrp1e/dboard_interface.cpp deleted file mode 100644 index ef91014ac..000000000 --- a/host/lib/usrp/usrp1e/dboard_interface.cpp +++ /dev/null @@ -1,189 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include -#include //std::copy -#include "usrp1e_impl.hpp" -#include - -using namespace uhd::usrp; - -class usrp1e_dboard_interface : public dboard_interface{ -public: - usrp1e_dboard_interface(usrp1e_impl *impl); - ~usrp1e_dboard_interface(void); - - void write_aux_dac(unit_type_t, int, int); - int read_aux_adc(unit_type_t, int); - - void set_atr_reg(gpio_bank_t, boost::uint16_t, boost::uint16_t, boost::uint16_t); - void set_gpio_ddr(gpio_bank_t, boost::uint16_t, boost::uint16_t); - void write_gpio(gpio_bank_t, boost::uint16_t, boost::uint16_t); - boost::uint16_t read_gpio(gpio_bank_t); - - void write_i2c(int, const byte_vector_t &); - byte_vector_t read_i2c(int, size_t); - - double get_rx_clock_rate(void); - double get_tx_clock_rate(void); - -private: - byte_vector_t transact_spi( - spi_dev_t dev, - spi_latch_t latch, - spi_push_t push, - const byte_vector_t &buf, - bool readback - ); - - usrp1e_impl *_impl; -}; - -/*********************************************************************** - * Make Function - **********************************************************************/ -dboard_interface::sptr make_usrp1e_dboard_interface(usrp1e_impl *impl){ - return dboard_interface::sptr(new usrp1e_dboard_interface(impl)); -} - -/*********************************************************************** - * Structors - **********************************************************************/ -usrp1e_dboard_interface::usrp1e_dboard_interface(usrp1e_impl *impl){ - _impl = impl; -} - -usrp1e_dboard_interface::~usrp1e_dboard_interface(void){ - /* NOP */ -} - -/*********************************************************************** - * Clock Rates - **********************************************************************/ -double usrp1e_dboard_interface::get_rx_clock_rate(void){ - throw std::runtime_error("not implemented"); -} - -double usrp1e_dboard_interface::get_tx_clock_rate(void){ - throw std::runtime_error("not implemented"); -} - -/*********************************************************************** - * GPIO - **********************************************************************/ -void usrp1e_dboard_interface::set_gpio_ddr(gpio_bank_t bank, boost::uint16_t value, boost::uint16_t mask){ - throw std::runtime_error("not implemented"); -} - -void usrp1e_dboard_interface::write_gpio(gpio_bank_t bank, boost::uint16_t value, boost::uint16_t mask){ - throw std::runtime_error("not implemented"); -} - -boost::uint16_t usrp1e_dboard_interface::read_gpio(gpio_bank_t bank){ - throw std::runtime_error("not implemented"); -} - -void usrp1e_dboard_interface::set_atr_reg(gpio_bank_t bank, boost::uint16_t tx_value, boost::uint16_t rx_value, boost::uint16_t mask){ - throw std::runtime_error("not implemented"); -} - -/*********************************************************************** - * SPI - **********************************************************************/ -dboard_interface::byte_vector_t usrp1e_dboard_interface::transact_spi( - spi_dev_t dev, - spi_latch_t latch, - spi_push_t push, - const byte_vector_t &buf, - bool readback -){ - //load data struct - usrp_e_spi data; - data.readback = (readback)? UE_SPI_TXRX : UE_SPI_TXONLY; - data.slave = (dev == SPI_RX_DEV)? UE_SPI_CTRL_RXNEG : UE_SPI_CTRL_TXNEG; - data.length = buf.size() * 8; //bytes to bits - boost::uint8_t *data_bytes = reinterpret_cast(&data.data); - - //load the data - ASSERT_THROW(buf.size() <= sizeof(data.data)); - std::copy(buf.begin(), buf.end(), data_bytes); - - //load the flags - data.flags = 0; - data.flags |= (latch == SPI_LATCH_RISE)? UE_SPI_LATCH_RISE : UE_SPI_LATCH_FALL; - data.flags |= (push == SPI_PUSH_RISE)? UE_SPI_PUSH_RISE : UE_SPI_PUSH_FALL; - - //call the spi ioctl - _impl->ioctl(USRP_E_SPI, &data); - - //unload the data - byte_vector_t ret(data.length/8); //bits to bytes - ASSERT_THROW(ret.size() <= sizeof(data.data)); - std::copy(data_bytes, data_bytes+ret.size(), ret.begin()); - return ret; -} - -/*********************************************************************** - * I2C - **********************************************************************/ -static const size_t max_i2c_data_bytes = 10; - -void usrp1e_dboard_interface::write_i2c(int i2c_addr, const byte_vector_t &buf){ - //allocate some memory for this transaction - ASSERT_THROW(buf.size() <= max_i2c_data_bytes); - boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; - - //load the data struct - usrp_e_i2c &data = reinterpret_cast(mem); - data.addr = i2c_addr; - data.len = buf.size(); - std::copy(buf.begin(), buf.end(), data.data); - - //call the spi ioctl - _impl->ioctl(USRP_E_I2C_WRITE, &data); -} - -dboard_interface::byte_vector_t usrp1e_dboard_interface::read_i2c(int i2c_addr, size_t num_bytes){ - //allocate some memory for this transaction - ASSERT_THROW(num_bytes <= max_i2c_data_bytes); - boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; - - //load the data struct - usrp_e_i2c &data = reinterpret_cast(mem); - data.addr = i2c_addr; - data.len = num_bytes; - - //call the spi ioctl - _impl->ioctl(USRP_E_I2C_READ, &data); - - //unload the data - byte_vector_t ret(data.len); - ASSERT_THROW(ret.size() == num_bytes); - std::copy(data.data, data.data+ret.size(), ret.begin()); - return ret; -} - -/*********************************************************************** - * Aux DAX/ADC - **********************************************************************/ -void usrp1e_dboard_interface::write_aux_dac(dboard_interface::unit_type_t unit, int which, int value){ - throw std::runtime_error("not implemented"); -} - -int usrp1e_dboard_interface::read_aux_adc(dboard_interface::unit_type_t unit, int which){ - throw std::runtime_error("not implemented"); -} diff --git a/host/lib/usrp/usrp1e/dsp_impl.cpp b/host/lib/usrp/usrp1e/dsp_impl.cpp deleted file mode 100644 index 862b89184..000000000 --- a/host/lib/usrp/usrp1e/dsp_impl.cpp +++ /dev/null @@ -1,70 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include -#include -#include "usrp1e_impl.hpp" - -using namespace uhd::usrp; - -/*********************************************************************** - * RX DDC Initialization - **********************************************************************/ -void usrp1e_impl::rx_ddc_init(void){ - _rx_ddc_proxy = wax_obj_proxy::make( - boost::bind(&usrp1e_impl::rx_ddc_get, this, _1, _2), - boost::bind(&usrp1e_impl::rx_ddc_set, this, _1, _2) - ); -} - -/*********************************************************************** - * RX DDC Get - **********************************************************************/ -void usrp1e_impl::rx_ddc_get(const wax::obj &, wax::obj &){ - -} - -/*********************************************************************** - * RX DDC Set - **********************************************************************/ -void usrp1e_impl::rx_ddc_set(const wax::obj &, const wax::obj &){ - -} - -/*********************************************************************** - * TX DUC Initialization - **********************************************************************/ -void usrp1e_impl::tx_duc_init(void){ - _tx_duc_proxy = wax_obj_proxy::make( - boost::bind(&usrp1e_impl::tx_duc_get, this, _1, _2), - boost::bind(&usrp1e_impl::tx_duc_set, this, _1, _2) - ); -} - -/*********************************************************************** - * TX DUC Get - **********************************************************************/ -void usrp1e_impl::tx_duc_get(const wax::obj &, wax::obj &){ - -} - -/*********************************************************************** - * TX DUC Set - **********************************************************************/ -void usrp1e_impl::tx_duc_set(const wax::obj &, const wax::obj &){ - -} diff --git a/host/lib/usrp/usrp1e/fpga-downloader.cc b/host/lib/usrp/usrp1e/fpga-downloader.cc deleted file mode 100644 index f7c78b875..000000000 --- a/host/lib/usrp/usrp1e/fpga-downloader.cc +++ /dev/null @@ -1,262 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -/* - * Configuration connections - * - * CCK - MCSPI1_CLK - * DIN - MCSPI1_MOSI - * PROG_B - GPIO_175 - output (change mux) - * DONE - GPIO_173 - input (change mux) - * INIT_B - GPIO_114 - input (change mux) - * -*/ - -const unsigned int PROG_B = 175; -const unsigned int DONE = 173; -const unsigned int INIT_B = 114; - -//static std::string bit_file = "safe_u1e.bin"; - -const int BUF_SIZE = 4096; - -enum gpio_direction {IN, OUT}; - -class gpio { - public: - - gpio(unsigned int gpio_num, gpio_direction pin_direction); - - bool get_value(); - void set_value(bool state); - - private: - - std::stringstream base_path; - std::fstream value_file; -}; - -class spidev { - public: - - spidev(std::string dev_name); - ~spidev(); - - void send(char *wbuf, char *rbuf, unsigned int nbytes); - - private: - - int fd; - -}; - -gpio::gpio(unsigned int gpio_num, gpio_direction pin_direction) -{ - std::fstream export_file; - - export_file.open("/sys/class/gpio/export", std::ios::out); - if (!export_file.is_open()) ///\todo Poor error handling - std::cout << "Failed to open gpio export file." << std::endl; - - export_file << gpio_num << std::endl; - - base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush; - - std::fstream direction_file; - std::string direction_file_name; - - direction_file_name = base_path.str() + "/direction"; - - direction_file.open(direction_file_name.c_str()); - if (!direction_file.is_open()) - std::cout << "Failed to open direction file." << std::endl; - if (pin_direction == OUT) - direction_file << "out" << std::endl; - else - direction_file << "in" << std::endl; - - std::string value_file_name; - - value_file_name = base_path.str() + "/value"; - - value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out); - if (!value_file.is_open()) - std::cout << "Failed to open value file." << std::endl; -} - -bool gpio::get_value() -{ - - std::string val; - - std::getline(value_file, val); - value_file.seekg(0); - - if (val == "0") - return false; - else if (val == "1") - return true; - else - std::cout << "Data read from value file|" << val << "|" << std::endl; - - return false; -} - -void gpio::set_value(bool state) -{ - - if (state) - value_file << "1" << std::endl; - else - value_file << "0" << std::endl; -} - -static void prepare_fpga_for_configuration(gpio &prog, gpio &)//init) -{ - - prog.set_value(true); - prog.set_value(false); - prog.set_value(true); - -#if 0 - bool ready_to_program(false); - unsigned int count(0); - do { - ready_to_program = init.get_value(); - count++; - - sleep(1); - } while (count < 10 && !ready_to_program); - - if (count == 10) { - std::cout << "FPGA not ready for programming." << std::endl; - exit(-1); - } -#endif -} - -spidev::spidev(std::string fname) -{ - int ret; - int mode = 0; - int speed = 12000000; - int bits = 8; - - fd = open(fname.c_str(), O_RDWR); - - ret = ioctl(fd, SPI_IOC_WR_MODE, &mode); - ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed); - ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits); -} - - -spidev::~spidev() -{ - close(fd); -} - -void spidev::send(char *buf, char *rbuf, unsigned int nbytes) -{ - int ret; - - struct spi_ioc_transfer tr; - tr.tx_buf = (unsigned long) buf; - tr.rx_buf = (unsigned long) rbuf; - tr.len = nbytes; - tr.delay_usecs = 0; - tr.speed_hz = 48000000; - tr.bits_per_word = 8; - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - -} - -static void send_file_to_fpga(const std::string &file_name, gpio &error, gpio &done) -{ - std::ifstream bitstream; - - std::cout << "File name - " << file_name.c_str() << std::endl; - - bitstream.open(file_name.c_str(), std::ios::binary); - if (!bitstream.is_open()) - std::cout << "File " << file_name << " not opened succesfully." << std::endl; - - spidev spi("/dev/spidev1.0"); - char buf[BUF_SIZE]; - char rbuf[BUF_SIZE]; - - do { - bitstream.read(buf, BUF_SIZE); - spi.send(buf, rbuf, bitstream.gcount()); - - if (error.get_value()) - std::cout << "INIT_B went high, error occured." << std::endl; - - if (!done.get_value()) - std::cout << "Configuration complete." << std::endl; - - } while (bitstream.gcount() == BUF_SIZE); -} - -/* -int main(int argc, char *argv[]) -{ - - gpio gpio_prog_b(PROG_B, OUT); - gpio gpio_init_b(INIT_B, IN); - gpio gpio_done (DONE, IN); - - if (argc == 2) - bit_file = argv[1]; - - std::cout << "FPGA config file: " << bit_file << std::endl; - - prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b); - - std::cout << "Done = " << gpio_done.get_value() << std::endl; - - send_file_to_fpga(bit_file, gpio_init_b, gpio_done); -} -*/ - -#include -void uhd::usrp::usrp1e::load_fpga(const std::string &bin_file){ - gpio gpio_prog_b(PROG_B, OUT); - gpio gpio_init_b(INIT_B, IN); - gpio gpio_done (DONE, IN); - - std::cout << "FPGA config file: " << bin_file << std::endl; - - prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b); - - std::cout << "Done = " << gpio_done.get_value() << std::endl; - - send_file_to_fpga(bin_file, gpio_init_b, gpio_done); -} diff --git a/host/lib/usrp/usrp1e/mboard_impl.cpp b/host/lib/usrp/usrp1e/mboard_impl.cpp deleted file mode 100644 index b480f7616..000000000 --- a/host/lib/usrp/usrp1e/mboard_impl.cpp +++ /dev/null @@ -1,46 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include -#include -#include "usrp1e_impl.hpp" - -using namespace uhd::usrp; - -/*********************************************************************** - * Mboard Initialization - **********************************************************************/ -void usrp1e_impl::mboard_init(void){ - _mboard_proxy = wax_obj_proxy::make( - boost::bind(&usrp1e_impl::mboard_get, this, _1, _2), - boost::bind(&usrp1e_impl::mboard_set, this, _1, _2) - ); -} - -/*********************************************************************** - * Mboard Get - **********************************************************************/ -void usrp1e_impl::mboard_get(const wax::obj &, wax::obj &){ - -} - -/*********************************************************************** - * Mboard Set - **********************************************************************/ -void usrp1e_impl::mboard_set(const wax::obj &, const wax::obj &){ - -} diff --git a/host/lib/usrp/usrp1e/usrp1e_impl.cpp b/host/lib/usrp/usrp1e/usrp1e_impl.cpp deleted file mode 100644 index 8230cc8e4..000000000 --- a/host/lib/usrp/usrp1e/usrp1e_impl.cpp +++ /dev/null @@ -1,178 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include -#include -#include -#include "usrp1e_impl.hpp" -#include //open -#include //ioctl - -using namespace uhd; -using namespace uhd::usrp; -namespace fs = boost::filesystem; - -STATIC_BLOCK(register_usrp1e_device){ - device::register_device(&usrp1e::discover, &usrp1e::make); -} - -/*********************************************************************** - * Helper Functions - **********************************************************************/ -static std::string abs_path(const std::string &file_path){ - return fs::system_complete(fs::path(file_path)).file_string(); -} - -/*********************************************************************** - * Discovery - **********************************************************************/ -device_addrs_t usrp1e::discover(const device_addr_t &device_addr){ - device_addrs_t usrp1e_addrs; - - //if a node was provided, use it and only it - if (device_addr.has_key("node")){ - if (not fs::exists(device_addr["node"])) return usrp1e_addrs; - device_addr_t new_addr; - new_addr["name"] = "USRP1E"; - new_addr["node"] = abs_path(device_addr["node"]); - usrp1e_addrs.push_back(new_addr); - } - - //otherwise look for a few nodes at small indexes - else{ - for(size_t i = 0; i < 5; i++){ - std::string node = str(boost::format("/dev/usrp1_e%d") % i); - if (not fs::exists(node)) continue; - device_addr_t new_addr; - new_addr["name"] = "USRP1E"; - new_addr["node"] = abs_path(node); - usrp1e_addrs.push_back(new_addr); - } - } - - return usrp1e_addrs; -} - -/*********************************************************************** - * Make - **********************************************************************/ -device::sptr usrp1e::make(const device_addr_t &device_addr){ - return sptr(new usrp1e_impl(device_addr["node"])); -} - -/*********************************************************************** - * Structors - **********************************************************************/ -usrp1e_impl::usrp1e_impl(const std::string &node){ - //open the device node and check file descriptor - if ((_node_fd = ::open(node.c_str(), O_RDWR)) < 0){ - throw std::runtime_error(str( - boost::format("Failed to open %s") % node - )); - } - - //initialize the mboard - mboard_init(); - - //initialize the dboards - dboard_init(); - - //initialize the dsps - rx_ddc_init(); - tx_duc_init(); -} - -usrp1e_impl::~usrp1e_impl(void){ - //close the device node file descriptor - ::close(_node_fd); -} - -/*********************************************************************** - * Misc Methods - **********************************************************************/ -void usrp1e_impl::ioctl(int request, void *mem){ - if (::ioctl(_node_fd, request, mem) < 0){ - throw std::runtime_error(str( - boost::format("ioctl failed with request %d") % request - )); - } -} - -/*********************************************************************** - * Device Get - **********************************************************************/ -void usrp1e_impl::get(const wax::obj &key_, wax::obj &val){ - wax::obj key; std::string name; - boost::tie(key, name) = extract_named_prop(key_); - - //handle the get request conditioned on the key - switch(key.as()){ - case DEVICE_PROP_NAME: - val = std::string("usrp1e device"); - return; - - case DEVICE_PROP_MBOARD: - ASSERT_THROW(name == ""); - val = _mboard_proxy->get_link(); - return; - - case DEVICE_PROP_MBOARD_NAMES: - val = prop_names_t(1, ""); //vector of size 1 with empty string - return; - - case DEVICE_PROP_MAX_RX_SAMPLES: - val = size_t(_max_num_samples); - return; - - case DEVICE_PROP_MAX_TX_SAMPLES: - val = size_t(_max_num_samples); - return; - - } -} - -/*********************************************************************** - * Device Set - **********************************************************************/ -void usrp1e_impl::set(const wax::obj &, const wax::obj &){ - throw std::runtime_error("Cannot set in usrp1e device"); -} - -/*********************************************************************** - * Device IO (TODO) - **********************************************************************/ -size_t usrp1e_impl::send( - const boost::asio::const_buffer &, - const uhd::tx_metadata_t &, - const std::string &type -){ - if (type != "16sc"){ - throw std::runtime_error(str(boost::format("usrp1e send: cannot handle type \"%s\"") % type)); - } - return 0; -} - -size_t usrp1e_impl::recv( - const boost::asio::mutable_buffer &, - uhd::rx_metadata_t &, - const std::string &type -){ - if (type != "16sc"){ - throw std::runtime_error(str(boost::format("usrp1e recv: cannot handle type \"%s\"") % type)); - } - return 0; -} diff --git a/host/lib/usrp/usrp1e/usrp1e_impl.hpp b/host/lib/usrp/usrp1e/usrp1e_impl.hpp deleted file mode 100644 index c199a0465..000000000 --- a/host/lib/usrp/usrp1e/usrp1e_impl.hpp +++ /dev/null @@ -1,135 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include -#include - -#ifndef INCLUDED_USRP1E_IMPL_HPP -#define INCLUDED_USRP1E_IMPL_HPP - -class usrp1e_impl; // dummy class declaration - -/*! - * Make a usrp1e dboard interface. - * \param impl a pointer to the usrp1e impl object - * \return a sptr to a new dboard interface - */ -uhd::usrp::dboard_interface::sptr make_usrp1e_dboard_interface(usrp1e_impl *impl); - -/*! - * Simple wax obj proxy class: - * Provides a wax obj interface for a set and a get function. - * This allows us to create nested properties structures - * while maintaining flattened code within the implementation. - */ -class wax_obj_proxy : public wax::obj{ -public: - typedef boost::function get_t; - typedef boost::function set_t; - typedef boost::shared_ptr sptr; - - static sptr make(const get_t &get, const set_t &set){ - return sptr(new wax_obj_proxy(get, set)); - } - - ~wax_obj_proxy(void){ - /* NOP */ - } - -private: - get_t _get; - set_t _set; - - wax_obj_proxy(const get_t &get, const set_t &set){ - _get = get; - _set = set; - }; - - void get(const wax::obj &key, wax::obj &val){ - return _get(key, val); - } - - void set(const wax::obj &key, const wax::obj &val){ - return _set(key, val); - } -}; - -/*! - * USRP1E implementation guts: - * The implementation details are encapsulated here. - * Handles properties on the mboard, dboard, dsps... - */ -class usrp1e_impl : public uhd::device{ -public: - //structors - usrp1e_impl(const std::string &node); - ~usrp1e_impl(void); - - //the io interface - size_t send(const boost::asio::const_buffer &, const uhd::tx_metadata_t &, const std::string &); - size_t recv(const boost::asio::mutable_buffer &, uhd::rx_metadata_t &, const std::string &); - - /*! - * Perform an ioctl call on the device node file descriptor. - * This will throw when the internal ioctl call fails. - * \param request the control word - * \param mem pointer to some memory - */ - void ioctl(int request, void *mem); - -private: - static const size_t _max_num_samples = 2048/sizeof(boost::uint32_t); - int _node_fd; - - //device functions and settings - void get(const wax::obj &, wax::obj &); - void set(const wax::obj &, const wax::obj &); - - //mboard functions and settings - void mboard_init(void); - void mboard_get(const wax::obj &, wax::obj &); - void mboard_set(const wax::obj &, const wax::obj &); - wax_obj_proxy::sptr _mboard_proxy; - - //xx dboard functions and settings - void dboard_init(void); - uhd::usrp::dboard_manager::sptr _dboard_manager; - - //rx dboard functions and settings - void rx_dboard_get(const wax::obj &, wax::obj &); - void rx_dboard_set(const wax::obj &, const wax::obj &); - wax_obj_proxy::sptr _rx_dboard_proxy; - - //tx dboard functions and settings - void tx_dboard_get(const wax::obj &, wax::obj &); - void tx_dboard_set(const wax::obj &, const wax::obj &); - wax_obj_proxy::sptr _tx_dboard_proxy; - - //rx ddc functions and settings - void rx_ddc_init(void); - void rx_ddc_get(const wax::obj &, wax::obj &); - void rx_ddc_set(const wax::obj &, const wax::obj &); - wax_obj_proxy::sptr _rx_ddc_proxy; - - //tx duc functions and settings - void tx_duc_init(void); - void tx_duc_get(const wax::obj &, wax::obj &); - void tx_duc_set(const wax::obj &, const wax::obj &); - wax_obj_proxy::sptr _tx_duc_proxy; -}; - -#endif /* INCLUDED_USRP1E_IMPL_HPP */ diff --git a/host/lib/usrp/usrp1e/usrp1e_none.cpp b/host/lib/usrp/usrp1e/usrp1e_none.cpp deleted file mode 100644 index 94243523d..000000000 --- a/host/lib/usrp/usrp1e/usrp1e_none.cpp +++ /dev/null @@ -1,38 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include - -using namespace uhd; -using namespace uhd::usrp; - -/*! - * This file defines the usrp1e discover and make functions - * when the required kernel module headers are not present. - */ - -device_addrs_t usrp1e::find(const device_addr_t &){ - return device_addrs_t(); //return empty list -} - -device::sptr usrp1e::make(const device_addr_t &){ - throw std::runtime_error("this build has no usrp1e support"); -} - -void usrp1e::load_fpga(const std::string &){ - throw std::runtime_error("this build has no usrp1e support"); -} diff --git a/host/lib/usrp/usrp2/usrp2_impl.cpp b/host/lib/usrp/usrp2/usrp2_impl.cpp index 67fbdf8d2..b0ee395fb 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.cpp +++ b/host/lib/usrp/usrp2/usrp2_impl.cpp @@ -29,7 +29,7 @@ using namespace uhd::usrp; using namespace uhd::transport; namespace asio = boost::asio; -STATIC_BLOCK(register_usrp2_device){ +UHD_STATIC_BLOCK(register_usrp2_device){ device::register_device(&usrp2::find, &usrp2::make); } diff --git a/host/lib/usrp/usrp_e/dboard_impl.cpp b/host/lib/usrp/usrp_e/dboard_impl.cpp new file mode 100644 index 000000000..88d04ce7a --- /dev/null +++ b/host/lib/usrp/usrp_e/dboard_impl.cpp @@ -0,0 +1,76 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include +#include "usrp_e_impl.hpp" + +using namespace uhd::usrp; + +/*********************************************************************** + * Dboard Initialization + **********************************************************************/ +void usrp_e_impl::dboard_init(void){ + dboard_id_t rx_dboard_id = dboard_id::NONE; //TODO get these from the eeprom + dboard_id_t tx_dboard_id = dboard_id::NONE; + + //create a new dboard interface and manager + dboard_interface::sptr dboard_interface( + make_usrp_e_dboard_interface(this) + ); + _dboard_manager = dboard_manager::make( + rx_dboard_id, tx_dboard_id, dboard_interface + ); + + //setup the dboard proxies + _rx_dboard_proxy = wax_obj_proxy::make( + boost::bind(&usrp_e_impl::rx_dboard_get, this, _1, _2), + boost::bind(&usrp_e_impl::rx_dboard_set, this, _1, _2) + ); + _tx_dboard_proxy = wax_obj_proxy::make( + boost::bind(&usrp_e_impl::tx_dboard_get, this, _1, _2), + boost::bind(&usrp_e_impl::tx_dboard_set, this, _1, _2) + ); +} + +/*********************************************************************** + * RX Dboard Get + **********************************************************************/ +void usrp_e_impl::rx_dboard_get(const wax::obj &, wax::obj &){ + +} + +/*********************************************************************** + * RX Dboard Set + **********************************************************************/ +void usrp_e_impl::rx_dboard_set(const wax::obj &, const wax::obj &){ + +} + +/*********************************************************************** + * TX Dboard Get + **********************************************************************/ +void usrp_e_impl::tx_dboard_get(const wax::obj &, wax::obj &){ + +} + +/*********************************************************************** + * TX Dboard Set + **********************************************************************/ +void usrp_e_impl::tx_dboard_set(const wax::obj &, const wax::obj &){ + +} diff --git a/host/lib/usrp/usrp_e/dboard_interface.cpp b/host/lib/usrp/usrp_e/dboard_interface.cpp new file mode 100644 index 000000000..c7c7d8c1f --- /dev/null +++ b/host/lib/usrp/usrp_e/dboard_interface.cpp @@ -0,0 +1,189 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include //std::copy +#include "usrp_e_impl.hpp" +#include + +using namespace uhd::usrp; + +class usrp_e_dboard_interface : public dboard_interface{ +public: + usrp_e_dboard_interface(usrp_e_impl *impl); + ~usrp_e_dboard_interface(void); + + void write_aux_dac(unit_type_t, int, int); + int read_aux_adc(unit_type_t, int); + + void set_atr_reg(gpio_bank_t, boost::uint16_t, boost::uint16_t, boost::uint16_t); + void set_gpio_ddr(gpio_bank_t, boost::uint16_t, boost::uint16_t); + void write_gpio(gpio_bank_t, boost::uint16_t, boost::uint16_t); + boost::uint16_t read_gpio(gpio_bank_t); + + void write_i2c(int, const byte_vector_t &); + byte_vector_t read_i2c(int, size_t); + + double get_rx_clock_rate(void); + double get_tx_clock_rate(void); + +private: + byte_vector_t transact_spi( + spi_dev_t dev, + spi_latch_t latch, + spi_push_t push, + const byte_vector_t &buf, + bool readback + ); + + usrp_e_impl *_impl; +}; + +/*********************************************************************** + * Make Function + **********************************************************************/ +dboard_interface::sptr make_usrp_e_dboard_interface(usrp_e_impl *impl){ + return dboard_interface::sptr(new usrp_e_dboard_interface(impl)); +} + +/*********************************************************************** + * Structors + **********************************************************************/ +usrp_e_dboard_interface::usrp_e_dboard_interface(usrp_e_impl *impl){ + _impl = impl; +} + +usrp_e_dboard_interface::~usrp_e_dboard_interface(void){ + /* NOP */ +} + +/*********************************************************************** + * Clock Rates + **********************************************************************/ +double usrp_e_dboard_interface::get_rx_clock_rate(void){ + throw std::runtime_error("not implemented"); +} + +double usrp_e_dboard_interface::get_tx_clock_rate(void){ + throw std::runtime_error("not implemented"); +} + +/*********************************************************************** + * GPIO + **********************************************************************/ +void usrp_e_dboard_interface::set_gpio_ddr(gpio_bank_t bank, boost::uint16_t value, boost::uint16_t mask){ + throw std::runtime_error("not implemented"); +} + +void usrp_e_dboard_interface::write_gpio(gpio_bank_t bank, boost::uint16_t value, boost::uint16_t mask){ + throw std::runtime_error("not implemented"); +} + +boost::uint16_t usrp_e_dboard_interface::read_gpio(gpio_bank_t bank){ + throw std::runtime_error("not implemented"); +} + +void usrp_e_dboard_interface::set_atr_reg(gpio_bank_t bank, boost::uint16_t tx_value, boost::uint16_t rx_value, boost::uint16_t mask){ + throw std::runtime_error("not implemented"); +} + +/*********************************************************************** + * SPI + **********************************************************************/ +dboard_interface::byte_vector_t usrp_e_dboard_interface::transact_spi( + spi_dev_t dev, + spi_latch_t latch, + spi_push_t push, + const byte_vector_t &buf, + bool readback +){ + //load data struct + usrp_e_spi data; + data.readback = (readback)? UE_SPI_TXRX : UE_SPI_TXONLY; + data.slave = (dev == SPI_RX_DEV)? UE_SPI_CTRL_RXNEG : UE_SPI_CTRL_TXNEG; + data.length = buf.size() * 8; //bytes to bits + boost::uint8_t *data_bytes = reinterpret_cast(&data.data); + + //load the data + ASSERT_THROW(buf.size() <= sizeof(data.data)); + std::copy(buf.begin(), buf.end(), data_bytes); + + //load the flags + data.flags = 0; + data.flags |= (latch == SPI_LATCH_RISE)? UE_SPI_LATCH_RISE : UE_SPI_LATCH_FALL; + data.flags |= (push == SPI_PUSH_RISE)? UE_SPI_PUSH_RISE : UE_SPI_PUSH_FALL; + + //call the spi ioctl + _impl->ioctl(USRP_E_SPI, &data); + + //unload the data + byte_vector_t ret(data.length/8); //bits to bytes + ASSERT_THROW(ret.size() <= sizeof(data.data)); + std::copy(data_bytes, data_bytes+ret.size(), ret.begin()); + return ret; +} + +/*********************************************************************** + * I2C + **********************************************************************/ +static const size_t max_i2c_data_bytes = 10; + +void usrp_e_dboard_interface::write_i2c(int i2c_addr, const byte_vector_t &buf){ + //allocate some memory for this transaction + ASSERT_THROW(buf.size() <= max_i2c_data_bytes); + boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; + + //load the data struct + usrp_e_i2c &data = reinterpret_cast(mem); + data.addr = i2c_addr; + data.len = buf.size(); + std::copy(buf.begin(), buf.end(), data.data); + + //call the spi ioctl + _impl->ioctl(USRP_E_I2C_WRITE, &data); +} + +dboard_interface::byte_vector_t usrp_e_dboard_interface::read_i2c(int i2c_addr, size_t num_bytes){ + //allocate some memory for this transaction + ASSERT_THROW(num_bytes <= max_i2c_data_bytes); + boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; + + //load the data struct + usrp_e_i2c &data = reinterpret_cast(mem); + data.addr = i2c_addr; + data.len = num_bytes; + + //call the spi ioctl + _impl->ioctl(USRP_E_I2C_READ, &data); + + //unload the data + byte_vector_t ret(data.len); + ASSERT_THROW(ret.size() == num_bytes); + std::copy(data.data, data.data+ret.size(), ret.begin()); + return ret; +} + +/*********************************************************************** + * Aux DAX/ADC + **********************************************************************/ +void usrp_e_dboard_interface::write_aux_dac(dboard_interface::unit_type_t unit, int which, int value){ + throw std::runtime_error("not implemented"); +} + +int usrp_e_dboard_interface::read_aux_adc(dboard_interface::unit_type_t unit, int which){ + throw std::runtime_error("not implemented"); +} diff --git a/host/lib/usrp/usrp_e/dsp_impl.cpp b/host/lib/usrp/usrp_e/dsp_impl.cpp new file mode 100644 index 000000000..e32c76a3d --- /dev/null +++ b/host/lib/usrp/usrp_e/dsp_impl.cpp @@ -0,0 +1,69 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include "usrp_e_impl.hpp" + +using namespace uhd::usrp; + +/*********************************************************************** + * RX DDC Initialization + **********************************************************************/ +void usrp_e_impl::rx_ddc_init(void){ + _rx_ddc_proxy = wax_obj_proxy::make( + boost::bind(&usrp_e_impl::rx_ddc_get, this, _1, _2), + boost::bind(&usrp_e_impl::rx_ddc_set, this, _1, _2) + ); +} + +/*********************************************************************** + * RX DDC Get + **********************************************************************/ +void usrp_e_impl::rx_ddc_get(const wax::obj &, wax::obj &){ + +} + +/*********************************************************************** + * RX DDC Set + **********************************************************************/ +void usrp_e_impl::rx_ddc_set(const wax::obj &, const wax::obj &){ + +} + +/*********************************************************************** + * TX DUC Initialization + **********************************************************************/ +void usrp_e_impl::tx_duc_init(void){ + _tx_duc_proxy = wax_obj_proxy::make( + boost::bind(&usrp_e_impl::tx_duc_get, this, _1, _2), + boost::bind(&usrp_e_impl::tx_duc_set, this, _1, _2) + ); +} + +/*********************************************************************** + * TX DUC Get + **********************************************************************/ +void usrp_e_impl::tx_duc_get(const wax::obj &, wax::obj &){ + +} + +/*********************************************************************** + * TX DUC Set + **********************************************************************/ +void usrp_e_impl::tx_duc_set(const wax::obj &, const wax::obj &){ + +} diff --git a/host/lib/usrp/usrp_e/fpga-downloader.cc b/host/lib/usrp/usrp_e/fpga-downloader.cc new file mode 100644 index 000000000..4429786a9 --- /dev/null +++ b/host/lib/usrp/usrp_e/fpga-downloader.cc @@ -0,0 +1,262 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +/* + * Configuration connections + * + * CCK - MCSPI1_CLK + * DIN - MCSPI1_MOSI + * PROG_B - GPIO_175 - output (change mux) + * DONE - GPIO_173 - input (change mux) + * INIT_B - GPIO_114 - input (change mux) + * +*/ + +const unsigned int PROG_B = 175; +const unsigned int DONE = 173; +const unsigned int INIT_B = 114; + +//static std::string bit_file = "safe_u1e.bin"; + +const int BUF_SIZE = 4096; + +enum gpio_direction {IN, OUT}; + +class gpio { + public: + + gpio(unsigned int gpio_num, gpio_direction pin_direction); + + bool get_value(); + void set_value(bool state); + + private: + + std::stringstream base_path; + std::fstream value_file; +}; + +class spidev { + public: + + spidev(std::string dev_name); + ~spidev(); + + void send(char *wbuf, char *rbuf, unsigned int nbytes); + + private: + + int fd; + +}; + +gpio::gpio(unsigned int gpio_num, gpio_direction pin_direction) +{ + std::fstream export_file; + + export_file.open("/sys/class/gpio/export", std::ios::out); + if (!export_file.is_open()) ///\todo Poor error handling + std::cout << "Failed to open gpio export file." << std::endl; + + export_file << gpio_num << std::endl; + + base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush; + + std::fstream direction_file; + std::string direction_file_name; + + direction_file_name = base_path.str() + "/direction"; + + direction_file.open(direction_file_name.c_str()); + if (!direction_file.is_open()) + std::cout << "Failed to open direction file." << std::endl; + if (pin_direction == OUT) + direction_file << "out" << std::endl; + else + direction_file << "in" << std::endl; + + std::string value_file_name; + + value_file_name = base_path.str() + "/value"; + + value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out); + if (!value_file.is_open()) + std::cout << "Failed to open value file." << std::endl; +} + +bool gpio::get_value() +{ + + std::string val; + + std::getline(value_file, val); + value_file.seekg(0); + + if (val == "0") + return false; + else if (val == "1") + return true; + else + std::cout << "Data read from value file|" << val << "|" << std::endl; + + return false; +} + +void gpio::set_value(bool state) +{ + + if (state) + value_file << "1" << std::endl; + else + value_file << "0" << std::endl; +} + +static void prepare_fpga_for_configuration(gpio &prog, gpio &)//init) +{ + + prog.set_value(true); + prog.set_value(false); + prog.set_value(true); + +#if 0 + bool ready_to_program(false); + unsigned int count(0); + do { + ready_to_program = init.get_value(); + count++; + + sleep(1); + } while (count < 10 && !ready_to_program); + + if (count == 10) { + std::cout << "FPGA not ready for programming." << std::endl; + exit(-1); + } +#endif +} + +spidev::spidev(std::string fname) +{ + int ret; + int mode = 0; + int speed = 12000000; + int bits = 8; + + fd = open(fname.c_str(), O_RDWR); + + ret = ioctl(fd, SPI_IOC_WR_MODE, &mode); + ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed); + ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits); +} + + +spidev::~spidev() +{ + close(fd); +} + +void spidev::send(char *buf, char *rbuf, unsigned int nbytes) +{ + int ret; + + struct spi_ioc_transfer tr; + tr.tx_buf = (unsigned long) buf; + tr.rx_buf = (unsigned long) rbuf; + tr.len = nbytes; + tr.delay_usecs = 0; + tr.speed_hz = 48000000; + tr.bits_per_word = 8; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + +} + +static void send_file_to_fpga(const std::string &file_name, gpio &error, gpio &done) +{ + std::ifstream bitstream; + + std::cout << "File name - " << file_name.c_str() << std::endl; + + bitstream.open(file_name.c_str(), std::ios::binary); + if (!bitstream.is_open()) + std::cout << "File " << file_name << " not opened succesfully." << std::endl; + + spidev spi("/dev/spidev1.0"); + char buf[BUF_SIZE]; + char rbuf[BUF_SIZE]; + + do { + bitstream.read(buf, BUF_SIZE); + spi.send(buf, rbuf, bitstream.gcount()); + + if (error.get_value()) + std::cout << "INIT_B went high, error occured." << std::endl; + + if (!done.get_value()) + std::cout << "Configuration complete." << std::endl; + + } while (bitstream.gcount() == BUF_SIZE); +} + +/* +int main(int argc, char *argv[]) +{ + + gpio gpio_prog_b(PROG_B, OUT); + gpio gpio_init_b(INIT_B, IN); + gpio gpio_done (DONE, IN); + + if (argc == 2) + bit_file = argv[1]; + + std::cout << "FPGA config file: " << bit_file << std::endl; + + prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b); + + std::cout << "Done = " << gpio_done.get_value() << std::endl; + + send_file_to_fpga(bit_file, gpio_init_b, gpio_done); +} +*/ + +#include +void uhd::usrp::usrp_e::load_fpga(const std::string &bin_file){ + gpio gpio_prog_b(PROG_B, OUT); + gpio gpio_init_b(INIT_B, IN); + gpio gpio_done (DONE, IN); + + std::cout << "FPGA config file: " << bin_file << std::endl; + + prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b); + + std::cout << "Done = " << gpio_done.get_value() << std::endl; + + send_file_to_fpga(bin_file, gpio_init_b, gpio_done); +} diff --git a/host/lib/usrp/usrp_e/mboard_impl.cpp b/host/lib/usrp/usrp_e/mboard_impl.cpp new file mode 100644 index 000000000..333fb2e51 --- /dev/null +++ b/host/lib/usrp/usrp_e/mboard_impl.cpp @@ -0,0 +1,45 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include "usrp_e_impl.hpp" + +using namespace uhd::usrp; + +/*********************************************************************** + * Mboard Initialization + **********************************************************************/ +void usrp_e_impl::mboard_init(void){ + _mboard_proxy = wax_obj_proxy::make( + boost::bind(&usrp_e_impl::mboard_get, this, _1, _2), + boost::bind(&usrp_e_impl::mboard_set, this, _1, _2) + ); +} + +/*********************************************************************** + * Mboard Get + **********************************************************************/ +void usrp_e_impl::mboard_get(const wax::obj &, wax::obj &){ + +} + +/*********************************************************************** + * Mboard Set + **********************************************************************/ +void usrp_e_impl::mboard_set(const wax::obj &, const wax::obj &){ + +} diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.cpp b/host/lib/usrp/usrp_e/usrp_e_impl.cpp new file mode 100644 index 000000000..e821add8c --- /dev/null +++ b/host/lib/usrp/usrp_e/usrp_e_impl.cpp @@ -0,0 +1,179 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "usrp_e_impl.hpp" +#include +#include +#include +#include +#include //open +#include //ioctl + +using namespace uhd; +using namespace uhd::usrp; +namespace fs = boost::filesystem; + +UHD_STATIC_BLOCK(register_usrp_e_device){ + device::register_device(&usrp_e::find, &usrp_e::make); +} + +/*********************************************************************** + * Helper Functions + **********************************************************************/ +static std::string abs_path(const std::string &file_path){ + return fs::system_complete(fs::path(file_path)).file_string(); +} + +/*********************************************************************** + * Discovery + **********************************************************************/ +device_addrs_t usrp_e::find(const device_addr_t &device_addr){ + device_addrs_t usrp_e_addrs; + + //if a node was provided, use it and only it + if (device_addr.has_key("node")){ + if (not fs::exists(device_addr["node"])) return usrp_e_addrs; + device_addr_t new_addr; + new_addr["name"] = "USRP-E"; + new_addr["node"] = abs_path(device_addr["node"]); + usrp_e_addrs.push_back(new_addr); + } + + //otherwise look for a few nodes at small indexes + else{ + for(size_t i = 0; i < 5; i++){ + std::string node = str(boost::format("/dev/usrp1_e%d") % i); + if (not fs::exists(node)) continue; + device_addr_t new_addr; + new_addr["name"] = "USRP-E"; + new_addr["node"] = abs_path(node); + usrp_e_addrs.push_back(new_addr); + } + } + + return usrp_e_addrs; +} + +/*********************************************************************** + * Make + **********************************************************************/ +device::sptr usrp_e::make(const device_addr_t &device_addr){ + return sptr(new usrp_e_impl(device_addr["node"])); +} + +/*********************************************************************** + * Structors + **********************************************************************/ +usrp_e_impl::usrp_e_impl(const std::string &node){ + //open the device node and check file descriptor + if ((_node_fd = ::open(node.c_str(), O_RDWR)) < 0){ + throw std::runtime_error(str( + boost::format("Failed to open %s") % node + )); + } + + //initialize the mboard + mboard_init(); + + //initialize the dboards + dboard_init(); + + //initialize the dsps + rx_ddc_init(); + tx_duc_init(); +} + +usrp_e_impl::~usrp_e_impl(void){ + //close the device node file descriptor + ::close(_node_fd); +} + +/*********************************************************************** + * Misc Methods + **********************************************************************/ +void usrp_e_impl::ioctl(int request, void *mem){ + if (::ioctl(_node_fd, request, mem) < 0){ + throw std::runtime_error(str( + boost::format("ioctl failed with request %d") % request + )); + } +} + +/*********************************************************************** + * Device Get + **********************************************************************/ +void usrp_e_impl::get(const wax::obj &key_, wax::obj &val){ + wax::obj key; std::string name; + boost::tie(key, name) = extract_named_prop(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case DEVICE_PROP_NAME: + val = std::string("usrp-e device"); + return; + + case DEVICE_PROP_MBOARD: + ASSERT_THROW(name == ""); + val = _mboard_proxy->get_link(); + return; + + case DEVICE_PROP_MBOARD_NAMES: + val = prop_names_t(1, ""); //vector of size 1 with empty string + return; + + case DEVICE_PROP_MAX_RX_SAMPLES: + val = size_t(_max_num_samples); + return; + + case DEVICE_PROP_MAX_TX_SAMPLES: + val = size_t(_max_num_samples); + return; + + } +} + +/*********************************************************************** + * Device Set + **********************************************************************/ +void usrp_e_impl::set(const wax::obj &, const wax::obj &){ + throw std::runtime_error("Cannot set in usrp-e device"); +} + +/*********************************************************************** + * Device IO (TODO) + **********************************************************************/ +size_t usrp_e_impl::send( + const boost::asio::const_buffer &, + const uhd::tx_metadata_t &, + const io_type_t & +){ + if (true){ + throw std::runtime_error(str(boost::format("usrp-e send: cannot handle type \"%s\"") % "")); + } + return 0; +} + +size_t usrp_e_impl::recv( + const boost::asio::mutable_buffer &, + uhd::rx_metadata_t &, + const io_type_t & +){ + if (true){ + throw std::runtime_error(str(boost::format("usrp-e recv: cannot handle type \"%s\"") % "")); + } + return 0; +} diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp new file mode 100644 index 000000000..e593b13ad --- /dev/null +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -0,0 +1,135 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include + +#ifndef INCLUDED_USRP_E_IMPL_HPP +#define INCLUDED_USRP_E_IMPL_HPP + +class usrp_e_impl; // dummy class declaration + +/*! + * Make a usrp_e dboard interface. + * \param impl a pointer to the usrp_e impl object + * \return a sptr to a new dboard interface + */ +uhd::usrp::dboard_interface::sptr make_usrp_e_dboard_interface(usrp_e_impl *impl); + +/*! + * Simple wax obj proxy class: + * Provides a wax obj interface for a set and a get function. + * This allows us to create nested properties structures + * while maintaining flattened code within the implementation. + */ +class wax_obj_proxy : public wax::obj{ +public: + typedef boost::function get_t; + typedef boost::function set_t; + typedef boost::shared_ptr sptr; + + static sptr make(const get_t &get, const set_t &set){ + return sptr(new wax_obj_proxy(get, set)); + } + + ~wax_obj_proxy(void){ + /* NOP */ + } + +private: + get_t _get; + set_t _set; + + wax_obj_proxy(const get_t &get, const set_t &set){ + _get = get; + _set = set; + }; + + void get(const wax::obj &key, wax::obj &val){ + return _get(key, val); + } + + void set(const wax::obj &key, const wax::obj &val){ + return _set(key, val); + } +}; + +/*! + * USRP1E implementation guts: + * The implementation details are encapsulated here. + * Handles properties on the mboard, dboard, dsps... + */ +class usrp_e_impl : public uhd::device{ +public: + //structors + usrp_e_impl(const std::string &node); + ~usrp_e_impl(void); + + //the io interface + size_t send(const boost::asio::const_buffer &, const uhd::tx_metadata_t &, const uhd::io_type_t &); + size_t recv(const boost::asio::mutable_buffer &, uhd::rx_metadata_t &, const uhd::io_type_t &); + + /*! + * Perform an ioctl call on the device node file descriptor. + * This will throw when the internal ioctl call fails. + * \param request the control word + * \param mem pointer to some memory + */ + void ioctl(int request, void *mem); + +private: + static const size_t _max_num_samples = 2048/sizeof(boost::uint32_t); + int _node_fd; + + //device functions and settings + void get(const wax::obj &, wax::obj &); + void set(const wax::obj &, const wax::obj &); + + //mboard functions and settings + void mboard_init(void); + void mboard_get(const wax::obj &, wax::obj &); + void mboard_set(const wax::obj &, const wax::obj &); + wax_obj_proxy::sptr _mboard_proxy; + + //xx dboard functions and settings + void dboard_init(void); + uhd::usrp::dboard_manager::sptr _dboard_manager; + + //rx dboard functions and settings + void rx_dboard_get(const wax::obj &, wax::obj &); + void rx_dboard_set(const wax::obj &, const wax::obj &); + wax_obj_proxy::sptr _rx_dboard_proxy; + + //tx dboard functions and settings + void tx_dboard_get(const wax::obj &, wax::obj &); + void tx_dboard_set(const wax::obj &, const wax::obj &); + wax_obj_proxy::sptr _tx_dboard_proxy; + + //rx ddc functions and settings + void rx_ddc_init(void); + void rx_ddc_get(const wax::obj &, wax::obj &); + void rx_ddc_set(const wax::obj &, const wax::obj &); + wax_obj_proxy::sptr _rx_ddc_proxy; + + //tx duc functions and settings + void tx_duc_init(void); + void tx_duc_get(const wax::obj &, wax::obj &); + void tx_duc_set(const wax::obj &, const wax::obj &); + wax_obj_proxy::sptr _tx_duc_proxy; +}; + +#endif /* INCLUDED_USRP_E_IMPL_HPP */ diff --git a/host/lib/usrp/usrp_e/usrp_e_none.cpp b/host/lib/usrp/usrp_e/usrp_e_none.cpp new file mode 100644 index 000000000..09a3c6946 --- /dev/null +++ b/host/lib/usrp/usrp_e/usrp_e_none.cpp @@ -0,0 +1,38 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include + +using namespace uhd; +using namespace uhd::usrp; + +/*! + * This file defines the usrp1e discover and make functions + * when the required kernel module headers are not present. + */ + +device_addrs_t usrp_e::find(const device_addr_t &){ + return device_addrs_t(); //return empty list +} + +device::sptr usrp_e::make(const device_addr_t &){ + throw std::runtime_error("this build has no usrp1e support"); +} + +void usrp_e::load_fpga(const std::string &){ + throw std::runtime_error("this build has no usrp1e support"); +} diff --git a/host/utils/CMakeLists.txt b/host/utils/CMakeLists.txt index 99e648d8a..0b1e058ef 100644 --- a/host/utils/CMakeLists.txt +++ b/host/utils/CMakeLists.txt @@ -19,8 +19,9 @@ ADD_EXECUTABLE(uhd_find_devices uhd_find_devices.cpp) TARGET_LINK_LIBRARIES(uhd_find_devices uhd) INSTALL(TARGETS uhd_find_devices RUNTIME DESTINATION ${RUNTIME_DIR}) -ADD_EXECUTABLE(usrp1e_load_fpga usrp1e_load_fpga.cpp) -TARGET_LINK_LIBRARIES(usrp1e_load_fpga uhd) +ADD_EXECUTABLE(usrp_e_load_fpga usrp_e_load_fpga.cpp) +TARGET_LINK_LIBRARIES(usrp_e_load_fpga uhd) +INSTALL(TARGETS usrp_e_load_fpga RUNTIME DESTINATION ${PKG_DATA_DIR}/utils) ADD_EXECUTABLE(usrp2_burner usrp2_burner.cpp) TARGET_LINK_LIBRARIES(usrp2_burner uhd) diff --git a/host/utils/usrp_e_load_fpga.cpp b/host/utils/usrp_e_load_fpga.cpp new file mode 100644 index 000000000..403130b53 --- /dev/null +++ b/host/utils/usrp_e_load_fpga.cpp @@ -0,0 +1,47 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include +#include +#include + +namespace po = boost::program_options; + +int main(int argc, char *argv[]){ + po::options_description desc("Allowed options"); + desc.add_options() + ("help", "help message") + ("file", po::value(), "path to fpga bin file") + ; + + po::variables_map vm; + po::store(po::parse_command_line(argc, argv, desc), vm); + po::notify(vm); + + //print the help message + if (vm.count("help") or vm.count("file") == 0){ + std::cout << boost::format("USRP1E Load FPGA %s") % desc << std::endl; + return ~0; + } + + //load the fpga + std::string file = vm["file"].as(); + uhd::usrp::usrp_e::load_fpga(file); + + return 0; +} -- cgit v1.2.3 From 2f81e2f7086eec7c0ae4370555ddae6e2f6ce2de Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 30 Mar 2010 17:24:39 +0000 Subject: tweak usrp-e cmake config --- host/lib/CMakeLists.txt | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/host/lib/CMakeLists.txt b/host/lib/CMakeLists.txt index db5e9d273..ff002bfc0 100644 --- a/host/lib/CMakeLists.txt +++ b/host/lib/CMakeLists.txt @@ -54,18 +54,18 @@ LIST(APPEND libuhd_sources MESSAGE(STATUS "Configuring usrp-e support...") INCLUDE(CheckIncludeFiles) -SET(usrp1e_required_headers +SET(usrp_e_required_headers linux/ioctl.h linux/spi/spidev.h - linux/usrp1_e.h + linux/usrp_e.h ) CHECK_INCLUDE_FILES( - "${usrp1e_required_headers}" - HAS_USRP1E_REQUIRED_HEADERS + "${usrp_e_required_headers}" + HAVE_USRP_E_REQUIRED_HEADERS ) -IF(HAS_USRP1E_REQUIRED_HEADERS) - MESSAGE(STATUS " Building usrp1e support.") +IF(HAVE_USRP_E_REQUIRED_HEADERS) + MESSAGE(STATUS " Building usrp-e support.") LIST(APPEND libuhd_sources usrp/usrp_e/dboard_impl.cpp usrp/usrp_e/dboard_interface.cpp @@ -74,12 +74,12 @@ IF(HAS_USRP1E_REQUIRED_HEADERS) usrp/usrp_e/mboard_impl.cpp usrp/usrp_e/usrp_e_impl.cpp ) -ELSE(HAS_USRP1E_REQUIRED_HEADERS) - MESSAGE(STATUS " Skipping usrp1e support.") +ELSE(HAVE_USRP_E_REQUIRED_HEADERS) + MESSAGE(STATUS " Skipping usrp-e support.") LIST(APPEND libuhd_sources usrp/usrp_e/usrp_e_none.cpp ) -ENDIF(HAS_USRP1E_REQUIRED_HEADERS) +ENDIF(HAVE_USRP_E_REQUIRED_HEADERS) ######################################################################## # Setup defines for module loading -- cgit v1.2.3 From 03be4d0673c5e0f597db7d27f535956a591bbeb7 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 30 Mar 2010 17:52:27 +0000 Subject: filled in some gpio handling code, some mboard impl, added usrp_e_regs (like memory map) --- host/include/uhd/types/clock_config.hpp | 1 + host/lib/usrp/usrp_e/dboard_impl.cpp | 1 - host/lib/usrp/usrp_e/dboard_interface.cpp | 89 +++++++++++++++++++++++++++---- host/lib/usrp/usrp_e/mboard_impl.cpp | 77 ++++++++++++++++++++++++-- host/lib/usrp/usrp_e/usrp_e_impl.hpp | 3 ++ host/lib/usrp/usrp_e/usrp_e_regs.hpp | 49 +++++++++++++++++ 6 files changed, 206 insertions(+), 14 deletions(-) create mode 100644 host/lib/usrp/usrp_e/usrp_e_regs.hpp diff --git a/host/include/uhd/types/clock_config.hpp b/host/include/uhd/types/clock_config.hpp index 42d74ad90..9342fbb7b 100644 --- a/host/include/uhd/types/clock_config.hpp +++ b/host/include/uhd/types/clock_config.hpp @@ -29,6 +29,7 @@ namespace uhd{ */ struct UHD_API clock_config_t{ enum ref_source_t { + REF_AUTO = 'a', //automatic (device specific) REF_INT = 'i', //internal reference REF_SMA = 's', //external sma port REF_MIMO = 'm' //mimo cable (usrp2 only) diff --git a/host/lib/usrp/usrp_e/dboard_impl.cpp b/host/lib/usrp/usrp_e/dboard_impl.cpp index 88d04ce7a..7c87361e0 100644 --- a/host/lib/usrp/usrp_e/dboard_impl.cpp +++ b/host/lib/usrp/usrp_e/dboard_impl.cpp @@ -16,7 +16,6 @@ // #include -#include #include "usrp_e_impl.hpp" using namespace uhd::usrp; diff --git a/host/lib/usrp/usrp_e/dboard_interface.cpp b/host/lib/usrp/usrp_e/dboard_interface.cpp index c7c7d8c1f..a343d93b8 100644 --- a/host/lib/usrp/usrp_e/dboard_interface.cpp +++ b/host/lib/usrp/usrp_e/dboard_interface.cpp @@ -15,10 +15,14 @@ // along with this program. If not, see . // +#include "usrp_e_impl.hpp" +#include "usrp_e_regs.hpp" +#include #include +#include #include //std::copy -#include "usrp_e_impl.hpp" -#include +#include +#include using namespace uhd::usrp; @@ -31,8 +35,8 @@ public: int read_aux_adc(unit_type_t, int); void set_atr_reg(gpio_bank_t, boost::uint16_t, boost::uint16_t, boost::uint16_t); - void set_gpio_ddr(gpio_bank_t, boost::uint16_t, boost::uint16_t); - void write_gpio(gpio_bank_t, boost::uint16_t, boost::uint16_t); + void set_gpio_ddr(gpio_bank_t, boost::uint16_t); + void write_gpio(gpio_bank_t, boost::uint16_t); boost::uint16_t read_gpio(gpio_bank_t); void write_i2c(int, const byte_vector_t &); @@ -85,20 +89,85 @@ double usrp_e_dboard_interface::get_tx_clock_rate(void){ /*********************************************************************** * GPIO **********************************************************************/ -void usrp_e_dboard_interface::set_gpio_ddr(gpio_bank_t bank, boost::uint16_t value, boost::uint16_t mask){ - throw std::runtime_error("not implemented"); +void usrp_e_dboard_interface::set_gpio_ddr(gpio_bank_t bank, boost::uint16_t value){ + //define mapping of gpio bank to register address + static const uhd::dict bank_to_addr = boost::assign::map_list_of + (GPIO_RX_BANK, GPIO_BASE + offsetof(gpio_regs_t, rx_ddr)) + (GPIO_TX_BANK, GPIO_BASE + offsetof(gpio_regs_t, tx_ddr)) + ; + + //load the data struct + usrp_e_ctl16 data; + data.offset = bank_to_addr[bank]; + data.count = 1; + data.buf[0] = value; + + //call the ioctl + _impl->ioctl(USRP_E_WRITE_CTL16, &data); } -void usrp_e_dboard_interface::write_gpio(gpio_bank_t bank, boost::uint16_t value, boost::uint16_t mask){ - throw std::runtime_error("not implemented"); +void usrp_e_dboard_interface::write_gpio(gpio_bank_t bank, boost::uint16_t value){ + //define mapping of gpio bank to register address + static const uhd::dict bank_to_addr = boost::assign::map_list_of + (GPIO_RX_BANK, GPIO_BASE + offsetof(gpio_regs_t, rx_io)) + (GPIO_TX_BANK, GPIO_BASE + offsetof(gpio_regs_t, tx_io)) + ; + + //load the data struct + usrp_e_ctl16 data; + data.offset = bank_to_addr[bank]; + data.count = 1; + data.buf[0] = value; + + //call the ioctl + _impl->ioctl(USRP_E_WRITE_CTL16, &data); } boost::uint16_t usrp_e_dboard_interface::read_gpio(gpio_bank_t bank){ - throw std::runtime_error("not implemented"); + //define mapping of gpio bank to register address + static const uhd::dict bank_to_addr = boost::assign::map_list_of + (GPIO_RX_BANK, GPIO_BASE + offsetof(gpio_regs_t, rx_io)) + (GPIO_TX_BANK, GPIO_BASE + offsetof(gpio_regs_t, tx_io)) + ; + + //load the data struct + usrp_e_ctl16 data; + data.offset = bank_to_addr[bank]; + data.count = 1; + + //call the ioctl + _impl->ioctl(USRP_E_READ_CTL16, &data); + + return data.buf[0]; } void usrp_e_dboard_interface::set_atr_reg(gpio_bank_t bank, boost::uint16_t tx_value, boost::uint16_t rx_value, boost::uint16_t mask){ - throw std::runtime_error("not implemented"); + //define mapping of gpio bank to register address + static const uhd::dict bank_to_addr = boost::assign::map_list_of + (GPIO_RX_BANK, GPIO_BASE + offsetof(gpio_regs_t, rx_sel_low)) + (GPIO_TX_BANK, GPIO_BASE + offsetof(gpio_regs_t, tx_sel_low)) + ; + + //set the gpio selection mux to atr or software controlled + boost::uint16_t low_sel = 0, high_sel = 0; + for(size_t i = 0; i < 16; i++){ + boost::uint16_t code = (mask & (1 << i))? GPIO_SEL_ATR : GPIO_SEL_SW; + if(i < 8) low_sel |= code << (2*i-0); + else high_sel |= code << (2*i-8); + } + + //load the data struct + usrp_e_ctl16 data; + data.offset = bank_to_addr[bank]; + data.count = 2; + data.buf[0] = low_sel; + data.buf[1] = high_sel; + + //call the ioctl + _impl->ioctl(USRP_E_READ_CTL16, &data); + + //----------------------------------------> TODO + //TODO set the atr regs } /*********************************************************************** diff --git a/host/lib/usrp/usrp_e/mboard_impl.cpp b/host/lib/usrp/usrp_e/mboard_impl.cpp index 333fb2e51..1d3f9f466 100644 --- a/host/lib/usrp/usrp_e/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e/mboard_impl.cpp @@ -15,9 +15,12 @@ // along with this program. If not, see . // -#include #include "usrp_e_impl.hpp" +#include +#include +#include +using namespace uhd; using namespace uhd::usrp; /*********************************************************************** @@ -28,13 +31,81 @@ void usrp_e_impl::mboard_init(void){ boost::bind(&usrp_e_impl::mboard_get, this, _1, _2), boost::bind(&usrp_e_impl::mboard_set, this, _1, _2) ); + + //init the clock config + _clock_config.ref_source = clock_config_t::REF_AUTO; + _clock_config.pps_source = clock_config_t::PPS_SMA; + + //TODO poke the clock config regs } /*********************************************************************** * Mboard Get **********************************************************************/ -void usrp_e_impl::mboard_get(const wax::obj &, wax::obj &){ - +void usrp_e_impl::mboard_get(const wax::obj &key_, wax::obj &val){ + wax::obj key; std::string name; + boost::tie(key, name) = extract_named_prop(key_); + + + //handle the get request conditioned on the key + switch(key.as()){ + case MBOARD_PROP_NAME: + val = std::string("usrp-e mboard"); + return; + + case MBOARD_PROP_OTHERS: + val = prop_names_t(); + return; + + case MBOARD_PROP_RX_DBOARD: + ASSERT_THROW(name == ""); + val = _rx_dboard_proxy->get_link(); + return; + + case MBOARD_PROP_RX_DBOARD_NAMES: + val = prop_names_t(1, ""); //vector of size 1 with empty string + return; + + case MBOARD_PROP_TX_DBOARD: + ASSERT_THROW(name == ""); + val = _tx_dboard_proxy->get_link(); + return; + + case MBOARD_PROP_TX_DBOARD_NAMES: + val = prop_names_t(1, ""); //vector of size 1 with empty string + return; + + case MBOARD_PROP_CLOCK_RATE: + //val = TODO probably remove this property + return; + + case MBOARD_PROP_RX_DSP: + ASSERT_THROW(name == "ddc0"); + val = _rx_ddc_proxy->get_link(); + return; + + case MBOARD_PROP_RX_DSP_NAMES: + val = prop_names_t(1, "ddc0"); + return; + + case MBOARD_PROP_TX_DSP: + ASSERT_THROW(name == "duc0"); + val = _tx_duc_proxy->get_link(); + return; + + case MBOARD_PROP_TX_DSP_NAMES: + val = prop_names_t(1, "duc0"); + return; + + case MBOARD_PROP_CLOCK_CONFIG: + val = _clock_config; + return; + + case MBOARD_PROP_TIME_NOW: + case MBOARD_PROP_TIME_NEXT_PPS: + throw std::runtime_error("Error: trying to get write-only property on usrp-e mboard"); + + } } /*********************************************************************** diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index e593b13ad..643589754 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -15,6 +15,7 @@ // along with this program. If not, see . // +#include #include #include @@ -95,6 +96,8 @@ private: static const size_t _max_num_samples = 2048/sizeof(boost::uint32_t); int _node_fd; + uhd::clock_config_t _clock_config; + //device functions and settings void get(const wax::obj &, wax::obj &); void set(const wax::obj &, const wax::obj &); diff --git a/host/lib/usrp/usrp_e/usrp_e_regs.hpp b/host/lib/usrp/usrp_e/usrp_e_regs.hpp new file mode 100644 index 000000000..219f459a5 --- /dev/null +++ b/host/lib/usrp/usrp_e/usrp_e_regs.hpp @@ -0,0 +1,49 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_USRP_E_REGS_HPP +#define INCLUDED_USRP_E_REGS_HPP + +#include + +//////////////////////////////////////////////// +// GPIO, Slave 4 +// +// These go to the daughterboard i/o pins + +#define GPIO_BASE 0x40 + +struct gpio_regs_t{ + boost::uint16_t rx_io; // tx data in high 16, rx in low 16 + boost::uint16_t tx_io; + boost::uint16_t rx_ddr; // 32 bits, 1 means output. tx in high 16, rx in low 16 + boost::uint16_t tx_ddr; + boost::uint16_t tx_sel_low; // 16 2-bit fields select which source goes to TX DB + boost::uint16_t tx_sel_high; + boost::uint16_t rx_sel_low; // 16 2-bit fields select which source goes to RX DB + boost::uint16_t rx_sel_high; +}; + +// each 2-bit sel field is layed out this way +#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg +#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic +#define GPIO_SEL_DEBUG_0 2 // if pin is an output, debug lines from FPGA fabric +#define GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from FPGA fabric + +//#define gpio_base ((gpio_regs_t *) GPIO_BASE) + +#endif /* INCLUDED_USRP_E_REGS_HPP */ -- cgit v1.2.3 From 3e01c94fe0c690293f13a09666deb79fcb6af58c Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 1 Apr 2010 12:44:55 +0000 Subject: Spi word length is in bits, not bytes. --- host/apps/omap_debug/usrp-e-spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/host/apps/omap_debug/usrp-e-spi.c b/host/apps/omap_debug/usrp-e-spi.c index 1af47b172..f7131bbe3 100644 --- a/host/apps/omap_debug/usrp-e-spi.c +++ b/host/apps/omap_debug/usrp-e-spi.c @@ -26,7 +26,7 @@ int main(int argc, char *argv[]) spi_dat.slave = slave; spi_dat.data = data; - spi_dat.length = 2; + spi_dat.length = 32; spi_dat.flags = 0; if (*argv[1] == 'r') { -- cgit v1.2.3 From 9b30d7293f93ec340c23448147c425c398c01db4 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 1 Apr 2010 19:27:59 +0000 Subject: Allow variable length spi messages. --- host/apps/omap_debug/usrp-e-spi.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-spi.c b/host/apps/omap_debug/usrp-e-spi.c index f7131bbe3..de1409647 100644 --- a/host/apps/omap_debug/usrp-e-spi.c +++ b/host/apps/omap_debug/usrp-e-spi.c @@ -10,23 +10,24 @@ int main(int argc, char *argv[]) { - int fp, slave, data, ret; + int fp, slave, length, data, ret; struct usrp_e_spi spi_dat; - if (argc < 4) { - printf("Usage: usrp_e_spi w|rb slave data\n"); + if (argc < 5) { + printf("Usage: usrp_e_spi w|rb slave transfer_length data\n"); exit(-1); } slave = atoi(argv[2]); - data = atoi(argv[3]); + length = atoi(argv[3]); + data = atoi(argv[4]); fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); spi_dat.slave = slave; spi_dat.data = data; - spi_dat.length = 32; + spi_dat.length = length; spi_dat.flags = 0; if (*argv[1] == 'r') { -- cgit v1.2.3 From 38233271a2d2ab84adfc5cc8c9700601933b717a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 1 Apr 2010 16:55:44 -0700 Subject: preliminary registers definition --- .gitignore | 1 + host/lib/usrp/usrp_e/usrp_e_regs.hpp | 131 +++++++++++++++++++++++++---------- 2 files changed, 95 insertions(+), 37 deletions(-) create mode 100644 .gitignore diff --git a/.gitignore b/.gitignore new file mode 100644 index 000000000..b25c15b81 --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +*~ diff --git a/host/lib/usrp/usrp_e/usrp_e_regs.hpp b/host/lib/usrp/usrp_e/usrp_e_regs.hpp index 219f459a5..edd87e649 100644 --- a/host/lib/usrp/usrp_e/usrp_e_regs.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_regs.hpp @@ -1,49 +1,106 @@ + + +//////////////////////////////////////////////////////////////// // -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . +// Memory map for embedded wishbone bus // +//////////////////////////////////////////////////////////////// + +// All addresses are byte addresses. All accesses are word (16-bit) accesses. +// This means that address bit 0 is usually 0. +// There are 11 bits of address for the control. + +#ifndef __USRP_E_REGS_H +#define __USRP_E_REGS_H + +///////////////////////////////////////////////////// +// Slave pointers + +#define UE_REG_SLAVE(n) ((n)<<7) + +///////////////////////////////////////////////////// +// Slave 0 -- Misc Regs + +#define UE_REG_MISC_BASE UE_REG_SLAVE(0) + +#define UE_REG_MISC_LED UE_REG_MISC_BASE + 0 +#define UE_REG_MISC_SW UE_REG_MISC_BASE + 2 +#define UE_REG_MISC_CGEN_CTRL UE_REG_MISC_BASE + 4 +#define UE_REG_MISC_CGEN_ST UE_REG_MISC_BASE + 6 +#define UE_REG_MISC_TEST UE_REG_MISC_BASE + 8 + +///////////////////////////////////////////////////// +// Slave 1 -- UART +// CLKDIV is 16 bits, others are only 8 + +#define UE_REG_UART_BASE UE_REG_SLAVE(1) -#ifndef INCLUDED_USRP_E_REGS_HPP -#define INCLUDED_USRP_E_REGS_HPP +#define UE_REG_UART_CLKDIV UE_REG_UART_BASE + 0 +#define UE_REG_UART_TXLEVEL UE_REG_UART_BASE + 2 +#define UE_REG_UART_RXLEVEL UE_REG_UART_BASE + 4 +#define UE_REG_UART_TXCHAR UE_REG_UART_BASE + 6 +#define UE_REG_UART_RXCHAR UE_REG_UART_BASE + 8 + +///////////////////////////////////////////////////// +// Slave 2 -- SPI Core +// This should be accessed through the IOCTL +// Users should not touch directly + +#define UE_REG_SPI_BASE UE_REG_SLAVE(2) -#include //////////////////////////////////////////////// -// GPIO, Slave 4 -// -// These go to the daughterboard i/o pins +// Slave 3 -- I2C Core +// This should be accessed through the IOCTL +// Users should not touch directly + +#define UE_REG_I2C_BASE UE_REG_SLAVE(3) + + +//////////////////////////////////////////////// +// Slave 4 -- GPIO -#define GPIO_BASE 0x40 +#define UE_REG_GPIO_BASE UE_REG_SLAVE(4) -struct gpio_regs_t{ - boost::uint16_t rx_io; // tx data in high 16, rx in low 16 - boost::uint16_t tx_io; - boost::uint16_t rx_ddr; // 32 bits, 1 means output. tx in high 16, rx in low 16 - boost::uint16_t tx_ddr; - boost::uint16_t tx_sel_low; // 16 2-bit fields select which source goes to TX DB - boost::uint16_t tx_sel_high; - boost::uint16_t rx_sel_low; // 16 2-bit fields select which source goes to RX DB - boost::uint16_t rx_sel_high; -}; +#define UE_REG_GPIO_RX_IO UE_REG_GPIO_BASE + 0 +#define UE_REG_GPIO_TX_IO UE_REG_GPIO_BASE + 2 +#define UE_REG_GPIO_RX_DDR UE_REG_GPIO_BASE + 4 +#define UE_REG_GPIO_TX_DDR UE_REG_GPIO_BASE + 6 +#define UE_REG_GPIO_RX_SEL UE_REG_GPIO_BASE + 8 +#define UE_REG_GPIO_TX_SEL UE_REG_GPIO_BASE + 10 +#define UE_REG_GPIO_RX_DBG UE_REG_GPIO_BASE + 12 +#define UE_REG_GPIO_TX_DBG UE_REG_GPIO_BASE + 14 // each 2-bit sel field is layed out this way -#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg -#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic -#define GPIO_SEL_DEBUG_0 2 // if pin is an output, debug lines from FPGA fabric -#define GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from FPGA fabric +#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg +#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic +#define GPIO_SEL_DEBUG_0 0 // if pin is an output, debug lines from FPGA fabric +#define GPIO_SEL_DEBUG_1 1 // if pin is an output, debug lines from FPGA fabric + + +//////////////////////////////////////////////////// +// Slave 5 -- Settings Bus +// +// Output-only, no readback, 32 registers total +// Each register must be written 32 bits at a time +// First the address xxx_xx00 and then xxx_xx10 + +#define UE_REG_SETTINGS_BASE UE_REG_SLAVE(5) + +/////////////////////////////////////////////////// +// Slave 6 -- ATR Controller +// 16 regs + +#define UE_REG_ATR_BASE UE_REG_SLAVE(6) + +#define UE_REG_ATR_IDLE_RXSIDE UE_REG_ATR_BASE + 0 +#define UE_REG_ATR_IDLE_TXSIDE UE_REG_ATR_BASE + 2 +#define UE_REG_ATR_INTX_RXSIDE UE_REG_ATR_BASE + 4 +#define UE_REG_ATR_INTX_TXSIDE UE_REG_ATR_BASE + 6 +#define UE_REG_ATR_INRX_RXSIDE UE_REG_ATR_BASE + 8 +#define UE_REG_ATR_INRX_TXSIDE UE_REG_ATR_BASE + 10 +#define UE_REG_ATR_FULL_RXSIDE UE_REG_ATR_BASE + 12 +#define UE_REG_ATR_FULL_TXSIDE UE_REG_ATR_BASE + 14 -//#define gpio_base ((gpio_regs_t *) GPIO_BASE) +#endif -#endif /* INCLUDED_USRP_E_REGS_HPP */ -- cgit v1.2.3 From bcd80dae09776eddaf4fdf9c6fb925c0b2586a11 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 1 Apr 2010 17:32:43 +0000 Subject: added peek and poke, using in dboard interface --- host/lib/usrp/usrp_e/dboard_interface.cpp | 106 +++++++++--------------------- host/lib/usrp/usrp_e/mboard_impl.cpp | 2 +- host/lib/usrp/usrp_e/usrp_e_impl.cpp | 48 ++++++++++++++ host/lib/usrp/usrp_e/usrp_e_impl.hpp | 6 ++ 4 files changed, 85 insertions(+), 77 deletions(-) diff --git a/host/lib/usrp/usrp_e/dboard_interface.cpp b/host/lib/usrp/usrp_e/dboard_interface.cpp index a343d93b8..47948f3d0 100644 --- a/host/lib/usrp/usrp_e/dboard_interface.cpp +++ b/host/lib/usrp/usrp_e/dboard_interface.cpp @@ -22,7 +22,6 @@ #include #include //std::copy #include -#include using namespace uhd::usrp; @@ -34,9 +33,8 @@ public: void write_aux_dac(unit_type_t, int, int); int read_aux_adc(unit_type_t, int); - void set_atr_reg(gpio_bank_t, boost::uint16_t, boost::uint16_t, boost::uint16_t); + void set_atr_reg(gpio_bank_t, atr_reg_t, boost::uint16_t); void set_gpio_ddr(gpio_bank_t, boost::uint16_t); - void write_gpio(gpio_bank_t, boost::uint16_t); boost::uint16_t read_gpio(gpio_bank_t); void write_i2c(int, const byte_vector_t &); @@ -48,8 +46,7 @@ public: private: byte_vector_t transact_spi( spi_dev_t dev, - spi_latch_t latch, - spi_push_t push, + spi_edge_t edge, const byte_vector_t &buf, bool readback ); @@ -92,82 +89,40 @@ double usrp_e_dboard_interface::get_tx_clock_rate(void){ void usrp_e_dboard_interface::set_gpio_ddr(gpio_bank_t bank, boost::uint16_t value){ //define mapping of gpio bank to register address static const uhd::dict bank_to_addr = boost::assign::map_list_of - (GPIO_RX_BANK, GPIO_BASE + offsetof(gpio_regs_t, rx_ddr)) - (GPIO_TX_BANK, GPIO_BASE + offsetof(gpio_regs_t, tx_ddr)) + (GPIO_BANK_RX, UE_REG_GPIO_RX_DDR) + (GPIO_BANK_TX, UE_REG_GPIO_TX_DDR) ; - - //load the data struct - usrp_e_ctl16 data; - data.offset = bank_to_addr[bank]; - data.count = 1; - data.buf[0] = value; - - //call the ioctl - _impl->ioctl(USRP_E_WRITE_CTL16, &data); -} - -void usrp_e_dboard_interface::write_gpio(gpio_bank_t bank, boost::uint16_t value){ - //define mapping of gpio bank to register address - static const uhd::dict bank_to_addr = boost::assign::map_list_of - (GPIO_RX_BANK, GPIO_BASE + offsetof(gpio_regs_t, rx_io)) - (GPIO_TX_BANK, GPIO_BASE + offsetof(gpio_regs_t, tx_io)) - ; - - //load the data struct - usrp_e_ctl16 data; - data.offset = bank_to_addr[bank]; - data.count = 1; - data.buf[0] = value; - - //call the ioctl - _impl->ioctl(USRP_E_WRITE_CTL16, &data); + _impl->poke16(bank_to_addr[bank], value); } boost::uint16_t usrp_e_dboard_interface::read_gpio(gpio_bank_t bank){ //define mapping of gpio bank to register address static const uhd::dict bank_to_addr = boost::assign::map_list_of - (GPIO_RX_BANK, GPIO_BASE + offsetof(gpio_regs_t, rx_io)) - (GPIO_TX_BANK, GPIO_BASE + offsetof(gpio_regs_t, tx_io)) + (GPIO_BANK_RX, UE_REG_GPIO_RX_IO) + (GPIO_BANK_TX, UE_REG_GPIO_TX_IO) ; - - //load the data struct - usrp_e_ctl16 data; - data.offset = bank_to_addr[bank]; - data.count = 1; - - //call the ioctl - _impl->ioctl(USRP_E_READ_CTL16, &data); - - return data.buf[0]; + return _impl->peek16(bank_to_addr[bank]); } -void usrp_e_dboard_interface::set_atr_reg(gpio_bank_t bank, boost::uint16_t tx_value, boost::uint16_t rx_value, boost::uint16_t mask){ - //define mapping of gpio bank to register address - static const uhd::dict bank_to_addr = boost::assign::map_list_of - (GPIO_RX_BANK, GPIO_BASE + offsetof(gpio_regs_t, rx_sel_low)) - (GPIO_TX_BANK, GPIO_BASE + offsetof(gpio_regs_t, tx_sel_low)) +void usrp_e_dboard_interface::set_atr_reg(gpio_bank_t bank, atr_reg_t atr, boost::uint16_t value){ + //define mapping of bank to atr regs to register address + static const uhd::dict< + gpio_bank_t, uhd::dict + > bank_to_atr_to_addr = boost::assign::map_list_of + (GPIO_BANK_RX, boost::assign::map_list_of + (ATR_REG_IDLE, UE_REG_ATR_IDLE_RXSIDE) + (ATR_REG_TX_ONLY, UE_REG_ATR_INTX_RXSIDE) + (ATR_REG_RX_ONLY, UE_REG_ATR_INRX_RXSIDE) + (ATR_REG_FULL_DUPLEX, UE_REG_ATR_FULL_RXSIDE) + ) + (GPIO_BANK_TX, boost::assign::map_list_of + (ATR_REG_IDLE, UE_REG_ATR_IDLE_TXSIDE) + (ATR_REG_TX_ONLY, UE_REG_ATR_INTX_TXSIDE) + (ATR_REG_RX_ONLY, UE_REG_ATR_INRX_TXSIDE) + (ATR_REG_FULL_DUPLEX, UE_REG_ATR_FULL_TXSIDE) + ) ; - - //set the gpio selection mux to atr or software controlled - boost::uint16_t low_sel = 0, high_sel = 0; - for(size_t i = 0; i < 16; i++){ - boost::uint16_t code = (mask & (1 << i))? GPIO_SEL_ATR : GPIO_SEL_SW; - if(i < 8) low_sel |= code << (2*i-0); - else high_sel |= code << (2*i-8); - } - - //load the data struct - usrp_e_ctl16 data; - data.offset = bank_to_addr[bank]; - data.count = 2; - data.buf[0] = low_sel; - data.buf[1] = high_sel; - - //call the ioctl - _impl->ioctl(USRP_E_READ_CTL16, &data); - - //----------------------------------------> TODO - //TODO set the atr regs + _impl->poke16(bank_to_atr_to_addr[bank][atr], value); } /*********************************************************************** @@ -175,15 +130,14 @@ void usrp_e_dboard_interface::set_atr_reg(gpio_bank_t bank, boost::uint16_t tx_v **********************************************************************/ dboard_interface::byte_vector_t usrp_e_dboard_interface::transact_spi( spi_dev_t dev, - spi_latch_t latch, - spi_push_t push, + spi_edge_t edge, const byte_vector_t &buf, bool readback ){ //load data struct usrp_e_spi data; data.readback = (readback)? UE_SPI_TXRX : UE_SPI_TXONLY; - data.slave = (dev == SPI_RX_DEV)? UE_SPI_CTRL_RXNEG : UE_SPI_CTRL_TXNEG; + data.slave = (dev == SPI_DEV_RX)? UE_SPI_CTRL_RXNEG : UE_SPI_CTRL_TXNEG; data.length = buf.size() * 8; //bytes to bits boost::uint8_t *data_bytes = reinterpret_cast(&data.data); @@ -193,8 +147,8 @@ dboard_interface::byte_vector_t usrp_e_dboard_interface::transact_spi( //load the flags data.flags = 0; - data.flags |= (latch == SPI_LATCH_RISE)? UE_SPI_LATCH_RISE : UE_SPI_LATCH_FALL; - data.flags |= (push == SPI_PUSH_RISE)? UE_SPI_PUSH_RISE : UE_SPI_PUSH_FALL; + data.flags |= (edge == SPI_EDGE_RISE)? UE_SPI_LATCH_RISE : UE_SPI_LATCH_FALL; + data.flags |= (edge == SPI_EDGE_RISE)? UE_SPI_PUSH_RISE : UE_SPI_PUSH_FALL; //call the spi ioctl _impl->ioctl(USRP_E_SPI, &data); diff --git a/host/lib/usrp/usrp_e/mboard_impl.cpp b/host/lib/usrp/usrp_e/mboard_impl.cpp index 1d3f9f466..ba15c394d 100644 --- a/host/lib/usrp/usrp_e/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e/mboard_impl.cpp @@ -17,7 +17,7 @@ #include "usrp_e_impl.hpp" #include -#include +#include #include using namespace uhd; diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.cpp b/host/lib/usrp/usrp_e/usrp_e_impl.cpp index e821add8c..3fefd6787 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.cpp @@ -16,12 +16,14 @@ // #include "usrp_e_impl.hpp" +#include #include #include #include #include #include //open #include //ioctl +#include using namespace uhd; using namespace uhd::usrp; @@ -113,6 +115,52 @@ void usrp_e_impl::ioctl(int request, void *mem){ } } +void usrp_e_impl::poke32(boost::uint32_t addr, boost::uint32_t value){ + //load the data struct + usrp_e_ctl32 data; + data.offset = addr; + data.count = 1; + data.buf[0] = value; + + //call the ioctl + this->ioctl(USRP_E_WRITE_CTL32, &data); +} + +void usrp_e_impl::poke16(boost::uint32_t addr, boost::uint16_t value){ + //load the data struct + usrp_e_ctl16 data; + data.offset = addr; + data.count = 1; + data.buf[0] = value; + + //call the ioctl + this->ioctl(USRP_E_WRITE_CTL16, &data); +} + +boost::uint32_t usrp_e_impl::peek32(boost::uint32_t addr){ + //load the data struct + usrp_e_ctl32 data; + data.offset = addr; + data.count = 1; + + //call the ioctl + this->ioctl(USRP_E_READ_CTL32, &data); + + return data.buf[0]; +} + +boost::uint16_t usrp_e_impl::peek16(boost::uint32_t addr){ + //load the data struct + usrp_e_ctl16 data; + data.offset = addr; + data.count = 1; + + //call the ioctl + this->ioctl(USRP_E_READ_CTL16, &data); + + return data.buf[0]; +} + /*********************************************************************** * Device Get **********************************************************************/ diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index 643589754..21023ae55 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -92,6 +92,12 @@ public: */ void ioctl(int request, void *mem); + //peekers and pokers + void poke32(boost::uint32_t addr, boost::uint32_t value); + void poke16(boost::uint32_t addr, boost::uint16_t value); + boost::uint32_t peek32(boost::uint32_t addr); + boost::uint16_t peek16(boost::uint32_t addr); + private: static const size_t _max_num_samples = 2048/sizeof(boost::uint32_t); int _node_fd; -- cgit v1.2.3 From 52c8d239ac4b2c448a15b7cc2e2cadf6f296c3e0 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 1 Apr 2010 17:05:50 -0700 Subject: added 16-bit wide atr controller settings_bus_16 now handles variable address window sizes split ctrl of nsgpio into ctrl (selector) and debug bits --- usrp2/control_lib/atr_controller16.v | 60 ++++++++++++++++++++++++++++ usrp2/control_lib/nsgpio16LE.v | 23 +++++------ usrp2/control_lib/settings_bus_16LE.v | 4 +- usrp2/top/u1e/Makefile | 2 +- usrp2/top/u1e/u1e_core.v | 75 ++++++++++++++++++++--------------- 5 files changed, 117 insertions(+), 47 deletions(-) create mode 100644 usrp2/control_lib/atr_controller16.v diff --git a/usrp2/control_lib/atr_controller16.v b/usrp2/control_lib/atr_controller16.v new file mode 100644 index 000000000..3d8b5b1e9 --- /dev/null +++ b/usrp2/control_lib/atr_controller16.v @@ -0,0 +1,60 @@ + +// Automatic transmit/receive switching of control pins to daughterboards +// Store everything in registers for now, but could use a RAM for more +// complex state machines in the future + +module atr_controller16 + (input clk_i, input rst_i, + input [5:0] adr_i, input [1:0] sel_i, input [15:0] dat_i, output reg [15:0] dat_o, + input we_i, input stb_i, input cyc_i, output reg ack_o, + input run_rx, input run_tx, input [31:0] master_time, + output [31:0] ctrl_lines); + + reg [3:0] state; + reg [31:0] atr_ram [0:15]; // DP distributed RAM + + wire [3:0] sel_int = { (sel_i[1] & adr_i[1]), (sel_i[0] & adr_i[1]), + (sel_i[1] & ~adr_i[1]), (sel_i[0] & ~adr_i[1]) }; + + // WB Interface + always @(posedge clk_i) + if(we_i & stb_i & cyc_i) + begin + if(sel_int[3]) + atr_ram[adr_i[5:2]][31:24] <= dat_i[15:8]; + if(sel_int[2]) + atr_ram[adr_i[5:2]][23:16] <= dat_i[7:0]; + if(sel_int[1]) + atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8]; + if(sel_int[0]) + atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0]; + end // if (we_i & stb_i & cyc_i) + + always @(posedge clk_i) + dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0]; + + always @(posedge clk_i) + ack_o <= stb_i & cyc_i & ~ack_o; + + // Control side of DP RAM + assign ctrl_lines = atr_ram[state]; + + // Put a more complex state machine with time delays and multiple states here + // if daughterboard requires more complex sequencing + localparam ATR_IDLE = 4'd0; + localparam ATR_TX = 4'd1; + localparam ATR_RX = 4'd2; + localparam ATR_FULL_DUPLEX = 4'd3; + + always @(posedge clk_i) + if(rst_i) + state <= ATR_IDLE; + else + case ({run_rx,run_tx}) + 2'b00 : state <= ATR_IDLE; + 2'b01 : state <= ATR_TX; + 2'b10 : state <= ATR_RX; + 2'b11 : state <= ATR_FULL_DUPLEX; + endcase // case({run_rx,run_tx}) + +endmodule // atr_controller16 diff --git a/usrp2/control_lib/nsgpio16LE.v b/usrp2/control_lib/nsgpio16LE.v index 6847bb4a9..d6d7dcf56 100644 --- a/usrp2/control_lib/nsgpio16LE.v +++ b/usrp2/control_lib/nsgpio16LE.v @@ -43,10 +43,7 @@ module nsgpio16LE inout [31:0] gpio ); - reg [63:0] ctrl; - reg [31:0] line; - reg [31:0] lgpio; // LatchedGPIO pins - reg [31:0] ddr; + reg [31:0] ctrl, line, ddr, dbg, lgpio; wire wb_acc = cyc_i & stb_i; // WISHBONE access wire wb_wr = wb_acc & we_i; // WISHBONE write access @@ -54,8 +51,10 @@ module nsgpio16LE always @(posedge clk_i or posedge rst_i) if (rst_i) begin - ctrl <= 64'h0; - line <= 0; + ctrl <= 32'h0; + line <= 32'h0; + ddr <= 32'h0; + dbg <= 32'h0; end else if (wb_wr) case( adr_i[3:1] ) @@ -72,9 +71,9 @@ module nsgpio16LE 3'b101 : ctrl[31:16] <= dat_i; 3'b110 : - ctrl[47:32] <= dat_i; + dbg[15:0] <= dat_i; 3'b111 : - ctrl[63:48] <= dat_i; + dbg[31:16] <= dat_i; endcase // case ( adr_i[3:1] ) always @(posedge clk_i) @@ -92,9 +91,9 @@ module nsgpio16LE 3'b101 : dat_o <= ctrl[31:16]; 3'b110 : - dat_o <= ctrl[47:32]; + dat_o <= dbg[15:0]; 3'b111 : - dat_o <= ctrl[63:48]; + dat_o <= dbg[31:16]; endcase // case (adr_i[3:1]) @@ -114,8 +113,8 @@ module nsgpio16LE always @(ctrl or line or debug_1 or debug_0 or atr) for(n=0;n<32;n=n+1) - igpio[n] <= ddr[n] ? (ctrl[2*n+1] ? (ctrl[2*n] ? debug_1[n] : debug_0[n]) : - (ctrl[2*n] ? atr[n] : line[n]) ) + igpio[n] <= ddr[n] ? (dbg[n] ? (ctrl[n] ? debug_1[n] : debug_0[n]) : + (ctrl[n] ? atr[n] : line[n]) ) : 1'bz; assign gpio = igpio; diff --git a/usrp2/control_lib/settings_bus_16LE.v b/usrp2/control_lib/settings_bus_16LE.v index fbef9b1c9..76061e9e0 100644 --- a/usrp2/control_lib/settings_bus_16LE.v +++ b/usrp2/control_lib/settings_bus_16LE.v @@ -5,7 +5,7 @@ // The setting regs are strobed when the high 16 bits are written module settings_bus_16LE - #(parameter AWIDTH=16) + #(parameter AWIDTH=16, RWIDTH=8) (input wb_clk, input wb_rst, input [AWIDTH-1:0] wb_adr_i, @@ -28,7 +28,7 @@ module settings_bus_16LE end else if(wb_we_i & wb_stb_i) begin - addr <= wb_adr_i[9:2]; + addr <= wb_adr_i[RWIDTH+1:2]; // Zero pad high bits if(wb_adr_i[1]) begin stb_int <= 1'b1; // We now have both halves diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 2b78b21bd..a0f921485 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -54,7 +54,7 @@ simulator "ISE Simulator (VHDL/Verilog)" \ export SOURCE_ROOT := ../../../ export SOURCES := \ control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ +control_lib/atr_controller16.v \ control_lib/bin2gray.v \ control_lib/dcache.v \ control_lib/decoder_3_8.v \ diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index f2415d7e1..e692cbc3d 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -147,48 +147,52 @@ module u1e_core .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); - assign s6_ack = 0; assign s7_ack = 0; + assign s7_ack = 0; assign s8_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; // ///////////////////////////////////////////////////////////////////////////////////// // Slave 0, Misc LEDs, Switches, controls - reg [15:0] reg_fast, reg_slow; - localparam REG_FAST = 7'd4; - localparam REG_SWITCHES = 7'd6; - localparam REG_GPIOS = 7'd8; - localparam REG_CGEN_ST = 7'd9; - localparam REG_CGEN_CTRL = 7'd10; + reg [15:0] reg_leds, reg_cgen_ctrl, reg_test; - reg [3:0] reg_gpios; - - always @(posedge wb_clk) - if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_FAST)) - reg_fast <= s0_dat_mosi; - - always @(posedge wb_clk) - if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_GPIOS)) - reg_gpios <= s0_dat_mosi; - - reg [1:0] reg_cgen_ctrls; + localparam REG_LEDS = 7'd0; // out + localparam REG_SWITCHES = 7'd2; // in + localparam REG_CGEN_CTRL = 7'd4; // out + localparam REG_CGEN_ST = 7'd6; // in + localparam REG_TEST = 7'd8; // out always @(posedge wb_clk) if(wb_rst) - reg_cgen_ctrls <= 2'b11; - else if(s0_cyc & s0_stb & s0_we & (s0_adr[6:0] == REG_CGEN_CTRL)) - reg_cgen_ctrls <= s0_dat_mosi; + begin + reg_leds <= 0; + reg_cgen_ctrl <= 2'b11; + reg_test <= 0; + end + else + if(s0_cyc & s0_stb & s0_we) + case(s0_adr[6:0]) + REG_LEDS : + reg_leds <= s0_dat_mosi; + REG_CGEN_CTRL : + reg_cgen_ctrl <= s0_dat_mosi; + REG_TEST : + reg_test <= s0_dat_mosi; + endcase // case (s0_adr[6:0]) - assign {cgen_sync_b, cgen_ref_sel} = reg_cgen_ctrls; + assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board + assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; + assign { rx_overrun, tx_undderun } = reg_test; - assign s0_dat_miso = (s0_adr[6:0] == REG_FAST) ? reg_fast : + assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : + (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : + (s0_adr[6:0] == REG_TEST) ? reg_test : 16'hBEEF; + assign s0_ack = s0_stb & s0_cyc; - assign { rx_overrun, tx_underrun } = reg_gpios; - // ///////////////////////////////////////////////////////////////////////////////////// // Slave 1, UART // depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock @@ -196,7 +200,7 @@ module u1e_core simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart (.clk_i(wb_clk),.rst_i(wb_rst), .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack), - .adr_i(s1_adr[4:2]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso), + .adr_i(s1_adr[3:1]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso), .rx_int_o(),.tx_int_o(), .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o()); @@ -246,16 +250,25 @@ module u1e_core wire [7:0] set_addr; wire [31:0] set_data; wire set_stb; - - settings_bus_16LE settings_bus_16LE + + // only have 32 regs, 32 bits each with current setup... + settings_bus_16LE #(.AWIDTH(11),.RWIDTH(11-4-2)) settings_bus_16LE (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s5_adr),.wb_dat_i(s5_dat_mosi), .wb_stb_i(s5_stb),.wb_we_i(s5_we),.wb_ack_o(s5_ack), .strobe(set_stb),.addr(set_addr),.data(set_data) ); - // ///////////////////////////////////////////////////////////////////////////////////// - // Debug Pins + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller -- Slave #6 + + atr_controller16 atr_controller16 + (.clk_i(wb_clk), .rst_i(wb_rst), + .adr_i(s6_adr), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), + .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), + .run_rx(), .run_tx(), .master_time(0), .ctrl_lines(atr_lines)); + // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry + assign debug_clk = { EM_CLK, clk_fpga }; assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, { EM_D } }; @@ -263,6 +276,4 @@ module u1e_core assign debug_gpio_0 = { debug_gpmc }; assign debug_gpio_1 = { debug_txd, debug_rxd }; - assign { debug_led[2],debug_led[0],debug_led[1] } = reg_fast; // LEDs are arranged funny on board - endmodule // u1e_core -- cgit v1.2.3 From 80b2b928df6e3c1caf68dee199593a0af1cb91ae Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Fri, 2 Apr 2010 12:33:37 +0000 Subject: Handle 32 bit data to spi controller. --- host/apps/omap_debug/usrp-e-spi.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-spi.c b/host/apps/omap_debug/usrp-e-spi.c index de1409647..f693d7db1 100644 --- a/host/apps/omap_debug/usrp-e-spi.c +++ b/host/apps/omap_debug/usrp-e-spi.c @@ -10,7 +10,8 @@ int main(int argc, char *argv[]) { - int fp, slave, length, data, ret; + int fp, slave, length, ret; + unsigned int data; struct usrp_e_spi spi_dat; if (argc < 5) { @@ -20,7 +21,9 @@ int main(int argc, char *argv[]) slave = atoi(argv[2]); length = atoi(argv[3]); - data = atoi(argv[4]); + data = atoll(argv[4]); + + printf("Data = %X\n", data); fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); -- cgit v1.2.3 From d8052db8e5614935241a4824a3f9711bfe34507d Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Fri, 2 Apr 2010 19:49:45 +0000 Subject: Convert to use register include file. Fix peek/poke16 program. Add program to cycle through LED's and test buttons. Only pushbuttons tested at the moment. --- host/apps/omap_debug/Makefile | 14 +++++++-- host/apps/omap_debug/usrp-e-button.c | 56 +++++++++++++++++++++++++++++++++++ host/apps/omap_debug/usrp-e-ctl.c | 20 ++++++------- host/apps/omap_debug/usrp-e-led.c | 35 ++++++++++++++++++++++ host/apps/omap_debug/usrp-e-uart | Bin 0 -> 7143 bytes 5 files changed, 112 insertions(+), 13 deletions(-) create mode 100644 host/apps/omap_debug/usrp-e-button.c create mode 100644 host/apps/omap_debug/usrp-e-led.c create mode 100755 host/apps/omap_debug/usrp-e-uart diff --git a/host/apps/omap_debug/Makefile b/host/apps/omap_debug/Makefile index 13b834e28..f292379f4 100644 --- a/host/apps/omap_debug/Makefile +++ b/host/apps/omap_debug/Makefile @@ -1,6 +1,6 @@ -CFLAGS=-Wall +CFLAGS=-Wall -I../../lib/usrp/usrp_e/ -all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart +all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-spi : usrp-e-spi.c @@ -11,9 +11,17 @@ usrp-e-rw : usrp-e-rw.c usrp-e-uart : usrp-e-uart.c +usrp-e-led : usrp-e-led.c + +usrp-e-ctl : usrp-e-ctl.c + +usrp-e-button : usrp-e-button.c + clean : rm -f usrp-e-spi rm -f usrp-e-i2c rm -f usrp-e-rw rm -f usrp-e-uart - + rm -f usrp-e-led + rm -f usrp-e-ctl + rm -f usrp-e-button diff --git a/host/apps/omap_debug/usrp-e-button.c b/host/apps/omap_debug/usrp-e-button.c new file mode 100644 index 000000000..fca501833 --- /dev/null +++ b/host/apps/omap_debug/usrp-e-button.c @@ -0,0 +1,56 @@ +#include +#include +#include +#include +#include +#include +#include + +#include "usrp_e.h" +#include "usrp_e_regs.hpp" + +// Usage: usrp_e_uart + +#define PB1 (1<<8) +#define PB2 (1<<9) +#define PB3 (1<<10) +#define P1 (0) +#define P2 (0xFF) +#define P3 (0xAA) +#define P4 (0x55) + +int main(int argc, char *argv[]) +{ + int fp, ret; + struct usrp_e_ctl16 d; + int pb1=0, pb2=0, pb3=0, p1=0, p2=0, p3=0, p4=0; + + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); + + d.offset = 6; + d.count = 1; + + do { + ret = ioctl(fp, USRP_E_READ_CTL16, &d); + if (d.buf[0] & PB1) { + pb1 = 1; + printf("Pushbutton 1 hit\n"); + } + + if (d.buf[0] & PB2) { + pb2 = 1; + printf("Pushbutton 2 hit\n"); + } + + if (d.buf[0] & PB3) { + pb3 = 1; + printf("Pushbutton 3 hit\n"); + } + + sleep(1); + + } while (!(pb1 && pb2 && pb3)); + + return 0; +} diff --git a/host/apps/omap_debug/usrp-e-ctl.c b/host/apps/omap_debug/usrp-e-ctl.c index 045e7ce19..501a4870e 100644 --- a/host/apps/omap_debug/usrp-e-ctl.c +++ b/host/apps/omap_debug/usrp-e-ctl.c @@ -2,44 +2,44 @@ #include #include #include -#include +#include -#include "usrp1_e.h" +#include "usrp_e.h" -// Usage: usrp1_e_ctl w|r offset number_of_values val1 val2 .... +// Usage: usrp_e_ctl w|r offset number_of_values val1 val2 .... int main(int argc, char *argv[]) { int fp, i, cnt, ret; - struct usrp1_e_ctl *ctl_data; + struct usrp_e_ctl16 *ctl_data; if (argc < 4) { - printf("Usage: usrp1_e_ctl w|r offset number_of_values val1 val2 ....\n"); + printf("Usage: usrp_e_ctl w|r offset number_of_values val1 val2 ....\n"); exit(-1); } cnt = atoi(argv[3]); - ctl_data = malloc(sizeof(struct usrp1_e_ctl) + cnt*2); + ctl_data = malloc(sizeof(struct usrp_e_ctl16) + cnt*2); ctl_data->offset = atoi(argv[2]); ctl_data->count = cnt; - printf("Sizeof usrp1_e_ctl struct = %d\n", sizeof(struct usrp1_e_ctl)); + printf("Sizeof usrp1_e_ctl struct = %d\n", sizeof(struct usrp_e_ctl16)); - fp = open("/dev/usrp1_e0", O_RDWR); + fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); if (*argv[1] == 'w') { for (i=0; ibuf[i] = atoi(argv[4+i]); - ret = ioctl(fp, USRP1_E_WRITE_CTL, ctl_data); + ret = ioctl(fp, USRP_E_WRITE_CTL16, ctl_data); printf("Return value from write ioctl = %d\n", ret); } if (*argv[1] == 'r') { - ret = ioctl(fp, USRP1_E_READ_CTL, ctl_data); + ret = ioctl(fp, USRP_E_READ_CTL16, ctl_data); printf("Return value from write ioctl = %d\n", ret); for (i=0; icount; i++) { diff --git a/host/apps/omap_debug/usrp-e-led.c b/host/apps/omap_debug/usrp-e-led.c new file mode 100644 index 000000000..159251c8a --- /dev/null +++ b/host/apps/omap_debug/usrp-e-led.c @@ -0,0 +1,35 @@ +#include +#include +#include +#include +#include +#include +#include + +#include "usrp_e.h" +#include "usrp_e_regs.hpp" + +// Usage: usrp_e_uart + + +int main(int argc, char *argv[]) +{ + int fp, i, ret; + struct usrp_e_ctl16 d; + + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); + + d.offset = 4; + d.count = 1; + + while (1) { + for (i=0; i<8; i++) { + d.buf[0] = i; + ret = ioctl(fp, USRP_E_WRITE_CTL16, &d); + sleep(1); + } + } + + return 0; +} diff --git a/host/apps/omap_debug/usrp-e-uart b/host/apps/omap_debug/usrp-e-uart new file mode 100755 index 000000000..5781f0db2 Binary files /dev/null and b/host/apps/omap_debug/usrp-e-uart differ -- cgit v1.2.3 From 5d7a5e66c05290c5e3957457680313a2e427af08 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Fri, 2 Apr 2010 21:16:13 +0000 Subject: Don't need to use malloc to get the correct sized struct anymore. --- host/apps/omap_debug/usrp-e-ctl.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-ctl.c b/host/apps/omap_debug/usrp-e-ctl.c index 501a4870e..69c48ee6f 100644 --- a/host/apps/omap_debug/usrp-e-ctl.c +++ b/host/apps/omap_debug/usrp-e-ctl.c @@ -11,7 +11,7 @@ int main(int argc, char *argv[]) { int fp, i, cnt, ret; - struct usrp_e_ctl16 *ctl_data; + struct usrp_e_ctl16 ctl_data; if (argc < 4) { printf("Usage: usrp_e_ctl w|r offset number_of_values val1 val2 ....\n"); @@ -20,32 +20,28 @@ int main(int argc, char *argv[]) cnt = atoi(argv[3]); - ctl_data = malloc(sizeof(struct usrp_e_ctl16) + cnt*2); - - ctl_data->offset = atoi(argv[2]); - ctl_data->count = cnt; - - printf("Sizeof usrp1_e_ctl struct = %d\n", sizeof(struct usrp_e_ctl16)); + ctl_data.offset = atoi(argv[2]); + ctl_data.count = cnt; fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); if (*argv[1] == 'w') { for (i=0; ibuf[i] = atoi(argv[4+i]); + ctl_data.buf[i] = atoi(argv[4+i]); - ret = ioctl(fp, USRP_E_WRITE_CTL16, ctl_data); + ret = ioctl(fp, USRP_E_WRITE_CTL16, &ctl_data); printf("Return value from write ioctl = %d\n", ret); } if (*argv[1] == 'r') { - ret = ioctl(fp, USRP_E_READ_CTL16, ctl_data); + ret = ioctl(fp, USRP_E_READ_CTL16, &ctl_data); printf("Return value from write ioctl = %d\n", ret); - for (i=0; icount; i++) { + for (i=0; ibuf[i]); + printf(" %5d", ctl_data.buf[i]); } printf("\n"); } -- cgit v1.2.3 From d4e9f3629021736b1330b4a9f22ee60336a53e0e Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Fri, 2 Apr 2010 21:58:55 +0000 Subject: Update to use register definitions from header file. --- host/apps/omap_debug/usrp-e-button.c | 2 +- host/apps/omap_debug/usrp-e-led.c | 2 +- host/apps/omap_debug/usrp-e-uart.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-button.c b/host/apps/omap_debug/usrp-e-button.c index fca501833..f13291491 100644 --- a/host/apps/omap_debug/usrp-e-button.c +++ b/host/apps/omap_debug/usrp-e-button.c @@ -28,7 +28,7 @@ int main(int argc, char *argv[]) fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); - d.offset = 6; + d.offset = UE_REG_MISC_SW; d.count = 1; do { diff --git a/host/apps/omap_debug/usrp-e-led.c b/host/apps/omap_debug/usrp-e-led.c index 159251c8a..d1b6c8996 100644 --- a/host/apps/omap_debug/usrp-e-led.c +++ b/host/apps/omap_debug/usrp-e-led.c @@ -20,7 +20,7 @@ int main(int argc, char *argv[]) fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); - d.offset = 4; + d.offset = UE_REG_MISC_BASE; d.count = 1; while (1) { diff --git a/host/apps/omap_debug/usrp-e-uart.c b/host/apps/omap_debug/usrp-e-uart.c index 239df9444..b0b14626a 100644 --- a/host/apps/omap_debug/usrp-e-uart.c +++ b/host/apps/omap_debug/usrp-e-uart.c @@ -6,10 +6,10 @@ #include #include "usrp_e.h" +#include "usrp_e_regs.hpp" // Usage: usrp_e_uart -#define UART_WRITE_ADDR (0x80 + 12) int main(int argc, char *argv[]) { @@ -26,7 +26,7 @@ int main(int argc, char *argv[]) printf("fp = %d\n", fp); for (i=0; i Date: Sat, 3 Apr 2010 14:54:54 +0000 Subject: Yes, I am an idiot. --- host/apps/omap_debug/usrp-e-uart | Bin 7143 -> 0 bytes 1 file changed, 0 insertions(+), 0 deletions(-) delete mode 100755 host/apps/omap_debug/usrp-e-uart diff --git a/host/apps/omap_debug/usrp-e-uart b/host/apps/omap_debug/usrp-e-uart deleted file mode 100755 index 5781f0db2..000000000 Binary files a/host/apps/omap_debug/usrp-e-uart and /dev/null differ -- cgit v1.2.3 From 317fc2d16288dcc621761a88119f279e1cfeafd6 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Sat, 3 Apr 2010 14:55:16 +0000 Subject: Add ability to change uart baud rate. (works) --- host/apps/omap_debug/usrp-e-uart.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/host/apps/omap_debug/usrp-e-uart.c b/host/apps/omap_debug/usrp-e-uart.c index b0b14626a..2956c407f 100644 --- a/host/apps/omap_debug/usrp-e-uart.c +++ b/host/apps/omap_debug/usrp-e-uart.c @@ -16,15 +16,26 @@ int main(int argc, char *argv[]) int fp, i, ret; struct usrp_e_ctl16 d; char *str = argv[1]; + __u16 clkdiv; if (argc < 2) { - printf("Usage: usrp_e_uart n"); + printf("Usage: usrp_e_uart \n"); + printf("clkdiv = 278 is 230.4k \n"); + printf("clkdiv = 556 is 115.2k \n"); exit(-1); } fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); + if (argc == 3) { + clkdiv = atoi(argv[2]); + d.offset = UE_REG_UART_CLKDIV; + d.count = 1; + d.buf[0] = clkdiv; + ret = ioctl(fp, USRP_E_WRITE_CTL16, &d); + } + for (i=0; i Date: Sat, 3 Apr 2010 15:25:37 +0000 Subject: Add program to read from serial port and print to screen. (works) --- host/apps/omap_debug/Makefile | 5 +++- host/apps/omap_debug/usrp-e-uart-rx.c | 53 +++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 host/apps/omap_debug/usrp-e-uart-rx.c diff --git a/host/apps/omap_debug/Makefile b/host/apps/omap_debug/Makefile index f292379f4..4779969de 100644 --- a/host/apps/omap_debug/Makefile +++ b/host/apps/omap_debug/Makefile @@ -1,6 +1,6 @@ CFLAGS=-Wall -I../../lib/usrp/usrp_e/ -all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button +all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx usrp-e-spi : usrp-e-spi.c @@ -11,6 +11,8 @@ usrp-e-rw : usrp-e-rw.c usrp-e-uart : usrp-e-uart.c +usrp-e-uart-rx : usrp-e-uart-rx.c + usrp-e-led : usrp-e-led.c usrp-e-ctl : usrp-e-ctl.c @@ -22,6 +24,7 @@ clean : rm -f usrp-e-i2c rm -f usrp-e-rw rm -f usrp-e-uart + rm -f usrp-e-uart-rx rm -f usrp-e-led rm -f usrp-e-ctl rm -f usrp-e-button diff --git a/host/apps/omap_debug/usrp-e-uart-rx.c b/host/apps/omap_debug/usrp-e-uart-rx.c new file mode 100644 index 000000000..24b417980 --- /dev/null +++ b/host/apps/omap_debug/usrp-e-uart-rx.c @@ -0,0 +1,53 @@ +#include +#include +#include +#include +#include +#include + +#include "usrp_e.h" +#include "usrp_e_regs.hpp" + +// Usage: usrp_e_uart + + +int main(int argc, char *argv[]) +{ + int fp, ret; + struct usrp_e_ctl16 d; + __u16 clkdiv; + + if (argc == 0) { + printf("Usage: usrp-e-uart-rx \n"); + printf("clkdiv = 278 is 230.4k \n"); + printf("clkdiv = 556 is 115.2k \n"); + exit(-1); + } + + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); + + if (argc == 2) { + clkdiv = atoi(argv[1]); + d.offset = UE_REG_UART_CLKDIV; + d.count = 1; + d.buf[0] = clkdiv; + ret = ioctl(fp, USRP_E_WRITE_CTL16, &d); + } + + while(1) { + d.offset = UE_REG_UART_RXLEVEL; + d.count = 1; + ret = ioctl(fp, USRP_E_READ_CTL16, &d); + + if (d.buf[0] > 0) { + d.offset = UE_REG_UART_RXCHAR; + d.count = 1; + ret = ioctl(fp, USRP_E_READ_CTL16, &d); + printf("%c", d.buf[0]); + fflush(stdout); + } + } + + return 0; +} -- cgit v1.2.3 From b0316af8ebc713afaddc5b6ded5c0304353a7ab6 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Sat, 3 Apr 2010 16:59:44 +0000 Subject: Attempt to make scripts run inside and outside GHQ. When at GHQ: export GHQ=1 export GHQ_USER="something that can log in to astro" --- host/apps/omap_debug/Makefile | 5 ++++- host/apps/omap_debug/fetch-bin.sh | 6 +++++- host/apps/omap_debug/fetch-kernel.sh | 5 ++++- host/apps/omap_debug/fetch-module.sh | 7 +++++-- host/apps/omap_debug/fetch-u-boot.sh | 5 ++++- 5 files changed, 22 insertions(+), 6 deletions(-) diff --git a/host/apps/omap_debug/Makefile b/host/apps/omap_debug/Makefile index 4779969de..cd95d36fc 100644 --- a/host/apps/omap_debug/Makefile +++ b/host/apps/omap_debug/Makefile @@ -1,6 +1,6 @@ CFLAGS=-Wall -I../../lib/usrp/usrp_e/ -all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx +all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-spi : usrp-e-spi.c @@ -19,6 +19,8 @@ usrp-e-ctl : usrp-e-ctl.c usrp-e-button : usrp-e-button.c +fpga-downloader : fpga-downloader.cc + clean : rm -f usrp-e-spi rm -f usrp-e-i2c @@ -28,3 +30,4 @@ clean : rm -f usrp-e-led rm -f usrp-e-ctl rm -f usrp-e-button + rm -f fpga-downloader diff --git a/host/apps/omap_debug/fetch-bin.sh b/host/apps/omap_debug/fetch-bin.sh index beff7ffcd..d1502f95c 100755 --- a/host/apps/omap_debug/fetch-bin.sh +++ b/host/apps/omap_debug/fetch-bin.sh @@ -1,2 +1,6 @@ -scp balister@astro:/workspace/usrp1-e-dev/u1e.bin . +if [ $GHQ ]; then + scp $GHQ_USER@astro:/workspace/usrp1-e-dev/u1e.bin . +else + scp -P 8822 balister@192.168.1.10:src/git/fpgapriv/usrp2/top/u1e/build/u1e.bin . +fi sync diff --git a/host/apps/omap_debug/fetch-kernel.sh b/host/apps/omap_debug/fetch-kernel.sh index 7023f5d28..f32666adf 100755 --- a/host/apps/omap_debug/fetch-kernel.sh +++ b/host/apps/omap_debug/fetch-kernel.sh @@ -1,3 +1,6 @@ -scp balister@192.168.1.167:src/git/kernel_usrp/arch/arm/boot/uImage /media/mmcblk0p1/uImage +if [ $GHQ]; then + scp $GHQ_USER@astro:/workspace/usrp1-e-dev/kernel_usrp/arch/arm/boot/uImage /media/mmcblk0p1/uImage +else + scp balister@192.168.1.167:src/git/kernel_usrp/arch/arm/boot/uImage /media/mmcblk0p1/uImage sync diff --git a/host/apps/omap_debug/fetch-module.sh b/host/apps/omap_debug/fetch-module.sh index 45cf1f052..52fbd4040 100755 --- a/host/apps/omap_debug/fetch-module.sh +++ b/host/apps/omap_debug/fetch-module.sh @@ -1,3 +1,6 @@ -scp balister@192.168.1.167:src/git/kernel_usrp/drivers/misc/usrp_e.ko /lib/modules/2.6.33-rc3/kernel/drivers/misc -scp balister@192.168.1.167:src/git/kernel_usrp/include/linux/usrp_e.h . +if [ $GHQ ]; then + scp $GHQ_USER@astro:/workspace/usrp1-e-dev/kernel_usrp/drivers/misc/usrp_e.ko /lib/modules/2.6.33-rc3/kernel/drivers/misc +else + scp balister@192.168.1.167:src/git/kernel_usrp/drivers/misc/usrp_e.ko /lib/modules/2.6.33-rc3/kernel/drivers/misc +fi sync diff --git a/host/apps/omap_debug/fetch-u-boot.sh b/host/apps/omap_debug/fetch-u-boot.sh index 63d4edcf2..a2a488fb2 100755 --- a/host/apps/omap_debug/fetch-u-boot.sh +++ b/host/apps/omap_debug/fetch-u-boot.sh @@ -1,3 +1,6 @@ -scp balister@astro:/workspace/usrp1-e-dev/u-boot-overo/u-boot.bin /media/mmcblk0p1/ +if [ $GHQ ]; then + scp $GHQ_USER@astro:/workspace/usrp1-e-dev/u-boot-overo/u-boot.bin /media/mmcblk0p1/ +else + scp balister@192.168.1.167:src/git/u-boot/u-boot.bin /media/mmcblk0p1/ sync -- cgit v1.2.3 From 50780640a1b9ed6abb2abebbc727ce19711fbcb4 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Fri, 9 Apr 2010 21:41:37 +0000 Subject: Test program to verify GPIO on daughterboards. For success, connect gpios on TX to corresponding ones on RX. --- host/apps/omap_debug/Makefile | 5 +- host/apps/omap_debug/set_debug_pins.py | 13 +++--- host/apps/omap_debug/usrp-e-gpio.c | 83 ++++++++++++++++++++++++++++++++++ 3 files changed, 94 insertions(+), 7 deletions(-) create mode 100644 host/apps/omap_debug/usrp-e-gpio.c diff --git a/host/apps/omap_debug/Makefile b/host/apps/omap_debug/Makefile index cd95d36fc..31229d45c 100644 --- a/host/apps/omap_debug/Makefile +++ b/host/apps/omap_debug/Makefile @@ -1,6 +1,6 @@ CFLAGS=-Wall -I../../lib/usrp/usrp_e/ -all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader +all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio usrp-e-spi : usrp-e-spi.c @@ -21,6 +21,8 @@ usrp-e-button : usrp-e-button.c fpga-downloader : fpga-downloader.cc +usrp-e-gpio : usrp-e-gpio.c + clean : rm -f usrp-e-spi rm -f usrp-e-i2c @@ -31,3 +33,4 @@ clean : rm -f usrp-e-ctl rm -f usrp-e-button rm -f fpga-downloader + rm -f usrp-e-gpio diff --git a/host/apps/omap_debug/set_debug_pins.py b/host/apps/omap_debug/set_debug_pins.py index fdd085c9e..0f9ecd7b9 100755 --- a/host/apps/omap_debug/set_debug_pins.py +++ b/host/apps/omap_debug/set_debug_pins.py @@ -3,12 +3,12 @@ import os # Memory Map -misc_base = 0 << 7 -uart_base = 1 << 7 -spi_base = 2 << 7 -i2c_base = 3 << 7 -gpio_base = 4 << 7 -settings_base = 5 << 7 +misc_base = 0 +uart_base = 1 +spi_base = 2 +i2c_base = 3 +gpio_base = 4 * 128 +settings_base = 5 # GPIO offset gpio_pins = 0 @@ -32,3 +32,4 @@ set_reg(gpio_base+gpio_ctrl_lo, 0xAAAA) set_reg(gpio_base+gpio_ctrl_lo+2, 0xAAAA) set_reg(gpio_base+gpio_ctrl_hi, 0xAAAA) set_reg(gpio_base+gpio_ctrl_hi+2, 0xAAAA) + diff --git a/host/apps/omap_debug/usrp-e-gpio.c b/host/apps/omap_debug/usrp-e-gpio.c new file mode 100644 index 000000000..adef877d3 --- /dev/null +++ b/host/apps/omap_debug/usrp-e-gpio.c @@ -0,0 +1,83 @@ +#include +#include +#include +#include +#include +#include +#include + +#include "usrp_e.h" +#include "usrp_e_regs.hpp" + +// Usage: usrp_e_gpio + +static int fp; + +static int read_reg(__u16 reg) +{ + int ret; + struct usrp_e_ctl16 d; + + d.offset = reg; + d.count = 1; + ret = ioctl(fp, USRP_E_READ_CTL16, &d); + return d.buf[0]; +} + +static void write_reg(__u16 reg, __u16 val) +{ + int ret; + struct usrp_e_ctl16 d; + + d.offset = reg; + d.count = 1; + d.buf[0] = val; + ret = ioctl(fp, USRP_E_WRITE_CTL16, &d); +} + +int main(int argc, char *argv[]) +{ + int i, test, data_in; + + test = 0; + if (argc > 1) + test = 1; + + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); + + write_reg(UE_REG_GPIO_TX_DDR, 0x0); + write_reg(UE_REG_GPIO_RX_DDR, 0xFFFF); + + for (i=0; i < 16; i++) { + write_reg(UE_REG_GPIO_RX_IO, 1 << i); + sleep(1); + if (test) { + data_in = read_reg(UE_REG_GPIO_TX_IO); + if (data_in != (1 << i)) + printf("Read failed, wrote: %X read: %X\n", \ + 1 << i, data_in); + } + } + + write_reg(UE_REG_GPIO_RX_DDR, 0x0); + write_reg(UE_REG_GPIO_TX_DDR, 0xFFFF); + + sleep(1); + + for (i=0; i < 16; i++) { + write_reg(UE_REG_GPIO_TX_IO, 1 << i); + sleep(1); + if (test) { + data_in = read_reg(UE_REG_GPIO_RX_IO); + if (data_in != (1 << i)) + printf("Read failed, wrote: %X read: %X\n", \ + 1 << i, data_in); + } + } + + write_reg(UE_REG_GPIO_RX_DDR, 0x0); + write_reg(UE_REG_GPIO_TX_DDR, 0x0); + + return 0; +} -- cgit v1.2.3 From 34854116a4fd287fe681222f2b7a881692e418d3 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 12 Apr 2010 13:54:50 +0000 Subject: put the dummy package back in --- host/lib/CMakeLists.txt | 7 +++++++ host/lib/usrp/usrp1e/usrp1e_none.cpp | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+) create mode 100644 host/lib/usrp/usrp1e/usrp1e_none.cpp diff --git a/host/lib/CMakeLists.txt b/host/lib/CMakeLists.txt index 9d328310f..a5345cae4 100644 --- a/host/lib/CMakeLists.txt +++ b/host/lib/CMakeLists.txt @@ -48,6 +48,13 @@ LIST(APPEND libuhd_sources transport/udp_zero_copy_asio.cpp ) +######################################################################## +# Conditionally add the usrp1e sources +######################################################################## +LIST(APPEND libuhd_sources + usrp/usrp1e/usrp1e_none.cpp +) + ######################################################################## # Setup defines for module loading ######################################################################## diff --git a/host/lib/usrp/usrp1e/usrp1e_none.cpp b/host/lib/usrp/usrp1e/usrp1e_none.cpp new file mode 100644 index 000000000..84fb9276c --- /dev/null +++ b/host/lib/usrp/usrp1e/usrp1e_none.cpp @@ -0,0 +1,34 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include + +using namespace uhd; +using namespace uhd::usrp; + +/*! + * This file defines the usrp1e discover and make functions + * when the required kernel module headers are not present. + */ + +device_addrs_t usrp1e::find(const device_addr_t &){ + return device_addrs_t(); //return empty list +} + +device::sptr usrp1e::make(const device_addr_t &){ + throw std::runtime_error("this build has no usrp1e support"); +} -- cgit v1.2.3 From 4aca5e04d026977272e35db4e0c1ccaac5da555f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 12 Apr 2010 19:06:04 -0700 Subject: split out gpmc to wishbone interface to make gpmc top level cleaner --- usrp2/gpmc/gpmc_wb.v | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 usrp2/gpmc/gpmc_wb.v diff --git a/usrp2/gpmc/gpmc_wb.v b/usrp2/gpmc/gpmc_wb.v new file mode 100644 index 000000000..64f6a1c00 --- /dev/null +++ b/usrp2/gpmc/gpmc_wb.v @@ -0,0 +1,57 @@ + + +module gpmc_wb + (input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_NCS, input EM_NWE, input EM_NOE, + + input wb_clk, input wb_rst, + output reg [10:0] wb_adr_o, output reg [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output reg [1:0] wb_sel_o, output wb_cyc_o, output reg wb_stb_o, output reg wb_we_o, input wb_ack_i); + + // //////////////////////////////////////////// + // Control Path, Wishbone bus bridge (wb master) + reg [1:0] cs_del, we_del, oe_del; + + // Synchronize the async control signals + always @(posedge wb_clk) + begin + cs_del <= { cs_del[0], EM_NCS }; + we_del <= { we_del[0], EM_NWE }; + oe_del <= { oe_del[0], EM_NOE }; + end + + always @(posedge wb_clk) + if(cs_del == 2'b10) // Falling Edge + wb_adr_o <= { EM_A, 1'b0 }; + + always @(posedge wb_clk) + if(we_del == 2'b10) // Falling Edge + begin + wb_dat_mosi <= EM_D; + wb_sel_o <= ~EM_NBE; + end + + reg [15:0] EM_D_hold; + + always @(posedge wb_clk) + if(wb_ack_i) + EM_D_hold <= wb_dat_miso; + + assign EM_D = wb_ack_i ? wb_dat_miso : EM_D_hold; + + assign wb_cyc_o = wb_stb_o; + + always @(posedge wb_clk) + if(~cs_del[0] & (we_del == 2'b10) ) + wb_we_o <= 1; + else if(wb_ack_i) // Turn off we when done. Could also use we_del[0], others... + wb_we_o <= 0; + + // FIXME should this look at cs_del[1]? + always @(posedge wb_clk) + if(~cs_del[0] & ((we_del == 2'b10) | (oe_del == 2'b10))) + wb_stb_o <= 1; + else if(wb_ack_i) + wb_stb_o <= 0; + +endmodule // gpmc_wb -- cgit v1.2.3 From 45b9ec4c39a2f4a3087b2f637f70818fd0efb94e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 12 Apr 2010 19:06:49 -0700 Subject: replaced ram interface with a fifo interface. still need to do rx side --- usrp2/gpmc/gpmc.v | 133 ++++++++++++++++++---------------------------- usrp2/gpmc/gpmc_to_fifo.v | 58 ++++++++++++++++++++ usrp2/top/u1e/u1e_core.v | 46 +++------------- 3 files changed, 117 insertions(+), 120 deletions(-) create mode 100644 usrp2/gpmc/gpmc_to_fifo.v diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v index cf1357232..2715414b3 100644 --- a/usrp2/gpmc/gpmc.v +++ b/usrp2/gpmc/gpmc.v @@ -10,13 +10,14 @@ module gpmc // Wishbone signals input wb_clk, input wb_rst, - output reg [10:0] wb_adr_o, output reg [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, - output reg [1:0] wb_sel_o, output wb_cyc_o, output reg wb_stb_o, output reg wb_we_o, input wb_ack_i, + output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, - // RAM Interface signals - input ram_clk, - input read_en, input [8:0] read_addr, output [31:0] read_data, output read_ready, input read_done, - input write_en, input [8:0] write_addr, input [31:0] write_data, output write_ready, input write_done, + // FIFO interface + input fifo_clk, input fifo_rst, + output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, + input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, + output [31:0] debug ); @@ -26,94 +27,64 @@ module gpmc assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_ram : EM_D_wb; - // CS4 is RAM_2PORT for high-speed data - // Writes go into one RAM, reads come from the other - + // CS4 is RAM_2PORT for DATA PATH (high-speed data) + // Writes go into one RAM, reads come from the other + // CS6 is for CONTROL PATH (wishbone) // //////////////////////////////////////////// - // Write path - wire read_sel_in, write_sel_in, clear_in; - wire write_done_in; - - edge_sync #(.POSEDGE(0)) - edge_sync_wdi(.clk(wb_clk), .rst(wb_rst), - .sig(~EM_NCS4 & ~EM_NWE & (EM_A == 10'h3FF)), .trig(write_done_in)); - - ram_2port_mixed_width buffer_in - (.clk16(wb_clk), .en16(~EM_NCS4), .we16(~EM_NWE), .addr16({write_sel_in,EM_A}), .di16(EM_D), .do16(), - .clk32(ram_clk), .en32(read_en), .we32(0), .addr32({read_sel_in,read_addr}), .di32(0), .do32(read_data)); + // TX Data Path - dbsm dbsm_in(.clk(wb_clk), .reset(wb_rst), .clear(clear_in), - .read_sel(read_sel_in), .read_ready(read_ready), .read_done(read_done), - .write_sel(write_sel_in), .write_ready(tx_have_space), .write_done(write_done_in)); + wire [17:0] tx18_data, tx18b_data; + wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; + wire [15:0] tx_fifo_space, tx_frame_len; + assign tx_frame_len = 10; + + gpmc_to_fifo gpmc_to_fifo + (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), + .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), + .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), + .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space)); + fifo_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), + .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy)); + + fifo19_to_fifo36 f19_to_f36 + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), + .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i)); + // //////////////////////////////////////////// - // Read path - wire read_sel_out, write_sel_out, clear_out; - wire read_done_out; + // RX Data Path + wire read_sel_rx, write_sel_rx, clear_rx; + wire read_done_rx; edge_sync #(.POSEDGE(0)) - edge_sync_rdo(.clk(wb_clk), .rst(wb_rst), - .sig(~EM_NCS4 & ~EM_NOE & (EM_A == 10'h3FF)), .trig(read_done_out)); + edge_sync_rx(.clk(wb_clk), .rst(wb_rst), + .sig(~EM_NCS4 & ~EM_NOE & (EM_A == 10'h3FF)), .trig(read_done_rx)); - ram_2port_mixed_width buffer_out - (.clk16(wb_clk), .en16(~EM_NCS4), .we16(0), .addr16({read_sel_out,EM_A}), .di16(0), .do16(EM_D_ram), - .clk32(ram_clk), .en32(write_en), .we32(write_en), .addr32({write_sel_out,write_addr}), .di32(write_data), .do32()); - - dbsm dbsm_out(.clk(wb_clk), .reset(wb_rst), .clear(clear_out), - .read_sel(read_sel_out), .read_ready(rx_have_data), .read_done(read_done_out), - .write_sel(write_sel_out), .write_ready(write_ready), .write_done(write_done)); + ram_2port_mixed_width buffer_rx + (.clk16(wb_clk), .en16(~EM_NCS4), .we16(0), .addr16({read_sel_rx,EM_A}), .di16(0), .do16(EM_D_ram), + .clk32(ram_clk), .en32(write_en), .we32(write_en), .addr32({write_sel_rx,write_addr}), .di32(write_data), .do32()); + dbsm dbsm_rx(.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), + .read_sel(read_sel_rx), .read_ready(rx_have_data), .read_done(read_done_rx), + .write_sel(write_sel_rx), .write_ready(write_ready), .write_done(write_done)); - assign debug = { { 2'b00, write_done_in, write_sel_in, read_en, read_sel_in, read_ready, read_done}, - { 2'b00, read_sel_out, write_en, write_sel_out, read_done_out, write_ready, write_done }, - { 8'd0 }, - { 8'd0 } }; + // //////////////////////////////////////////// + // Control path on CS6 - // CS6 is Control, Wishbone bus bridge (wb master) - // Sync version - reg [1:0] cs_del, we_del, oe_del; - - // Synchronize the async control signals - always @(posedge wb_clk) - begin - cs_del <= { cs_del[0], EM_NCS6 }; - we_del <= { we_del[0], EM_NWE }; - oe_del <= { oe_del[0], EM_NOE }; - end - - always @(posedge wb_clk) - if(cs_del == 2'b10) // Falling Edge - wb_adr_o <= { EM_A, 1'b0 }; - - always @(posedge wb_clk) - if(we_del == 2'b10) // Falling Edge - begin - wb_dat_mosi <= EM_D; - wb_sel_o <= ~EM_NBE; - end - - reg [15:0] EM_D_wb_reg; - always @(posedge wb_clk) - if(wb_ack_i) - EM_D_wb_reg <= wb_dat_miso; - - assign EM_D_wb = wb_ack_i ? wb_dat_miso : EM_D_wb_reg; + gpmc_wb gpmc_wb + (.EM_CLK(EM_CLK), .EM_D(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), + .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), + .wb_ack_i(wb_ack_i) ); - assign wb_cyc_o = wb_stb_o; - - always @(posedge wb_clk) - if(~cs_del[0] & (we_del == 2'b10) ) - wb_we_o <= 1; - else if(wb_ack_i) // Turn off we when done. Could also use we_del[0], others... - wb_we_o <= 0; - - always @(posedge wb_clk) - if(~cs_del[0] & ((we_del == 2'b10) | (oe_del == 2'b10))) - wb_stb_o <= 1; - else if(wb_ack_i) - wb_stb_o <= 0; + assign debug = 0; endmodule // gpmc diff --git a/usrp2/gpmc/gpmc_to_fifo.v b/usrp2/gpmc/gpmc_to_fifo.v new file mode 100644 index 000000000..5d499494f --- /dev/null +++ b/usrp2/gpmc/gpmc_to_fifo.v @@ -0,0 +1,58 @@ + +module gpmc_to_fifo + (input EM_CLK, input [15:0] EM_D, input [1:0] EM_NBE, + input EM_NCS, input EM_NWE, + + input fifo_clk, input fifo_rst, + output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i, + + input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready); + + // Synchronize the async control signals + reg [1:0] cs_del, we_del; + always @(posedge fifo_clk) + if(fifo_rst) + begin + cs_del <= 2'b11; + we_del <= 2'b11; + end + else + begin + cs_del <= { cs_del[0], EM_NCS }; + we_del <= { we_del[0], EM_NWE }; + end + + wire do_write = (~cs_del[0] & (we_del == 2'b10)); + wire first_write = (counter == 0); + wire last_write = ((counter+1) == frame_len); + + always @(posedge fifo_clk) + if(do_write) + begin + data_o[15:0] <= EM_D; + data_o[16] <= first_write; + data_o[17] <= last_write; + // no byte writes data_o[18] <= |EM_NBE; // mark half full if either is not enabled FIXME + end + + always @(posedge fifo_clk) + if(fifo_rst) + src_rdy_o <= 0; + else if(do_write) + src_rdy_o <= 1; + else + src_rdy_o <= 0; // Assume it was taken + + reg [10:0] counter; + always @(posedge fifo_clk) + if(fifo_rst) + counter <= 0; + else if(do_write) + if(last_write) + counter <= 0; + else + counter <= counter + 1; + + assign fifo_ready = first_write & (fifo_space > frame_len); + +endmodule // gpmc_to_fifo diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index e692cbc3d..e5e5285bd 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -30,15 +30,8 @@ module u1e_core wire [sw-1:0] m0_sel; wire m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty; - // FIFO buffers - wire [31:0] read_data, write_data; - wire [8:0] read_addr, write_addr; - reg [8:0] addr; - - wire read_done, write_done, read_en, write_en, read_ready, write_ready; - wire [31:0] debug_gpmc; - + gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), @@ -50,37 +43,12 @@ module u1e_core .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), .wb_ack_i(m0_ack), - .ram_clk(wb_clk), - .read_en(read_en), .read_addr(read_addr), .read_data(read_data), - .read_ready(read_ready), .read_done(read_done), - .write_en(write_en), .write_addr(write_addr), .write_data(write_data), - .write_ready(write_ready), .write_done(write_done), + .fifo_clk(wb_clk), .fifo_rst(wb_rst), + .tx_data_o(), .tx_src_rdy_o(), .tx_dst_rdy_i(0), + .rx_data_i(0), .rx_src_rdy_i(0), .rx_dst_rdy_o(), + .debug(debug_gpmc)); - // Loopback - assign write_data = read_data; - - reg [10:0] counter; - assign write_addr = counter[10:2]; - assign read_addr = counter[10:2]; - - assign read_done = (counter == 11'h7FF); - assign write_done = (counter == 11'h7FF); - - always @(posedge wb_clk) - if(wb_rst) - counter <= 0; - else - if(counter == 0) - counter <= write_ready & read_ready; - else if(counter == 11'h7FF) - counter <= 0; - else - counter <= counter + 1; - - assign read_en = (counter[1:0] == 1); - assign write_en = (counter[1:0] == 2); - // ///////////////////////////////////////////////////////////////////////////////////// // Wishbone Intercon, single master @@ -182,7 +150,7 @@ module u1e_core assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; - assign { rx_overrun, tx_undderun } = reg_test; + assign { rx_overrun, tx_underrun } = reg_test; assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : @@ -210,7 +178,7 @@ module u1e_core spi_top16 shared_spi (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_mosi), .wb_dat_o(s2_dat_miso),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), - .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(), .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) ); // ///////////////////////////////////////////////////////////////////////// -- cgit v1.2.3 From f95bf4d8d94511d26a5bb1f52823f8ffd5f637fe Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 12 Apr 2010 19:20:22 -0700 Subject: lengthened delay between cycles, added more transactions on the data bus --- usrp2/models/gpmc_model.v | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/usrp2/models/gpmc_model.v b/usrp2/models/gpmc_model.v index 3424671bd..6066ede6e 100644 --- a/usrp2/models/gpmc_model.v +++ b/usrp2/models/gpmc_model.v @@ -41,7 +41,7 @@ module gpmc_model EM_NCS6 <= 1; //#1.5; EM_NWE <= 1; - #6; + #60; EM_A <= 10'bz; EM_D_int <= 16'bz; end @@ -82,7 +82,12 @@ module gpmc_model GPMC_Write(0,38,16'h5678); GPMC_Write(0,40,16'h9abc); GPMC_Write(0,11'h2F4,16'hF00D); - GPMC_Write(0,11'h7FE,16'hF00D); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); #100000; $finish; end -- cgit v1.2.3 From c6a76aa03773d22c36d7e33b1fa53b4522fc566b Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 13 Apr 2010 07:46:25 -0700 Subject: merge reverse diff --- host/include/uhd/usrp/CMakeLists.txt | 1 + host/include/uhd/usrp/usrp1e.hpp | 48 ++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) create mode 100644 host/include/uhd/usrp/usrp1e.hpp diff --git a/host/include/uhd/usrp/CMakeLists.txt b/host/include/uhd/usrp/CMakeLists.txt index 9140d98ca..7815a4fb9 100644 --- a/host/include/uhd/usrp/CMakeLists.txt +++ b/host/include/uhd/usrp/CMakeLists.txt @@ -31,6 +31,7 @@ INSTALL(FILES dboard_manager.hpp ### usrp headers ### + usrp1e.hpp usrp2.hpp ### utilities ### diff --git a/host/include/uhd/usrp/usrp1e.hpp b/host/include/uhd/usrp/usrp1e.hpp new file mode 100644 index 000000000..cee9dc3d5 --- /dev/null +++ b/host/include/uhd/usrp/usrp1e.hpp @@ -0,0 +1,48 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_UHD_USRP_USRP1E_HPP +#define INCLUDED_UHD_USRP_USRP1E_HPP + +#include +#include + +namespace uhd{ namespace usrp{ + +/*! + * The usrp1e device class. + */ +class UHD_API usrp1e : public device{ +public: + /*! + * Find usrp1e devices on the system via the device node. + * \param hint a device addr with the usrp1e address filled in + * \return a vector of device addresses for all usrp1es found + */ + static device_addrs_t find(const device_addr_t &hint); + + /*! + * Make a usrp1e from a device address. + * \param addr the device address + * \return a device sptr to a new usrp1e + */ + static device::sptr make(const device_addr_t &addr); +}; + +}} //namespace + +#endif /* INCLUDED_UHD_USRP_USRP1E_HPP */ -- cgit v1.2.3 From b59c54e334dfc1c6ab7da81c62038444f93efe61 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Tue, 13 Apr 2010 16:37:22 +0000 Subject: Fix typo. --- host/apps/omap_debug/fetch-kernel.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/host/apps/omap_debug/fetch-kernel.sh b/host/apps/omap_debug/fetch-kernel.sh index f32666adf..a3cddb339 100755 --- a/host/apps/omap_debug/fetch-kernel.sh +++ b/host/apps/omap_debug/fetch-kernel.sh @@ -2,5 +2,6 @@ if [ $GHQ]; then scp $GHQ_USER@astro:/workspace/usrp1-e-dev/kernel_usrp/arch/arm/boot/uImage /media/mmcblk0p1/uImage else scp balister@192.168.1.167:src/git/kernel_usrp/arch/arm/boot/uImage /media/mmcblk0p1/uImage +fi sync -- cgit v1.2.3 From 19d476df81cdf7a51b871154510be8f7c575ffde Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 13 Apr 2010 17:33:16 -0700 Subject: minor changes to get it to synthesize --- usrp2/gpmc/gpmc_to_fifo.v | 2 +- usrp2/top/u1e/Makefile | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/usrp2/gpmc/gpmc_to_fifo.v b/usrp2/gpmc/gpmc_to_fifo.v index 5d499494f..267804469 100644 --- a/usrp2/gpmc/gpmc_to_fifo.v +++ b/usrp2/gpmc/gpmc_to_fifo.v @@ -8,6 +8,7 @@ module gpmc_to_fifo input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready); + reg [10:0] counter; // Synchronize the async control signals reg [1:0] cs_del, we_del; always @(posedge fifo_clk) @@ -43,7 +44,6 @@ module gpmc_to_fifo else src_rdy_o <= 0; // Assume it was taken - reg [10:0] counter; always @(posedge fifo_clk) if(fifo_rst) counter <= 0; diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index a0f921485..1cb56d7a9 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -109,6 +109,7 @@ control_lib/newfifo/fifo_short.v \ control_lib/newfifo/fifo_long.v \ control_lib/newfifo/fifo_cascade.v \ control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/newfifo/fifo19_to_fifo36.v \ control_lib/longfifo.v \ control_lib/shortfifo.v \ control_lib/medfifo.v \ @@ -177,6 +178,8 @@ timing/timer.v \ gpmc/gpmc.v \ gpmc/edge_sync.v \ gpmc/dbsm.v \ +gpmc/gpmc_to_fifo.v \ +gpmc/gpmc_wb.v \ top/u1e/u1e_core.v \ top/u1e/u1e.ucf \ top/u1e/u1e.v -- cgit v1.2.3 From 8cef80c8ebb9b59f1fe65971c9066fd832ab2504 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 14 Apr 2010 18:01:28 -0700 Subject: probably won't be using this, and it hasn't been tested --- usrp2/gpmc/ram_to_fifo.v | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 usrp2/gpmc/ram_to_fifo.v diff --git a/usrp2/gpmc/ram_to_fifo.v b/usrp2/gpmc/ram_to_fifo.v new file mode 100644 index 000000000..8549dcc35 --- /dev/null +++ b/usrp2/gpmc/ram_to_fifo.v @@ -0,0 +1,46 @@ + + +module ram_to_fifo + (input clk, input reset, + input [10:0] read_length, // From the dbsm (?) + output read_en, output reg [8:0] read_addr, input [31:0] read_data, input read_ready, output read_done, + output [35:0] data_o, output src_rdy_o, input dst_rdy_i); + + // read_length/2 = number of 32 bit lines, numbered 0 through read_length/2-1 + wire [8:0] last_line = (read_length[10:1]-1); + + reg read_phase, sop; + + assign read_en = (read_phase == 0) | dst_rdy_i; + assign src_rdy_o = (read_phase == 1); + + always @(posedge clk) + if(reset) + begin + read_addr <= 0; + read_phase <= 0; + sop <= 1; + end + else + if(read_phase == 0) + begin + read_addr <= read_ready; + read_phase <= read_ready; + end + else if(dst_rdy_i) + begin + sop <= 0; + if(read_addr == last_line) + begin + read_addr <= 0; + read_phase <= 0; + end + else + read_addr <= read_addr + 1; + end + + assign read_done = (read_phase == 1) & (read_addr == last_line) & dst_rdy_i; + wire eop = (read_addr == last_line); + assign data_o = { 2'b00, eop, sop, read_data }; + +endmodule // ram_to_fifo -- cgit v1.2.3 From 17fc80cb82309879dd2b1dc03681058dd432327b Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 14 Apr 2010 18:02:29 -0700 Subject: added in a loopback fifo --- usrp2/top/u1e/u1e_core.v | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index e5e5285bd..7df7b0a48 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -32,6 +32,9 @@ module u1e_core wire [31:0] debug_gpmc; + wire [35:0] tx_data, rx_data; + wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy; + gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), @@ -44,12 +47,16 @@ module u1e_core .wb_ack_i(m0_ack), .fifo_clk(wb_clk), .fifo_rst(wb_rst), - .tx_data_o(), .tx_src_rdy_o(), .tx_dst_rdy_i(0), - .rx_data_i(0), .rx_src_rdy_i(0), .rx_dst_rdy_o(), + .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), + .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), .debug(debug_gpmc)); - - + + fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), + .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + // ///////////////////////////////////////////////////////////////////////////////////// // Wishbone Intercon, single master wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, -- cgit v1.2.3 From fc54a55f97171f5714c370d566f31429ce112e89 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 14 Apr 2010 18:07:00 -0700 Subject: make timing diagrams for bus transactions. Still need to do reads --- usrp2/gpmc/.gitignore | 2 ++ usrp2/gpmc/burst_data_write.txt | 16 ++++++++++++++++ usrp2/gpmc/make_timing_diag | 6 ++++++ usrp2/gpmc/single_data_read.txt | 12 ++++++++++++ usrp2/gpmc/single_data_write.txt | 10 ++++++++++ 5 files changed, 46 insertions(+) create mode 100644 usrp2/gpmc/.gitignore create mode 100644 usrp2/gpmc/burst_data_write.txt create mode 100755 usrp2/gpmc/make_timing_diag create mode 100644 usrp2/gpmc/single_data_read.txt create mode 100644 usrp2/gpmc/single_data_write.txt diff --git a/usrp2/gpmc/.gitignore b/usrp2/gpmc/.gitignore new file mode 100644 index 000000000..3e14fa4f7 --- /dev/null +++ b/usrp2/gpmc/.gitignore @@ -0,0 +1,2 @@ +*.gif + diff --git a/usrp2/gpmc/burst_data_write.txt b/usrp2/gpmc/burst_data_write.txt new file mode 100644 index 000000000..3b5dfc785 --- /dev/null +++ b/usrp2/gpmc/burst_data_write.txt @@ -0,0 +1,16 @@ +# OMAP burst writes to FPGA + +CLK=0,nWE=1,nCS=1,nOE=1,DATA=Z. +CLK=1. +CLK=0,nWE=0,nCS=0,DATA=WR_DATA1. +CLK=1. +CLK=0,nWE=0,nCS=0,DATA=WR_DATA2. +CLK=1. +CLK=0,nWE=0,nCS=0,DATA=WR_DATA3. +CLK=1. +CLK=0,nWE=0,nCS=0,DATA=WR_DATA4. +CLK=1. +CLK=0,nWE=1,nCS=1,DATA=Z. +CLK=1. + + diff --git a/usrp2/gpmc/make_timing_diag b/usrp2/gpmc/make_timing_diag new file mode 100755 index 000000000..03166ad35 --- /dev/null +++ b/usrp2/gpmc/make_timing_diag @@ -0,0 +1,6 @@ +#!/bin/sh +drawtiming -o single_data_write.gif single_data_write.txt +drawtiming -o single_data_read.gif single_data_read.txt +drawtiming -o burst_data_write.gif burst_data_write.txt +#drawtiming -o burst_data_read.gif burst_data_read.txt + diff --git a/usrp2/gpmc/single_data_read.txt b/usrp2/gpmc/single_data_read.txt new file mode 100644 index 000000000..1dc0e3a78 --- /dev/null +++ b/usrp2/gpmc/single_data_read.txt @@ -0,0 +1,12 @@ +# OMAP writes to FPGA +# initialize the signals +CLK=0,nWE=1,nCS=1,nOE=1,DATA=Z. +CLK=1. +CLK=0,nOE=0,nCS=0,DATA=RD_DATA. +CLK=1. +CLK=0. +CLK=1. +CLK=0,nOE=1,nCS=1,DATA=Z. +CLK=1. + + diff --git a/usrp2/gpmc/single_data_write.txt b/usrp2/gpmc/single_data_write.txt new file mode 100644 index 000000000..287e3e2c1 --- /dev/null +++ b/usrp2/gpmc/single_data_write.txt @@ -0,0 +1,10 @@ +# OMAP writes to FPGA +# initialize the signals +CLK=0,nWE=1,nCS=1,nOE=1,DATA=Z. +CLK=1. +CLK=0,nWE=0,nCS=0,DATA=WR_DATA. +CLK=1. +CLK=0,nWE=1,nCS=1,DATA=Z. +CLK=1. + + -- cgit v1.2.3 From 204c591cd478958b4e2ddea4c61d3908d9520bbe Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 14 Apr 2010 18:13:49 -0700 Subject: renamed to async. Will be building a sync version for GPMC_CLK --- usrp2/gpmc/gpmc_to_fifo.v | 58 ----------------------------------------- usrp2/gpmc/gpmc_to_fifo_async.v | 58 +++++++++++++++++++++++++++++++++++++++++ usrp2/top/u1e/Makefile | 2 +- 3 files changed, 59 insertions(+), 59 deletions(-) delete mode 100644 usrp2/gpmc/gpmc_to_fifo.v create mode 100644 usrp2/gpmc/gpmc_to_fifo_async.v diff --git a/usrp2/gpmc/gpmc_to_fifo.v b/usrp2/gpmc/gpmc_to_fifo.v deleted file mode 100644 index 267804469..000000000 --- a/usrp2/gpmc/gpmc_to_fifo.v +++ /dev/null @@ -1,58 +0,0 @@ - -module gpmc_to_fifo - (input EM_CLK, input [15:0] EM_D, input [1:0] EM_NBE, - input EM_NCS, input EM_NWE, - - input fifo_clk, input fifo_rst, - output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i, - - input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready); - - reg [10:0] counter; - // Synchronize the async control signals - reg [1:0] cs_del, we_del; - always @(posedge fifo_clk) - if(fifo_rst) - begin - cs_del <= 2'b11; - we_del <= 2'b11; - end - else - begin - cs_del <= { cs_del[0], EM_NCS }; - we_del <= { we_del[0], EM_NWE }; - end - - wire do_write = (~cs_del[0] & (we_del == 2'b10)); - wire first_write = (counter == 0); - wire last_write = ((counter+1) == frame_len); - - always @(posedge fifo_clk) - if(do_write) - begin - data_o[15:0] <= EM_D; - data_o[16] <= first_write; - data_o[17] <= last_write; - // no byte writes data_o[18] <= |EM_NBE; // mark half full if either is not enabled FIXME - end - - always @(posedge fifo_clk) - if(fifo_rst) - src_rdy_o <= 0; - else if(do_write) - src_rdy_o <= 1; - else - src_rdy_o <= 0; // Assume it was taken - - always @(posedge fifo_clk) - if(fifo_rst) - counter <= 0; - else if(do_write) - if(last_write) - counter <= 0; - else - counter <= counter + 1; - - assign fifo_ready = first_write & (fifo_space > frame_len); - -endmodule // gpmc_to_fifo diff --git a/usrp2/gpmc/gpmc_to_fifo_async.v b/usrp2/gpmc/gpmc_to_fifo_async.v new file mode 100644 index 000000000..c47d69d7d --- /dev/null +++ b/usrp2/gpmc/gpmc_to_fifo_async.v @@ -0,0 +1,58 @@ + +module gpmc_to_fifo_async + (input EM_CLK, input [15:0] EM_D, input [1:0] EM_NBE, + input EM_NCS, input EM_NWE, + + input fifo_clk, input fifo_rst, + output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i, + + input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready); + + reg [10:0] counter; + // Synchronize the async control signals + reg [1:0] cs_del, we_del; + always @(posedge fifo_clk) + if(fifo_rst) + begin + cs_del <= 2'b11; + we_del <= 2'b11; + end + else + begin + cs_del <= { cs_del[0], EM_NCS }; + we_del <= { we_del[0], EM_NWE }; + end + + wire do_write = (~cs_del[0] & (we_del == 2'b10)); + wire first_write = (counter == 0); + wire last_write = ((counter+1) == frame_len); + + always @(posedge fifo_clk) + if(do_write) + begin + data_o[15:0] <= EM_D; + data_o[16] <= first_write; + data_o[17] <= last_write; + // no byte writes data_o[18] <= |EM_NBE; // mark half full if either is not enabled FIXME + end + + always @(posedge fifo_clk) + if(fifo_rst) + src_rdy_o <= 0; + else if(do_write) + src_rdy_o <= 1; + else + src_rdy_o <= 0; // Assume it was taken + + always @(posedge fifo_clk) + if(fifo_rst) + counter <= 0; + else if(do_write) + if(last_write) + counter <= 0; + else + counter <= counter + 1; + + assign fifo_ready = first_write & (fifo_space > frame_len); + +endmodule // gpmc_to_fifo_async diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 1cb56d7a9..ca4d9ce89 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -178,7 +178,7 @@ timing/timer.v \ gpmc/gpmc.v \ gpmc/edge_sync.v \ gpmc/dbsm.v \ -gpmc/gpmc_to_fifo.v \ +gpmc/gpmc_to_fifo_async.v \ gpmc/gpmc_wb.v \ top/u1e/u1e_core.v \ top/u1e/u1e.ucf \ -- cgit v1.2.3 From 108109e649397147ecf6f5d6b82bdb3d5b852539 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 14 Apr 2010 19:14:46 -0700 Subject: more progress on synchronous interface --- usrp2/gpmc/gpmc.v | 61 ++++++++++++++++++++++++----------------- usrp2/gpmc/gpmc_to_fifo_async.v | 2 +- usrp2/gpmc/gpmc_to_fifo_sync.v | 57 ++++++++++++++++++++++++++++++++++++++ usrp2/top/u1e/Makefile | 1 + 4 files changed, 95 insertions(+), 26 deletions(-) create mode 100644 usrp2/gpmc/gpmc_to_fifo_sync.v diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v index 2715414b3..d6a685bba 100644 --- a/usrp2/gpmc/gpmc.v +++ b/usrp2/gpmc/gpmc.v @@ -4,7 +4,8 @@ module gpmc (// GPMC signals input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, - + output bus_error, + // GPIOs for FIFO signalling output rx_have_data, output tx_have_space, @@ -17,15 +18,15 @@ module gpmc input fifo_clk, input fifo_rst, output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, - + output [31:0] debug ); wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); - wire [15:0] EM_D_ram; + wire [15:0] EM_D_fifo; wire [15:0] EM_D_wb; - assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_ram : EM_D_wb; + assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb; // CS4 is RAM_2PORT for DATA PATH (high-speed data) // Writes go into one RAM, reads come from the other @@ -37,19 +38,22 @@ module gpmc wire [17:0] tx18_data, tx18b_data; wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; wire [15:0] tx_fifo_space, tx_frame_len; - + assign tx_frame_len = 10; + wire arst; - gpmc_to_fifo gpmc_to_fifo - (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), - .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), + gpmc_to_fifo_sync gpmc_to_fifo_sync + (.arst(arst), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), - .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space)); + .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space), + .bus_error(bus_error) ); - fifo_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), - .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy)); + fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo + (.wclk(EM_CLK), .datain(tx18_data), + .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), + .rclk(fifo_clk), .dataout(tx18b_data), + .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied(), .arst(arst)); fifo19_to_fifo36 f19_to_f36 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), @@ -59,21 +63,28 @@ module gpmc // //////////////////////////////////////////// // RX Data Path - wire read_sel_rx, write_sel_rx, clear_rx; - wire read_done_rx; - - edge_sync #(.POSEDGE(0)) - edge_sync_rx(.clk(wb_clk), .rst(wb_rst), - .sig(~EM_NCS4 & ~EM_NOE & (EM_A == 10'h3FF)), .trig(read_done_rx)); + + wire [17:0] rx18_data, rx18b_data; + wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; + wire [15:0] rx_fifo_space, rx_frame_len; - ram_2port_mixed_width buffer_rx - (.clk16(wb_clk), .en16(~EM_NCS4), .we16(0), .addr16({read_sel_rx,EM_A}), .di16(0), .do16(EM_D_ram), - .clk32(ram_clk), .en32(write_en), .we32(write_en), .addr32({write_sel_rx,write_addr}), .di32(write_data), .do32()); + fifo36_to_fifo18 f18_to_f36 + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o), + .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) ); - dbsm dbsm_rx(.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), - .read_sel(read_sel_rx), .read_ready(rx_have_data), .read_done(read_done_rx), - .write_sel(write_sel_rx), .write_ready(write_ready), .write_done(write_done)); + fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) rx_fifo + (.wclk(fifo_clk), .datain(rx18_data), + .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space), + .rclk(EM_CLK), .dataout(rx18b_data), + .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied(), .arst(arst)); + fifo_to_gpmc_sync fifo_to_gpmc_sync + (.arst(arst), + .data_i(tx18b_data), .src_rdy_i(tx18b_src_rdy), .dst_rdy_o(tx18b_dst_rdy), + .EM_CLK(EM_CLK), .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), + .fifo_ready(rx_have_data) ); + // //////////////////////////////////////////// // Control path on CS6 diff --git a/usrp2/gpmc/gpmc_to_fifo_async.v b/usrp2/gpmc/gpmc_to_fifo_async.v index c47d69d7d..a8068022f 100644 --- a/usrp2/gpmc/gpmc_to_fifo_async.v +++ b/usrp2/gpmc/gpmc_to_fifo_async.v @@ -1,6 +1,6 @@ module gpmc_to_fifo_async - (input EM_CLK, input [15:0] EM_D, input [1:0] EM_NBE, + (input [15:0] EM_D, input [1:0] EM_NBE, input EM_NCS, input EM_NWE, input fifo_clk, input fifo_rst, diff --git a/usrp2/gpmc/gpmc_to_fifo_sync.v b/usrp2/gpmc/gpmc_to_fifo_sync.v new file mode 100644 index 000000000..688de0e17 --- /dev/null +++ b/usrp2/gpmc/gpmc_to_fifo_sync.v @@ -0,0 +1,57 @@ + +// Assumes a GPMC cycle with GPMC clock, as in the timing diagrams +// If a packet bigger or smaller than we are told is sent, behavior is undefined. +// If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error. +// If there is a bus error, we should be reset + +module gpmc_to_fifo_sync + (input arst, + input EM_CLK, input [15:0] EM_D, input [1:0] EM_NBE, + input EM_NCS, input EM_NWE, + output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i, + input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready, + output reg bus_error); + + reg [10:0] counter; + wire first_write = (counter == 0); + wire last_write = ((counter+1) == frame_len); + wire do_write = ~EM_NCS & ~EM_NWE; + + always @(posedge EM_CLK or posedge arst) + if(arst) + data_o <= 0; + else if(do_write) + begin + data_o[15:0] <= EM_D; + data_o[16] <= first_write; + data_o[17] <= last_write; + // no byte writes data_o[18] <= |EM_NBE; // mark half full if either is not enabled FIXME + end + + always @(posedge EM_CLK or posedge arst) + if(arst) + src_rdy_o <= 0; + else if(do_write & ~bus_error) // Don't put junk in if there is a bus error + src_rdy_o <= 1; + else + src_rdy_o <= 0; // Assume it was taken, ignore dst_rdy_i + + always @(posedge EM_CLK or posedge arst) + if(arst) + counter <= 0; + else if(do_write) + if(last_write) + counter <= 0; + else + counter <= counter + 1; + + assign fifo_ready = first_write & (fifo_space > frame_len); + + always @(posedge EM_CLK or posedge arst) + if(arst) + bus_error <= 0; + else if(src_rdy_o & ~dst_rdy_i) + bus_error <= 1; + // must be reset to make the error go away + +endmodule // gpmc_to_fifo_sync diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index ca4d9ce89..057de64cf 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -179,6 +179,7 @@ gpmc/gpmc.v \ gpmc/edge_sync.v \ gpmc/dbsm.v \ gpmc/gpmc_to_fifo_async.v \ +gpmc/gpmc_to_fifo_sync.v \ gpmc/gpmc_wb.v \ top/u1e/u1e_core.v \ top/u1e/u1e.ucf \ -- cgit v1.2.3 From f89ed91930f5933c827726d17b8c5b0313b6c297 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 14 Apr 2010 19:16:47 -0700 Subject: more sync progress. This is just a skeleton for now, with junk content --- usrp2/gpmc/fifo_to_gpmc_sync.v | 56 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 usrp2/gpmc/fifo_to_gpmc_sync.v diff --git a/usrp2/gpmc/fifo_to_gpmc_sync.v b/usrp2/gpmc/fifo_to_gpmc_sync.v new file mode 100644 index 000000000..647a507b4 --- /dev/null +++ b/usrp2/gpmc/fifo_to_gpmc_sync.v @@ -0,0 +1,56 @@ + +// Assumes a GPMC cycle with GPMC clock, as in the timing diagrams +// If a packet bigger or smaller than we are told is sent, behavior is undefined. +// If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error. +// If there is a bus error, we should be reset + +module fifo_to_gpmc_sync + (input arst, + input [17:0] data_i, input src_rdy_i, output reg dst_rdy_o, + input EM_CLK, inout [15:0] EM_D, input EM_NCS, input EM_NOE, + output fifo_ready, + output reg bus_error); + + reg [10:0] counter; + wire first_write = (counter == 0); + wire last_write = ((counter+1) == frame_len); + wire do_write = ~EM_NCS & ~EM_NWE; + + always @(posedge EM_CLK or posedge arst) + if(arst) + data_o <= 0; + else if(do_write) + begin + data_o[15:0] <= EM_D; + data_o[16] <= first_write; + data_o[17] <= last_write; + // no byte writes data_o[18] <= |EM_NBE; // mark half full if either is not enabled FIXME + end + + always @(posedge EM_CLK or posedge arst) + if(arst) + src_rdy_o <= 0; + else if(do_write & ~bus_error) // Don't put junk in if there is a bus error + src_rdy_o <= 1; + else + src_rdy_o <= 0; // Assume it was taken, ignore dst_rdy_i + + always @(posedge EM_CLK or posedge arst) + if(arst) + counter <= 0; + else if(do_write) + if(last_write) + counter <= 0; + else + counter <= counter + 1; + + assign fifo_ready = first_write & (fifo_space > frame_len); + + always @(posedge EM_CLK or posedge arst) + if(arst) + bus_error <= 0; + else if(src_rdy_o & ~dst_rdy_i) + bus_error <= 1; + // must be reset to make the error go away + +endmodule // fifo_to_gpmc_sync -- cgit v1.2.3 From 7d00d3a7b93d53b2f60107f0e43645d35788cf2f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 15 Apr 2010 12:52:18 -0700 Subject: handle all tri-state in the top level of gpmc --- usrp2/gpmc/gpmc.v | 6 +++--- usrp2/gpmc/gpmc_wb.v | 6 +++--- usrp2/top/u1e/Makefile | 2 ++ 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v index d6a685bba..93308a2d2 100644 --- a/usrp2/gpmc/gpmc.v +++ b/usrp2/gpmc/gpmc.v @@ -77,11 +77,11 @@ module gpmc (.wclk(fifo_clk), .datain(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space), .rclk(EM_CLK), .dataout(rx18b_data), - .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied(), .arst(arst)); + .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied(), .arst(arst)); fifo_to_gpmc_sync fifo_to_gpmc_sync (.arst(arst), - .data_i(tx18b_data), .src_rdy_i(tx18b_src_rdy), .dst_rdy_o(tx18b_dst_rdy), + .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy), .EM_CLK(EM_CLK), .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), .fifo_ready(rx_have_data) ); @@ -89,7 +89,7 @@ module gpmc // Control path on CS6 gpmc_wb gpmc_wb - (.EM_CLK(EM_CLK), .EM_D(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE), + (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), diff --git a/usrp2/gpmc/gpmc_wb.v b/usrp2/gpmc/gpmc_wb.v index 64f6a1c00..db6fbc6e9 100644 --- a/usrp2/gpmc/gpmc_wb.v +++ b/usrp2/gpmc/gpmc_wb.v @@ -1,7 +1,7 @@ module gpmc_wb - (input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + (input EM_CLK, input [15:0] EM_D_in, output [15:0] EM_D_out, input [10:1] EM_A, input [1:0] EM_NBE, input EM_NCS, input EM_NWE, input EM_NOE, input wb_clk, input wb_rst, @@ -27,7 +27,7 @@ module gpmc_wb always @(posedge wb_clk) if(we_del == 2'b10) // Falling Edge begin - wb_dat_mosi <= EM_D; + wb_dat_mosi <= EM_D_in; wb_sel_o <= ~EM_NBE; end @@ -37,7 +37,7 @@ module gpmc_wb if(wb_ack_i) EM_D_hold <= wb_dat_miso; - assign EM_D = wb_ack_i ? wb_dat_miso : EM_D_hold; + assign EM_D_out = wb_ack_i ? wb_dat_miso : EM_D_hold; assign wb_cyc_o = wb_stb_o; diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 057de64cf..160e67894 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -109,6 +109,7 @@ control_lib/newfifo/fifo_short.v \ control_lib/newfifo/fifo_long.v \ control_lib/newfifo/fifo_cascade.v \ control_lib/newfifo/fifo36_to_ll8.v \ +control_lib/newfifo/fifo36_to_fifo18.v \ control_lib/newfifo/fifo19_to_fifo36.v \ control_lib/longfifo.v \ control_lib/shortfifo.v \ @@ -180,6 +181,7 @@ gpmc/edge_sync.v \ gpmc/dbsm.v \ gpmc/gpmc_to_fifo_async.v \ gpmc/gpmc_to_fifo_sync.v \ +gpmc/fifo_to_gpmc_sync.v \ gpmc/gpmc_wb.v \ top/u1e/u1e_core.v \ top/u1e/u1e.ucf \ -- cgit v1.2.3 From d7342b46abac60bf4e2811ac4798dc4e06b5844f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 15 Apr 2010 14:51:41 -0700 Subject: synchronous and asynchronous gpmc models --- usrp2/models/gpmc_model.v | 95 ---------------------------------------- usrp2/models/gpmc_model_async.v | 95 ++++++++++++++++++++++++++++++++++++++++ usrp2/models/gpmc_model_sync.v | 97 +++++++++++++++++++++++++++++++++++++++++ usrp2/top/u1e/tb_u1e.v | 2 +- 4 files changed, 193 insertions(+), 96 deletions(-) delete mode 100644 usrp2/models/gpmc_model.v create mode 100644 usrp2/models/gpmc_model_async.v create mode 100644 usrp2/models/gpmc_model_sync.v diff --git a/usrp2/models/gpmc_model.v b/usrp2/models/gpmc_model.v deleted file mode 100644 index 6066ede6e..000000000 --- a/usrp2/models/gpmc_model.v +++ /dev/null @@ -1,95 +0,0 @@ - - -module gpmc_model - (output EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE, - output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, - output reg EM_NWE, output reg EM_NOE ); - - assign EM_CLK = 0; - reg [15:0] EM_D_int; - assign EM_D = EM_D_int; - - initial - begin - EM_A <= 10'bz; - EM_NBE <= 2'b11; - EM_NWE <= 1; - EM_NOE <= 1; - EM_NCS4 <= 1; - EM_NCS6 <= 1; - EM_D_int <= 16'bz; - EM_WAIT0 <= 0; // FIXME this is actually an input - end - - task GPMC_Write; - input ctrl; - input [10:0] addr; - input [15:0] data; - begin - #2.3; - EM_A <= addr[10:1]; - EM_D_int <= data; - #2.01; - if(ctrl) - EM_NCS6 <= 0; - else - EM_NCS4 <= 0; - #14; - EM_NWE <= 0; - #77.5; - EM_NCS4 <= 1; - EM_NCS6 <= 1; - //#1.5; - EM_NWE <= 1; - #60; - EM_A <= 10'bz; - EM_D_int <= 16'bz; - end - endtask // GPMC_Write - - task GPMC_Read; - input ctrl; - input [10:0] addr; - begin - #1.3; - EM_A <= addr[10:1]; - #3; - if(ctrl) - EM_NCS6 <= 0; - else - EM_NCS4 <= 0; - #14; - EM_NOE <= 0; - #77.5; - EM_NCS4 <= 1; - EM_NCS6 <= 1; - //#1.5; - $display("Data Read from GPMC: %X",EM_D); - EM_NOE <= 1; - #254; - EM_A <= 10'bz; - end - endtask // GPMC_Read - - initial - begin - #1000; - GPMC_Write(1,36,16'hF00D); - #1000; - GPMC_Read(1,36); - #1000; - GPMC_Write(0,36,16'h1234); - GPMC_Write(0,38,16'h5678); - GPMC_Write(0,40,16'h9abc); - GPMC_Write(0,11'h2F4,16'hF00D); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - #100000; - $finish; - end - -endmodule // gpmc_model diff --git a/usrp2/models/gpmc_model_async.v b/usrp2/models/gpmc_model_async.v new file mode 100644 index 000000000..a63a5a8fd --- /dev/null +++ b/usrp2/models/gpmc_model_async.v @@ -0,0 +1,95 @@ + + +module gpmc_model_async + (output EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE, + output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, + output reg EM_NWE, output reg EM_NOE ); + + assign EM_CLK = 0; + reg [15:0] EM_D_int; + assign EM_D = EM_D_int; + + initial + begin + EM_A <= 10'bz; + EM_NBE <= 2'b11; + EM_NWE <= 1; + EM_NOE <= 1; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + EM_D_int <= 16'bz; + EM_WAIT0 <= 0; // FIXME this is actually an input + end + + task GPMC_Write; + input ctrl; + input [10:0] addr; + input [15:0] data; + begin + #2.3; + EM_A <= addr[10:1]; + EM_D_int <= data; + #2.01; + if(ctrl) + EM_NCS6 <= 0; + else + EM_NCS4 <= 0; + #14; + EM_NWE <= 0; + #77.5; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + //#1.5; + EM_NWE <= 1; + #60; + EM_A <= 10'bz; + EM_D_int <= 16'bz; + end + endtask // GPMC_Write + + task GPMC_Read; + input ctrl; + input [10:0] addr; + begin + #1.3; + EM_A <= addr[10:1]; + #3; + if(ctrl) + EM_NCS6 <= 0; + else + EM_NCS4 <= 0; + #14; + EM_NOE <= 0; + #77.5; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + //#1.5; + $display("Data Read from GPMC: %X",EM_D); + EM_NOE <= 1; + #254; + EM_A <= 10'bz; + end + endtask // GPMC_Read + + initial + begin + #1000; + GPMC_Write(1,36,16'hF00D); + #1000; + GPMC_Read(1,36); + #1000; + GPMC_Write(0,36,16'h1234); + GPMC_Write(0,38,16'h5678); + GPMC_Write(0,40,16'h9abc); + GPMC_Write(0,11'h2F4,16'hF00D); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + #100000; + $finish; + end + +endmodule // gpmc_model_async diff --git a/usrp2/models/gpmc_model_sync.v b/usrp2/models/gpmc_model_sync.v new file mode 100644 index 000000000..641720c15 --- /dev/null +++ b/usrp2/models/gpmc_model_sync.v @@ -0,0 +1,97 @@ + + +module gpmc_model_sync + (output reg EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE, + output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, + output reg EM_NWE, output reg EM_NOE ); + + reg [15:0] EM_D_int; + assign EM_D = EM_D_int; + + initial + begin + EM_CLK <= 0; + EM_A <= 10'bz; + EM_NBE <= 2'b11; + EM_NWE <= 1; + EM_NOE <= 1; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + EM_D_int <= 16'bz; + EM_WAIT0 <= 0; // FIXME this is actually an input + end + + task GPMC_Write; + input ctrl; + input [10:0] addr; + input [15:0] data; + begin + EM_CLK <= 1; + #10; + EM_CLK <= 0; + EM_NWE <= 0; + if(ctrl) + EM_NCS6 <= 0; + else + EM_NCS4 <= 0; + EM_A <= addr[10:1]; + EM_D_int <= data; + #10; + EM_CLK <= 1; + #10; + EM_CLK <= 0; + EM_NWE <= 1; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + EM_A <= 10'bz; + EM_D_int <= 16'bz; + #100; + end + endtask // GPMC_Write + + task GPMC_Read; + input ctrl; + input [10:0] addr; + begin + #1.3; + EM_A <= addr[10:1]; + #3; + if(ctrl) + EM_NCS6 <= 0; + else + EM_NCS4 <= 0; + #14; + EM_NOE <= 0; + #77.5; + EM_NCS4 <= 1; + EM_NCS6 <= 1; + //#1.5; + $display("Data Read from GPMC: %X",EM_D); + EM_NOE <= 1; + #254; + EM_A <= 10'bz; + end + endtask // GPMC_Read + + initial + begin + #1000; + GPMC_Write(1,36,16'hF00D); + #1000; + GPMC_Read(1,36); + #1000; + GPMC_Write(0,36,16'h1234); + GPMC_Write(0,38,16'h5678); + GPMC_Write(0,40,16'h9abc); + GPMC_Write(0,11'h2F4,16'hF00D); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + GPMC_Write(0,11'h7FE,16'hDEAD); + #100000; + $finish; + end + +endmodule // gpmc_model diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v index 3cae74c8a..31e4fcb69 100644 --- a/usrp2/top/u1e/tb_u1e.v +++ b/usrp2/top/u1e/tb_u1e.v @@ -33,7 +33,7 @@ module tb_u1e(); .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); - gpmc_model gpmc_model + gpmc_model_async gpmc_model_async (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) ); -- cgit v1.2.3 From 6dd46af16008e46ee8830748194bbc2a1df9fdf3 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 15 Apr 2010 14:56:19 -0700 Subject: progress on synchronous gpmc, but it may not be possible due to the limited number of clock edges --- usrp2/gpmc/fifo_to_gpmc_sync.v | 44 +++-------------- usrp2/gpmc/fifo_watcher.v | 26 ++++++++++ usrp2/gpmc/gpmc.v | 101 -------------------------------------- usrp2/gpmc/gpmc_sync.v | 107 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 140 insertions(+), 138 deletions(-) create mode 100644 usrp2/gpmc/fifo_watcher.v delete mode 100644 usrp2/gpmc/gpmc.v create mode 100644 usrp2/gpmc/gpmc_sync.v diff --git a/usrp2/gpmc/fifo_to_gpmc_sync.v b/usrp2/gpmc/fifo_to_gpmc_sync.v index 647a507b4..ef59d7137 100644 --- a/usrp2/gpmc/fifo_to_gpmc_sync.v +++ b/usrp2/gpmc/fifo_to_gpmc_sync.v @@ -6,51 +6,21 @@ module fifo_to_gpmc_sync (input arst, - input [17:0] data_i, input src_rdy_i, output reg dst_rdy_o, - input EM_CLK, inout [15:0] EM_D, input EM_NCS, input EM_NOE, + input [17:0] data_i, input src_rdy_i, output dst_rdy_o, + input EM_CLK, output [15:0] EM_D, input EM_NCS, input EM_NOE, output fifo_ready, output reg bus_error); - - reg [10:0] counter; - wire first_write = (counter == 0); - wire last_write = ((counter+1) == frame_len); - wire do_write = ~EM_NCS & ~EM_NWE; - - always @(posedge EM_CLK or posedge arst) - if(arst) - data_o <= 0; - else if(do_write) - begin - data_o[15:0] <= EM_D; - data_o[16] <= first_write; - data_o[17] <= last_write; - // no byte writes data_o[18] <= |EM_NBE; // mark half full if either is not enabled FIXME - end - always @(posedge EM_CLK or posedge arst) - if(arst) - src_rdy_o <= 0; - else if(do_write & ~bus_error) // Don't put junk in if there is a bus error - src_rdy_o <= 1; - else - src_rdy_o <= 0; // Assume it was taken, ignore dst_rdy_i + assign EM_D = data_i[15:0]; + wire read_access = ~EM_NCS & ~EM_NOE; - always @(posedge EM_CLK or posedge arst) - if(arst) - counter <= 0; - else if(do_write) - if(last_write) - counter <= 0; - else - counter <= counter + 1; + assign dst_rdy_o = read_access; - assign fifo_ready = first_write & (fifo_space > frame_len); - always @(posedge EM_CLK or posedge arst) if(arst) bus_error <= 0; - else if(src_rdy_o & ~dst_rdy_i) + else if(dst_rdy_o & ~src_rdy_i) bus_error <= 1; - // must be reset to make the error go away + endmodule // fifo_to_gpmc_sync diff --git a/usrp2/gpmc/fifo_watcher.v b/usrp2/gpmc/fifo_watcher.v new file mode 100644 index 000000000..8b8f1abfb --- /dev/null +++ b/usrp2/gpmc/fifo_watcher.v @@ -0,0 +1,26 @@ + + +module fifo_watcher + (input clk, input reset, input clear, + input src_rdy, input dst_rdy, input sof, input eof, + output have_packet, output [15:0] length, input next); + + wire write = src_rdy & dst_rdy & eof; + + fifo_short #(.WIDTH(16)) frame_lengths + (.clk(clk), .reset(reset), .clear(clear), + .datain(counter), .src_rdy_i(write), .dst_rdy_o(), + .dataout(length), .src_rdy_o(have_packet), .dst_rdy_i(next) ); + + reg [15:0] counter; + always @(posedge clk) + if(reset | clear) + counter <= 1; // Start at 1 + else if(src_rdy & dst_rdy) + if(eof) + counter <= 1; + else + counter <= counter + 1; + + +endmodule // fifo_watcher diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v deleted file mode 100644 index 93308a2d2..000000000 --- a/usrp2/gpmc/gpmc.v +++ /dev/null @@ -1,101 +0,0 @@ -////////////////////////////////////////////////////////////////////////////////// - -module gpmc - (// GPMC signals - input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, - input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, - output bus_error, - - // GPIOs for FIFO signalling - output rx_have_data, output tx_have_space, - - // Wishbone signals - input wb_clk, input wb_rst, - output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, - output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, - - // FIFO interface - input fifo_clk, input fifo_rst, - output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, - input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, - - output [31:0] debug - ); - - wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); - wire [15:0] EM_D_fifo; - wire [15:0] EM_D_wb; - - assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb; - - // CS4 is RAM_2PORT for DATA PATH (high-speed data) - // Writes go into one RAM, reads come from the other - // CS6 is for CONTROL PATH (wishbone) - - // //////////////////////////////////////////// - // TX Data Path - - wire [17:0] tx18_data, tx18b_data; - wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; - wire [15:0] tx_fifo_space, tx_frame_len; - - assign tx_frame_len = 10; - wire arst; - - gpmc_to_fifo_sync gpmc_to_fifo_sync - (.arst(arst), - .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), - .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), - .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space), - .bus_error(bus_error) ); - - fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo - (.wclk(EM_CLK), .datain(tx18_data), - .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), - .rclk(fifo_clk), .dataout(tx18b_data), - .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied(), .arst(arst)); - - fifo19_to_fifo36 f19_to_f36 - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), - .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i)); - - - // //////////////////////////////////////////// - // RX Data Path - - wire [17:0] rx18_data, rx18b_data; - wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; - wire [15:0] rx_fifo_space, rx_frame_len; - - fifo36_to_fifo18 f18_to_f36 - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o), - .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) ); - - fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) rx_fifo - (.wclk(fifo_clk), .datain(rx18_data), - .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space), - .rclk(EM_CLK), .dataout(rx18b_data), - .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied(), .arst(arst)); - - fifo_to_gpmc_sync fifo_to_gpmc_sync - (.arst(arst), - .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy), - .EM_CLK(EM_CLK), .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), - .fifo_ready(rx_have_data) ); - - // //////////////////////////////////////////// - // Control path on CS6 - - gpmc_wb gpmc_wb - (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), - .wb_clk(wb_clk), .wb_rst(wb_rst), - .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), - .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), - .wb_ack_i(wb_ack_i) ); - - assign debug = 0; - -endmodule // gpmc diff --git a/usrp2/gpmc/gpmc_sync.v b/usrp2/gpmc/gpmc_sync.v new file mode 100644 index 000000000..41dfeb49e --- /dev/null +++ b/usrp2/gpmc/gpmc_sync.v @@ -0,0 +1,107 @@ +////////////////////////////////////////////////////////////////////////////////// + +module gpmc + (// GPMC signals + input arst, + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + + // GPIOs for FIFO signalling + output rx_have_data, output tx_have_space, output bus_error, input bus_reset, + + // Wishbone signals + input wb_clk, input wb_rst, + output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + + // FIFO interface + input fifo_clk, input fifo_rst, + output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, + input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, + + output [31:0] debug + ); + + wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); + wire [15:0] EM_D_fifo; + wire [15:0] EM_D_wb; + + assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb; + + wire bus_error_tx, bus_error_rx; + assign bus_error = bus_error_tx | bus_error_rx; + + // CS4 is RAM_2PORT for DATA PATH (high-speed data) + // Writes go into one RAM, reads come from the other + // CS6 is for CONTROL PATH (wishbone) + + // //////////////////////////////////////////// + // TX Data Path + + wire [17:0] tx18_data, tx18b_data; + wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; + wire [15:0] tx_fifo_space, tx_frame_len; + + assign tx_frame_len = 10; + + gpmc_to_fifo_sync gpmc_to_fifo_sync + (.arst(arst), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), + .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), + .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space), + .bus_error(bus_error_tx) ); + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) tx_fifo + (.wclk(EM_CLK), .datain(tx18_data), + .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), + .rclk(fifo_clk), .dataout(tx18b_data), + .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied(), .arst(arst)); + + fifo19_to_fifo36 f19_to_f36 + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), + .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i)); + + // //////////////////////////////////////////// + // RX Data Path + + wire [17:0] rx18_data, rx18b_data; + wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; + wire [15:0] rx_fifo_space, rx_frame_len; + + fifo36_to_fifo18 f18_to_f36 + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o), + .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) ); + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) rx_fifo + (.wclk(fifo_clk), .datain(rx18_data), + .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space), + .rclk(EM_CLK), .dataout(rx18b_data), + .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied(), .arst(arst)); + + fifo_to_gpmc_sync fifo_to_gpmc_sync + (.arst(arst), + .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy), + .EM_CLK(EM_CLK), .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), + .fifo_ready(rx_have_data) ); + + fifo_watcher fifo_watcher + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .src_rdy(rx18_src_rdy), .dst_rdy(rx18_dst_rdy), .sof(rx18_data[16]), .eof(rx18_data[17]), + .have_packet(), .length(), .next() ); + + // //////////////////////////////////////////// + // Control path on CS6 + + gpmc_wb gpmc_wb + (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), + .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), + .wb_ack_i(wb_ack_i) ); + + assign debug = 0; + +endmodule // gpmc -- cgit v1.2.3 From 8f6ddf93ef81deb73a8b84496e115be299769951 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 15 Apr 2010 16:13:42 -0700 Subject: correct name of module --- usrp2/gpmc/gpmc_sync.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/gpmc/gpmc_sync.v b/usrp2/gpmc/gpmc_sync.v index 41dfeb49e..825d131d8 100644 --- a/usrp2/gpmc/gpmc_sync.v +++ b/usrp2/gpmc/gpmc_sync.v @@ -1,6 +1,6 @@ ////////////////////////////////////////////////////////////////////////////////// -module gpmc +module gpmc_sync (// GPMC signals input arst, input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, @@ -104,4 +104,4 @@ module gpmc assign debug = 0; -endmodule // gpmc +endmodule // gpmc_sync -- cgit v1.2.3 From 883c60cad6756042b5e90785668be3dd98e920bf Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 15 Apr 2010 16:14:24 -0700 Subject: add bus error reporting --- usrp2/gpmc/gpmc_to_fifo_async.v | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/usrp2/gpmc/gpmc_to_fifo_async.v b/usrp2/gpmc/gpmc_to_fifo_async.v index a8068022f..1df93f910 100644 --- a/usrp2/gpmc/gpmc_to_fifo_async.v +++ b/usrp2/gpmc/gpmc_to_fifo_async.v @@ -1,12 +1,12 @@ module gpmc_to_fifo_async - (input [15:0] EM_D, input [1:0] EM_NBE, - input EM_NCS, input EM_NWE, + (input [15:0] EM_D, input [1:0] EM_NBE, input EM_NCS, input EM_NWE, input fifo_clk, input fifo_rst, output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i, - input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready); + input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready, + output reg bus_error ); reg [10:0] counter; // Synchronize the async control signals @@ -54,5 +54,11 @@ module gpmc_to_fifo_async counter <= counter + 1; assign fifo_ready = first_write & (fifo_space > frame_len); + + always @(posedge fifo_clk) + if(fifo_rst) + bus_error <= 0; + else if(src_rdy_o & ~dst_rdy_i) + bus_error <= 1; endmodule // gpmc_to_fifo_async -- cgit v1.2.3 From 2e6079841b7509f08a54c67db2ec19e07329e0d9 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 15 Apr 2010 16:14:57 -0700 Subject: change time parameters because Xilinx IP has a 1ps timescale --- usrp2/models/gpmc_model_async.v | 41 +++++++++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 14 deletions(-) diff --git a/usrp2/models/gpmc_model_async.v b/usrp2/models/gpmc_model_async.v index a63a5a8fd..64b596284 100644 --- a/usrp2/models/gpmc_model_async.v +++ b/usrp2/models/gpmc_model_async.v @@ -1,4 +1,4 @@ - +`timescale 1ps/1ps module gpmc_model_async (output EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE, @@ -26,22 +26,22 @@ module gpmc_model_async input [10:0] addr; input [15:0] data; begin - #2.3; + #23000; EM_A <= addr[10:1]; EM_D_int <= data; - #2.01; + #20100; if(ctrl) EM_NCS6 <= 0; else EM_NCS4 <= 0; - #14; + #14000; EM_NWE <= 0; - #77.5; + #77500; EM_NCS4 <= 1; EM_NCS6 <= 1; //#1.5; EM_NWE <= 1; - #60; + #60000; EM_A <= 10'bz; EM_D_int <= 16'bz; end @@ -51,33 +51,33 @@ module gpmc_model_async input ctrl; input [10:0] addr; begin - #1.3; + #13000; EM_A <= addr[10:1]; - #3; + #3000; if(ctrl) EM_NCS6 <= 0; else EM_NCS4 <= 0; - #14; + #14000; EM_NOE <= 0; - #77.5; + #77500; EM_NCS4 <= 1; EM_NCS6 <= 1; //#1.5; $display("Data Read from GPMC: %X",EM_D); EM_NOE <= 1; - #254; + #254000; EM_A <= 10'bz; end endtask // GPMC_Read initial begin - #1000; + #1000000; GPMC_Write(1,36,16'hF00D); - #1000; + #1000000; GPMC_Read(1,36); - #1000; + #1000000; GPMC_Write(0,36,16'h1234); GPMC_Write(0,38,16'h5678); GPMC_Write(0,40,16'h9abc); @@ -89,6 +89,19 @@ module gpmc_model_async GPMC_Write(0,11'h7FE,16'hDEAD); GPMC_Write(0,11'h7FE,16'hDEAD); #100000; + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + #100000; + GPMC_Read(0,0); + #100000000; $finish; end -- cgit v1.2.3 From 449a420f4024004abc49f3a17d224910710def92 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 15 Apr 2010 16:16:31 -0700 Subject: async gpmc progress --- usrp2/gpmc/fifo_to_gpmc_async.v | 45 +++++++++++++++++ usrp2/gpmc/gpmc_async.v | 108 ++++++++++++++++++++++++++++++++++++++++ usrp2/top/u1e/tb_u1e.v | 4 +- usrp2/top/u1e/u1e_core.v | 34 +++++++------ 4 files changed, 173 insertions(+), 18 deletions(-) create mode 100644 usrp2/gpmc/fifo_to_gpmc_async.v create mode 100644 usrp2/gpmc/gpmc_async.v diff --git a/usrp2/gpmc/fifo_to_gpmc_async.v b/usrp2/gpmc/fifo_to_gpmc_async.v new file mode 100644 index 000000000..4f253e1b5 --- /dev/null +++ b/usrp2/gpmc/fifo_to_gpmc_async.v @@ -0,0 +1,45 @@ + +// Assumes an asynchronous GPMC cycle +// If a packet bigger or smaller than we are told is sent, behavior is undefined. +// If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error. +// If there is a bus error, we should be reset + +module fifo_to_gpmc_async + (input clk, input reset, input clear, + input [17:0] data_i, input src_rdy_i, output dst_rdy_o, + output [15:0] EM_D, input EM_NCS, input EM_NOE, + input [15:0] frame_len, output reg bus_error); + + // Synchronize the async control signals + reg [1:0] cs_del, oe_del; + reg [15:0] counter; + + always @(posedge clk) + if(reset) + begin + cs_del <= 2'b11; + oe_del <= 2'b11; + end + else + begin + cs_del <= { cs_del[0], EM_NCS }; + oe_del <= { oe_del[0], EM_NOE }; + end + + //wire do_read = (~cs_del[0] & (oe_del == 2'b10)); + wire do_read = (~cs_del[1] & (oe_del == 2'b01)); // change output on trailing edge + wire first_read = (counter == 0); + wire last_read = ((counter+1) == frame_len); + + assign EM_D = data_i[15:0]; + + assign dst_rdy_o = do_read; + + always @(posedge clk) + if(reset) + bus_error <= 0; + else if(dst_rdy_o & ~src_rdy_i) + bus_error <= 1; + + +endmodule // fifo_to_gpmc_async diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v new file mode 100644 index 000000000..c4cf0ef89 --- /dev/null +++ b/usrp2/gpmc/gpmc_async.v @@ -0,0 +1,108 @@ +////////////////////////////////////////////////////////////////////////////////// + +module gpmc_async + (// GPMC signals + input arst, + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + + // GPIOs for FIFO signalling + output rx_have_data, output tx_have_space, output bus_error, input bus_reset, + + // Wishbone signals + input wb_clk, input wb_rst, + output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + + // FIFO interface + input fifo_clk, input fifo_rst, + output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, + input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, + + output [31:0] debug + ); + + wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); + wire [15:0] EM_D_fifo; + wire [15:0] EM_D_wb; + + assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb; + + wire bus_error_tx, bus_error_rx; + assign bus_error = bus_error_tx | bus_error_rx; + + // CS4 is RAM_2PORT for DATA PATH (high-speed data) + // Writes go into one RAM, reads come from the other + // CS6 is for CONTROL PATH (wishbone) + + // //////////////////////////////////////////// + // TX Data Path + + wire [17:0] tx18_data, tx18b_data; + wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; + wire [15:0] tx_fifo_space, tx_frame_len; + + assign tx_frame_len = 10; + + gpmc_to_fifo_async gpmc_to_fifo_async + (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), + .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), + .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), + .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space), + .bus_error(bus_error_tx) ); + + fifo_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), + .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied()); + + fifo19_to_fifo36 f19_to_f36 + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), + .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i)); + + // //////////////////////////////////////////// + // RX Data Path + + wire [17:0] rx18_data, rx18b_data; + wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; + wire [15:0] rx_fifo_space, rx_frame_len; + assign rx_frame_len = tx_frame_len; + + fifo36_to_fifo18 f18_to_f36 + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o), + .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) ); + + fifo_cascade #(.WIDTH(18), .SIZE(10)) rx_fifo + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .datain(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space), + .dataout(rx18b_data), .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied()); + + fifo_to_gpmc_async fifo_to_gpmc_async + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy), + .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), + .frame_len(rx_frame_len), .bus_error(bus_error_rx) ); + + fifo_watcher fifo_watcher + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .src_rdy(rx18_src_rdy), .dst_rdy(rx18_dst_rdy), .sof(rx18_data[16]), .eof(rx18_data[17]), + .have_packet(), .length(), .next() ); + + assign rx_have_data = 0; + + // //////////////////////////////////////////// + // Control path on CS6 + + gpmc_wb gpmc_wb + (.EM_CLK(EM_CLK), .EM_D_in(EM_D), .EM_D_out(EM_D_wb), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_NCS(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), + .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), + .wb_ack_i(wb_ack_i) ); + + assign debug = 0; + +endmodule // gpmc_async diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v index 31e4fcb69..5fc8134fb 100644 --- a/usrp2/top/u1e/tb_u1e.v +++ b/usrp2/top/u1e/tb_u1e.v @@ -21,9 +21,9 @@ module tb_u1e(); wire [1:0] EM_NBE; reg clk_fpga = 0, rst_fpga = 1; - always #15.625 clk_fpga = ~clk_fpga; + always #15625 clk_fpga = ~clk_fpga; - initial #200 + initial #200000 @(posedge clk_fpga) rst_fpga <= 0; diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 7df7b0a48..40950bf82 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -35,22 +35,24 @@ module u1e_core wire [35:0] tx_data, rx_data; wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy; - gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), - .EM_NOE(EM_NOE), - - .rx_have_data(rx_have_data), .tx_have_space(tx_have_space), - - .wb_clk(wb_clk), .wb_rst(wb_rst), - .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), - .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), - .wb_ack_i(m0_ack), - - .fifo_clk(wb_clk), .fifo_rst(wb_rst), - .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), - .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), - - .debug(debug_gpmc)); + gpmc_async gpmc (.arst(wb_rst), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), + .EM_NOE(EM_NOE), + + .rx_have_data(rx_have_data), .tx_have_space(tx_have_space), + .bus_error(), .bus_reset(0), + + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), + .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), + .wb_ack_i(m0_ack), + + .fifo_clk(wb_clk), .fifo_rst(wb_rst), + .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), + .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), + + .debug(debug_gpmc)); fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo (.clk(wb_clk), .reset(wb_rst), .clear(0), -- cgit v1.2.3 From beccd823da07b7c8b8d95b4688c6e05732f66165 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 15 Apr 2010 17:55:22 -0700 Subject: async seems to work with packet lengths now. Still need to do wishbone regs for gpmc --- usrp2/gpmc/fifo_to_gpmc_async.v | 9 +------- usrp2/gpmc/fifo_watcher.v | 38 +++++++++++++++++++++++++++------- usrp2/gpmc/gpmc_async.v | 10 ++++----- usrp2/models/gpmc_model_async.v | 46 ++++++++++++++++++++++++++++++----------- usrp2/top/u1e/Makefile | 6 +++--- 5 files changed, 72 insertions(+), 37 deletions(-) diff --git a/usrp2/gpmc/fifo_to_gpmc_async.v b/usrp2/gpmc/fifo_to_gpmc_async.v index 4f253e1b5..5ac8b19bd 100644 --- a/usrp2/gpmc/fifo_to_gpmc_async.v +++ b/usrp2/gpmc/fifo_to_gpmc_async.v @@ -8,7 +8,7 @@ module fifo_to_gpmc_async (input clk, input reset, input clear, input [17:0] data_i, input src_rdy_i, output dst_rdy_o, output [15:0] EM_D, input EM_NCS, input EM_NOE, - input [15:0] frame_len, output reg bus_error); + input [15:0] frame_len); // Synchronize the async control signals reg [1:0] cs_del, oe_del; @@ -35,11 +35,4 @@ module fifo_to_gpmc_async assign dst_rdy_o = do_read; - always @(posedge clk) - if(reset) - bus_error <= 0; - else if(dst_rdy_o & ~src_rdy_i) - bus_error <= 1; - - endmodule // fifo_to_gpmc_async diff --git a/usrp2/gpmc/fifo_watcher.v b/usrp2/gpmc/fifo_watcher.v index 8b8f1abfb..da2051b04 100644 --- a/usrp2/gpmc/fifo_watcher.v +++ b/usrp2/gpmc/fifo_watcher.v @@ -2,25 +2,47 @@ module fifo_watcher (input clk, input reset, input clear, - input src_rdy, input dst_rdy, input sof, input eof, - output have_packet, output [15:0] length, input next); + input src_rdy1, input dst_rdy1, input sof1, input eof1, + input src_rdy2, input dst_rdy2, input sof2, input eof2, + output have_packet, output [15:0] length, output reg bus_error); - wire write = src_rdy & dst_rdy & eof; + wire write = src_rdy1 & dst_rdy1 & eof1; + wire read = src_rdy2 & dst_rdy2 & eof2; + wire have_packet_int; + reg [15:0] counter; fifo_short #(.WIDTH(16)) frame_lengths (.clk(clk), .reset(reset), .clear(clear), .datain(counter), .src_rdy_i(write), .dst_rdy_o(), - .dataout(length), .src_rdy_o(have_packet), .dst_rdy_i(next) ); + .dataout(length), .src_rdy_o(have_packet_int), .dst_rdy_i(read) ); - reg [15:0] counter; always @(posedge clk) if(reset | clear) counter <= 1; // Start at 1 - else if(src_rdy & dst_rdy) - if(eof) + else if(src_rdy1 & dst_rdy1) + if(eof1) counter <= 1; else counter <= counter + 1; - + always @(posedge clk) + if(reset | clear) + bus_error <= 0; + else if(dst_rdy2 & ~src_rdy2) + bus_error <= 1; + else if(read & ~have_packet_int) + bus_error <= 1; + + reg in_packet; + assign have_packet = have_packet_int & ~in_packet; + + always @(posedge clk) + if(reset | clear) + in_packet <= 0; + else if(src_rdy2 & dst_rdy2) + if(eof2) + in_packet <= 0; + else + in_packet <= 1; + endmodule // fifo_watcher diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index c4cf0ef89..22e56cc89 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -67,7 +67,6 @@ module gpmc_async wire [17:0] rx18_data, rx18b_data; wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; wire [15:0] rx_fifo_space, rx_frame_len; - assign rx_frame_len = tx_frame_len; fifo36_to_fifo18 f18_to_f36 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), @@ -83,15 +82,14 @@ module gpmc_async (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy), .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), - .frame_len(rx_frame_len), .bus_error(bus_error_rx) ); + .frame_len(rx_frame_len) ); fifo_watcher fifo_watcher (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .src_rdy(rx18_src_rdy), .dst_rdy(rx18_dst_rdy), .sof(rx18_data[16]), .eof(rx18_data[17]), - .have_packet(), .length(), .next() ); + .src_rdy1(rx18_src_rdy), .dst_rdy1(rx18_dst_rdy), .sof1(rx18_data[16]), .eof1(rx18_data[17]), + .src_rdy2(rx18b_src_rdy), .dst_rdy2(rx18b_dst_rdy), .sof2(rx18b_data[16]), .eof2(rx18b_data[17]), + .have_packet(rx_have_data), .length(rx_frame_len), .bus_error(bus_error_rx) ); - assign rx_have_data = 0; - // //////////////////////////////////////////// // Control path on CS6 diff --git a/usrp2/models/gpmc_model_async.v b/usrp2/models/gpmc_model_async.v index 64b596284..beeaee028 100644 --- a/usrp2/models/gpmc_model_async.v +++ b/usrp2/models/gpmc_model_async.v @@ -78,28 +78,50 @@ module gpmc_model_async #1000000; GPMC_Read(1,36); #1000000; - GPMC_Write(0,36,16'h1234); - GPMC_Write(0,38,16'h5678); - GPMC_Write(0,40,16'h9abc); - GPMC_Write(0,11'h2F4,16'hF00D); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - GPMC_Write(0,11'h7FE,16'hDEAD); - #100000; + GPMC_Write(0,0,16'h1234); + GPMC_Write(0,0,16'h5678); + GPMC_Write(0,0,16'h9abc); + GPMC_Write(0,0,16'hF00D); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + #1000000; + GPMC_Write(0,0,16'h1234); + GPMC_Write(0,0,16'h5678); + GPMC_Write(0,0,16'h9abc); + GPMC_Write(0,0,16'hF00D); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'hDEAD); + GPMC_Write(0,0,16'h9876); + #1000000; + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); GPMC_Read(0,0); GPMC_Read(0,0); GPMC_Read(0,0); GPMC_Read(0,0); GPMC_Read(0,0); + #1000000; + GPMC_Read(0,0); + GPMC_Read(0,0); + GPMC_Read(0,0); GPMC_Read(0,0); GPMC_Read(0,0); GPMC_Read(0,0); GPMC_Read(0,0); GPMC_Read(0,0); - #100000; + GPMC_Read(0,0); + GPMC_Read(0,0); + #1000000; GPMC_Read(0,0); #100000000; $finish; diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 160e67894..e15a49e10 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -176,12 +176,12 @@ timing/time_receiver.v \ timing/time_sender.v \ timing/time_sync.v \ timing/timer.v \ -gpmc/gpmc.v \ +gpmc/gpmc_async.v \ gpmc/edge_sync.v \ gpmc/dbsm.v \ gpmc/gpmc_to_fifo_async.v \ -gpmc/gpmc_to_fifo_sync.v \ -gpmc/fifo_to_gpmc_sync.v \ +gpmc/fifo_to_gpmc_async.v \ +gpmc/fifo_watcher.v \ gpmc/gpmc_wb.v \ top/u1e/u1e_core.v \ top/u1e/u1e.ucf \ -- cgit v1.2.3 From d94a0fbea165463a132006a15eb8548cde79a4d2 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 15 Apr 2010 18:55:20 -0700 Subject: access frame length regs from wishbone --- usrp2/gpmc/gpmc_async.v | 8 ++++---- usrp2/top/u1e/u1e_core.v | 20 ++++++++++++++------ 2 files changed, 18 insertions(+), 10 deletions(-) diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 22e56cc89..b1a545907 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -19,6 +19,8 @@ module gpmc_async output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, + input [15:0] tx_frame_len, output [15:0] rx_frame_len, + output [31:0] debug ); @@ -40,9 +42,7 @@ module gpmc_async wire [17:0] tx18_data, tx18b_data; wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; - wire [15:0] tx_fifo_space, tx_frame_len; - - assign tx_frame_len = 10; + wire [15:0] tx_fifo_space; gpmc_to_fifo_async gpmc_to_fifo_async (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), @@ -66,7 +66,7 @@ module gpmc_async wire [17:0] rx18_data, rx18b_data; wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; - wire [15:0] rx_fifo_space, rx_frame_len; + wire [15:0] rx_fifo_space; fifo36_to_fifo18 f18_to_f36 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 40950bf82..30396de3a 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -34,6 +34,8 @@ module u1e_core wire [35:0] tx_data, rx_data; wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy; + reg [15:0] tx_frame_len; + wire [15:0] rx_frame_len; gpmc_async gpmc (.arst(wb_rst), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), @@ -51,7 +53,8 @@ module u1e_core .fifo_clk(wb_clk), .fifo_rst(wb_rst), .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), - + + .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), .debug(debug_gpmc)); fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo @@ -133,11 +136,13 @@ module u1e_core reg [15:0] reg_leds, reg_cgen_ctrl, reg_test; - localparam REG_LEDS = 7'd0; // out - localparam REG_SWITCHES = 7'd2; // in - localparam REG_CGEN_CTRL = 7'd4; // out - localparam REG_CGEN_ST = 7'd6; // in - localparam REG_TEST = 7'd8; // out + localparam REG_LEDS = 7'd0; // out + localparam REG_SWITCHES = 7'd2; // in + localparam REG_CGEN_CTRL = 7'd4; // out + localparam REG_CGEN_ST = 7'd6; // in + localparam REG_TEST = 7'd8; // out + localparam REG_RX_FRAMELEN = 7'd10; // out + localparam REG_TX_FRAMELEN = 7'd12; // in always @(posedge wb_clk) if(wb_rst) @@ -155,6 +160,8 @@ module u1e_core reg_cgen_ctrl <= s0_dat_mosi; REG_TEST : reg_test <= s0_dat_mosi; + REG_TX_FRAMELEN : + tx_frame_len <= s0_dat_mosi; endcase // case (s0_adr[6:0]) assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board @@ -166,6 +173,7 @@ module u1e_core (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : (s0_adr[6:0] == REG_TEST) ? reg_test : + (s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len : 16'hBEEF; assign s0_ack = s0_stb & s0_cyc; -- cgit v1.2.3 From 23316f1ac73c917757a70980c3a9f251852ee426 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 15 Apr 2010 21:27:03 -0700 Subject: added pps and time capability --- usrp2/top/u1e/u1e.ucf | 2 +- usrp2/top/u1e/u1e.v | 6 ++++-- usrp2/top/u1e/u1e_core.v | 18 ++++++++++++++++-- 3 files changed, 21 insertions(+), 5 deletions(-) diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index c39759d0b..1c8dfc197 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -208,7 +208,7 @@ NET "dip_sw<0>" LOC = "J7" ; #NET "TXSYNC" LOC = "U18" ; #NET "TXBLANK" LOC = "U19" ; -#NET "PPS_IN" LOC = "M17" ; +NET "PPS_IN" LOC = "M17" ; NET "io_tx<0>" LOC = "AB20" ; NET "io_tx<1>" LOC = "Y17" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index ab270879c..b8f716d26 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -20,7 +20,8 @@ module u1e input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls - inout [15:0] io_tx, inout [15:0] io_rx + inout [15:0] io_tx, inout [15:0] io_rx, + input PPS_IN ); // FPGA-specific pins connections @@ -50,6 +51,7 @@ module u1e .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel), .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), - .io_tx(io_tx), .io_rx(io_rx) ); + .io_tx(io_tx), .io_rx(io_rx), + .pps_in(PPS_IN) ); endmodule // u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 30396de3a..9e65faeed 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -13,7 +13,9 @@ module u1e_core input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, - inout [15:0] io_tx, inout [15:0] io_rx + inout [15:0] io_tx, inout [15:0] io_rx, + + input pps_in ); wire wb_clk = clk_fpga; @@ -249,7 +251,19 @@ module u1e_core (.clk_i(wb_clk), .rst_i(wb_rst), .adr_i(s6_adr), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), - .run_rx(), .run_tx(), .master_time(0), .ctrl_lines(atr_lines)); + .run_rx(0), .run_tx(0), .ctrl_lines(atr_lines)); + + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing + + localparam SR_TIME64 = 0; + wire pps_int; + wire [63:0] vita_time; + + time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit + (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry -- cgit v1.2.3 From 839d9c39542db356ad1b955e3a3d9e7aabb071bc Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 16 Apr 2010 12:58:42 +0000 Subject: pulled in master and got usrp-e code compiling --- host/apps/omap_debug/fetch-kernel.sh | 2 +- host/apps/omap_debug/fetch-module.sh | 2 +- host/lib/CMakeLists.txt | 3 +- host/lib/usrp/usrp_e/dboard_iface.cpp | 218 ++++++++++++++++++++++++++++++ host/lib/usrp/usrp_e/dboard_impl.cpp | 6 +- host/lib/usrp/usrp_e/dboard_interface.cpp | 212 ----------------------------- host/lib/usrp/usrp_e/mboard_impl.cpp | 4 +- host/lib/usrp/usrp_e/usrp_e_iface.cpp | 135 ++++++++++++++++++ host/lib/usrp/usrp_e/usrp_e_iface.hpp | 97 +++++++++++++ host/lib/usrp/usrp_e/usrp_e_impl.cpp | 89 ++---------- host/lib/usrp/usrp_e/usrp_e_impl.hpp | 26 +--- 11 files changed, 478 insertions(+), 316 deletions(-) create mode 100644 host/lib/usrp/usrp_e/dboard_iface.cpp delete mode 100644 host/lib/usrp/usrp_e/dboard_interface.cpp create mode 100644 host/lib/usrp/usrp_e/usrp_e_iface.cpp create mode 100644 host/lib/usrp/usrp_e/usrp_e_iface.hpp diff --git a/host/apps/omap_debug/fetch-kernel.sh b/host/apps/omap_debug/fetch-kernel.sh index a3cddb339..f25f139fa 100755 --- a/host/apps/omap_debug/fetch-kernel.sh +++ b/host/apps/omap_debug/fetch-kernel.sh @@ -1,4 +1,4 @@ -if [ $GHQ]; then +if [ $GHQ ]; then scp $GHQ_USER@astro:/workspace/usrp1-e-dev/kernel_usrp/arch/arm/boot/uImage /media/mmcblk0p1/uImage else scp balister@192.168.1.167:src/git/kernel_usrp/arch/arm/boot/uImage /media/mmcblk0p1/uImage diff --git a/host/apps/omap_debug/fetch-module.sh b/host/apps/omap_debug/fetch-module.sh index 52fbd4040..0957ad7b4 100755 --- a/host/apps/omap_debug/fetch-module.sh +++ b/host/apps/omap_debug/fetch-module.sh @@ -1,5 +1,5 @@ if [ $GHQ ]; then - scp $GHQ_USER@astro:/workspace/usrp1-e-dev/kernel_usrp/drivers/misc/usrp_e.ko /lib/modules/2.6.33-rc3/kernel/drivers/misc + scp $GHQ_USER@astro:/workspace/usrp1-e-dev/kernel_usrp/drivers/misc/usrp_e.ko /lib/modules/2.6.34-rc1/kernel/drivers/misc else scp balister@192.168.1.167:src/git/kernel_usrp/drivers/misc/usrp_e.ko /lib/modules/2.6.33-rc3/kernel/drivers/misc fi diff --git a/host/lib/CMakeLists.txt b/host/lib/CMakeLists.txt index dfcb88ec9..ff7f2c0df 100644 --- a/host/lib/CMakeLists.txt +++ b/host/lib/CMakeLists.txt @@ -138,11 +138,12 @@ IF(HAVE_USRP_E_REQUIRED_HEADERS) MESSAGE(STATUS " Building usrp-e support.") LIST(APPEND libuhd_sources usrp/usrp_e/dboard_impl.cpp - usrp/usrp_e/dboard_interface.cpp + usrp/usrp_e/dboard_iface.cpp usrp/usrp_e/dsp_impl.cpp usrp/usrp_e/fpga-downloader.cc usrp/usrp_e/mboard_impl.cpp usrp/usrp_e/usrp_e_impl.cpp + usrp/usrp_e/usrp_e_iface.cpp ) ELSE(HAVE_USRP_E_REQUIRED_HEADERS) MESSAGE(STATUS " Skipping usrp-e support.") diff --git a/host/lib/usrp/usrp_e/dboard_iface.cpp b/host/lib/usrp/usrp_e/dboard_iface.cpp new file mode 100644 index 000000000..12e8fe206 --- /dev/null +++ b/host/lib/usrp/usrp_e/dboard_iface.cpp @@ -0,0 +1,218 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "usrp_e_iface.hpp" +#include "usrp_e_regs.hpp" +#include +#include +#include +#include +#include //i2c and spi constants + +using namespace uhd::usrp; + +class usrp_e_dboard_iface : public dboard_iface{ +public: + usrp_e_dboard_iface(usrp_e_iface::sptr iface); + ~usrp_e_dboard_iface(void); + + void write_aux_dac(unit_t, int, float); + float read_aux_adc(unit_t, int); + + void set_atr_reg(unit_t, atr_reg_t, boost::uint16_t); + void set_gpio_ddr(unit_t, boost::uint16_t); + boost::uint16_t read_gpio(unit_t); + + void write_i2c(int, const byte_vector_t &); + byte_vector_t read_i2c(int, size_t); + + void write_spi( + unit_t unit, + const spi_config_t &config, + boost::uint32_t data, + size_t num_bits + ); + + boost::uint32_t read_write_spi( + unit_t unit, + const spi_config_t &config, + boost::uint32_t data, + size_t num_bits + ); + + double get_clock_rate(unit_t); + void set_clock_enabled(unit_t, bool); + +private: + usrp_e_iface::sptr _iface; +}; + +/*********************************************************************** + * Make Function + **********************************************************************/ +dboard_iface::sptr make_usrp_e_dboard_iface(usrp_e_iface::sptr iface){ + return dboard_iface::sptr(new usrp_e_dboard_iface(iface)); +} + +/*********************************************************************** + * Structors + **********************************************************************/ +usrp_e_dboard_iface::usrp_e_dboard_iface(usrp_e_iface::sptr iface){ + _iface = iface; +} + +usrp_e_dboard_iface::~usrp_e_dboard_iface(void){ + /* NOP */ +} + +/*********************************************************************** + * Clock Rates + **********************************************************************/ +double usrp_e_dboard_iface::get_clock_rate(unit_t){ + throw std::runtime_error("not implemented"); +} + +void usrp_e_dboard_iface::set_clock_enabled(unit_t, bool){ + throw std::runtime_error("not implemented"); +} + +/*********************************************************************** + * GPIO + **********************************************************************/ +void usrp_e_dboard_iface::set_gpio_ddr(unit_t bank, boost::uint16_t value){ + //define mapping of gpio bank to register address + static const uhd::dict bank_to_addr = boost::assign::map_list_of + (UNIT_RX, UE_REG_GPIO_RX_DDR) + (UNIT_TX, UE_REG_GPIO_TX_DDR) + ; + _iface->poke16(bank_to_addr[bank], value); +} + +boost::uint16_t usrp_e_dboard_iface::read_gpio(unit_t bank){ + //define mapping of gpio bank to register address + static const uhd::dict bank_to_addr = boost::assign::map_list_of + (UNIT_RX, UE_REG_GPIO_RX_IO) + (UNIT_TX, UE_REG_GPIO_TX_IO) + ; + return _iface->peek16(bank_to_addr[bank]); +} + +void usrp_e_dboard_iface::set_atr_reg(unit_t bank, atr_reg_t atr, boost::uint16_t value){ + //define mapping of bank to atr regs to register address + static const uhd::dict< + unit_t, uhd::dict + > bank_to_atr_to_addr = boost::assign::map_list_of + (UNIT_RX, boost::assign::map_list_of + (ATR_REG_IDLE, UE_REG_ATR_IDLE_RXSIDE) + (ATR_REG_TX_ONLY, UE_REG_ATR_INTX_RXSIDE) + (ATR_REG_RX_ONLY, UE_REG_ATR_INRX_RXSIDE) + (ATR_REG_FULL_DUPLEX, UE_REG_ATR_FULL_RXSIDE) + ) + (UNIT_TX, boost::assign::map_list_of + (ATR_REG_IDLE, UE_REG_ATR_IDLE_TXSIDE) + (ATR_REG_TX_ONLY, UE_REG_ATR_INTX_TXSIDE) + (ATR_REG_RX_ONLY, UE_REG_ATR_INRX_TXSIDE) + (ATR_REG_FULL_DUPLEX, UE_REG_ATR_FULL_TXSIDE) + ) + ; + _iface->poke16(bank_to_atr_to_addr[bank][atr], value); +} + +/*********************************************************************** + * SPI + **********************************************************************/ +/*! + * Static function to convert a unit type to a spi slave device number. + * \param unit the dboard interface unit type enum + * \return the slave device number + */ +static boost::uint32_t unit_to_otw_spi_dev(dboard_iface::unit_t unit){ + switch(unit){ + case dboard_iface::UNIT_TX: return UE_SPI_CTRL_TXNEG; + case dboard_iface::UNIT_RX: return UE_SPI_CTRL_RXNEG; + } + throw std::invalid_argument("unknown unit type"); +} + +void usrp_e_dboard_iface::write_spi( + unit_t unit, + const spi_config_t &config, + boost::uint32_t data, + size_t num_bits +){ + _iface->transact_spi(unit_to_otw_spi_dev(unit), config, data, num_bits, false /*no rb*/); +} + +boost::uint32_t usrp_e_dboard_iface::read_write_spi( + unit_t unit, + const spi_config_t &config, + boost::uint32_t data, + size_t num_bits +){ + return _iface->transact_spi(unit_to_otw_spi_dev(unit), config, data, num_bits, true /*rb*/); +} + +/*********************************************************************** + * I2C + **********************************************************************/ +static const size_t max_i2c_data_bytes = 10; + +void usrp_e_dboard_iface::write_i2c(int i2c_addr, const byte_vector_t &buf){ + //allocate some memory for this transaction + ASSERT_THROW(buf.size() <= max_i2c_data_bytes); + boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; + + //load the data struct + usrp_e_i2c &data = reinterpret_cast(mem); + data.addr = i2c_addr; + data.len = buf.size(); + std::copy(buf.begin(), buf.end(), data.data); + + //call the spi ioctl + _iface->ioctl(USRP_E_I2C_WRITE, &data); +} + +dboard_iface::byte_vector_t usrp_e_dboard_iface::read_i2c(int i2c_addr, size_t num_bytes){ + //allocate some memory for this transaction + ASSERT_THROW(num_bytes <= max_i2c_data_bytes); + boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; + + //load the data struct + usrp_e_i2c &data = reinterpret_cast(mem); + data.addr = i2c_addr; + data.len = num_bytes; + + //call the spi ioctl + _iface->ioctl(USRP_E_I2C_READ, &data); + + //unload the data + byte_vector_t ret(data.len); + ASSERT_THROW(ret.size() == num_bytes); + std::copy(data.data, data.data+ret.size(), ret.begin()); + return ret; +} + +/*********************************************************************** + * Aux DAX/ADC + **********************************************************************/ +void usrp_e_dboard_iface::write_aux_dac(dboard_iface::unit_t unit, int which, float value){ + throw std::runtime_error("not implemented"); +} + +float usrp_e_dboard_iface::read_aux_adc(dboard_iface::unit_t unit, int which){ + throw std::runtime_error("not implemented"); +} diff --git a/host/lib/usrp/usrp_e/dboard_impl.cpp b/host/lib/usrp/usrp_e/dboard_impl.cpp index 7c87361e0..df0f1d9a9 100644 --- a/host/lib/usrp/usrp_e/dboard_impl.cpp +++ b/host/lib/usrp/usrp_e/dboard_impl.cpp @@ -28,11 +28,11 @@ void usrp_e_impl::dboard_init(void){ dboard_id_t tx_dboard_id = dboard_id::NONE; //create a new dboard interface and manager - dboard_interface::sptr dboard_interface( - make_usrp_e_dboard_interface(this) + dboard_iface::sptr dboard_iface( + make_usrp_e_dboard_iface(_iface) ); _dboard_manager = dboard_manager::make( - rx_dboard_id, tx_dboard_id, dboard_interface + rx_dboard_id, tx_dboard_id, dboard_iface ); //setup the dboard proxies diff --git a/host/lib/usrp/usrp_e/dboard_interface.cpp b/host/lib/usrp/usrp_e/dboard_interface.cpp deleted file mode 100644 index 47948f3d0..000000000 --- a/host/lib/usrp/usrp_e/dboard_interface.cpp +++ /dev/null @@ -1,212 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "usrp_e_impl.hpp" -#include "usrp_e_regs.hpp" -#include -#include -#include -#include //std::copy -#include - -using namespace uhd::usrp; - -class usrp_e_dboard_interface : public dboard_interface{ -public: - usrp_e_dboard_interface(usrp_e_impl *impl); - ~usrp_e_dboard_interface(void); - - void write_aux_dac(unit_type_t, int, int); - int read_aux_adc(unit_type_t, int); - - void set_atr_reg(gpio_bank_t, atr_reg_t, boost::uint16_t); - void set_gpio_ddr(gpio_bank_t, boost::uint16_t); - boost::uint16_t read_gpio(gpio_bank_t); - - void write_i2c(int, const byte_vector_t &); - byte_vector_t read_i2c(int, size_t); - - double get_rx_clock_rate(void); - double get_tx_clock_rate(void); - -private: - byte_vector_t transact_spi( - spi_dev_t dev, - spi_edge_t edge, - const byte_vector_t &buf, - bool readback - ); - - usrp_e_impl *_impl; -}; - -/*********************************************************************** - * Make Function - **********************************************************************/ -dboard_interface::sptr make_usrp_e_dboard_interface(usrp_e_impl *impl){ - return dboard_interface::sptr(new usrp_e_dboard_interface(impl)); -} - -/*********************************************************************** - * Structors - **********************************************************************/ -usrp_e_dboard_interface::usrp_e_dboard_interface(usrp_e_impl *impl){ - _impl = impl; -} - -usrp_e_dboard_interface::~usrp_e_dboard_interface(void){ - /* NOP */ -} - -/*********************************************************************** - * Clock Rates - **********************************************************************/ -double usrp_e_dboard_interface::get_rx_clock_rate(void){ - throw std::runtime_error("not implemented"); -} - -double usrp_e_dboard_interface::get_tx_clock_rate(void){ - throw std::runtime_error("not implemented"); -} - -/*********************************************************************** - * GPIO - **********************************************************************/ -void usrp_e_dboard_interface::set_gpio_ddr(gpio_bank_t bank, boost::uint16_t value){ - //define mapping of gpio bank to register address - static const uhd::dict bank_to_addr = boost::assign::map_list_of - (GPIO_BANK_RX, UE_REG_GPIO_RX_DDR) - (GPIO_BANK_TX, UE_REG_GPIO_TX_DDR) - ; - _impl->poke16(bank_to_addr[bank], value); -} - -boost::uint16_t usrp_e_dboard_interface::read_gpio(gpio_bank_t bank){ - //define mapping of gpio bank to register address - static const uhd::dict bank_to_addr = boost::assign::map_list_of - (GPIO_BANK_RX, UE_REG_GPIO_RX_IO) - (GPIO_BANK_TX, UE_REG_GPIO_TX_IO) - ; - return _impl->peek16(bank_to_addr[bank]); -} - -void usrp_e_dboard_interface::set_atr_reg(gpio_bank_t bank, atr_reg_t atr, boost::uint16_t value){ - //define mapping of bank to atr regs to register address - static const uhd::dict< - gpio_bank_t, uhd::dict - > bank_to_atr_to_addr = boost::assign::map_list_of - (GPIO_BANK_RX, boost::assign::map_list_of - (ATR_REG_IDLE, UE_REG_ATR_IDLE_RXSIDE) - (ATR_REG_TX_ONLY, UE_REG_ATR_INTX_RXSIDE) - (ATR_REG_RX_ONLY, UE_REG_ATR_INRX_RXSIDE) - (ATR_REG_FULL_DUPLEX, UE_REG_ATR_FULL_RXSIDE) - ) - (GPIO_BANK_TX, boost::assign::map_list_of - (ATR_REG_IDLE, UE_REG_ATR_IDLE_TXSIDE) - (ATR_REG_TX_ONLY, UE_REG_ATR_INTX_TXSIDE) - (ATR_REG_RX_ONLY, UE_REG_ATR_INRX_TXSIDE) - (ATR_REG_FULL_DUPLEX, UE_REG_ATR_FULL_TXSIDE) - ) - ; - _impl->poke16(bank_to_atr_to_addr[bank][atr], value); -} - -/*********************************************************************** - * SPI - **********************************************************************/ -dboard_interface::byte_vector_t usrp_e_dboard_interface::transact_spi( - spi_dev_t dev, - spi_edge_t edge, - const byte_vector_t &buf, - bool readback -){ - //load data struct - usrp_e_spi data; - data.readback = (readback)? UE_SPI_TXRX : UE_SPI_TXONLY; - data.slave = (dev == SPI_DEV_RX)? UE_SPI_CTRL_RXNEG : UE_SPI_CTRL_TXNEG; - data.length = buf.size() * 8; //bytes to bits - boost::uint8_t *data_bytes = reinterpret_cast(&data.data); - - //load the data - ASSERT_THROW(buf.size() <= sizeof(data.data)); - std::copy(buf.begin(), buf.end(), data_bytes); - - //load the flags - data.flags = 0; - data.flags |= (edge == SPI_EDGE_RISE)? UE_SPI_LATCH_RISE : UE_SPI_LATCH_FALL; - data.flags |= (edge == SPI_EDGE_RISE)? UE_SPI_PUSH_RISE : UE_SPI_PUSH_FALL; - - //call the spi ioctl - _impl->ioctl(USRP_E_SPI, &data); - - //unload the data - byte_vector_t ret(data.length/8); //bits to bytes - ASSERT_THROW(ret.size() <= sizeof(data.data)); - std::copy(data_bytes, data_bytes+ret.size(), ret.begin()); - return ret; -} - -/*********************************************************************** - * I2C - **********************************************************************/ -static const size_t max_i2c_data_bytes = 10; - -void usrp_e_dboard_interface::write_i2c(int i2c_addr, const byte_vector_t &buf){ - //allocate some memory for this transaction - ASSERT_THROW(buf.size() <= max_i2c_data_bytes); - boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; - - //load the data struct - usrp_e_i2c &data = reinterpret_cast(mem); - data.addr = i2c_addr; - data.len = buf.size(); - std::copy(buf.begin(), buf.end(), data.data); - - //call the spi ioctl - _impl->ioctl(USRP_E_I2C_WRITE, &data); -} - -dboard_interface::byte_vector_t usrp_e_dboard_interface::read_i2c(int i2c_addr, size_t num_bytes){ - //allocate some memory for this transaction - ASSERT_THROW(num_bytes <= max_i2c_data_bytes); - boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; - - //load the data struct - usrp_e_i2c &data = reinterpret_cast(mem); - data.addr = i2c_addr; - data.len = num_bytes; - - //call the spi ioctl - _impl->ioctl(USRP_E_I2C_READ, &data); - - //unload the data - byte_vector_t ret(data.len); - ASSERT_THROW(ret.size() == num_bytes); - std::copy(data.data, data.data+ret.size(), ret.begin()); - return ret; -} - -/*********************************************************************** - * Aux DAX/ADC - **********************************************************************/ -void usrp_e_dboard_interface::write_aux_dac(dboard_interface::unit_type_t unit, int which, int value){ - throw std::runtime_error("not implemented"); -} - -int usrp_e_dboard_interface::read_aux_adc(dboard_interface::unit_type_t unit, int which){ - throw std::runtime_error("not implemented"); -} diff --git a/host/lib/usrp/usrp_e/mboard_impl.cpp b/host/lib/usrp/usrp_e/mboard_impl.cpp index ba15c394d..2d225c6ea 100644 --- a/host/lib/usrp/usrp_e/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e/mboard_impl.cpp @@ -75,8 +75,8 @@ void usrp_e_impl::mboard_get(const wax::obj &key_, wax::obj &val){ val = prop_names_t(1, ""); //vector of size 1 with empty string return; - case MBOARD_PROP_CLOCK_RATE: - //val = TODO probably remove this property + case MBOARD_PROP_STREAM_CMD: + //val = TODO return; case MBOARD_PROP_RX_DSP: diff --git a/host/lib/usrp/usrp_e/usrp_e_iface.cpp b/host/lib/usrp/usrp_e/usrp_e_iface.cpp new file mode 100644 index 000000000..d4c988211 --- /dev/null +++ b/host/lib/usrp/usrp_e/usrp_e_iface.cpp @@ -0,0 +1,135 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "usrp_e_iface.hpp" +#include //ioctl +#include //ioctl structures and constants +#include +#include + +class usrp_e_iface_impl : public usrp_e_iface{ +public: + + /******************************************************************* + * Structors + ******************************************************************/ + usrp_e_iface_impl(int node_fd){ + _node_fd = node_fd; + } + + ~usrp_e_iface_impl(void){ + /* NOP */ + } + + /******************************************************************* + * IOCTL: provides the communication base for all other calls + ******************************************************************/ + void ioctl(int request, void *mem){ + if (::ioctl(_node_fd, request, mem) < 0){ + throw std::runtime_error(str( + boost::format("ioctl failed with request %d") % request + )); + } + } + + /******************************************************************* + * Peek and Poke + ******************************************************************/ + void poke32(boost::uint32_t addr, boost::uint32_t value){ + //load the data struct + usrp_e_ctl32 data; + data.offset = addr; + data.count = 1; + data.buf[0] = value; + + //call the ioctl + this->ioctl(USRP_E_WRITE_CTL32, &data); + } + + void poke16(boost::uint32_t addr, boost::uint16_t value){ + //load the data struct + usrp_e_ctl16 data; + data.offset = addr; + data.count = 1; + data.buf[0] = value; + + //call the ioctl + this->ioctl(USRP_E_WRITE_CTL16, &data); + } + + boost::uint32_t peek32(boost::uint32_t addr){ + //load the data struct + usrp_e_ctl32 data; + data.offset = addr; + data.count = 1; + + //call the ioctl + this->ioctl(USRP_E_READ_CTL32, &data); + + return data.buf[0]; + } + + boost::uint16_t peek16(boost::uint32_t addr){ + //load the data struct + usrp_e_ctl16 data; + data.offset = addr; + data.count = 1; + + //call the ioctl + this->ioctl(USRP_E_READ_CTL16, &data); + + return data.buf[0]; + } + + /******************************************************************* + * SPI + ******************************************************************/ + boost::uint32_t transact_spi( + int which_slave, + const uhd::usrp::spi_config_t &config, + boost::uint32_t bits, + size_t num_bits, + bool readback + ){ + //load data struct + usrp_e_spi data; + data.readback = (readback)? UE_SPI_TXRX : UE_SPI_TXONLY; + data.slave = which_slave; + data.length = num_bits; + data.data = bits; + + //load the flags + data.flags = 0; + data.flags |= (config.miso_edge == uhd::usrp::spi_config_t::EDGE_RISE)? UE_SPI_LATCH_RISE : UE_SPI_LATCH_FALL; + data.flags |= (config.mosi_edge == uhd::usrp::spi_config_t::EDGE_RISE)? UE_SPI_PUSH_FALL : UE_SPI_PUSH_RISE; + + //call the spi ioctl + this->ioctl(USRP_E_SPI, &data); + + //unload the data + return data.data; + } + +private: int _node_fd; +}; + +/*********************************************************************** + * Public Make Function + **********************************************************************/ +usrp_e_iface::sptr usrp_e_iface::make(int node_fd){ + return sptr(new usrp_e_iface_impl(node_fd)); +} diff --git a/host/lib/usrp/usrp_e/usrp_e_iface.hpp b/host/lib/usrp/usrp_e/usrp_e_iface.hpp new file mode 100644 index 000000000..4fc3bb33d --- /dev/null +++ b/host/lib/usrp/usrp_e/usrp_e_iface.hpp @@ -0,0 +1,97 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_USRP_E_IFACE_HPP +#define INCLUDED_USRP_E_IFACE_HPP + +#include +#include //spi config +#include +#include +#include + +/*! + * The usrp-e interface class: + * Provides a set of functions to implementation layer. + * Including spi, peek, poke, control... + */ +class usrp_e_iface : boost::noncopyable{ +public: + typedef boost::shared_ptr sptr; + + /*! + * Make a new usrp-e interface with the control transport. + * \param node_fd the file descriptor for the kernel module node + * \return a new usrp-e interface object + */ + static sptr make(int node_fd); + + /*! + * Perform an ioctl call on the device node file descriptor. + * This will throw when the internal ioctl call fails. + * \param request the control word + * \param mem pointer to some memory + */ + virtual void ioctl(int request, void *mem) = 0; + + /*! + * Write a register (32 bits) + * \param addr the address + * \param data the 32bit data + */ + virtual void poke32(boost::uint32_t addr, boost::uint32_t data) = 0; + + /*! + * Read a register (32 bits) + * \param addr the address + * \return the 32bit data + */ + virtual boost::uint32_t peek32(boost::uint32_t addr) = 0; + + /*! + * Write a register (16 bits) + * \param addr the address + * \param data the 16bit data + */ + virtual void poke16(boost::uint32_t addr, boost::uint16_t data) = 0; + + /*! + * Read a register (16 bits) + * \param addr the address + * \return the 16bit data + */ + virtual boost::uint16_t peek16(boost::uint32_t addr) = 0; + + /*! + * Perform an spi transaction. + * \param which_slave the slave device number + * \param config spi config args + * \param data the bits to write + * \param num_bits how many bits in data + * \param readback true to readback a value + * \return spi data if readback set + */ + virtual boost::uint32_t transact_spi( + int which_slave, + const uhd::usrp::spi_config_t &config, + boost::uint32_t data, + size_t num_bits, + bool readback + ) = 0; +}; + +#endif /* INCLUDED_USRP_E_IFACE_HPP */ diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.cpp b/host/lib/usrp/usrp_e/usrp_e_impl.cpp index 3fefd6787..4d08210e2 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.cpp @@ -22,8 +22,6 @@ #include #include #include //open -#include //ioctl -#include using namespace uhd; using namespace uhd::usrp; @@ -43,30 +41,24 @@ static std::string abs_path(const std::string &file_path){ /*********************************************************************** * Discovery **********************************************************************/ -device_addrs_t usrp_e::find(const device_addr_t &device_addr){ +device_addrs_t usrp_e::find(const device_addr_t &hint){ device_addrs_t usrp_e_addrs; - //if a node was provided, use it and only it - if (device_addr.has_key("node")){ - if (not fs::exists(device_addr["node"])) return usrp_e_addrs; + //device node not provided, assume its 0 + if (not hint.has_key("node")){ + device_addr_t new_addr = hint; + new_addr["node"] = "/dev/usrp_e0"; + return usrp_e::find(new_addr); + } + + //use the given device node name + if (fs::exists(hint["node"])){ device_addr_t new_addr; new_addr["name"] = "USRP-E"; - new_addr["node"] = abs_path(device_addr["node"]); + new_addr["node"] = abs_path(hint["node"]); usrp_e_addrs.push_back(new_addr); } - //otherwise look for a few nodes at small indexes - else{ - for(size_t i = 0; i < 5; i++){ - std::string node = str(boost::format("/dev/usrp1_e%d") % i); - if (not fs::exists(node)) continue; - device_addr_t new_addr; - new_addr["name"] = "USRP-E"; - new_addr["node"] = abs_path(node); - usrp_e_addrs.push_back(new_addr); - } - } - return usrp_e_addrs; } @@ -88,6 +80,8 @@ usrp_e_impl::usrp_e_impl(const std::string &node){ )); } + _iface = usrp_e_iface::make(_node_fd); + //initialize the mboard mboard_init(); @@ -104,63 +98,6 @@ usrp_e_impl::~usrp_e_impl(void){ ::close(_node_fd); } -/*********************************************************************** - * Misc Methods - **********************************************************************/ -void usrp_e_impl::ioctl(int request, void *mem){ - if (::ioctl(_node_fd, request, mem) < 0){ - throw std::runtime_error(str( - boost::format("ioctl failed with request %d") % request - )); - } -} - -void usrp_e_impl::poke32(boost::uint32_t addr, boost::uint32_t value){ - //load the data struct - usrp_e_ctl32 data; - data.offset = addr; - data.count = 1; - data.buf[0] = value; - - //call the ioctl - this->ioctl(USRP_E_WRITE_CTL32, &data); -} - -void usrp_e_impl::poke16(boost::uint32_t addr, boost::uint16_t value){ - //load the data struct - usrp_e_ctl16 data; - data.offset = addr; - data.count = 1; - data.buf[0] = value; - - //call the ioctl - this->ioctl(USRP_E_WRITE_CTL16, &data); -} - -boost::uint32_t usrp_e_impl::peek32(boost::uint32_t addr){ - //load the data struct - usrp_e_ctl32 data; - data.offset = addr; - data.count = 1; - - //call the ioctl - this->ioctl(USRP_E_READ_CTL32, &data); - - return data.buf[0]; -} - -boost::uint16_t usrp_e_impl::peek16(boost::uint32_t addr){ - //load the data struct - usrp_e_ctl16 data; - data.offset = addr; - data.count = 1; - - //call the ioctl - this->ioctl(USRP_E_READ_CTL16, &data); - - return data.buf[0]; -} - /*********************************************************************** * Device Get **********************************************************************/ diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index 21023ae55..08ace2ffb 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -15,21 +15,20 @@ // along with this program. If not, see . // -#include +#include "usrp_e_iface.hpp" #include +#include #include #ifndef INCLUDED_USRP_E_IMPL_HPP #define INCLUDED_USRP_E_IMPL_HPP -class usrp_e_impl; // dummy class declaration - /*! - * Make a usrp_e dboard interface. - * \param impl a pointer to the usrp_e impl object + * Make a usrp-e dboard interface. + * \param iface the usrp-e interface object * \return a sptr to a new dboard interface */ -uhd::usrp::dboard_interface::sptr make_usrp_e_dboard_interface(usrp_e_impl *impl); +uhd::usrp::dboard_iface::sptr make_usrp_e_dboard_iface(usrp_e_iface::sptr iface); /*! * Simple wax obj proxy class: @@ -84,22 +83,9 @@ public: size_t send(const boost::asio::const_buffer &, const uhd::tx_metadata_t &, const uhd::io_type_t &); size_t recv(const boost::asio::mutable_buffer &, uhd::rx_metadata_t &, const uhd::io_type_t &); - /*! - * Perform an ioctl call on the device node file descriptor. - * This will throw when the internal ioctl call fails. - * \param request the control word - * \param mem pointer to some memory - */ - void ioctl(int request, void *mem); - - //peekers and pokers - void poke32(boost::uint32_t addr, boost::uint32_t value); - void poke16(boost::uint32_t addr, boost::uint16_t value); - boost::uint32_t peek32(boost::uint32_t addr); - boost::uint16_t peek16(boost::uint32_t addr); - private: static const size_t _max_num_samples = 2048/sizeof(boost::uint32_t); + usrp_e_iface::sptr _iface; int _node_fd; uhd::clock_config_t _clock_config; -- cgit v1.2.3 From de668d9924b6176e8296dee5929aab1e37374d8b Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Tue, 20 Apr 2010 21:46:51 +0000 Subject: Add scripts to read and write board id info into usrp e id eeprom --- host/apps/omap_debug/read_board_id.sh | 10 ++++++++++ host/apps/omap_debug/write_board_id.sh | 10 ++++++++++ 2 files changed, 20 insertions(+) create mode 100755 host/apps/omap_debug/read_board_id.sh create mode 100755 host/apps/omap_debug/write_board_id.sh diff --git a/host/apps/omap_debug/read_board_id.sh b/host/apps/omap_debug/read_board_id.sh new file mode 100755 index 000000000..96081f219 --- /dev/null +++ b/host/apps/omap_debug/read_board_id.sh @@ -0,0 +1,10 @@ +#!/bin/sh + +i2cget -y 3 0x51 0x00 b +i2cget -y 3 0x51 0x01 b +i2cget -y 3 0x51 0x02 b +i2cget -y 3 0x51 0x03 b +i2cget -y 3 0x51 0x04 b +i2cget -y 3 0x51 0x05 b + + diff --git a/host/apps/omap_debug/write_board_id.sh b/host/apps/omap_debug/write_board_id.sh new file mode 100755 index 000000000..139394a4c --- /dev/null +++ b/host/apps/omap_debug/write_board_id.sh @@ -0,0 +1,10 @@ +#!/bin/sh + +i2cset -y 3 0x51 0x00 0x00 +i2cset -y 3 0x51 0x01 0x03 +i2cset -y 3 0x51 0x02 0x00 +i2cset -y 3 0x51 0x03 0x00 +i2cset -y 3 0x51 0x04 0x01 +i2cset -y 3 0x51 0x05 0x00 + + -- cgit v1.2.3 From bbfb3a7a9554c06fd54c3c572eb9a716627cc50c Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 20 Apr 2010 11:06:28 +0000 Subject: Fix script to write board id eeprom. --- host/apps/omap_debug/write_board_id.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/host/apps/omap_debug/write_board_id.sh b/host/apps/omap_debug/write_board_id.sh index 139394a4c..067269c64 100755 --- a/host/apps/omap_debug/write_board_id.sh +++ b/host/apps/omap_debug/write_board_id.sh @@ -3,8 +3,8 @@ i2cset -y 3 0x51 0x00 0x00 i2cset -y 3 0x51 0x01 0x03 i2cset -y 3 0x51 0x02 0x00 -i2cset -y 3 0x51 0x03 0x00 -i2cset -y 3 0x51 0x04 0x01 +i2cset -y 3 0x51 0x03 0x01 +i2cset -y 3 0x51 0x04 0x00 i2cset -y 3 0x51 0x05 0x00 -- cgit v1.2.3 From 0e11c5ddbcee0ca6afaf06920764a05d046df358 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 20 Apr 2010 11:07:05 +0000 Subject: Fix silly typo in script. --- host/apps/omap_debug/fetch-u-boot.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/host/apps/omap_debug/fetch-u-boot.sh b/host/apps/omap_debug/fetch-u-boot.sh index a2a488fb2..5309364b8 100755 --- a/host/apps/omap_debug/fetch-u-boot.sh +++ b/host/apps/omap_debug/fetch-u-boot.sh @@ -2,5 +2,6 @@ if [ $GHQ ]; then scp $GHQ_USER@astro:/workspace/usrp1-e-dev/u-boot-overo/u-boot.bin /media/mmcblk0p1/ else scp balister@192.168.1.167:src/git/u-boot/u-boot.bin /media/mmcblk0p1/ +fi sync -- cgit v1.2.3 From dfd5bed2b32131cd398a5daae184cec81488b5de Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Tue, 20 Apr 2010 13:33:32 +0000 Subject: Always put new bin file in /home/root. --- host/apps/omap_debug/fetch-bin.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/host/apps/omap_debug/fetch-bin.sh b/host/apps/omap_debug/fetch-bin.sh index d1502f95c..019ddaaf2 100755 --- a/host/apps/omap_debug/fetch-bin.sh +++ b/host/apps/omap_debug/fetch-bin.sh @@ -1,6 +1,6 @@ if [ $GHQ ]; then - scp $GHQ_USER@astro:/workspace/usrp1-e-dev/u1e.bin . + scp $GHQ_USER@astro:/workspace/usrp1-e-dev/u1e.bin /home/root else - scp -P 8822 balister@192.168.1.10:src/git/fpgapriv/usrp2/top/u1e/build/u1e.bin . + scp -P 8822 balister@192.168.1.10:src/git/fpgapriv/usrp2/top/u1e/build/u1e.bin /home/root fi sync -- cgit v1.2.3 From 29a3b01fb48d1c10f489103b9012b14be6f1553d Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Tue, 20 Apr 2010 13:34:24 +0000 Subject: usrp-e-i2c always uses hex arguments. --- host/apps/omap_debug/usrp-e-i2c.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-i2c.c b/host/apps/omap_debug/usrp-e-i2c.c index 19d64731b..c8fcc3f98 100644 --- a/host/apps/omap_debug/usrp-e-i2c.c +++ b/host/apps/omap_debug/usrp-e-i2c.c @@ -12,13 +12,14 @@ int main(int argc, char *argv[]) { - int fp, ret, i; + int fp, ret, i, tmp; struct usrp_e_i2c *i2c_msg; int direction, address, count; if (argc < 3) { - printf("Usage: usrp_e_i2c w address data0 data1 data2 ...\n"); - printf("Usage: usrp_e_i2c r address count\n"); + printf("Usage: usrp-e-i2c w address data0 data1 data2 ...\n"); + printf("Usage: usrp-e-i2c r address count\n"); + printf("All addresses and data in hex.\n"); exit(-1); } @@ -30,7 +31,8 @@ int main(int argc, char *argv[]) return -1; } - address = atoi(argv[2]); + sscanf(argv[2], "%X", &address); + printf("Address = %X\n", address); fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); @@ -38,8 +40,9 @@ int main(int argc, char *argv[]) if (direction) { count = argc - 3; } else { - count = atoi(argv[3]); + sscanf(argv[3], "%X", &count); } + printf("Count = %X\n", count); i2c_msg = malloc(sizeof(i2c_msg) + count * sizeof(char)); @@ -50,7 +53,8 @@ int main(int argc, char *argv[]) // Write for (i=0; idata[i] = atoi(argv[3+i]); + sscanf(argv[3+i], "%X", &tmp); + i2c_msg->data[i] = tmp; } ret = ioctl(fp, USRP_E_I2C_WRITE, i2c_msg); -- cgit v1.2.3 From c05fc634407741ce202cccc0781e937897c51361 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Tue, 20 Apr 2010 13:35:00 +0000 Subject: usrp-e-spi: change active edges around. --- host/apps/omap_debug/usrp-e-spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/host/apps/omap_debug/usrp-e-spi.c b/host/apps/omap_debug/usrp-e-spi.c index f693d7db1..caa36b3f1 100644 --- a/host/apps/omap_debug/usrp-e-spi.c +++ b/host/apps/omap_debug/usrp-e-spi.c @@ -31,7 +31,7 @@ int main(int argc, char *argv[]) spi_dat.slave = slave; spi_dat.data = data; spi_dat.length = length; - spi_dat.flags = 0; + spi_dat.flags = UE_SPI_PUSH_FALL | UE_SPI_LATCH_RISE; if (*argv[1] == 'r') { spi_dat.readback = 1; -- cgit v1.2.3 From 4e4d8556a43f7f054e760b66749c034aa5741a7f Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Tue, 20 Apr 2010 15:53:07 +0000 Subject: Initialize data array to help show when reads fail. Report return value from ioctl --- host/apps/omap_debug/usrp-e-i2c.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/host/apps/omap_debug/usrp-e-i2c.c b/host/apps/omap_debug/usrp-e-i2c.c index c8fcc3f98..575430f84 100644 --- a/host/apps/omap_debug/usrp-e-i2c.c +++ b/host/apps/omap_debug/usrp-e-i2c.c @@ -49,6 +49,10 @@ int main(int argc, char *argv[]) i2c_msg->addr = address; i2c_msg->len = count; + for (i = 0; i < count; i++) { + i2c_msg->data[i] = i; + } + if (direction) { // Write @@ -63,6 +67,7 @@ int main(int argc, char *argv[]) // Read ret = ioctl(fp, USRP_E_I2C_READ, i2c_msg); + printf("Return value from i2c_read ioctl: %d\n", ret); printf("Ioctl: %d Data read :", ret); for (i=0; i Date: Tue, 20 Apr 2010 15:54:37 +0000 Subject: Add program to setup debug pins. Add script to reload fpga and module. --- host/apps/omap_debug/Makefile | 4 +- host/apps/omap_debug/reload-fpga.sh | 7 +++ host/apps/omap_debug/usrp-e-debug-pins.c | 73 ++++++++++++++++++++++++++++++++ 3 files changed, 83 insertions(+), 1 deletion(-) create mode 100755 host/apps/omap_debug/reload-fpga.sh create mode 100644 host/apps/omap_debug/usrp-e-debug-pins.c diff --git a/host/apps/omap_debug/Makefile b/host/apps/omap_debug/Makefile index 31229d45c..61f659b3e 100644 --- a/host/apps/omap_debug/Makefile +++ b/host/apps/omap_debug/Makefile @@ -1,6 +1,6 @@ CFLAGS=-Wall -I../../lib/usrp/usrp_e/ -all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio +all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio usrp-e-debug-pins usrp-e-spi : usrp-e-spi.c @@ -23,6 +23,7 @@ fpga-downloader : fpga-downloader.cc usrp-e-gpio : usrp-e-gpio.c +usrp-e-debug-pins : usrp-e-debug-pins.c clean : rm -f usrp-e-spi rm -f usrp-e-i2c @@ -34,3 +35,4 @@ clean : rm -f usrp-e-button rm -f fpga-downloader rm -f usrp-e-gpio + rm -f usrp-e-debug-pins diff --git a/host/apps/omap_debug/reload-fpga.sh b/host/apps/omap_debug/reload-fpga.sh new file mode 100755 index 000000000..2754718a4 --- /dev/null +++ b/host/apps/omap_debug/reload-fpga.sh @@ -0,0 +1,7 @@ +#!/bin/sh + +rmmod usrp_e +fpga-downloader /home/root/u1e.bin +modprobe usrp_e +usrp-e-debug-pins 1 + diff --git a/host/apps/omap_debug/usrp-e-debug-pins.c b/host/apps/omap_debug/usrp-e-debug-pins.c new file mode 100644 index 000000000..d4e3f5223 --- /dev/null +++ b/host/apps/omap_debug/usrp-e-debug-pins.c @@ -0,0 +1,73 @@ +#include +#include +#include +#include +#include +#include +#include + +#include "usrp_e.h" +#include "usrp_e_regs.hpp" + +// Usage: usrp_e_gpio + +static int fp; + +static int read_reg(__u16 reg) +{ + int ret; + struct usrp_e_ctl16 d; + + d.offset = reg; + d.count = 1; + ret = ioctl(fp, USRP_E_READ_CTL16, &d); + return d.buf[0]; +} + +static void write_reg(__u16 reg, __u16 val) +{ + int ret; + struct usrp_e_ctl16 d; + + d.offset = reg; + d.count = 1; + d.buf[0] = val; + ret = ioctl(fp, USRP_E_WRITE_CTL16, &d); +} + +int main(int argc, char *argv[]) +{ + int test; + + test = 0; + if (argc < 2) { + printf("%s 0|1|off\n", argv[0]); + } + + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); + + if (strcmp(argv[1], "0") == 0) { + printf("Selected 0 based on %s\n", argv[1]); + write_reg(UE_REG_GPIO_TX_DDR, 0xFFFF); + write_reg(UE_REG_GPIO_RX_DDR, 0xFFFF); + write_reg(UE_REG_GPIO_TX_SEL, 0x0); + write_reg(UE_REG_GPIO_RX_SEL, 0x0); + write_reg(UE_REG_GPIO_TX_DBG, 0xFFFF); + write_reg(UE_REG_GPIO_RX_DBG, 0xFFFF); + } else if (strcmp(argv[1], "1") == 0) { + printf("Selected 1 based on %s\n", argv[1]); + write_reg(UE_REG_GPIO_TX_DDR, 0xFFFF); + write_reg(UE_REG_GPIO_RX_DDR, 0xFFFF); + write_reg(UE_REG_GPIO_TX_SEL, 0xFFFF); + write_reg(UE_REG_GPIO_RX_SEL, 0xFFFF); + write_reg(UE_REG_GPIO_TX_DBG, 0xFFFF); + write_reg(UE_REG_GPIO_RX_DBG, 0xFFFF); + } else { + printf("Selected off based on %s\n", argv[1]); + write_reg(UE_REG_GPIO_TX_DDR, 0x0); + write_reg(UE_REG_GPIO_RX_DDR, 0x0); + } + + return 0; +} -- cgit v1.2.3 From 21ceee337d61ccb2f31edaefd5c7418e8025b4b1 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 20 Apr 2010 10:51:23 -0700 Subject: find time_64bit --- usrp2/top/u1e/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index e15a49e10..5f712b046 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -176,6 +176,7 @@ timing/time_receiver.v \ timing/time_sender.v \ timing/time_sync.v \ timing/timer.v \ +timing/time_64bit.v \ gpmc/gpmc_async.v \ gpmc/edge_sync.v \ gpmc/dbsm.v \ -- cgit v1.2.3 From 61d8449f95c5c9f2c21c310f298e2ef7d66afdbb Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 21 Apr 2010 15:40:59 +0000 Subject: Add register definitions for new transfer scheme. --- host/lib/usrp/usrp_e/usrp_e_regs.hpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/host/lib/usrp/usrp_e/usrp_e_regs.hpp b/host/lib/usrp/usrp_e/usrp_e_regs.hpp index edd87e649..e7f89db7b 100644 --- a/host/lib/usrp/usrp_e/usrp_e_regs.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_regs.hpp @@ -28,6 +28,8 @@ #define UE_REG_MISC_CGEN_CTRL UE_REG_MISC_BASE + 4 #define UE_REG_MISC_CGEN_ST UE_REG_MISC_BASE + 6 #define UE_REG_MISC_TEST UE_REG_MISC_BASE + 8 +#define UE_REG_MISC_RX_LEN UE_REG_MISC_BASE + 10 +#define UE_REG_MISC_TX_LEN UE_REG_MISC_BASE + 12 ///////////////////////////////////////////////////// // Slave 1 -- UART -- cgit v1.2.3 From eb2f38d4af5345a64cd1feb92fa5cb44433d037b Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 22 Apr 2010 15:41:42 +0000 Subject: Update transfer test program to use usrp_transfer_frame struct. --- host/apps/omap_debug/usrp-e-rw.c | 64 +++++++++++++++++++++++++++++----------- host/apps/omap_debug/usrp_e.h | 13 ++++++++ 2 files changed, 60 insertions(+), 17 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-rw.c b/host/apps/omap_debug/usrp-e-rw.c index 5607166b0..5fd73e9b6 100644 --- a/host/apps/omap_debug/usrp-e-rw.c +++ b/host/apps/omap_debug/usrp-e-rw.c @@ -4,11 +4,16 @@ #include #include #include +#include +#include "usrp_e.h" + +#define PKT_DATA_LENGTH 30 +// max length #define PKT_DATA_LENGTH 1016 struct pkt { int checksum; int seq_num; - short data[1020]; + short data[PKT_DATA_LENGTH]; }; static int fp; @@ -20,7 +25,7 @@ static int calc_checksum(struct pkt *p) i = 0; sum = 0; - for (i=0; i<1020; i++) + for (i=0; idata[i]; sum += p->seq_num; @@ -31,23 +36,35 @@ static int calc_checksum(struct pkt *p) static void *read_thread(void *threadid) { int cnt, prev_seq_num; - struct pkt rx_data; + struct usrp_transfer_frame *rx_data; + struct pkt *p; printf("Greetings from the reading thread!\n"); + rx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt)); + p = (struct pkt *) ((void *)rx_data + offsetof(struct usrp_transfer_frame, buf)); + //p = &(rx_data->buf[0]); + printf("Address of rx_data = %p, p = %p\n", rx_data, p); + printf("offsetof = %d\n", offsetof(struct usrp_transfer_frame, buf)); + printf("sizeof rx data = %X\n", sizeof(struct usrp_transfer_frame) + sizeof(struct pkt)); + prev_seq_num = 0; while (1) { - cnt = read(fp, &rx_data, 2048); - if (rx_data.seq_num != prev_seq_num + 1) - printf("Sequence number fail, current = %d, previous = %d\n", - rx_data.seq_num, prev_seq_num); - prev_seq_num = rx_data.seq_num; + cnt = read(fp, rx_data, 2048); + printf("Packet received, flags = %X, len = %X\n", rx_data->flags, rx_data->len); + printf("p->seq_num = %d\n", p->seq_num); + + if (p->seq_num != prev_seq_num + 1) + printf("Sequence number fail, current = %X, previous = %X\n", + p->seq_num, prev_seq_num); + prev_seq_num = p->seq_num; - if (calc_checksum(&rx_data) != rx_data.checksum) - printf("Checksum fail packet = %d, expected = %d\n", - calc_checksum(&rx_data), rx_data.checksum); + if (calc_checksum(p) != p->checksum) + printf("Checksum fail packet = %X, expected = %X\n", + calc_checksum(p), p->checksum); + printf("\n"); } } @@ -55,20 +72,31 @@ static void *read_thread(void *threadid) static void *write_thread(void *threadid) { int seq_number, i, cnt; - struct pkt tx_data; + struct usrp_transfer_frame *tx_data; + struct pkt *p; printf("Greetings from the write thread!\n"); - for (i=0; i<1020; i++) - tx_data.data[i] = random() >> 16; + tx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt)); + p = (struct pkt *) ((void *)tx_data + offsetof(struct usrp_transfer_frame, buf)); + printf("Address of tx_data = %p, p = %p\n", tx_data, p); + printf("sizeof tx data = %X\n", sizeof(struct usrp_transfer_frame) + sizeof(struct pkt)); + + for (i=0; idata[i] = random() >> 16; + p->data[i] = i; + + tx_data->flags = 0xdeadbeef; + tx_data->len = 8 + PKT_DATA_LENGTH * 2; seq_number = 1; while (1) { - tx_data.seq_num = seq_number++; - tx_data.checksum = calc_checksum(&tx_data); - cnt = write(fp, &tx_data, 2048); + p->seq_num = seq_number++; + p->checksum = calc_checksum(p); + cnt = write(fp, tx_data, 2048); + sleep(1); } } @@ -86,6 +114,8 @@ int main(int argc, char *argv[]) exit(-1); } + sleep(1); + if (pthread_create(&tx, NULL, write_thread, (void *) t)) { printf("Failed to create tx thread\n"); exit(-1); diff --git a/host/apps/omap_debug/usrp_e.h b/host/apps/omap_debug/usrp_e.h index aa8ef3d57..48a3201cb 100644 --- a/host/apps/omap_debug/usrp_e.h +++ b/host/apps/omap_debug/usrp_e.h @@ -69,4 +69,17 @@ struct usrp_e_i2c { #define USRP_E_I2C_READ _IOR(USRP_E_IOC_MAGIC, 0x25, struct usrp_e_i2c) #define USRP_E_I2C_WRITE _IOW(USRP_E_IOC_MAGIC, 0x26, struct usrp_e_i2c) +// Data transfer frame definition + +struct usrp_transfer_frame { + __u32 flags; + __u32 len; + __u8 buf[]; +}; + +struct ring_buffer_entry { + unsigned long dma_addr; + struct usrp_transfer_frame *frame_addr; +}; + #endif -- cgit v1.2.3 From f5b6776a0b642c0357fbecdead9d2b1ac6ece3d3 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Fri, 23 Apr 2010 14:04:37 +0000 Subject: Updates to test programs. --- host/apps/omap_debug/Makefile | 6 +- host/apps/omap_debug/usrp-e-rw-random.c | 147 ++++++++++++++++++++++++++++++++ host/apps/omap_debug/usrp-e-rw.c | 42 ++++++--- 3 files changed, 181 insertions(+), 14 deletions(-) create mode 100644 host/apps/omap_debug/usrp-e-rw-random.c diff --git a/host/apps/omap_debug/Makefile b/host/apps/omap_debug/Makefile index 61f659b3e..b00210c4f 100644 --- a/host/apps/omap_debug/Makefile +++ b/host/apps/omap_debug/Makefile @@ -1,6 +1,6 @@ CFLAGS=-Wall -I../../lib/usrp/usrp_e/ -all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio usrp-e-debug-pins +all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio usrp-e-debug-pins usrp-e-rw-random usrp-e-spi : usrp-e-spi.c @@ -9,6 +9,9 @@ usrp-e-i2c : usrp-e-i2c.c usrp-e-rw : usrp-e-rw.c gcc -o $@ $< -lpthread +usrp-e-rw-random : usrp-e-rw-random.c + gcc -o $@ $< -lpthread + usrp-e-uart : usrp-e-uart.c usrp-e-uart-rx : usrp-e-uart-rx.c @@ -28,6 +31,7 @@ clean : rm -f usrp-e-spi rm -f usrp-e-i2c rm -f usrp-e-rw + rm -f usrp-e-rw-random rm -f usrp-e-uart rm -f usrp-e-uart-rx rm -f usrp-e-led diff --git a/host/apps/omap_debug/usrp-e-rw-random.c b/host/apps/omap_debug/usrp-e-rw-random.c new file mode 100644 index 000000000..67d6ca803 --- /dev/null +++ b/host/apps/omap_debug/usrp-e-rw-random.c @@ -0,0 +1,147 @@ +#include +#include +#include +#include +#include +#include +#include +#include "usrp_e.h" + +// max length #define PKT_DATA_LENGTH 1014 +static int packet_data_length; + +struct pkt { + int checksum; + int seq_num; + int len; + short data[]; +}; + +static int fp; + +static int calc_checksum(struct pkt *p) +{ + int i, sum; + + i = 0; + sum = 0; + + for (i=0; i < p->len; i++) + sum += p->data[i]; + + sum += p->seq_num; + + return sum; +} + +int randN(int n) +{ + long tmp; + + tmp = rand() % n; + + return tmp; +} + +static void *read_thread(void *threadid) +{ + int cnt, prev_seq_num; + struct usrp_transfer_frame *rx_data; + struct pkt *p; + + printf("Greetings from the reading thread!\n"); + + // IMPORTANT: must assume max length packet from fpga + rx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (1014 * 2)); + rx_data = malloc(2048); + p = (struct pkt *) ((void *)rx_data + offsetof(struct usrp_transfer_frame, buf)); + //p = &(rx_data->buf[0]); + printf("Address of rx_data = %p, p = %p\n", rx_data, p); + printf("offsetof = %d\n", offsetof(struct usrp_transfer_frame, buf)); + printf("sizeof rx data = %d\n", sizeof(struct usrp_transfer_frame) + sizeof(struct pkt)); + + prev_seq_num = 0; + + while (1) { + + cnt = read(fp, rx_data, 2048); +// printf("Packet received, flags = %X, len = %d\n", rx_data->flags, rx_data->len); +// printf("p->seq_num = %d\n", p->seq_num); + + if (p->seq_num != prev_seq_num + 1) + printf("Sequence number fail, current = %d, previous = %d\n", + p->seq_num, prev_seq_num); + prev_seq_num = p->seq_num; + + if (calc_checksum(p) != p->checksum) + printf("Checksum fail packet = %d, expected = %d\n", + calc_checksum(p), p->checksum); +// printf("\n"); + } + +} + +static void *write_thread(void *threadid) +{ + int seq_number, i, cnt, pkt_cnt; + struct usrp_transfer_frame *tx_data; + struct pkt *p; + + printf("Greetings from the write thread!\n"); + + // Allocate max length buffer for frame + tx_data = malloc(2048); + p = (struct pkt *) ((void *)tx_data + offsetof(struct usrp_transfer_frame, buf)); + printf("Address of tx_data = %p, p = %p\n", tx_data, p); + + printf("sizeof rp_transfer_frame = %d, sizeof pkt = %d\n", sizeof(struct usrp_transfer_frame), sizeof(struct pkt)); + + for (i=0; i < 1014; i++) +// p->data[i] = random() >> 16; + p->data[i] = i; + + tx_data->flags = 0xdeadbeef; + tx_data->len = 8 + packet_data_length * 2; + + printf("tx_data->len = %d\n", tx_data->len); + + seq_number = 1; + + while (1) { + pkt_cnt = randN(16); + for (i = 0; i < pkt_cnt; i++) { + p->seq_num = seq_number++; + p->len = randN(1013) + 1; + p->checksum = calc_checksum(p); + tx_data->len = 12 + p->len * 2; + cnt = write(fp, tx_data, 2048); + } + sleep(random() >> 31); + } +} + + +int main(int argc, char *argv[]) +{ + pthread_t tx, rx; + long int t; + + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); + + if (pthread_create(&rx, NULL, read_thread, (void *) t)) { + printf("Failed to create rx thread\n"); + exit(-1); + } + + sleep(1); + + if (pthread_create(&tx, NULL, write_thread, (void *) t)) { + printf("Failed to create tx thread\n"); + exit(-1); + } + + sleep(10000); + + printf("Done sleeping\n"); +} diff --git a/host/apps/omap_debug/usrp-e-rw.c b/host/apps/omap_debug/usrp-e-rw.c index 5fd73e9b6..edfcea92a 100644 --- a/host/apps/omap_debug/usrp-e-rw.c +++ b/host/apps/omap_debug/usrp-e-rw.c @@ -7,13 +7,13 @@ #include #include "usrp_e.h" -#define PKT_DATA_LENGTH 30 // max length #define PKT_DATA_LENGTH 1016 +static int packet_data_length; struct pkt { int checksum; int seq_num; - short data[PKT_DATA_LENGTH]; + short data[]; }; static int fp; @@ -25,7 +25,7 @@ static int calc_checksum(struct pkt *p) i = 0; sum = 0; - for (i=0; idata[i]; sum += p->seq_num; @@ -41,20 +41,24 @@ static void *read_thread(void *threadid) printf("Greetings from the reading thread!\n"); - rx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt)); + // IMPORTANT: must assume max length packet from fpga + rx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (1016 * 2)); p = (struct pkt *) ((void *)rx_data + offsetof(struct usrp_transfer_frame, buf)); //p = &(rx_data->buf[0]); printf("Address of rx_data = %p, p = %p\n", rx_data, p); printf("offsetof = %d\n", offsetof(struct usrp_transfer_frame, buf)); - printf("sizeof rx data = %X\n", sizeof(struct usrp_transfer_frame) + sizeof(struct pkt)); + printf("sizeof rx data = %d\n", sizeof(struct usrp_transfer_frame) + sizeof(struct pkt)); prev_seq_num = 0; while (1) { cnt = read(fp, rx_data, 2048); - printf("Packet received, flags = %X, len = %X\n", rx_data->flags, rx_data->len); - printf("p->seq_num = %d\n", p->seq_num); + if (cnt < 0) + printf("Error returned from read: %d\n", cnt); + +// printf("Packet received, flags = %X, len = %d\n", rx_data->flags, rx_data->len); +// printf("p->seq_num = %d\n", p->seq_num); if (p->seq_num != prev_seq_num + 1) printf("Sequence number fail, current = %X, previous = %X\n", @@ -64,7 +68,7 @@ static void *read_thread(void *threadid) if (calc_checksum(p) != p->checksum) printf("Checksum fail packet = %X, expected = %X\n", calc_checksum(p), p->checksum); - printf("\n"); +// printf("\n"); } } @@ -77,26 +81,31 @@ static void *write_thread(void *threadid) printf("Greetings from the write thread!\n"); - tx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt)); + tx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (packet_data_length * 2)); p = (struct pkt *) ((void *)tx_data + offsetof(struct usrp_transfer_frame, buf)); printf("Address of tx_data = %p, p = %p\n", tx_data, p); - printf("sizeof tx data = %X\n", sizeof(struct usrp_transfer_frame) + sizeof(struct pkt)); + printf("sizeof rp_transfer_frame = %d, sizeof pkt = %d\n", sizeof(struct usrp_transfer_frame), sizeof(struct pkt)); - for (i=0; idata[i] = random() >> 16; p->data[i] = i; tx_data->flags = 0xdeadbeef; - tx_data->len = 8 + PKT_DATA_LENGTH * 2; + tx_data->len = 8 + packet_data_length * 2; + + printf("tx_data->len = %d\n", tx_data->len); seq_number = 1; while (1) { +// printf("tx flags = %X, len = %d\n", tx_data->flags, tx_data->len); p->seq_num = seq_number++; p->checksum = calc_checksum(p); cnt = write(fp, tx_data, 2048); - sleep(1); + if (cnt < 0) + printf("Error returned from write: %d\n", cnt); + // sleep(1); } } @@ -106,6 +115,13 @@ int main(int argc, char *argv[]) pthread_t tx, rx; long int t; + if (argc < 2) { + printf("%s data_size\n", argv[0]); + return -1; + } + + packet_data_length = atoi(argv[1]); + fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); -- cgit v1.2.3 From 5de2543e9cee644009d9ec15c19c70986df89594 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 23 Apr 2010 14:43:29 -0700 Subject: Register outputs to omap to prevent runt pulses from falsely triggering interrupts --- usrp2/gpmc/fifo_watcher.v | 8 ++++++-- usrp2/gpmc/gpmc_async.v | 9 +++++++-- usrp2/gpmc/gpmc_to_fifo_async.v | 10 +++++++--- 3 files changed, 20 insertions(+), 7 deletions(-) diff --git a/usrp2/gpmc/fifo_watcher.v b/usrp2/gpmc/fifo_watcher.v index da2051b04..7a3f00483 100644 --- a/usrp2/gpmc/fifo_watcher.v +++ b/usrp2/gpmc/fifo_watcher.v @@ -4,7 +4,7 @@ module fifo_watcher (input clk, input reset, input clear, input src_rdy1, input dst_rdy1, input sof1, input eof1, input src_rdy2, input dst_rdy2, input sof2, input eof2, - output have_packet, output [15:0] length, output reg bus_error); + output reg have_packet, output [15:0] length, output reg bus_error); wire write = src_rdy1 & dst_rdy1 & eof1; wire read = src_rdy2 & dst_rdy2 & eof2; @@ -34,7 +34,11 @@ module fifo_watcher bus_error <= 1; reg in_packet; - assign have_packet = have_packet_int & ~in_packet; + always @(posedge clk) + if(reset | clear) + have_packet <= 0; + else + have_packet <= have_packet_int & ~in_packet; always @(posedge clk) if(reset | clear) diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index b1a545907..02a00ce57 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -7,7 +7,7 @@ module gpmc_async input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, // GPIOs for FIFO signalling - output rx_have_data, output tx_have_space, output bus_error, input bus_reset, + output rx_have_data, output tx_have_space, output reg bus_error, input bus_reset, // Wishbone signals input wb_clk, input wb_rst, @@ -31,7 +31,12 @@ module gpmc_async assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb; wire bus_error_tx, bus_error_rx; - assign bus_error = bus_error_tx | bus_error_rx; + + always @(posedge fifo_clk) + if(fifo_rst) + bus_error <= 0; + else + bus_error <= bus_error_tx | bus_error_rx; // CS4 is RAM_2PORT for DATA PATH (high-speed data) // Writes go into one RAM, reads come from the other diff --git a/usrp2/gpmc/gpmc_to_fifo_async.v b/usrp2/gpmc/gpmc_to_fifo_async.v index 1df93f910..38f1165fc 100644 --- a/usrp2/gpmc/gpmc_to_fifo_async.v +++ b/usrp2/gpmc/gpmc_to_fifo_async.v @@ -5,10 +5,10 @@ module gpmc_to_fifo_async input fifo_clk, input fifo_rst, output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i, - input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready, + input [15:0] frame_len, input [15:0] fifo_space, output reg fifo_ready, output reg bus_error ); - reg [10:0] counter; + reg [15:0] counter; // Synchronize the async control signals reg [1:0] cs_del, we_del; always @(posedge fifo_clk) @@ -53,7 +53,11 @@ module gpmc_to_fifo_async else counter <= counter + 1; - assign fifo_ready = first_write & (fifo_space > frame_len); + always @(posedge fifo_clk) + if(fifo_rst) + fifo_ready <= 0; + else + fifo_ready <= first_write & (fifo_space > frame_len); always @(posedge fifo_clk) if(fifo_rst) -- cgit v1.2.3 From aeed16ec6e220f99df41534febe85336e5b384e6 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 23 Apr 2010 18:06:28 -0700 Subject: Only allow new packets if we can fit the largest possible packet (2KB) --- usrp2/gpmc/gpmc_to_fifo_async.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/gpmc/gpmc_to_fifo_async.v b/usrp2/gpmc/gpmc_to_fifo_async.v index 38f1165fc..6232244d4 100644 --- a/usrp2/gpmc/gpmc_to_fifo_async.v +++ b/usrp2/gpmc/gpmc_to_fifo_async.v @@ -57,7 +57,7 @@ module gpmc_to_fifo_async if(fifo_rst) fifo_ready <= 0; else - fifo_ready <= first_write & (fifo_space > frame_len); + fifo_ready <= first_write & (fifo_space > 16'd1023); always @(posedge fifo_clk) if(fifo_rst) -- cgit v1.2.3 From b317f4df86d24cc9a47b8a8191f57545875f3afe Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 25 Apr 2010 00:42:52 +0000 Subject: removed boost exception stuff that makes it incompadible with 1.36, remember this diff --- host/include/uhd/utils/assert.hpp | 4 ++++ host/include/uhd/utils/props.hpp | 4 ++++ host/include/uhd/utils/safe_main.hpp | 6 +++--- 3 files changed, 11 insertions(+), 3 deletions(-) diff --git a/host/include/uhd/utils/assert.hpp b/host/include/uhd/utils/assert.hpp index 01beed757..0a278312e 100644 --- a/host/include/uhd/utils/assert.hpp +++ b/host/include/uhd/utils/assert.hpp @@ -28,6 +28,10 @@ #include #include +#ifndef BOOST_THROW_EXCEPTION +#define BOOST_THROW_EXCEPTION(x) throw std::runtime_error("") +#endif + namespace uhd{ //! The exception to throw when assertions fail diff --git a/host/include/uhd/utils/props.hpp b/host/include/uhd/utils/props.hpp index 516102a5f..6c40c32e0 100644 --- a/host/include/uhd/utils/props.hpp +++ b/host/include/uhd/utils/props.hpp @@ -27,6 +27,10 @@ #include #include +#ifndef BOOST_THROW_EXCEPTION +#define BOOST_THROW_EXCEPTION(x) throw std::runtime_error("") +#endif + namespace uhd{ //! The type for a vector of property names diff --git a/host/include/uhd/utils/safe_main.hpp b/host/include/uhd/utils/safe_main.hpp index a4e4e06e8..39d2282cd 100644 --- a/host/include/uhd/utils/safe_main.hpp +++ b/host/include/uhd/utils/safe_main.hpp @@ -19,7 +19,7 @@ #define INCLUDED_UHD_UTILS_SAFE_MAIN_HPP #include -#include +//#include #include #include @@ -34,9 +34,9 @@ int main(int argc, char *argv[]){ \ try { \ return _main(argc, argv); \ - } catch(const boost::exception &e){ \ + } /*catch(const boost::exception &e){ \ std::cerr << "Error: " << boost::diagnostic_information(e) << std::endl; \ - } catch(const std::exception &e) { \ + }*/ catch(const std::exception &e) { \ std::cerr << "Error: " << e.what() << std::endl; \ } catch(...) { \ std::cerr << "Error: unknown exception" << std::endl; \ -- cgit v1.2.3 From ae4b885e3533a73f0781e2fdb892f5d505081240 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sat, 24 Apr 2010 22:58:06 -0700 Subject: Pass previously unused GPIOs to debug pins to help debug interrupts --- usrp2/top/u1e/u1e.ucf | 24 ++++++++++++------------ usrp2/top/u1e/u1e.v | 7 +++++++ usrp2/top/u1e/u1e_core.v | 6 ++---- 3 files changed, 21 insertions(+), 16 deletions(-) diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 1c8dfc197..9c42b00ac 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -47,22 +47,22 @@ NET "EM_NOE" LOC = "A14" ; #NET "EM_NWP" LOC = "F13" ; ## Overo GPIO -#NET "overo_gpio0" LOC = "F9" ; -#NET "overo_gpio14" LOC = "C4" ; -#NET "overo_gpio21" LOC = "D5" ; -#NET "overo_gpio22" LOC = "A3" ; -#NET "overo_gpio23" LOC = "B3" ; -#NET "overo_gpio64" LOC = "A4" ; -#NET "overo_gpio65" LOC = "F8" ; -#NET "overo_gpio127" LOC = "C8" ; -#NET "overo_gpio128" LOC = "G8" ; +NET "overo_gpio0" LOC = "F9" ; # MISC GPIO for debug +NET "overo_gpio14" LOC = "C4" ; # MISC GPIO for debug +NET "overo_gpio21" LOC = "D5" ; # MISC GPIO for debug +NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug +NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug +NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug +NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug +NET "overo_gpio127" LOC = "C8" ; # MISC GPIO for debug +NET "overo_gpio128" LOC = "G8" ; # MISC GPIO for debug NET "overo_gpio144" LOC = "A5" ; # tx_have_space NET "overo_gpio145" LOC = "C7" ; # tx_underrun NET "overo_gpio146" LOC = "A6" ; # rx_have_data NET "overo_gpio147" LOC = "B6" ; # rx_overrun -#NET "overo_gpio163" LOC = "D7" ; -#NET "overo_gpio170" LOC = "E8" ; -#NET "overo_gpio176" LOC = "B4" ; +NET "overo_gpio163" LOC = "D7" ; # MISC GPIO for debug +NET "overo_gpio170" LOC = "E8" ; # MISC GPIO for debug +NET "overo_gpio176" LOC = "B4" ; # MISC GPIO for debug ## Overo UART #NET "overo_txd1" LOC = "C6" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index b8f716d26..2ed6b71c8 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -20,6 +20,10 @@ module u1e input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output overo_gpio144, output overo_gpio145, output overo_gpio146, output overo_gpio147, // Fifo controls + input overo_gpio0, input overo_gpio14, input overo_gpio21, input overo_gpio22, // Misc GPIO + input overo_gpio23, input overo_gpio64, input overo_gpio65, input overo_gpio127, // Misc GPIO + input overo_gpio128, input overo_gpio163, input overo_gpio170, input overo_gpio176, // Misc GPIO + inout [15:0] io_tx, inout [15:0] io_rx, input PPS_IN ); @@ -52,6 +56,9 @@ module u1e .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), .io_tx(io_tx), .io_rx(io_rx), + .misc_gpio( {{overo_gpio128,overo_gpio163,overo_gpio170,overo_gpio176}, + {overo_gpio0,overo_gpio14,overo_gpio21,overo_gpio22}, + {overo_gpio23,overo_gpio64,overo_gpio65,overo_gpio127}}), .pps_in(PPS_IN) ); endmodule // u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 9e65faeed..e67b1b158 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -13,9 +13,7 @@ module u1e_core input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, - inout [15:0] io_tx, inout [15:0] io_rx, - - input pps_in + inout [15:0] io_tx, inout [15:0] io_rx, input [11:0] misc_gpio, input pps_in ); wire wb_clk = clk_fpga; @@ -273,6 +271,6 @@ module u1e_core { EM_D } }; assign debug_gpio_0 = { debug_gpmc }; - assign debug_gpio_1 = { debug_txd, debug_rxd }; + assign debug_gpio_1 = { misc_gpio }; endmodule // u1e_core -- cgit v1.2.3 From 97af4bd12673fbb8d68dd087690dabb3e9488c4d Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 26 Apr 2010 17:15:53 -0700 Subject: send bus error to debug pins --- usrp2/top/u1e/u1e_core.v | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index e67b1b158..f231791da 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -36,6 +36,8 @@ module u1e_core wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy; reg [15:0] tx_frame_len; wire [15:0] rx_frame_len; + + wire bus_error; gpmc_async gpmc (.arst(wb_rst), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), @@ -43,7 +45,7 @@ module u1e_core .EM_NOE(EM_NOE), .rx_have_data(rx_have_data), .tx_have_space(tx_have_space), - .bus_error(), .bus_reset(0), + .bus_error(bus_error), .bus_reset(0), .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), @@ -271,6 +273,6 @@ module u1e_core { EM_D } }; assign debug_gpio_0 = { debug_gpmc }; - assign debug_gpio_1 = { misc_gpio }; + assign debug_gpio_1 = { bus_error, misc_gpio[11:0] }; endmodule // u1e_core -- cgit v1.2.3 From 7953156249776ce7d45bb2a24c8ac88edb644c64 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Tue, 27 Apr 2010 08:17:46 +0000 Subject: Send only required number of bytes. Do it for longer. --- host/apps/omap_debug/usrp-e-rw-random.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-rw-random.c b/host/apps/omap_debug/usrp-e-rw-random.c index 67d6ca803..c6a838067 100644 --- a/host/apps/omap_debug/usrp-e-rw-random.c +++ b/host/apps/omap_debug/usrp-e-rw-random.c @@ -114,7 +114,7 @@ static void *write_thread(void *threadid) p->len = randN(1013) + 1; p->checksum = calc_checksum(p); tx_data->len = 12 + p->len * 2; - cnt = write(fp, tx_data, 2048); + cnt = write(fp, tx_data, tx_data->len + 8); } sleep(random() >> 31); } @@ -141,7 +141,7 @@ int main(int argc, char *argv[]) exit(-1); } - sleep(10000); + sleep(1000000000); printf("Done sleeping\n"); } -- cgit v1.2.3 From 245b46da0b603e3c12c56fdad782ff884b2a6432 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Tue, 27 Apr 2010 08:18:24 +0000 Subject: Add program to exercise interface using internal fpga data source and data sink. --- host/apps/omap_debug/Makefile | 6 +- host/apps/omap_debug/usrp-e-fpga-rw.c | 167 ++++++++++++++++++++++++++++++++++ 2 files changed, 172 insertions(+), 1 deletion(-) create mode 100644 host/apps/omap_debug/usrp-e-fpga-rw.c diff --git a/host/apps/omap_debug/Makefile b/host/apps/omap_debug/Makefile index b00210c4f..f48eb9539 100644 --- a/host/apps/omap_debug/Makefile +++ b/host/apps/omap_debug/Makefile @@ -1,6 +1,6 @@ CFLAGS=-Wall -I../../lib/usrp/usrp_e/ -all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio usrp-e-debug-pins usrp-e-rw-random +all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio usrp-e-debug-pins usrp-e-rw-random usrp-e-fpga-rw usrp-e-spi : usrp-e-spi.c @@ -9,6 +9,9 @@ usrp-e-i2c : usrp-e-i2c.c usrp-e-rw : usrp-e-rw.c gcc -o $@ $< -lpthread +usrp-e-fpga-rw : usrp-e-fpga-rw.c + gcc -o $@ $< -lpthread + usrp-e-rw-random : usrp-e-rw-random.c gcc -o $@ $< -lpthread @@ -31,6 +34,7 @@ clean : rm -f usrp-e-spi rm -f usrp-e-i2c rm -f usrp-e-rw + rm -f usrp-e-fpga-rw rm -f usrp-e-rw-random rm -f usrp-e-uart rm -f usrp-e-uart-rx diff --git a/host/apps/omap_debug/usrp-e-fpga-rw.c b/host/apps/omap_debug/usrp-e-fpga-rw.c new file mode 100644 index 000000000..455657203 --- /dev/null +++ b/host/apps/omap_debug/usrp-e-fpga-rw.c @@ -0,0 +1,167 @@ +#include +#include +#include +#include +#include +#include +#include +#include "usrp_e.h" + +// max length #define PKT_DATA_LENGTH 1016 +static int packet_data_length; + +struct pkt { + int checksum; + int seq_num; + short data[]; +}; + +static int fp; + +static int calc_checksum(struct pkt *p) +{ + int i, sum; + + i = 0; + sum = 0; + + for (i=0; i < packet_data_length; i++) + sum += p->data[i]; + + sum += p->seq_num; + + return sum; +} + +static void *read_thread(void *threadid) +{ + int cnt, prev_seq_num; + struct usrp_transfer_frame *rx_data; + struct pkt *p; + + printf("Greetings from the reading thread!\n"); + + // IMPORTANT: must assume max length packet from fpga + rx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (1016 * 2)); + p = (struct pkt *) ((void *)rx_data + offsetof(struct usrp_transfer_frame, buf)); + //p = &(rx_data->buf[0]); + printf("Address of rx_data = %p, p = %p\n", rx_data, p); + printf("offsetof = %d\n", offsetof(struct usrp_transfer_frame, buf)); + printf("sizeof rx data = %d\n", sizeof(struct usrp_transfer_frame) + sizeof(struct pkt)); + + prev_seq_num = 0; + + while (1) { + + cnt = read(fp, rx_data, 2048); + if (cnt < 0) + printf("Error returned from read: %d\n", cnt); + +// printf("Packet received, flags = %X, len = %d\n", rx_data->flags, rx_data->len); +// printf("p->seq_num = %d\n", p->seq_num); + + if (p->seq_num != prev_seq_num + 1) + printf("Sequence number fail, current = %X, previous = %X\n", + p->seq_num, prev_seq_num); + prev_seq_num = p->seq_num; + + if (calc_checksum(p) != p->checksum) + printf("Checksum fail packet = %X, expected = %X\n", + calc_checksum(p), p->checksum); +// printf("\n"); + } + +} + +static void *write_thread(void *threadid) +{ + int seq_number, i, cnt; + struct usrp_transfer_frame *tx_data; + struct pkt *p; + + printf("Greetings from the write thread!\n"); + + tx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (packet_data_length * 2)); + p = (struct pkt *) ((void *)tx_data + offsetof(struct usrp_transfer_frame, buf)); + printf("Address of tx_data = %p, p = %p\n", tx_data, p); + + printf("sizeof rp_transfer_frame = %d, sizeof pkt = %d\n", sizeof(struct usrp_transfer_frame), sizeof(struct pkt)); + + for (i=0; i < packet_data_length; i++) +// p->data[i] = random() >> 16; + p->data[i] = i; + + tx_data->flags = 0; + tx_data->len = 8 + packet_data_length * 2; + + printf("tx_data->len = %d\n", tx_data->len); + + seq_number = 1; + + while (1) { +// printf("tx flags = %X, len = %d\n", tx_data->flags, tx_data->len); + p->seq_num = seq_number++; + p->checksum = calc_checksum(p); + cnt = write(fp, tx_data, 2048); + if (cnt < 0) + printf("Error returned from write: %d\n", cnt); +// sleep(1); + } +} + + +int main(int argc, char *argv[]) +{ + pthread_t tx, rx; + long int t; + int fpga_config_flag ,decimation; + struct usrp_e_ctl16 d; + + if (argc < 4) { + printf("%s t|w|rw decimation data_size\n", argv[0]); + return -1; + } + + decimation = atoi(argv[2]); + packet_data_length = atoi(argv[3]); + + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); + + fpga_config_flag = 0; + if (strcmp(argv[1], "w") == 0) + fpga_config_flag |= (1 << 15); + else if (strcmp(argv[1], "r") == 0) + fpga_config_flag |= (1 << 14); + else if (strcmp(argv[1], "rw") == 0) + fpga_config_flag |= ((1 << 15) | (1 << 14)); + + fpga_config_flag |= decimation; + + d.offset = 14; + d.count = 1; + d.buf[0] = fpga_config_flag; + ioctl(fp, USRP_E_WRITE_CTL16, &d); + + sleep(1); // in case the kernel threads need time to start. FIXME if so + + if (fpga_config_flag & (1 << 14)) { + if (pthread_create(&rx, NULL, read_thread, (void *) t)) { + printf("Failed to create rx thread\n"); + exit(-1); + } + } + + sleep(1); + + if (fpga_config_flag & (1 << 15)) { + if (pthread_create(&tx, NULL, write_thread, (void *) t)) { + printf("Failed to create tx thread\n"); + exit(-1); + } + } + + sleep(10000); + + printf("Done sleeping\n"); +} -- cgit v1.2.3 From 1b924876d7d7216504e604137ed0ade36460169f Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 28 Apr 2010 11:25:26 -0700 Subject: usrp-e branch compiling with recent master pulled in --- host/lib/usrp/usrp_e/dboard_iface.cpp | 19 ++++++++++--------- host/lib/usrp/usrp_e/dboard_impl.cpp | 8 ++++---- host/lib/usrp/usrp_e/dsp_impl.cpp | 8 ++++---- host/lib/usrp/usrp_e/mboard_impl.cpp | 15 ++++++--------- host/lib/usrp/usrp_e/usrp_e_iface.cpp | 6 +++--- host/lib/usrp/usrp_e/usrp_e_iface.hpp | 4 ++-- host/lib/usrp/usrp_e/usrp_e_impl.cpp | 5 +++-- 7 files changed, 32 insertions(+), 33 deletions(-) diff --git a/host/lib/usrp/usrp_e/dboard_iface.cpp b/host/lib/usrp/usrp_e/dboard_iface.cpp index 12e8fe206..c4784d29c 100644 --- a/host/lib/usrp/usrp_e/dboard_iface.cpp +++ b/host/lib/usrp/usrp_e/dboard_iface.cpp @@ -23,6 +23,7 @@ #include #include //i2c and spi constants +using namespace uhd; using namespace uhd::usrp; class usrp_e_dboard_iface : public dboard_iface{ @@ -37,8 +38,8 @@ public: void set_gpio_ddr(unit_t, boost::uint16_t); boost::uint16_t read_gpio(unit_t); - void write_i2c(int, const byte_vector_t &); - byte_vector_t read_i2c(int, size_t); + void write_i2c(boost::uint8_t, const byte_vector_t &); + byte_vector_t read_i2c(boost::uint8_t, size_t); void write_spi( unit_t unit, @@ -171,14 +172,14 @@ boost::uint32_t usrp_e_dboard_iface::read_write_spi( **********************************************************************/ static const size_t max_i2c_data_bytes = 10; -void usrp_e_dboard_iface::write_i2c(int i2c_addr, const byte_vector_t &buf){ +void usrp_e_dboard_iface::write_i2c(boost::uint8_t addr, const byte_vector_t &buf){ //allocate some memory for this transaction - ASSERT_THROW(buf.size() <= max_i2c_data_bytes); + UHD_ASSERT_THROW(buf.size() <= max_i2c_data_bytes); boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; //load the data struct usrp_e_i2c &data = reinterpret_cast(mem); - data.addr = i2c_addr; + data.addr = addr; data.len = buf.size(); std::copy(buf.begin(), buf.end(), data.data); @@ -186,14 +187,14 @@ void usrp_e_dboard_iface::write_i2c(int i2c_addr, const byte_vector_t &buf){ _iface->ioctl(USRP_E_I2C_WRITE, &data); } -dboard_iface::byte_vector_t usrp_e_dboard_iface::read_i2c(int i2c_addr, size_t num_bytes){ +byte_vector_t usrp_e_dboard_iface::read_i2c(boost::uint8_t addr, size_t num_bytes){ //allocate some memory for this transaction - ASSERT_THROW(num_bytes <= max_i2c_data_bytes); + UHD_ASSERT_THROW(num_bytes <= max_i2c_data_bytes); boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; //load the data struct usrp_e_i2c &data = reinterpret_cast(mem); - data.addr = i2c_addr; + data.addr = addr; data.len = num_bytes; //call the spi ioctl @@ -201,7 +202,7 @@ dboard_iface::byte_vector_t usrp_e_dboard_iface::read_i2c(int i2c_addr, size_t n //unload the data byte_vector_t ret(data.len); - ASSERT_THROW(ret.size() == num_bytes); + UHD_ASSERT_THROW(ret.size() == num_bytes); std::copy(data.data, data.data+ret.size(), ret.begin()); return ret; } diff --git a/host/lib/usrp/usrp_e/dboard_impl.cpp b/host/lib/usrp/usrp_e/dboard_impl.cpp index df0f1d9a9..e87a2c0a5 100644 --- a/host/lib/usrp/usrp_e/dboard_impl.cpp +++ b/host/lib/usrp/usrp_e/dboard_impl.cpp @@ -50,26 +50,26 @@ void usrp_e_impl::dboard_init(void){ * RX Dboard Get **********************************************************************/ void usrp_e_impl::rx_dboard_get(const wax::obj &, wax::obj &){ - + UHD_THROW_PROP_GET_ERROR(); } /*********************************************************************** * RX Dboard Set **********************************************************************/ void usrp_e_impl::rx_dboard_set(const wax::obj &, const wax::obj &){ - + UHD_THROW_PROP_SET_ERROR(); } /*********************************************************************** * TX Dboard Get **********************************************************************/ void usrp_e_impl::tx_dboard_get(const wax::obj &, wax::obj &){ - + UHD_THROW_PROP_GET_ERROR(); } /*********************************************************************** * TX Dboard Set **********************************************************************/ void usrp_e_impl::tx_dboard_set(const wax::obj &, const wax::obj &){ - + UHD_THROW_PROP_SET_ERROR(); } diff --git a/host/lib/usrp/usrp_e/dsp_impl.cpp b/host/lib/usrp/usrp_e/dsp_impl.cpp index e32c76a3d..272ac71b3 100644 --- a/host/lib/usrp/usrp_e/dsp_impl.cpp +++ b/host/lib/usrp/usrp_e/dsp_impl.cpp @@ -34,14 +34,14 @@ void usrp_e_impl::rx_ddc_init(void){ * RX DDC Get **********************************************************************/ void usrp_e_impl::rx_ddc_get(const wax::obj &, wax::obj &){ - + UHD_THROW_PROP_GET_ERROR(); } /*********************************************************************** * RX DDC Set **********************************************************************/ void usrp_e_impl::rx_ddc_set(const wax::obj &, const wax::obj &){ - + UHD_THROW_PROP_SET_ERROR(); } /*********************************************************************** @@ -58,12 +58,12 @@ void usrp_e_impl::tx_duc_init(void){ * TX DUC Get **********************************************************************/ void usrp_e_impl::tx_duc_get(const wax::obj &, wax::obj &){ - + UHD_THROW_PROP_GET_ERROR(); } /*********************************************************************** * TX DUC Set **********************************************************************/ void usrp_e_impl::tx_duc_set(const wax::obj &, const wax::obj &){ - + UHD_THROW_PROP_SET_ERROR(); } diff --git a/host/lib/usrp/usrp_e/mboard_impl.cpp b/host/lib/usrp/usrp_e/mboard_impl.cpp index 2d225c6ea..00ce4b782 100644 --- a/host/lib/usrp/usrp_e/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e/mboard_impl.cpp @@ -58,7 +58,7 @@ void usrp_e_impl::mboard_get(const wax::obj &key_, wax::obj &val){ return; case MBOARD_PROP_RX_DBOARD: - ASSERT_THROW(name == ""); + UHD_ASSERT_THROW(name == ""); val = _rx_dboard_proxy->get_link(); return; @@ -67,7 +67,7 @@ void usrp_e_impl::mboard_get(const wax::obj &key_, wax::obj &val){ return; case MBOARD_PROP_TX_DBOARD: - ASSERT_THROW(name == ""); + UHD_ASSERT_THROW(name == ""); val = _tx_dboard_proxy->get_link(); return; @@ -80,7 +80,7 @@ void usrp_e_impl::mboard_get(const wax::obj &key_, wax::obj &val){ return; case MBOARD_PROP_RX_DSP: - ASSERT_THROW(name == "ddc0"); + UHD_ASSERT_THROW(name == "ddc0"); val = _rx_ddc_proxy->get_link(); return; @@ -89,7 +89,7 @@ void usrp_e_impl::mboard_get(const wax::obj &key_, wax::obj &val){ return; case MBOARD_PROP_TX_DSP: - ASSERT_THROW(name == "duc0"); + UHD_ASSERT_THROW(name == "duc0"); val = _tx_duc_proxy->get_link(); return; @@ -101,10 +101,7 @@ void usrp_e_impl::mboard_get(const wax::obj &key_, wax::obj &val){ val = _clock_config; return; - case MBOARD_PROP_TIME_NOW: - case MBOARD_PROP_TIME_NEXT_PPS: - throw std::runtime_error("Error: trying to get write-only property on usrp-e mboard"); - + default: UHD_THROW_PROP_GET_ERROR(); } } @@ -112,5 +109,5 @@ void usrp_e_impl::mboard_get(const wax::obj &key_, wax::obj &val){ * Mboard Set **********************************************************************/ void usrp_e_impl::mboard_set(const wax::obj &, const wax::obj &){ - + UHD_THROW_PROP_SET_ERROR(); } diff --git a/host/lib/usrp/usrp_e/usrp_e_iface.cpp b/host/lib/usrp/usrp_e/usrp_e_iface.cpp index d4c988211..f12eee177 100644 --- a/host/lib/usrp/usrp_e/usrp_e_iface.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_iface.cpp @@ -100,7 +100,7 @@ public: ******************************************************************/ boost::uint32_t transact_spi( int which_slave, - const uhd::usrp::spi_config_t &config, + const uhd::spi_config_t &config, boost::uint32_t bits, size_t num_bits, bool readback @@ -114,8 +114,8 @@ public: //load the flags data.flags = 0; - data.flags |= (config.miso_edge == uhd::usrp::spi_config_t::EDGE_RISE)? UE_SPI_LATCH_RISE : UE_SPI_LATCH_FALL; - data.flags |= (config.mosi_edge == uhd::usrp::spi_config_t::EDGE_RISE)? UE_SPI_PUSH_FALL : UE_SPI_PUSH_RISE; + data.flags |= (config.miso_edge == uhd::spi_config_t::EDGE_RISE)? UE_SPI_LATCH_RISE : UE_SPI_LATCH_FALL; + data.flags |= (config.mosi_edge == uhd::spi_config_t::EDGE_RISE)? UE_SPI_PUSH_FALL : UE_SPI_PUSH_RISE; //call the spi ioctl this->ioctl(USRP_E_SPI, &data); diff --git a/host/lib/usrp/usrp_e/usrp_e_iface.hpp b/host/lib/usrp/usrp_e/usrp_e_iface.hpp index 4fc3bb33d..850e15ac4 100644 --- a/host/lib/usrp/usrp_e/usrp_e_iface.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_iface.hpp @@ -19,7 +19,7 @@ #define INCLUDED_USRP_E_IFACE_HPP #include -#include //spi config +#include #include #include #include @@ -87,7 +87,7 @@ public: */ virtual boost::uint32_t transact_spi( int which_slave, - const uhd::usrp::spi_config_t &config, + const uhd::spi_config_t &config, boost::uint32_t data, size_t num_bits, bool readback diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.cpp b/host/lib/usrp/usrp_e/usrp_e_impl.cpp index 4d08210e2..211b939ee 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.cpp @@ -112,7 +112,7 @@ void usrp_e_impl::get(const wax::obj &key_, wax::obj &val){ return; case DEVICE_PROP_MBOARD: - ASSERT_THROW(name == ""); + UHD_ASSERT_THROW(name == ""); val = _mboard_proxy->get_link(); return; @@ -128,6 +128,7 @@ void usrp_e_impl::get(const wax::obj &key_, wax::obj &val){ val = size_t(_max_num_samples); return; + default: UHD_THROW_PROP_GET_ERROR(); } } @@ -135,7 +136,7 @@ void usrp_e_impl::get(const wax::obj &key_, wax::obj &val){ * Device Set **********************************************************************/ void usrp_e_impl::set(const wax::obj &, const wax::obj &){ - throw std::runtime_error("Cannot set in usrp-e device"); + UHD_THROW_PROP_SET_ERROR(); } /*********************************************************************** -- cgit v1.2.3 From 1c4e9bd614dc8b7a17dc2bd95c322bbea940ca35 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 28 Apr 2010 11:33:10 -0700 Subject: moved i2c into usrp-e interface, used by dboard interface and eeprom --- host/lib/usrp/usrp_e/dboard_iface.cpp | 35 +++---------------------- host/lib/usrp/usrp_e/usrp_e_iface.cpp | 49 ++++++++++++++++++++++++++++++++--- host/lib/usrp/usrp_e/usrp_e_iface.hpp | 2 +- 3 files changed, 50 insertions(+), 36 deletions(-) diff --git a/host/lib/usrp/usrp_e/dboard_iface.cpp b/host/lib/usrp/usrp_e/dboard_iface.cpp index c4784d29c..f69cdd2b4 100644 --- a/host/lib/usrp/usrp_e/dboard_iface.cpp +++ b/host/lib/usrp/usrp_e/dboard_iface.cpp @@ -170,41 +170,12 @@ boost::uint32_t usrp_e_dboard_iface::read_write_spi( /*********************************************************************** * I2C **********************************************************************/ -static const size_t max_i2c_data_bytes = 10; - -void usrp_e_dboard_iface::write_i2c(boost::uint8_t addr, const byte_vector_t &buf){ - //allocate some memory for this transaction - UHD_ASSERT_THROW(buf.size() <= max_i2c_data_bytes); - boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; - - //load the data struct - usrp_e_i2c &data = reinterpret_cast(mem); - data.addr = addr; - data.len = buf.size(); - std::copy(buf.begin(), buf.end(), data.data); - - //call the spi ioctl - _iface->ioctl(USRP_E_I2C_WRITE, &data); +void usrp_e_dboard_iface::write_i2c(boost::uint8_t addr, const byte_vector_t &bytes){ + return _iface->write_i2c(addr, bytes); } byte_vector_t usrp_e_dboard_iface::read_i2c(boost::uint8_t addr, size_t num_bytes){ - //allocate some memory for this transaction - UHD_ASSERT_THROW(num_bytes <= max_i2c_data_bytes); - boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; - - //load the data struct - usrp_e_i2c &data = reinterpret_cast(mem); - data.addr = addr; - data.len = num_bytes; - - //call the spi ioctl - _iface->ioctl(USRP_E_I2C_READ, &data); - - //unload the data - byte_vector_t ret(data.len); - UHD_ASSERT_THROW(ret.size() == num_bytes); - std::copy(data.data, data.data+ret.size(), ret.begin()); - return ret; + return _iface->read_i2c(addr, num_bytes); } /*********************************************************************** diff --git a/host/lib/usrp/usrp_e/usrp_e_iface.cpp b/host/lib/usrp/usrp_e/usrp_e_iface.cpp index f12eee177..41737a716 100644 --- a/host/lib/usrp/usrp_e/usrp_e_iface.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_iface.cpp @@ -16,11 +16,14 @@ // #include "usrp_e_iface.hpp" +#include #include //ioctl #include //ioctl structures and constants #include #include +using namespace uhd; + class usrp_e_iface_impl : public usrp_e_iface{ public: @@ -95,12 +98,52 @@ public: return data.buf[0]; } + /******************************************************************* + * I2C + ******************************************************************/ + static const size_t max_i2c_data_bytes = 10; + + void write_i2c(boost::uint8_t addr, const byte_vector_t &bytes){ + //allocate some memory for this transaction + UHD_ASSERT_THROW(bytes.size() <= max_i2c_data_bytes); + boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; + + //load the data struct + usrp_e_i2c &data = reinterpret_cast(mem); + data.addr = addr; + data.len = bytes.size(); + std::copy(bytes.begin(), bytes.end(), data.data); + + //call the spi ioctl + this->ioctl(USRP_E_I2C_WRITE, &data); + } + + byte_vector_t read_i2c(boost::uint8_t addr, size_t num_bytes){ + //allocate some memory for this transaction + UHD_ASSERT_THROW(num_bytes <= max_i2c_data_bytes); + boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; + + //load the data struct + usrp_e_i2c &data = reinterpret_cast(mem); + data.addr = addr; + data.len = num_bytes; + + //call the spi ioctl + this->ioctl(USRP_E_I2C_READ, &data); + + //unload the data + byte_vector_t bytes(data.len); + UHD_ASSERT_THROW(bytes.size() == num_bytes); + std::copy(data.data, data.data+bytes.size(), bytes.begin()); + return bytes; + } + /******************************************************************* * SPI ******************************************************************/ boost::uint32_t transact_spi( int which_slave, - const uhd::spi_config_t &config, + const spi_config_t &config, boost::uint32_t bits, size_t num_bits, bool readback @@ -114,8 +157,8 @@ public: //load the flags data.flags = 0; - data.flags |= (config.miso_edge == uhd::spi_config_t::EDGE_RISE)? UE_SPI_LATCH_RISE : UE_SPI_LATCH_FALL; - data.flags |= (config.mosi_edge == uhd::spi_config_t::EDGE_RISE)? UE_SPI_PUSH_FALL : UE_SPI_PUSH_RISE; + data.flags |= (config.miso_edge == spi_config_t::EDGE_RISE)? UE_SPI_LATCH_RISE : UE_SPI_LATCH_FALL; + data.flags |= (config.mosi_edge == spi_config_t::EDGE_RISE)? UE_SPI_PUSH_FALL : UE_SPI_PUSH_RISE; //call the spi ioctl this->ioctl(USRP_E_SPI, &data); diff --git a/host/lib/usrp/usrp_e/usrp_e_iface.hpp b/host/lib/usrp/usrp_e/usrp_e_iface.hpp index 850e15ac4..763d19581 100644 --- a/host/lib/usrp/usrp_e/usrp_e_iface.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_iface.hpp @@ -29,7 +29,7 @@ * Provides a set of functions to implementation layer. * Including spi, peek, poke, control... */ -class usrp_e_iface : boost::noncopyable{ +class usrp_e_iface : boost::noncopyable, public uhd::i2c_iface{ public: typedef boost::shared_ptr sptr; -- cgit v1.2.3 From f2454f90023552c00b5b25aca4e8eaa8d46c0751 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 28 Apr 2010 13:07:22 +0000 Subject: Various updates to test programs. --- host/apps/omap_debug/Makefile | 5 ++- host/apps/omap_debug/usrp-e-fpga-rw.c | 32 ++++++++++++++----- host/apps/omap_debug/usrp-e-lb-test.c | 58 +++++++++++++++++++++++++++++++++++ host/apps/omap_debug/usrp_e.h | 6 ++++ 4 files changed, 93 insertions(+), 8 deletions(-) create mode 100644 host/apps/omap_debug/usrp-e-lb-test.c diff --git a/host/apps/omap_debug/Makefile b/host/apps/omap_debug/Makefile index f48eb9539..14be592ff 100644 --- a/host/apps/omap_debug/Makefile +++ b/host/apps/omap_debug/Makefile @@ -1,6 +1,6 @@ CFLAGS=-Wall -I../../lib/usrp/usrp_e/ -all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio usrp-e-debug-pins usrp-e-rw-random usrp-e-fpga-rw +all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio usrp-e-debug-pins usrp-e-rw-random usrp-e-fpga-rw usrp-e-lb-test usrp-e-spi : usrp-e-spi.c @@ -29,6 +29,8 @@ fpga-downloader : fpga-downloader.cc usrp-e-gpio : usrp-e-gpio.c +usrp-e-lb-test : usrp-e-lb-test.c + usrp-e-debug-pins : usrp-e-debug-pins.c clean : rm -f usrp-e-spi @@ -44,3 +46,4 @@ clean : rm -f fpga-downloader rm -f usrp-e-gpio rm -f usrp-e-debug-pins + rm -f usrp-e-lb-test diff --git a/host/apps/omap_debug/usrp-e-fpga-rw.c b/host/apps/omap_debug/usrp-e-fpga-rw.c index 455657203..f3fa1499a 100644 --- a/host/apps/omap_debug/usrp-e-fpga-rw.c +++ b/host/apps/omap_debug/usrp-e-fpga-rw.c @@ -38,6 +38,8 @@ static void *read_thread(void *threadid) int cnt, prev_seq_num; struct usrp_transfer_frame *rx_data; struct pkt *p; + int rx_pkt_cnt; + int i; printf("Greetings from the reading thread!\n"); @@ -51,23 +53,39 @@ static void *read_thread(void *threadid) prev_seq_num = 0; + rx_pkt_cnt = 0; + while (1) { cnt = read(fp, rx_data, 2048); if (cnt < 0) printf("Error returned from read: %d\n", cnt); + rx_pkt_cnt++; + + if (rx_pkt_cnt == 512) { + printf("."); + fflush(stdout); + rx_pkt_cnt = 0; + } + if (rx_data->flags & RB_OVERRUN) + printf("RX ring buffer overrun occurred at packet %d\n", rx_pkt_cnt); + +// for (i = 0; i < 10; i++) +// printf(" %d", p->data[i]); +// printf("\n"); + // printf("Packet received, flags = %X, len = %d\n", rx_data->flags, rx_data->len); // printf("p->seq_num = %d\n", p->seq_num); - if (p->seq_num != prev_seq_num + 1) - printf("Sequence number fail, current = %X, previous = %X\n", - p->seq_num, prev_seq_num); - prev_seq_num = p->seq_num; +// if (p->seq_num != prev_seq_num + 1) +// printf("Sequence number fail, current = %X, previous = %X\n", +// p->seq_num, prev_seq_num); +// prev_seq_num = p->seq_num; - if (calc_checksum(p) != p->checksum) - printf("Checksum fail packet = %X, expected = %X\n", - calc_checksum(p), p->checksum); +// if (calc_checksum(p) != p->checksum) +// printf("Checksum fail packet = %X, expected = %X\n", +// calc_checksum(p), p->checksum); // printf("\n"); } diff --git a/host/apps/omap_debug/usrp-e-lb-test.c b/host/apps/omap_debug/usrp-e-lb-test.c new file mode 100644 index 000000000..675de8622 --- /dev/null +++ b/host/apps/omap_debug/usrp-e-lb-test.c @@ -0,0 +1,58 @@ +#include +#include +#include +#include +#include +#include +#include +#include "usrp_e.h" + +// max length #define PKT_DATA_LENGTH 1016 + +int main(int argc, char *argv[]) +{ + struct usrp_transfer_frame *tx_data, *rx_data; + int i, fp, packet_data_length, cnt; + struct usrp_e_ctl16 d; + + if (argc < 2) { + printf("%s data_size (in bytes < 2040)\n", argv[0]); + return -1; + } + + packet_data_length = atoi(argv[1]); + + fp = open("/dev/usrp_e0", O_RDWR); + + d.offset = 14; + d.count = 1; + d.buf[0] = (1 << 13); + ioctl(fp, USRP_E_WRITE_CTL16, &d); + + tx_data = malloc(2048); + rx_data = malloc(2048); + + tx_data->flags = 0; + tx_data->len = sizeof(struct usrp_transfer_frame) + packet_data_length; + + while (1) { + + for (i = 0; i < packet_data_length; i++) { + tx_data->buf[i] = random() >> 24; + + } + + cnt = write(fp, tx_data, 2048); + cnt = read(fp, rx_data, 2048); + + if (tx_data->len != rx_data->len) + printf("Bad frame length sent %d, read %d\n", tx_data->len, rx_data->len); + + for (i = 0; i < packet_data_length; i++) { + if (tx_data->buf[i] != rx_data->buf[i]) + printf("Bad data at %d, sent %d, received %d\n", i, tx_data->buf[i], rx_data->buf[i]); + } + printf("---------------------------------------------------\n"); + sleep(1); + } +} diff --git a/host/apps/omap_debug/usrp_e.h b/host/apps/omap_debug/usrp_e.h index 48a3201cb..d4132021f 100644 --- a/host/apps/omap_debug/usrp_e.h +++ b/host/apps/omap_debug/usrp_e.h @@ -1,3 +1,4 @@ + /* * Copyright (C) 2010 Ettus Research, LLC * @@ -77,6 +78,11 @@ struct usrp_transfer_frame { __u8 buf[]; }; +// Flag defines +#define RB_USER (1 << 0) +#define RB_KERNEL (1 << 1) +#define RB_OVERRUN (1 << 2) + struct ring_buffer_entry { unsigned long dma_addr; struct usrp_transfer_frame *frame_addr; -- cgit v1.2.3 From eb5bfb963459dbb3e51df49b5aa22fcbda1627d5 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 28 Apr 2010 17:03:14 -0700 Subject: separate timed tx and rx instead of loopback --- usrp2/top/u1e/u1e_core.v | 54 +++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 51 insertions(+), 3 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index f231791da..d5a3ddf68 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -58,12 +58,48 @@ module u1e_core .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), .debug(debug_gpmc)); - +/* fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo (.clk(wb_clk), .reset(wb_rst), .clear(0), .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); +*/ + wire tx_strobe, rx_strobe, tx_enable, rx_enable; + wire [7:0] rate; + wire tx_fifo_rdy, rx_fifo_rdy; + + cic_strober tx_strober (.clock(wb_clk), .reset(wb_rst), .enable(tx_enable), + .rate(rate), .strobe_fast(1), .strobe_slow(tx_strobe)); + + fifo_cascade #(.WIDTH(36), .SIZE(11)) tx_fifo + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), + .dataout(), .src_rdy_o(tx_fifo_rdy), .dst_rdy_i(tx_strobe)); + + + reg [15:0] ctr; + wire [15:0] rx_pkt_len = 480; + wire rx_eof = (ctr == rx_pkt_len); + wire rx_sof = (ctr == 0); + + cic_strober rx_strober (.clock(wb_clk), .reset(wb_rst), .enable(rx_enable), + .rate(rate), .strobe_fast(1), .strobe_slow(rx_strobe)); + + fifo_cascade #(.WIDTH(36), .SIZE(11)) rx_fifo + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .datain({2'b00,rx_eof,rx_sof,16'd0,ctr}), .src_rdy_i(rx_strobe), .dst_rdy_o(rx_fifo_rdy), + .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + always @(posedge wb_clk) + if(wb_rst) + ctr <= 0; + else if(rx_strobe & rx_fifo_rdy) + if(ctr == rx_pkt_len) + ctr <= 0; + else + ctr <= ctr + 1; + + // ///////////////////////////////////////////////////////////////////////////////////// // Wishbone Intercon, single master wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, @@ -136,7 +172,7 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////////////////// // Slave 0, Misc LEDs, Switches, controls - reg [15:0] reg_leds, reg_cgen_ctrl, reg_test; + reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; localparam REG_LEDS = 7'd0; // out localparam REG_SWITCHES = 7'd2; // in @@ -145,6 +181,7 @@ module u1e_core localparam REG_TEST = 7'd8; // out localparam REG_RX_FRAMELEN = 7'd10; // out localparam REG_TX_FRAMELEN = 7'd12; // in + localparam REG_XFER_RATE = 7'd14; // in always @(posedge wb_clk) if(wb_rst) @@ -152,6 +189,8 @@ module u1e_core reg_leds <= 0; reg_cgen_ctrl <= 2'b11; reg_test <= 0; + tx_frame_len <= 0; + xfer_rate <= 0; end else if(s0_cyc & s0_stb & s0_we) @@ -164,7 +203,13 @@ module u1e_core reg_test <= s0_dat_mosi; REG_TX_FRAMELEN : tx_frame_len <= s0_dat_mosi; + REG_XFER_RATE : + xfer_rate <= s0_dat_mosi; endcase // case (s0_adr[6:0]) + + assign tx_enable = xfer_rate[15]; + assign rx_enable = xfer_rate[14]; + assign rate = xfer_rate[7:0]; assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; @@ -273,6 +318,9 @@ module u1e_core { EM_D } }; assign debug_gpio_0 = { debug_gpmc }; - assign debug_gpio_1 = { bus_error, misc_gpio[11:0] }; + assign debug_gpio_1 = { {rx_enable, rx_strobe, rx_fifo_rdy, rx_strobe & ~rx_fifo_rdy}, + {tx_enable, tx_strobe, tx_fifo_rdy, tx_strobe & ~tx_fifo_rdy}, + {rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0}, + {3'b0, bus_error, misc_gpio[11:0]} }; endmodule // u1e_core -- cgit v1.2.3 From 2de179640be9d897a63f7423f6e04399394abb8b Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 29 Apr 2010 05:26:29 +0000 Subject: Add script to setup board id info in eeprom. --- host/apps/omap_debug/setup-board-id-eeprom.sh | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100755 host/apps/omap_debug/setup-board-id-eeprom.sh diff --git a/host/apps/omap_debug/setup-board-id-eeprom.sh b/host/apps/omap_debug/setup-board-id-eeprom.sh new file mode 100755 index 000000000..4dba1cce5 --- /dev/null +++ b/host/apps/omap_debug/setup-board-id-eeprom.sh @@ -0,0 +1,17 @@ +#!/bin/sh + +i2cset -y 3 0x51 0x00 0x00 +i2cset -y 3 0x51 0x01 0x03 +i2cset -y 3 0x51 0x02 0x00 +i2cset -y 3 0x51 0x03 0x01 +i2cset -y 3 0x51 0x04 0x01 +i2cset -y 3 0x51 0x05 0x00 +i2cset -y 3 0x51 0x06 0x00 + +i2cget -y 3 0x51 0 b +i2cget -y 3 0x51 1 b +i2cget -y 3 0x51 2 b +i2cget -y 3 0x51 3 b +i2cget -y 3 0x51 4 b +i2cget -y 3 0x51 5 b +i2cget -y 3 0x51 6 b -- cgit v1.2.3 From 3a8577aeb3c76dce0d0dcf0c9c7ce8d9aaf0a1d8 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 29 Apr 2010 11:50:56 +0000 Subject: work on clock control init, added dummy spi slaves: must fix --- host/lib/CMakeLists.txt | 1 + host/lib/ic_reg_maps/.gitignore | 1 + host/lib/ic_reg_maps/gen_ad9522_regs.py | 4 +- host/lib/usrp/usrp_e/clock_ctrl.cpp | 129 ++++++++++++++++++++++++++++++++ host/lib/usrp/usrp_e/clock_ctrl.hpp | 55 ++++++++++++++ host/lib/usrp/usrp_e/dboard_iface.cpp | 4 +- host/lib/usrp/usrp_e/usrp_e_regs.hpp | 9 +++ 7 files changed, 199 insertions(+), 4 deletions(-) create mode 100644 host/lib/usrp/usrp_e/clock_ctrl.cpp create mode 100644 host/lib/usrp/usrp_e/clock_ctrl.hpp diff --git a/host/lib/CMakeLists.txt b/host/lib/CMakeLists.txt index 310c81bfb..75d4ac2c4 100644 --- a/host/lib/CMakeLists.txt +++ b/host/lib/CMakeLists.txt @@ -177,6 +177,7 @@ CHECK_INCLUDE_FILES( IF(HAVE_USRP_E_REQUIRED_HEADERS) MESSAGE(STATUS " Building usrp-e support.") LIST(APPEND libuhd_sources + usrp/usrp_e/clock_ctrl.cpp usrp/usrp_e/dboard_impl.cpp usrp/usrp_e/dboard_iface.cpp usrp/usrp_e/dsp_impl.cpp diff --git a/host/lib/ic_reg_maps/.gitignore b/host/lib/ic_reg_maps/.gitignore index a74b07aee..053049d05 100644 --- a/host/lib/ic_reg_maps/.gitignore +++ b/host/lib/ic_reg_maps/.gitignore @@ -1 +1,2 @@ /*.pyc +/*.pyo diff --git a/host/lib/ic_reg_maps/gen_ad9522_regs.py b/host/lib/ic_reg_maps/gen_ad9522_regs.py index 63d8abe24..9da51205b 100755 --- a/host/lib/ic_reg_maps/gen_ad9522_regs.py +++ b/host/lib/ic_reg_maps/gen_ad9522_regs.py @@ -42,7 +42,7 @@ reset_all_counters 0x016[4] 0 b_counter_bypass 0x016[3] 0 normal, div1 prescaler_p 0x016[2:0] 6 div1, div2, div2_3, div4_5, div8_9, div16_17, div32_33, div3 status_pin_control 0x017[7:2] 0 -antibacklash_pulse_width 0x017[1:0] 0 2_9ns, 1_3ns, 6_0ns, 2_9ns +antibacklash_pulse_width 0x017[1:0] 0 2_9ns, 1_3ns, 6_0ns enb_cmos_ref_input_dc_off 0x018[7] 0 lock_detect_counter 0x018[6:5] 0 5cyc, 16cyc, 64cyc, 255cyc digital_lock_detect_window 0x018[4] 0 high_range, low_range @@ -60,7 +60,7 @@ enable_ref2_freq_monitor 0x01B[6] 0 enable_ref1_freq_monitor 0x01B[5] 0 refmon_pin_control 0x01B[4:0] 0 disable_switchover_deglitch 0x01C[7] 0 -select_ref2 0x01C[6] 0 ref1, ref2 +select_ref 0x01C[6] 0 ref1, ref2 use_ref_sel_pin 0x01C[5] 0 register, ref_sel enb_auto_ref_switchover 0x01C[4] 0 manual, auto stay_on_ref2 0x01C[3] 0 return_ref1, stay_ref2 diff --git a/host/lib/usrp/usrp_e/clock_ctrl.cpp b/host/lib/usrp/usrp_e/clock_ctrl.cpp new file mode 100644 index 000000000..5f6fb4bfb --- /dev/null +++ b/host/lib/usrp/usrp_e/clock_ctrl.cpp @@ -0,0 +1,129 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "clock_ctrl.hpp" +#include "ad9522_regs.hpp" +#include +#include "usrp_e_regs.hpp" //spi slave constants +#include +#include +#include + +using namespace uhd; + +/*********************************************************************** + * Clock Control Implementation + **********************************************************************/ +class clock_ctrl_impl : public clock_ctrl{ +public: + //structors + clock_ctrl_impl(usrp_e_iface::sptr iface); + ~clock_ctrl_impl(void); + + void enable_rx_dboard_clock(bool enb); + void enable_tx_dboard_clock(bool enb); + +private: + usrp_e_iface::sptr _iface; + ad9522_regs_t _ad9522_regs; + + void latch_regs(void){ + _ad9522_regs.io_update = 1; + this->send_reg(0x232); + } + void send_reg(boost::uint16_t addr); +}; + +/*********************************************************************** + * Clock Control Methods + **********************************************************************/ +clock_ctrl_impl::clock_ctrl_impl(usrp_e_iface::sptr iface){ + _iface = iface; + + //init the clock gen registers + //Note: out0 should already be clocking the FPGA or this isnt going to work + _ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO; + _ad9522_regs.status_pin_control = 0x1; //n divider + _ad9522_regs.ld_pin_control = 0x32; //show ref2 + _ad9522_regs.refmon_pin_control = 0x12; //show ref2 + + _ad9522_regs.enable_ref2 = 1; + _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF2; + + _ad9522_regs.r_counter_lsb = 1; + _ad9522_regs.r_counter_msb = 0; + _ad9522_regs.a_counter = 0; + _ad9522_regs.b_counter_lsb = 20; + _ad9522_regs.b_counter_msb = 0; + _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV8_9; + + _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL; + _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_3_0MA; + + _ad9522_regs.vco_calibration_now = 1; //calibrate it! + _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5; + _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_VCO; + + _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; + _ad9522_regs.divider0_low_cycles = 2; //3 low + _ad9522_regs.divider0_high_cycles = 1; //2 high + + //setup a list of register ranges to write + typedef std::pair range_t; + static const std::vector ranges = boost::assign::list_of + (range_t(0x000, 0x000)) (range_t(0x010, 0x01F)) + (range_t(0x0F0, 0x0FD)) (range_t(0x190, 0x19B)) + (range_t(0x1E0, 0x1E1)) (range_t(0x230, 0x230)) + ; + + //write initial register values and latch/update + BOOST_FOREACH(const range_t &range, ranges){ + for(boost::uint16_t addr = range.first; addr <= range.second; addr++){ + this->send_reg(addr); + } + } + this->latch_regs(); +} + +clock_ctrl_impl::~clock_ctrl_impl(void){ + this->enable_rx_dboard_clock(false); + this->enable_tx_dboard_clock(false); +} + +void clock_ctrl_impl::enable_rx_dboard_clock(bool enb){ + +} + +void clock_ctrl_impl::enable_tx_dboard_clock(bool enb){ + +} + +void clock_ctrl_impl::send_reg(boost::uint16_t addr){ + _iface->transact_spi( + UE_SPI_SS_AD9522, + spi_config_t::EDGE_RISE, + _ad9522_regs.get_write_reg(addr), + 24, false /*no rb*/ + ); +} + +/*********************************************************************** + * Clock Control Make + **********************************************************************/ +clock_ctrl::sptr clock_ctrl::make(usrp_e_iface::sptr iface){ + return sptr(new clock_ctrl_impl(iface)); +} diff --git a/host/lib/usrp/usrp_e/clock_ctrl.hpp b/host/lib/usrp/usrp_e/clock_ctrl.hpp new file mode 100644 index 000000000..d0b896a8f --- /dev/null +++ b/host/lib/usrp/usrp_e/clock_ctrl.hpp @@ -0,0 +1,55 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_USRP_E_CLOCK_CTRL_HPP +#define INCLUDED_USRP_E_CLOCK_CTRL_HPP + +#include "usrp_e_iface.hpp" +#include +#include + +/*! + * The usrp-e clock control: + * - Setup system clocks. + * - Disable/enable clock lines. + */ +class clock_ctrl : boost::noncopyable{ +public: + typedef boost::shared_ptr sptr; + + /*! + * Make a new clock control object. + * \param iface the usrp_e iface object + * \return the clock control object + */ + static sptr make(usrp_e_iface::sptr iface); + + /*! + * Enable/disable the rx dboard clock. + * \param enb true to enable + */ + virtual void enable_rx_dboard_clock(bool enb) = 0; + + /*! + * Enable/disable the tx dboard clock. + * \param enb true to enable + */ + virtual void enable_tx_dboard_clock(bool enb) = 0; + +}; + +#endif /* INCLUDED_USRP_E_CLOCK_CTRL_HPP */ diff --git a/host/lib/usrp/usrp_e/dboard_iface.cpp b/host/lib/usrp/usrp_e/dboard_iface.cpp index f69cdd2b4..2a3976ba1 100644 --- a/host/lib/usrp/usrp_e/dboard_iface.cpp +++ b/host/lib/usrp/usrp_e/dboard_iface.cpp @@ -143,8 +143,8 @@ void usrp_e_dboard_iface::set_atr_reg(unit_t bank, atr_reg_t atr, boost::uint16_ */ static boost::uint32_t unit_to_otw_spi_dev(dboard_iface::unit_t unit){ switch(unit){ - case dboard_iface::UNIT_TX: return UE_SPI_CTRL_TXNEG; - case dboard_iface::UNIT_RX: return UE_SPI_CTRL_RXNEG; + case dboard_iface::UNIT_TX: return UE_SPI_SS_TX_DB; + case dboard_iface::UNIT_RX: return UE_SPI_SS_RX_DB; } throw std::invalid_argument("unknown unit type"); } diff --git a/host/lib/usrp/usrp_e/usrp_e_regs.hpp b/host/lib/usrp/usrp_e/usrp_e_regs.hpp index e7f89db7b..46df8d089 100644 --- a/host/lib/usrp/usrp_e/usrp_e_regs.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_regs.hpp @@ -50,6 +50,15 @@ #define UE_REG_SPI_BASE UE_REG_SLAVE(2) +//spi slave constants (copied from usrp2, TODO FIXME) +#define UE_SPI_SS_AD9522 1 +#define UE_SPI_SS_AD9777 2 +#define UE_SPI_SS_RX_DAC 4 +#define UE_SPI_SS_RX_ADC 8 +#define UE_SPI_SS_RX_DB 16 +#define UE_SPI_SS_TX_DAC 32 +#define UE_SPI_SS_TX_ADC 64 +#define UE_SPI_SS_TX_DB 128 //////////////////////////////////////////////// // Slave 3 -- I2C Core -- cgit v1.2.3 From e526627270cf2846d0cba0d30a5947621c545be1 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Sun, 2 May 2010 08:52:36 +0000 Subject: Update IP address for my home desktop. Change module version to 2.6.33. --- host/apps/omap_debug/fetch-kernel.sh | 2 +- host/apps/omap_debug/fetch-module.sh | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/host/apps/omap_debug/fetch-kernel.sh b/host/apps/omap_debug/fetch-kernel.sh index f25f139fa..ce420f3d2 100755 --- a/host/apps/omap_debug/fetch-kernel.sh +++ b/host/apps/omap_debug/fetch-kernel.sh @@ -1,7 +1,7 @@ if [ $GHQ ]; then scp $GHQ_USER@astro:/workspace/usrp1-e-dev/kernel_usrp/arch/arm/boot/uImage /media/mmcblk0p1/uImage else - scp balister@192.168.1.167:src/git/kernel_usrp/arch/arm/boot/uImage /media/mmcblk0p1/uImage + scp balister@192.168.1.10:src/git/kernel_usrp/arch/arm/boot/uImage /media/mmcblk0p1/uImage fi sync diff --git a/host/apps/omap_debug/fetch-module.sh b/host/apps/omap_debug/fetch-module.sh index 0957ad7b4..e23289050 100755 --- a/host/apps/omap_debug/fetch-module.sh +++ b/host/apps/omap_debug/fetch-module.sh @@ -1,6 +1,6 @@ if [ $GHQ ]; then - scp $GHQ_USER@astro:/workspace/usrp1-e-dev/kernel_usrp/drivers/misc/usrp_e.ko /lib/modules/2.6.34-rc1/kernel/drivers/misc + scp $GHQ_USER@astro:/workspace/usrp1-e-dev/kernel_usrp/drivers/misc/usrp_e.ko /lib/modules/2.6.33/kernel/drivers/misc else - scp balister@192.168.1.167:src/git/kernel_usrp/drivers/misc/usrp_e.ko /lib/modules/2.6.33-rc3/kernel/drivers/misc + scp balister@192.168.1.10:src/git/kernel_usrp/drivers/misc/usrp_e.ko /lib/modules/2.6.33-rc3/kernel/drivers/misc fi sync -- cgit v1.2.3 From 084459a16892c393af08b674ea1df7777e47423a Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Sun, 2 May 2010 08:53:32 +0000 Subject: Change overrun indication. New progress indicator. Turn on RT scheduler for user space. --- host/apps/omap_debug/usrp-e-fpga-rw.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-fpga-rw.c b/host/apps/omap_debug/usrp-e-fpga-rw.c index f3fa1499a..6b585913e 100644 --- a/host/apps/omap_debug/usrp-e-fpga-rw.c +++ b/host/apps/omap_debug/usrp-e-fpga-rw.c @@ -69,7 +69,7 @@ static void *read_thread(void *threadid) } if (rx_data->flags & RB_OVERRUN) - printf("RX ring buffer overrun occurred at packet %d\n", rx_pkt_cnt); + printf("O"); // for (i = 0; i < 10; i++) // printf(" %d", p->data[i]); @@ -93,7 +93,7 @@ static void *read_thread(void *threadid) static void *write_thread(void *threadid) { - int seq_number, i, cnt; + int seq_number, i, cnt, tx_pkt_cnt; struct usrp_transfer_frame *tx_data; struct pkt *p; @@ -115,8 +115,25 @@ static void *write_thread(void *threadid) printf("tx_data->len = %d\n", tx_data->len); seq_number = 1; + tx_pkt_cnt = 0; while (1) { + + tx_pkt_cnt++; + if (tx_pkt_cnt == 512) { + printf("."); + fflush(stdout); + } + if (tx_pkt_cnt == 1024) { + printf("'"); + fflush(stdout); + } + if (tx_pkt_cnt == 1536) { + printf(":"); + fflush(stdout); + tx_pkt_cnt = 0; + } + // printf("tx flags = %X, len = %d\n", tx_data->flags, tx_data->len); p->seq_num = seq_number++; p->checksum = calc_checksum(p); @@ -134,6 +151,9 @@ int main(int argc, char *argv[]) long int t; int fpga_config_flag ,decimation; struct usrp_e_ctl16 d; + struct sched_param s = { + .sched_priority = 1 + }; if (argc < 4) { printf("%s t|w|rw decimation data_size\n", argv[0]); @@ -163,6 +183,8 @@ int main(int argc, char *argv[]) sleep(1); // in case the kernel threads need time to start. FIXME if so + sched_setscheduler(0, SCHED_RR, &s); + if (fpga_config_flag & (1 << 14)) { if (pthread_create(&rx, NULL, read_thread, (void *) t)) { printf("Failed to create rx thread\n"); -- cgit v1.2.3 From 2e222f4a77df389551d08b42a1bf947487d1442f Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 3 May 2010 11:30:17 +0000 Subject: spi working, talked to ad9522 --- host/include/uhd/utils/assert.hpp | 9 ++++++++- host/lib/usrp/usrp_e/clock_ctrl.cpp | 14 ++++++++++++-- host/lib/usrp/usrp_e/dboard_impl.cpp | 6 +++--- host/lib/usrp/usrp_e/usrp_e_iface.hpp | 9 +++++++++ host/lib/usrp/usrp_e/usrp_e_impl.cpp | 6 ++++++ host/lib/usrp/usrp_e/usrp_e_impl.hpp | 3 +++ host/lib/usrp/usrp_e/usrp_e_regs.hpp | 14 +++++--------- host/test/error_test.cpp | 5 +++-- host/utils/uhd_find_devices.cpp | 2 +- 9 files changed, 50 insertions(+), 18 deletions(-) diff --git a/host/include/uhd/utils/assert.hpp b/host/include/uhd/utils/assert.hpp index 6aca64f8c..577050aff 100644 --- a/host/include/uhd/utils/assert.hpp +++ b/host/include/uhd/utils/assert.hpp @@ -29,7 +29,14 @@ #include #ifndef BOOST_THROW_EXCEPTION -#define BOOST_THROW_EXCEPTION(x) throw std::runtime_error("") + #include + #include + #define BOOST_THROW_EXCEPTION(x)\ + ::boost::throw_exception( ::boost::enable_error_info(x) <<\ + ::boost::throw_function(BOOST_CURRENT_FUNCTION) <<\ + ::boost::throw_file(__FILE__) <<\ + ::boost::throw_line((int)__LINE__) ) + #endif namespace uhd{ diff --git a/host/lib/usrp/usrp_e/clock_ctrl.cpp b/host/lib/usrp/usrp_e/clock_ctrl.cpp index 5f6fb4bfb..fa4028cc5 100644 --- a/host/lib/usrp/usrp_e/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e/clock_ctrl.cpp @@ -22,6 +22,7 @@ #include #include #include +#include using namespace uhd; @@ -97,6 +98,14 @@ clock_ctrl_impl::clock_ctrl_impl(usrp_e_iface::sptr iface){ } } this->latch_regs(); + //test read: + //boost::uint32_t reg = _ad9522_regs.get_read_reg(0x01b); + //boost::uint32_t result = _iface->transact_spi( + // UE_SPI_SS_AD9522, + // spi_config_t::EDGE_RISE, + // reg, 24, true /*no*/ + //); + //std::cout << "result " << std::hex << result << std::endl; } clock_ctrl_impl::~clock_ctrl_impl(void){ @@ -113,11 +122,12 @@ void clock_ctrl_impl::enable_tx_dboard_clock(bool enb){ } void clock_ctrl_impl::send_reg(boost::uint16_t addr){ + boost::uint32_t reg = _ad9522_regs.get_write_reg(addr); + std::cout << "clock control write reg: " << std::hex << reg << std::endl; _iface->transact_spi( UE_SPI_SS_AD9522, spi_config_t::EDGE_RISE, - _ad9522_regs.get_write_reg(addr), - 24, false /*no rb*/ + reg, 24, false /*no rb*/ ); } diff --git a/host/lib/usrp/usrp_e/dboard_impl.cpp b/host/lib/usrp/usrp_e/dboard_impl.cpp index e87a2c0a5..00b5d77d7 100644 --- a/host/lib/usrp/usrp_e/dboard_impl.cpp +++ b/host/lib/usrp/usrp_e/dboard_impl.cpp @@ -24,15 +24,15 @@ using namespace uhd::usrp; * Dboard Initialization **********************************************************************/ void usrp_e_impl::dboard_init(void){ - dboard_id_t rx_dboard_id = dboard_id::NONE; //TODO get these from the eeprom - dboard_id_t tx_dboard_id = dboard_id::NONE; + _rx_db_eeprom = dboard_eeprom_t(_iface->read_eeprom(I2C_ADDR_RX_DB, 0, dboard_eeprom_t::num_bytes())); + _tx_db_eeprom = dboard_eeprom_t(_iface->read_eeprom(I2C_ADDR_TX_DB, 0, dboard_eeprom_t::num_bytes())); //create a new dboard interface and manager dboard_iface::sptr dboard_iface( make_usrp_e_dboard_iface(_iface) ); _dboard_manager = dboard_manager::make( - rx_dboard_id, tx_dboard_id, dboard_iface + _rx_db_eeprom.id, _tx_db_eeprom.id, dboard_iface ); //setup the dboard proxies diff --git a/host/lib/usrp/usrp_e/usrp_e_iface.hpp b/host/lib/usrp/usrp_e/usrp_e_iface.hpp index 763d19581..016d7448f 100644 --- a/host/lib/usrp/usrp_e/usrp_e_iface.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_iface.hpp @@ -24,6 +24,15 @@ #include #include +//////////////////////////////////////////////////////////////////////// +// I2C addresses +//////////////////////////////////////////////////////////////////////// +#define I2C_DEV_EEPROM 0x50 // 24LC02[45]: 7-bits 1010xxx +#define I2C_ADDR_MBOARD (I2C_DEV_EEPROM | 0x0) +#define I2C_ADDR_TX_DB (I2C_DEV_EEPROM | 0x4) +#define I2C_ADDR_RX_DB (I2C_DEV_EEPROM | 0x5) +//////////////////////////////////////////////////////////////////////// + /*! * The usrp-e interface class: * Provides a set of functions to implementation layer. diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.cpp b/host/lib/usrp/usrp_e/usrp_e_impl.cpp index 211b939ee..52bbcdd32 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.cpp @@ -21,7 +21,9 @@ #include #include #include +#include #include //open +#include "clock_ctrl.hpp" using namespace uhd; using namespace uhd::usrp; @@ -73,6 +75,8 @@ device::sptr usrp_e::make(const device_addr_t &device_addr){ * Structors **********************************************************************/ usrp_e_impl::usrp_e_impl(const std::string &node){ + std::cout << boost::format("Opening USRP-E on %s") % node << std::endl; + //open the device node and check file descriptor if ((_node_fd = ::open(node.c_str(), O_RDWR)) < 0){ throw std::runtime_error(str( @@ -82,6 +86,8 @@ usrp_e_impl::usrp_e_impl(const std::string &node){ _iface = usrp_e_iface::make(_node_fd); + clock_ctrl::sptr my_clk_ctrl = clock_ctrl::make(_iface); + //initialize the mboard mboard_init(); diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index 08ace2ffb..23e36ed05 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -17,6 +17,7 @@ #include "usrp_e_iface.hpp" #include +#include #include #include @@ -105,11 +106,13 @@ private: uhd::usrp::dboard_manager::sptr _dboard_manager; //rx dboard functions and settings + uhd::usrp::dboard_eeprom_t _rx_db_eeprom; void rx_dboard_get(const wax::obj &, wax::obj &); void rx_dboard_set(const wax::obj &, const wax::obj &); wax_obj_proxy::sptr _rx_dboard_proxy; //tx dboard functions and settings + uhd::usrp::dboard_eeprom_t _tx_db_eeprom; void tx_dboard_get(const wax::obj &, wax::obj &); void tx_dboard_set(const wax::obj &, const wax::obj &); wax_obj_proxy::sptr _tx_dboard_proxy; diff --git a/host/lib/usrp/usrp_e/usrp_e_regs.hpp b/host/lib/usrp/usrp_e/usrp_e_regs.hpp index 46df8d089..7f35212f4 100644 --- a/host/lib/usrp/usrp_e/usrp_e_regs.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_regs.hpp @@ -50,15 +50,11 @@ #define UE_REG_SPI_BASE UE_REG_SLAVE(2) -//spi slave constants (copied from usrp2, TODO FIXME) -#define UE_SPI_SS_AD9522 1 -#define UE_SPI_SS_AD9777 2 -#define UE_SPI_SS_RX_DAC 4 -#define UE_SPI_SS_RX_ADC 8 -#define UE_SPI_SS_RX_DB 16 -#define UE_SPI_SS_TX_DAC 32 -#define UE_SPI_SS_TX_ADC 64 -#define UE_SPI_SS_TX_DB 128 +//spi slave constants +#define UE_SPI_SS_AD9522 (1 << 3) +#define UE_SPI_SS_AD9862 (1 << 2) +#define UE_SPI_SS_TX_DB (1 << 1) +#define UE_SPI_SS_RX_DB (1 << 0) //////////////////////////////////////////////// // Slave 3 -- I2C Core diff --git a/host/test/error_test.cpp b/host/test/error_test.cpp index c5b0af45e..3f2479f99 100644 --- a/host/test/error_test.cpp +++ b/host/test/error_test.cpp @@ -17,7 +17,7 @@ #include #include -#include +//#include #include #include @@ -30,11 +30,12 @@ BOOST_AUTO_TEST_CASE(test_assert_has){ //verify the std::has utility BOOST_CHECK(std::has(vec, 2)); BOOST_CHECK(not std::has(vec, 1)); - +/* std::cout << "The output of the assert_has error:" << std::endl; try{ uhd::assert_has(vec, 1, "prime"); }catch(const boost::exception &e){ std::cout << boost::diagnostic_information(e) << std::endl; } +*/ } diff --git a/host/utils/uhd_find_devices.cpp b/host/utils/uhd_find_devices.cpp index b778eeb68..8281c92bc 100644 --- a/host/utils/uhd_find_devices.cpp +++ b/host/utils/uhd_find_devices.cpp @@ -53,7 +53,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ std::cout << "-- UHD Device " << i << std::endl; std::cout << "--------------------------------------------------" << std::endl; std::cout << device_addrs[i].to_pp_string() << std::endl << std::endl; - //uhd::device::make(device_addrs[i]); //test make + uhd::device::make(device_addrs[i]); //test make } return 0; -- cgit v1.2.3 From a8f284d03d061a2fb9a6daf6e6bc2493daccd5d4 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Mon, 3 May 2010 12:44:41 +0000 Subject: Add a hack to work around a driver race. Remove when teh driver is fixed. --- host/apps/omap_debug/usrp-e-spi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/host/apps/omap_debug/usrp-e-spi.c b/host/apps/omap_debug/usrp-e-spi.c index caa36b3f1..264231731 100644 --- a/host/apps/omap_debug/usrp-e-spi.c +++ b/host/apps/omap_debug/usrp-e-spi.c @@ -28,6 +28,8 @@ int main(int argc, char *argv[]) fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); + sleep(1); // HACK HACK + spi_dat.slave = slave; spi_dat.data = data; spi_dat.length = length; -- cgit v1.2.3 From 4c4e0f48534a735cc7f5780f4483871264a880ad Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Mon, 3 May 2010 12:51:02 +0000 Subject: Add hack to work around driver race. --- host/apps/omap_debug/usrp-e-i2c.c | 3 +++ host/apps/omap_debug/usrp-e-spi.c | 1 + 2 files changed, 4 insertions(+) diff --git a/host/apps/omap_debug/usrp-e-i2c.c b/host/apps/omap_debug/usrp-e-i2c.c index 575430f84..57a3f4739 100644 --- a/host/apps/omap_debug/usrp-e-i2c.c +++ b/host/apps/omap_debug/usrp-e-i2c.c @@ -1,6 +1,7 @@ #include #include #include +#include #include #include #include @@ -37,6 +38,8 @@ int main(int argc, char *argv[]) fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); + sleep(1); + if (direction) { count = argc - 3; } else { diff --git a/host/apps/omap_debug/usrp-e-spi.c b/host/apps/omap_debug/usrp-e-spi.c index 264231731..47ee9369c 100644 --- a/host/apps/omap_debug/usrp-e-spi.c +++ b/host/apps/omap_debug/usrp-e-spi.c @@ -1,5 +1,6 @@ #include #include +#include #include #include #include -- cgit v1.2.3 From b30cbe85e8537de6a94e481a57033b5e57a73e12 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 3 May 2010 12:34:45 -0700 Subject: have_space and have_packet now stay high even while busy, as long as there really is more data/space. This should allow bursting without having additional interrupts. Also lenghten RX FIFO --- usrp2/gpmc/fifo_watcher.v | 6 ++++-- usrp2/gpmc/gpmc_async.v | 2 +- usrp2/gpmc/gpmc_to_fifo_async.v | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/usrp2/gpmc/fifo_watcher.v b/usrp2/gpmc/fifo_watcher.v index 7a3f00483..4bba142b0 100644 --- a/usrp2/gpmc/fifo_watcher.v +++ b/usrp2/gpmc/fifo_watcher.v @@ -10,11 +10,13 @@ module fifo_watcher wire read = src_rdy2 & dst_rdy2 & eof2; wire have_packet_int; reg [15:0] counter; + wire [4:0] pkt_count; fifo_short #(.WIDTH(16)) frame_lengths (.clk(clk), .reset(reset), .clear(clear), .datain(counter), .src_rdy_i(write), .dst_rdy_o(), - .dataout(length), .src_rdy_o(have_packet_int), .dst_rdy_i(read) ); + .dataout(length), .src_rdy_o(have_packet_int), .dst_rdy_i(read), + .occupied(pkt_count), .space()); always @(posedge clk) if(reset | clear) @@ -38,7 +40,7 @@ module fifo_watcher if(reset | clear) have_packet <= 0; else - have_packet <= have_packet_int & ~in_packet; + have_packet <= (have_packet_int & ~in_packet) | (pkt_count>1) ; always @(posedge clk) if(reset | clear) diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 02a00ce57..dd06478b3 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -78,7 +78,7 @@ module gpmc_async .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o), .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) ); - fifo_cascade #(.WIDTH(18), .SIZE(10)) rx_fifo + fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .datain(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space), .dataout(rx18b_data), .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied()); diff --git a/usrp2/gpmc/gpmc_to_fifo_async.v b/usrp2/gpmc/gpmc_to_fifo_async.v index 6232244d4..3d29745a2 100644 --- a/usrp2/gpmc/gpmc_to_fifo_async.v +++ b/usrp2/gpmc/gpmc_to_fifo_async.v @@ -57,7 +57,7 @@ module gpmc_to_fifo_async if(fifo_rst) fifo_ready <= 0; else - fifo_ready <= first_write & (fifo_space > 16'd1023); + fifo_ready <= /* first_write & */ (fifo_space > 16'd1023); always @(posedge fifo_clk) if(fifo_rst) -- cgit v1.2.3 From 31d4e1362cd222c688a3bfd3b528a2de51a4b03b Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Mon, 3 May 2010 22:36:24 +0000 Subject: Update path to put module in. --- host/apps/omap_debug/fetch-module.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/host/apps/omap_debug/fetch-module.sh b/host/apps/omap_debug/fetch-module.sh index e23289050..ec28989bd 100755 --- a/host/apps/omap_debug/fetch-module.sh +++ b/host/apps/omap_debug/fetch-module.sh @@ -1,6 +1,6 @@ if [ $GHQ ]; then scp $GHQ_USER@astro:/workspace/usrp1-e-dev/kernel_usrp/drivers/misc/usrp_e.ko /lib/modules/2.6.33/kernel/drivers/misc else - scp balister@192.168.1.10:src/git/kernel_usrp/drivers/misc/usrp_e.ko /lib/modules/2.6.33-rc3/kernel/drivers/misc + scp balister@192.168.1.10:src/git/kernel_usrp/drivers/misc/usrp_e.ko /lib/modules/2.6.33/kernel/drivers/misc fi sync -- cgit v1.2.3 From 5583cb575e45441c98480f7beecb48437842fc5c Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Mon, 3 May 2010 22:36:56 +0000 Subject: Spi data returned in struct now. --- host/apps/omap_debug/usrp-e-spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/host/apps/omap_debug/usrp-e-spi.c b/host/apps/omap_debug/usrp-e-spi.c index 47ee9369c..2fcc39b9b 100644 --- a/host/apps/omap_debug/usrp-e-spi.c +++ b/host/apps/omap_debug/usrp-e-spi.c @@ -39,7 +39,7 @@ int main(int argc, char *argv[]) if (*argv[1] == 'r') { spi_dat.readback = 1; ret = ioctl(fp, USRP_E_SPI, &spi_dat); - printf("Data returned = %d\n", ret); + printf("Ioctl returns: %d, Data returned = %d\n", ret, spi_dat.data); } else { spi_dat.readback = 0; ioctl(fp, USRP_E_SPI, &spi_dat); -- cgit v1.2.3 From 8f21adbed40db490bec8ead6b8d50d2b3d1a4136 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 4 May 2010 09:32:38 +0000 Subject: created codec control for ad9862, wip --- host/lib/CMakeLists.txt | 1 + host/lib/ic_reg_maps/gen_ad9862_regs.py | 16 ++--- host/lib/usrp/usrp_e/clock_ctrl.cpp | 39 +++++++++- host/lib/usrp/usrp_e/codec_ctrl.cpp | 122 ++++++++++++++++++++++++++++++++ host/lib/usrp/usrp_e/codec_ctrl.hpp | 73 +++++++++++++++++++ host/lib/usrp/usrp_e/usrp_e_iface.cpp | 7 +- host/lib/usrp/usrp_e/usrp_e_impl.cpp | 8 ++- host/lib/usrp/usrp_e/usrp_e_impl.hpp | 8 +++ 8 files changed, 259 insertions(+), 15 deletions(-) create mode 100644 host/lib/usrp/usrp_e/codec_ctrl.cpp create mode 100644 host/lib/usrp/usrp_e/codec_ctrl.hpp diff --git a/host/lib/CMakeLists.txt b/host/lib/CMakeLists.txt index 20373cd59..be57699fc 100644 --- a/host/lib/CMakeLists.txt +++ b/host/lib/CMakeLists.txt @@ -185,6 +185,7 @@ IF(HAVE_USRP_E_REQUIRED_HEADERS) MESSAGE(STATUS " Building usrp-e support.") LIST(APPEND libuhd_sources usrp/usrp_e/clock_ctrl.cpp + usrp/usrp_e/codec_ctrl.cpp usrp/usrp_e/dboard_impl.cpp usrp/usrp_e/dboard_iface.cpp usrp/usrp_e/dsp_impl.cpp diff --git a/host/lib/ic_reg_maps/gen_ad9862_regs.py b/host/lib/ic_reg_maps/gen_ad9862_regs.py index fdbea5828..2094f5e4b 100755 --- a/host/lib/ic_reg_maps/gen_ad9862_regs.py +++ b/host/lib/ic_reg_maps/gen_ad9862_regs.py @@ -30,14 +30,14 @@ soft_reset 0[5] 0 ######################################################################## ## Rx Power Down ######################################################################## -pd_vref_diff 1[7] 0 -pd_vref 1[6] 0 -pd_rx_digital 1[5] 0 -pd_rx_channel_b 1[4] 0 -pd_rx_channel_a 1[3] 0 -pd_buffer_b 1[2] 0 -pd_buffer_a 1[1] 0 -pd_all_rx 1[0] 0 +vref_diff_pd 1[7] 0 +vref_pd 1[6] 0 +rx_digital_pd 1[5] 0 +rx_channel_b_pd 1[4] 0 +rx_channel_a_pd 1[3] 0 +buffer_b_pd 1[2] 0 +buffer_a_pd 1[1] 0 +all_rx_pd 1[0] 0 ######################################################################## ## Rx A and B ######################################################################## diff --git a/host/lib/usrp/usrp_e/clock_ctrl.cpp b/host/lib/usrp/usrp_e/clock_ctrl.cpp index fa4028cc5..2fe3c9294 100644 --- a/host/lib/usrp/usrp_e/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e/clock_ctrl.cpp @@ -37,6 +37,7 @@ public: void enable_rx_dboard_clock(bool enb); void enable_tx_dboard_clock(bool enb); + void enable_codec_clock(bool enb); private: usrp_e_iface::sptr _iface; @@ -79,10 +80,22 @@ clock_ctrl_impl::clock_ctrl_impl(usrp_e_iface::sptr iface){ _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5; _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_VCO; + //setup fpga master clock _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; _ad9522_regs.divider0_low_cycles = 2; //3 low _ad9522_regs.divider0_high_cycles = 1; //2 high + //setup codec clock + _ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS; + _ad9522_regs.divider1_low_cycles = 2; //3 low + _ad9522_regs.divider1_high_cycles = 1; //2 high + + //setup test clock (same divider as codec clock) + _ad9522_regs.out4_format = ad9522_regs_t::OUT4_FORMAT_CMOS; + _ad9522_regs.out4_cmos_configuration = (true)? + ad9522_regs_t::OUT4_CMOS_CONFIGURATION_A_ON : + ad9522_regs_t::OUT4_CMOS_CONFIGURATION_OFF; + //setup a list of register ranges to write typedef std::pair range_t; static const std::vector ranges = boost::assign::list_of @@ -106,6 +119,8 @@ clock_ctrl_impl::clock_ctrl_impl(usrp_e_iface::sptr iface){ // reg, 24, true /*no*/ //); //std::cout << "result " << std::hex << result << std::endl; + this->enable_rx_dboard_clock(false); + this->enable_tx_dboard_clock(false); } clock_ctrl_impl::~clock_ctrl_impl(void){ @@ -114,16 +129,34 @@ clock_ctrl_impl::~clock_ctrl_impl(void){ } void clock_ctrl_impl::enable_rx_dboard_clock(bool enb){ - + _ad9522_regs.out9_format = ad9522_regs_t::OUT9_FORMAT_CMOS; + _ad9522_regs.out9_cmos_configuration = (enb)? + ad9522_regs_t::OUT9_CMOS_CONFIGURATION_B_ON : + ad9522_regs_t::OUT9_CMOS_CONFIGURATION_OFF; + this->send_reg(0x0F9); + + _ad9522_regs.divider3_low_cycles = 2; //3 low + _ad9522_regs.divider3_high_cycles = 1; //2 high + this->send_reg(0x199); + this->latch_regs(); } void clock_ctrl_impl::enable_tx_dboard_clock(bool enb){ - + _ad9522_regs.out6_format = ad9522_regs_t::OUT6_FORMAT_CMOS; + _ad9522_regs.out6_cmos_configuration = (enb)? + ad9522_regs_t::OUT6_CMOS_CONFIGURATION_B_ON : + ad9522_regs_t::OUT6_CMOS_CONFIGURATION_OFF; + this->send_reg(0x0F6); + + _ad9522_regs.divider2_low_cycles = 2; //3 low + _ad9522_regs.divider2_high_cycles = 1; //2 high + this->send_reg(0x196); + this->latch_regs(); } void clock_ctrl_impl::send_reg(boost::uint16_t addr){ boost::uint32_t reg = _ad9522_regs.get_write_reg(addr); - std::cout << "clock control write reg: " << std::hex << reg << std::endl; + //std::cout << "clock control write reg: " << std::hex << reg << std::endl; _iface->transact_spi( UE_SPI_SS_AD9522, spi_config_t::EDGE_RISE, diff --git a/host/lib/usrp/usrp_e/codec_ctrl.cpp b/host/lib/usrp/usrp_e/codec_ctrl.cpp new file mode 100644 index 000000000..daa6ed3e3 --- /dev/null +++ b/host/lib/usrp/usrp_e/codec_ctrl.cpp @@ -0,0 +1,122 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "codec_ctrl.hpp" +#include "ad9862_regs.hpp" +#include +#include "usrp_e_regs.hpp" //spi slave constants +#include +//#include +//#include +#include + + //test out codec ls dac/adc + //ad9862_regs_t ad9862_regs; + //ad9862_regs.select_a = ad9862_regs_t::SELECT_A_AUX_ADC1; + //ad9862_regs.aux_dac_a = 0xff/2; + //_iface->transact_spi( + // UE_SPI_SS_AD9862, + // spi_config_t::EDGE_RISE, + // ad9862_regs.get_write_reg(34), 16, false /*no rb*/ + //); + //_iface->transact_spi( + // UE_SPI_SS_AD9862, + // spi_config_t::EDGE_RISE, + // ad9862_regs.get_write_reg(36), 16, false /*no rb*/ + //); + //boost::uint32_t val = _iface->transact_spi( + // UE_SPI_SS_AD9862, + // spi_config_t::EDGE_RISE, + // ad9862_regs.get_read_reg(29), 16, true + //); + //std::cout << "value: " << std::hex << val << std::endl; + +using namespace uhd; + +/*********************************************************************** + * Codec Control Implementation + **********************************************************************/ +class codec_ctrl_impl : public codec_ctrl{ +public: + //structors + codec_ctrl_impl(usrp_e_iface::sptr iface); + ~codec_ctrl_impl(void); + + //aux adc and dac control + float read_aux_adc(aux_adc_t which); + void read_aux_adc(aux_dac_t which, float volts); + +private: + usrp_e_iface::sptr _iface; + ad9862_regs_t _ad9862_regs; + void send_reg(boost::uint8_t addr); +}; + +/*********************************************************************** + * Codec Control Methods + **********************************************************************/ +codec_ctrl_impl::codec_ctrl_impl(usrp_e_iface::sptr iface){ + _iface = iface; + + //soft reset + _ad9862_regs.soft_reset = 1; + this->send_reg(0); + + //initialize the codec register settings + _ad9862_regs.sdio_bidir = ad9862_regs_t::SDIO_BIDIR_SDIO_SDO; + _ad9862_regs.lsb_first = ad9862_regs_t::LSB_FIRST_MSB; + _ad9862_regs.soft_reset = 0; + + //write the register settings to the codec + for (uint8_t addr = 0; addr <= 50; addr++){ + this->send_reg(addr); + } +} + +codec_ctrl_impl::~codec_ctrl_impl(void){ + _ad9862_regs.all_rx_pd = 1; + this->send_reg(1); + _ad9862_regs.tx_digital_pd = 1; + _ad9862_regs.tx_analog_pd = ad9862_regs_t::TX_ANALOG_PD_BOTH; + this->send_reg(8); +} + +float codec_ctrl_impl::read_aux_adc(aux_adc_t which){ + return 0; + +} + +void codec_ctrl_impl::read_aux_adc(aux_dac_t which, float volts){ + +} + +void codec_ctrl_impl::send_reg(boost::uint8_t addr){ + boost::uint32_t reg = _ad9862_regs.get_write_reg(addr); + //std::cout << "codec control write reg: " << std::hex << reg << std::endl; + _iface->transact_spi( + UE_SPI_SS_AD9862, + spi_config_t::EDGE_RISE, + reg, 24, false /*no rb*/ + ); +} + +/*********************************************************************** + * Codec Control Make + **********************************************************************/ +codec_ctrl::sptr codec_ctrl::make(usrp_e_iface::sptr iface){ + return sptr(new codec_ctrl_impl(iface)); +} diff --git a/host/lib/usrp/usrp_e/codec_ctrl.hpp b/host/lib/usrp/usrp_e/codec_ctrl.hpp new file mode 100644 index 000000000..0fe70c4a2 --- /dev/null +++ b/host/lib/usrp/usrp_e/codec_ctrl.hpp @@ -0,0 +1,73 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_USRP_E_CODEC_CTRL_HPP +#define INCLUDED_USRP_E_CODEC_CTRL_HPP + +#include "usrp_e_iface.hpp" +#include +#include + +/*! + * The usrp-e codec control: + * - Init/power down codec. + * - Read aux adc, write aux dac. + */ +class codec_ctrl : boost::noncopyable{ +public: + typedef boost::shared_ptr sptr; + + /*! + * Make a new clock control object. + * \param iface the usrp_e iface object + * \return the clock control object + */ + static sptr make(usrp_e_iface::sptr iface); + + //! aux adc identifier constants + enum aux_adc_t{ + AUX_ADC_A2 = 0xA2, + AUX_ADC_A1 = 0xA1, + AUX_ADC_B2 = 0xB2, + AUX_ADC_B1 = 0xB1 + }; + + /*! + * Read the aux adc. + * \param which which of the 4 adcs + * \return a value in volts + */ + virtual float read_aux_adc(aux_adc_t which) = 0; + + //! aux dac identifier constants + enum aux_dac_t{ + AUX_DAC_A = 0xA, + AUX_DAC_B = 0xB, + AUX_DAC_C = 0xC, + AUX_DAC_D = 0xD + }; + + /*! + * Write the aux dac. + * \param which which of the 4 dacs + * \param volts the level in in volts + */ + virtual void read_aux_adc(aux_dac_t which, float volts) = 0; + +}; + +#endif /* INCLUDED_USRP_E_CODEC_CTRL_HPP */ diff --git a/host/lib/usrp/usrp_e/usrp_e_iface.cpp b/host/lib/usrp/usrp_e/usrp_e_iface.cpp index 41737a716..1dbe383fa 100644 --- a/host/lib/usrp/usrp_e/usrp_e_iface.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_iface.cpp @@ -20,6 +20,7 @@ #include //ioctl #include //ioctl structures and constants #include +#include //mutex #include using namespace uhd; @@ -42,6 +43,8 @@ public: * IOCTL: provides the communication base for all other calls ******************************************************************/ void ioctl(int request, void *mem){ + boost::mutex::scoped_lock lock(_ctrl_mutex); + if (::ioctl(_node_fd, request, mem) < 0){ throw std::runtime_error(str( boost::format("ioctl failed with request %d") % request @@ -167,7 +170,9 @@ public: return data.data; } -private: int _node_fd; +private: + int _node_fd; + boost::mutex _ctrl_mutex; }; /*********************************************************************** diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.cpp b/host/lib/usrp/usrp_e/usrp_e_impl.cpp index 52bbcdd32..b6fed6a74 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.cpp @@ -23,7 +23,6 @@ #include #include #include //open -#include "clock_ctrl.hpp" using namespace uhd; using namespace uhd::usrp; @@ -84,9 +83,12 @@ usrp_e_impl::usrp_e_impl(const std::string &node){ )); } - _iface = usrp_e_iface::make(_node_fd); + sleep(1); //FIXME sleep here until the kernel driver stops hanging - clock_ctrl::sptr my_clk_ctrl = clock_ctrl::make(_iface); + //setup various interfaces into hardware + _iface = usrp_e_iface::make(_node_fd); + _clock_ctrl = clock_ctrl::make(_iface); + _codec_ctrl = codec_ctrl::make(_iface); //initialize the mboard mboard_init(); diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index 23e36ed05..6746e012a 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -16,6 +16,8 @@ // #include "usrp_e_iface.hpp" +#include "clock_ctrl.hpp" +#include "codec_ctrl.hpp" #include #include #include @@ -91,6 +93,12 @@ private: uhd::clock_config_t _clock_config; + //ad9522 clock control + clock_ctrl::sptr _clock_ctrl; + + //ad9862 codec control + codec_ctrl::sptr _codec_ctrl; + //device functions and settings void get(const wax::obj &, wax::obj &); void set(const wax::obj &, const wax::obj &); -- cgit v1.2.3 From 6929d0cba40a2bf4f4b3b81819bb915bdbb16488 Mon Sep 17 00:00:00 2001 From: root Date: Wed, 5 May 2010 21:12:43 +0000 Subject: Remove workaround for driver hang. --- host/apps/omap_debug/usrp-e-i2c.c | 2 -- host/apps/omap_debug/usrp-e-spi.c | 2 -- host/apps/omap_debug/usrp_e.h | 4 ++-- 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-i2c.c b/host/apps/omap_debug/usrp-e-i2c.c index 57a3f4739..615dc557b 100644 --- a/host/apps/omap_debug/usrp-e-i2c.c +++ b/host/apps/omap_debug/usrp-e-i2c.c @@ -38,8 +38,6 @@ int main(int argc, char *argv[]) fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); - sleep(1); - if (direction) { count = argc - 3; } else { diff --git a/host/apps/omap_debug/usrp-e-spi.c b/host/apps/omap_debug/usrp-e-spi.c index 2fcc39b9b..d2c38e524 100644 --- a/host/apps/omap_debug/usrp-e-spi.c +++ b/host/apps/omap_debug/usrp-e-spi.c @@ -29,8 +29,6 @@ int main(int argc, char *argv[]) fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); - sleep(1); // HACK HACK - spi_dat.slave = slave; spi_dat.data = data; spi_dat.length = length; diff --git a/host/apps/omap_debug/usrp_e.h b/host/apps/omap_debug/usrp_e.h index d4132021f..0b582f59b 100644 --- a/host/apps/omap_debug/usrp_e.h +++ b/host/apps/omap_debug/usrp_e.h @@ -66,8 +66,8 @@ struct usrp_e_i2c { #define USRP_E_READ_CTL16 _IOWR(USRP_E_IOC_MAGIC, 0x21, struct usrp_e_ctl16) #define USRP_E_WRITE_CTL32 _IOW(USRP_E_IOC_MAGIC, 0x22, struct usrp_e_ctl32) #define USRP_E_READ_CTL32 _IOWR(USRP_E_IOC_MAGIC, 0x23, struct usrp_e_ctl32) -#define USRP_E_SPI _IOW(USRP_E_IOC_MAGIC, 0x24, struct usrp_e_spi) -#define USRP_E_I2C_READ _IOR(USRP_E_IOC_MAGIC, 0x25, struct usrp_e_i2c) +#define USRP_E_SPI _IOWR(USRP_E_IOC_MAGIC, 0x24, struct usrp_e_spi) +#define USRP_E_I2C_READ _IOWR(USRP_E_IOC_MAGIC, 0x25, struct usrp_e_i2c) #define USRP_E_I2C_WRITE _IOW(USRP_E_IOC_MAGIC, 0x26, struct usrp_e_i2c) // Data transfer frame definition -- cgit v1.2.3 From 77b9aaf5bdb9c50a2456f1aa5e3498ec228ab679 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 4 May 2010 09:46:02 +0000 Subject: fix files before pull --- host/include/uhd/utils/assert.hpp | 32 ++++++++++---------------------- host/include/uhd/utils/props.hpp | 17 +++-------------- host/include/uhd/utils/safe_main.hpp | 5 +---- host/test/error_test.cpp | 17 ++++++++++++----- 4 files changed, 26 insertions(+), 45 deletions(-) diff --git a/host/include/uhd/utils/assert.hpp b/host/include/uhd/utils/assert.hpp index 577050aff..2f0ed4ff1 100644 --- a/host/include/uhd/utils/assert.hpp +++ b/host/include/uhd/utils/assert.hpp @@ -19,37 +19,24 @@ #define INCLUDED_UHD_UTILS_ASSERT_HPP #include +#include #include #include #include #include -#include -#include #include #include -#ifndef BOOST_THROW_EXCEPTION - #include - #include - #define BOOST_THROW_EXCEPTION(x)\ - ::boost::throw_exception( ::boost::enable_error_info(x) <<\ - ::boost::throw_function(BOOST_CURRENT_FUNCTION) <<\ - ::boost::throw_file(__FILE__) <<\ - ::boost::throw_line((int)__LINE__) ) - -#endif - namespace uhd{ //! The exception to throw when assertions fail - struct UHD_API assert_error : virtual std::exception, virtual boost::exception{}; - - //! The assertion info, the code that failed - typedef boost::error_info assert_info; + struct UHD_API assert_error : std::runtime_error{ + assert_error(const std::string &what); + }; //! Throw an assert error with throw-site information #define UHD_ASSERT_THROW(_x) if (not (_x)) \ - BOOST_THROW_EXCEPTION(uhd::assert_error() << uhd::assert_info(#_x)) + throw uhd::assert_error(UHD_THROW_SITE_INFO("assertion failed: " + std::string(#_x))) /*! * Check that an element is found in a container. @@ -74,13 +61,14 @@ namespace uhd{ if (i++ > 0) possible_values += ", "; possible_values += boost::lexical_cast(v); } - boost::throw_exception(uhd::assert_error() << assert_info(str(boost::format( - "Error: %s is not a valid %s. " - "Possible values are: [%s]." + throw uhd::assert_error(str(boost::format( + "assertion failed:\n" + " %s is not a valid %s.\n" + " possible values are: [%s].\n" ) % boost::lexical_cast(value) % what % possible_values - ))); + )); } }//namespace uhd diff --git a/host/include/uhd/utils/props.hpp b/host/include/uhd/utils/props.hpp index 6c40c32e0..f376d2612 100644 --- a/host/include/uhd/utils/props.hpp +++ b/host/include/uhd/utils/props.hpp @@ -20,17 +20,12 @@ #include #include +#include #include -#include -#include #include #include #include -#ifndef BOOST_THROW_EXCEPTION -#define BOOST_THROW_EXCEPTION(x) throw std::runtime_error("") -#endif - namespace uhd{ //! The type for a vector of property names @@ -63,25 +58,19 @@ namespace uhd{ const std::string &name = "" ); - //! The exception to throw for property errors - struct UHD_API prop_error : virtual std::exception, virtual boost::exception{}; - - //! The property error info (verbose or message) - typedef boost::error_info prop_info; - /*! * Throw when getting a not-implemented or write-only property. * Throw-site information will be included with this error. */ #define UHD_THROW_PROP_GET_ERROR() \ - BOOST_THROW_EXCEPTION(uhd::prop_error() << uhd::prop_info("cannot get this property")) + throw std::runtime_error(UHD_THROW_SITE_INFO("cannot get this property")) /*! * Throw when setting a not-implemented or read-only property. * Throw-site information will be included with this error. */ #define UHD_THROW_PROP_SET_ERROR() \ - BOOST_THROW_EXCEPTION(uhd::prop_error() << uhd::prop_info("cannot set this property")) + throw std::runtime_error(UHD_THROW_SITE_INFO("cannot set this property")) } //namespace uhd diff --git a/host/include/uhd/utils/safe_main.hpp b/host/include/uhd/utils/safe_main.hpp index 39d2282cd..b682aa540 100644 --- a/host/include/uhd/utils/safe_main.hpp +++ b/host/include/uhd/utils/safe_main.hpp @@ -19,7 +19,6 @@ #define INCLUDED_UHD_UTILS_SAFE_MAIN_HPP #include -//#include #include #include @@ -34,9 +33,7 @@ int main(int argc, char *argv[]){ \ try { \ return _main(argc, argv); \ - } /*catch(const boost::exception &e){ \ - std::cerr << "Error: " << boost::diagnostic_information(e) << std::endl; \ - }*/ catch(const std::exception &e) { \ + } catch(const std::exception &e) { \ std::cerr << "Error: " << e.what() << std::endl; \ } catch(...) { \ std::cerr << "Error: unknown exception" << std::endl; \ diff --git a/host/test/error_test.cpp b/host/test/error_test.cpp index 3f2479f99..c76a15ab7 100644 --- a/host/test/error_test.cpp +++ b/host/test/error_test.cpp @@ -17,7 +17,6 @@ #include #include -//#include #include #include @@ -30,12 +29,20 @@ BOOST_AUTO_TEST_CASE(test_assert_has){ //verify the std::has utility BOOST_CHECK(std::has(vec, 2)); BOOST_CHECK(not std::has(vec, 1)); -/* + std::cout << "The output of the assert_has error:" << std::endl; try{ uhd::assert_has(vec, 1, "prime"); - }catch(const boost::exception &e){ - std::cout << boost::diagnostic_information(e) << std::endl; + }catch(const std::exception &e){ + std::cout << e.what() << std::endl; + } +} + +BOOST_AUTO_TEST_CASE(test_assert_throw){ + std::cout << "The output of the assert throw error:" << std::endl; + try{ + UHD_ASSERT_THROW(2 + 2 == 5); + }catch(const std::exception &e){ + std::cout << e.what() << std::endl; } -*/ } -- cgit v1.2.3 From c4698bb0a42b60dea924a83d18b27131a15958a2 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 4 May 2010 09:44:28 -0700 Subject: changed comment --- usrp2/top/u1e/u1e.ucf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 9c42b00ac..055a1ef17 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -254,7 +254,7 @@ NET "io_rx<15>" LOC = "Y4" ; #NET "fpga_cfg_cclk" LOC = "V17" ; #NET "fpga_cfg_init_b" LOC = "W15" ; -## Unnamed, need to figure out what they do +## Unused #NET "unnamed_net37" LOC = "B1" ; # TMS #NET "unnamed_net36" LOC = "B22" ; # TDO #NET "unnamed_net35" LOC = "D2" ; # TDI -- cgit v1.2.3 From 031becd1f05f0fbcab6a4f2be353292cd667a88f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 4 May 2010 12:30:56 -0700 Subject: add timing constraints. Just have main clock signal at 64 MHz for now. --- usrp2/top/u1e/Makefile | 1 + usrp2/top/u1e/timing.ucf | 13 +++++++++++++ 2 files changed, 14 insertions(+) create mode 100644 usrp2/top/u1e/timing.ucf diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 5f712b046..2aebb33f9 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -186,6 +186,7 @@ gpmc/fifo_watcher.v \ gpmc/gpmc_wb.v \ top/u1e/u1e_core.v \ top/u1e/u1e.ucf \ +top/u1e/timing.ucf \ top/u1e/u1e.v ################################################## diff --git a/usrp2/top/u1e/timing.ucf b/usrp2/top/u1e/timing.ucf new file mode 100644 index 000000000..8df28c9d3 --- /dev/null +++ b/usrp2/top/u1e/timing.ucf @@ -0,0 +1,13 @@ + +NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; + + + + +#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; +#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; +#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; + +#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; +#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; -- cgit v1.2.3 From 2ddaba2d8bdcdda07b949f007d2555cf57c7c8d7 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 4 May 2010 15:06:03 -0700 Subject: added DAC output pins, and a sine wave generator to test them --- usrp2/top/u1e/u1e.ucf | 32 ++++++++++++++++---------------- usrp2/top/u1e/u1e.v | 4 ++++ usrp2/top/u1e/u1e_core.v | 45 +++++++++++++++++++++++++++++++++++++++++++-- 3 files changed, 63 insertions(+), 18 deletions(-) diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 055a1ef17..a73ebceb8 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -191,22 +191,22 @@ NET "dip_sw<0>" LOC = "J7" ; #NET "DA<1>" LOC = "P22" ; #NET "DA<0>" LOC = "N17" ; -#NET "TX<13>" LOC = "P19" ; -#NET "TX<12>" LOC = "R18" ; -#NET "TX<11>" LOC = "U20" ; -#NET "TX<10>" LOC = "T20" ; -#NET "TX<9>" LOC = "R19" ; -#NET "TX<8>" LOC = "R20" ; -#NET "TX<7>" LOC = "W22" ; -#NET "TX<6>" LOC = "Y22" ; -#NET "TX<5>" LOC = "T18" ; -#NET "TX<4>" LOC = "T17" ; -#NET "TX<3>" LOC = "W19" ; -#NET "TX<2>" LOC = "V20" ; -#NET "TX<1>" LOC = "Y21" ; -#NET "TX<0>" LOC = "AA22" ; -#NET "TXSYNC" LOC = "U18" ; -#NET "TXBLANK" LOC = "U19" ; +NET "TX<13>" LOC = "P19" ; +NET "TX<12>" LOC = "R18" ; +NET "TX<11>" LOC = "U20" ; +NET "TX<10>" LOC = "T20" ; +NET "TX<9>" LOC = "R19" ; +NET "TX<8>" LOC = "R20" ; +NET "TX<7>" LOC = "W22" ; +NET "TX<6>" LOC = "Y22" ; +NET "TX<5>" LOC = "T18" ; +NET "TX<4>" LOC = "T17" ; +NET "TX<3>" LOC = "W19" ; +NET "TX<2>" LOC = "V20" ; +NET "TX<1>" LOC = "Y21" ; +NET "TX<0>" LOC = "AA22" ; +NET "TXSYNC" LOC = "U18" ; +NET "TXBLANK" LOC = "U19" ; NET "PPS_IN" LOC = "M17" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 2ed6b71c8..35818e8c8 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -25,6 +25,9 @@ module u1e input overo_gpio128, input overo_gpio163, input overo_gpio170, input overo_gpio176, // Misc GPIO inout [15:0] io_tx, inout [15:0] io_rx, + + output [13:0] TX, output TXSYNC, output TXBLANK, + input PPS_IN ); @@ -56,6 +59,7 @@ module u1e .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), .io_tx(io_tx), .io_rx(io_rx), + .tx(TX), .txsync(TXSYNC), .txblank(TXBLANK), .misc_gpio( {{overo_gpio128,overo_gpio163,overo_gpio170,overo_gpio176}, {overo_gpio0,overo_gpio14,overo_gpio21,overo_gpio22}, {overo_gpio23,overo_gpio64,overo_gpio65,overo_gpio127}}), diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index d5a3ddf68..74ffc4657 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -13,7 +13,10 @@ module u1e_core input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, - inout [15:0] io_tx, inout [15:0] io_rx, input [11:0] misc_gpio, input pps_in + inout [15:0] io_tx, inout [15:0] io_rx, + output reg [13:0] tx, output reg txsync, output txblank, + + input [11:0] misc_gpio, input pps_in ); wire wb_clk = clk_fpga; @@ -213,7 +216,7 @@ module u1e_core assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; - assign { rx_overrun, tx_underrun } = reg_test; + assign { rx_overrun, tx_underrun } = 0; // reg_test; assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : @@ -309,6 +312,44 @@ module u1e_core time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); + + + // ///////////////////////////////////////////////////////////////////////// + // TX + + assign txblank = 0; + + wire [23:0] freq = {reg_test,8'd0}; + + reg [23:0] tx_q_hold; + wire [23:0] tx_i, tx_q; + + reg tx_stb; + always @(posedge wb_clk) + tx_stb <= ~tx_stb; + + always @(posedge wb_clk) + if(tx_stb) + tx <= tx_i[23:10]; + else + tx <= tx_q_hold[23:10]; + + always @(posedge wb_clk) + if(tx_stb) + tx_q_hold <= tx_q; + + always @(posedge wb_clk) + txsync <= ~tx_stb; // TX Sync low indicates first data item + // We invert here if we don't use inv_txsync in the 9862 + + reg [23:0] phase; + always @(posedge wb_clk) + if(tx_stb) + phase <= phase + freq; + + cordic_z24 #(.bitwidth(24)) tx_cordic + (.clock(wb_clk), .reset(wb_rst), .enable(1), + .xi(24'd15000), .yi(24'd0), .zi(phase), .xo(tx_i), .yo(tx_q), .zo()); // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry -- cgit v1.2.3 From 06bcfc6b872d8efcb94b312b963f18678a862b93 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 6 May 2010 22:00:21 +0000 Subject: moved usrp_e specific build stuff into its own cmake file --- host/lib/CMakeLists.txt | 37 +-------------------------- host/lib/usrp/usrp_e/CMakeLists.txt | 51 +++++++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+), 36 deletions(-) create mode 100644 host/lib/usrp/usrp_e/CMakeLists.txt diff --git a/host/lib/CMakeLists.txt b/host/lib/CMakeLists.txt index f64f1dbac..6cf896db8 100644 --- a/host/lib/CMakeLists.txt +++ b/host/lib/CMakeLists.txt @@ -72,42 +72,7 @@ INCLUDE(${CMAKE_CURRENT_SOURCE_DIR}/transport/CMakeLists.txt) INCLUDE(${CMAKE_CURRENT_SOURCE_DIR}/usrp/CMakeLists.txt) INCLUDE(${CMAKE_CURRENT_SOURCE_DIR}/usrp/dboard/CMakeLists.txt) INCLUDE(${CMAKE_CURRENT_SOURCE_DIR}/usrp/usrp2/CMakeLists.txt) - -######################################################################## -# Conditionally add the usrp1e sources -######################################################################## -MESSAGE(STATUS "Configuring usrp-e support...") - -INCLUDE(CheckIncludeFiles) -SET(usrp_e_required_headers - linux/ioctl.h - linux/spi/spidev.h - linux/usrp_e.h -) -CHECK_INCLUDE_FILES( - "${usrp_e_required_headers}" - HAVE_USRP_E_REQUIRED_HEADERS -) - -IF(HAVE_USRP_E_REQUIRED_HEADERS) - MESSAGE(STATUS " Building usrp-e support.") - LIST(APPEND libuhd_sources - usrp/usrp_e/clock_ctrl.cpp - usrp/usrp_e/codec_ctrl.cpp - usrp/usrp_e/dboard_impl.cpp - usrp/usrp_e/dboard_iface.cpp - usrp/usrp_e/dsp_impl.cpp - usrp/usrp_e/fpga-downloader.cc - usrp/usrp_e/mboard_impl.cpp - usrp/usrp_e/usrp_e_impl.cpp - usrp/usrp_e/usrp_e_iface.cpp - ) -ELSE(HAVE_USRP_E_REQUIRED_HEADERS) - MESSAGE(STATUS " Skipping usrp-e support.") - LIST(APPEND libuhd_sources - usrp/usrp_e/usrp_e_none.cpp - ) -ENDIF(HAVE_USRP_E_REQUIRED_HEADERS) +INCLUDE(${CMAKE_CURRENT_SOURCE_DIR}/usrp/usrp_e/CMakeLists.txt) ######################################################################## # Setup defines for module loading diff --git a/host/lib/usrp/usrp_e/CMakeLists.txt b/host/lib/usrp/usrp_e/CMakeLists.txt new file mode 100644 index 000000000..2eff3147d --- /dev/null +++ b/host/lib/usrp/usrp_e/CMakeLists.txt @@ -0,0 +1,51 @@ +# +# Copyright 2010 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + +#This file will be included by cmake, use absolute paths! + +MESSAGE(STATUS "Configuring usrp-e support...") + +INCLUDE(CheckIncludeFiles) +SET(usrp_e_required_headers + linux/ioctl.h + linux/spi/spidev.h + linux/usrp_e.h +) +CHECK_INCLUDE_FILES( + "${usrp_e_required_headers}" + HAVE_USRP_E_REQUIRED_HEADERS +) + +IF(HAVE_USRP_E_REQUIRED_HEADERS) + MESSAGE(STATUS " Building usrp-e support.") + LIBUHD_APPEND_SOURCES( + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/clock_ctrl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/codec_ctrl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/dboard_impl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/dboard_iface.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/dsp_impl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/fpga-downloader.cc + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/mboard_impl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_impl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_iface.cpp + ) +ELSE(HAVE_USRP_E_REQUIRED_HEADERS) + MESSAGE(STATUS " Skipping usrp-e support.") + LIBUHD_APPEND_SOURCES( + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_none.cpp + ) +ENDIF(HAVE_USRP_E_REQUIRED_HEADERS) -- cgit v1.2.3 From 272b08ce9a66b3ba1b9dc91922afff410145231f Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 7 May 2010 01:02:20 +0000 Subject: work on codec control, writing aux dacs, read aux adc --- host/lib/ic_reg_maps/gen_ad9862_regs.py | 2 +- host/lib/usrp/usrp_e/CMakeLists.txt | 28 +++--- host/lib/usrp/usrp_e/clock_ctrl.cpp | 1 - host/lib/usrp/usrp_e/codec_ctrl.cpp | 145 +++++++++++++++++++++++++------- host/lib/usrp/usrp_e/codec_ctrl.hpp | 10 ++- 5 files changed, 141 insertions(+), 45 deletions(-) diff --git a/host/lib/ic_reg_maps/gen_ad9862_regs.py b/host/lib/ic_reg_maps/gen_ad9862_regs.py index 2094f5e4b..4444c6240 100755 --- a/host/lib/ic_reg_maps/gen_ad9862_regs.py +++ b/host/lib/ic_reg_maps/gen_ad9862_regs.py @@ -233,7 +233,7 @@ boost::uint16_t get_write_reg(boost::uint8_t addr){ } boost::uint16_t get_read_reg(boost::uint8_t addr){ - return (boost::uint16_t(addr) << 8) | (1 << 7); + return (boost::uint16_t(addr) << 8) | (1 << 15); } """ diff --git a/host/lib/usrp/usrp_e/CMakeLists.txt b/host/lib/usrp/usrp_e/CMakeLists.txt index 2eff3147d..c25b2cba4 100644 --- a/host/lib/usrp/usrp_e/CMakeLists.txt +++ b/host/lib/usrp/usrp_e/CMakeLists.txt @@ -17,18 +17,26 @@ #This file will be included by cmake, use absolute paths! +######################################################################## +# Helpful macro to check for required headers +######################################################################## +INCLUDE(CheckIncludeFileCXX) +SET(HAVE_USRP_E_REQUIRED_HEADERS TRUE) +MACRO(USRP_E_REQUIRE_HEADER header variable) + CHECK_INCLUDE_FILE_CXX(${header} ${variable}) + IF(NOT ${variable}) + SET(HAVE_USRP_E_REQUIRED_HEADERS FALSE) + ENDIF(NOT ${variable}) +ENDMACRO(USRP_E_REQUIRE_HEADER) + +######################################################################## +# Conditionally configure the USRP-E support +######################################################################## MESSAGE(STATUS "Configuring usrp-e support...") -INCLUDE(CheckIncludeFiles) -SET(usrp_e_required_headers - linux/ioctl.h - linux/spi/spidev.h - linux/usrp_e.h -) -CHECK_INCLUDE_FILES( - "${usrp_e_required_headers}" - HAVE_USRP_E_REQUIRED_HEADERS -) +USRP_E_REQUIRE_HEADER(linux/ioctl.h HAVE_LINUX_IOCTL_H) +USRP_E_REQUIRE_HEADER(linux/spi/spidev.h HAVE_LINUX_SPI_SPIDEV_H) +USRP_E_REQUIRE_HEADER(linux/usrp_e.h HAVE_LINUX_USRP_E_H) IF(HAVE_USRP_E_REQUIRED_HEADERS) MESSAGE(STATUS " Building usrp-e support.") diff --git a/host/lib/usrp/usrp_e/clock_ctrl.cpp b/host/lib/usrp/usrp_e/clock_ctrl.cpp index 2fe3c9294..9c2ddf670 100644 --- a/host/lib/usrp/usrp_e/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e/clock_ctrl.cpp @@ -37,7 +37,6 @@ public: void enable_rx_dboard_clock(bool enb); void enable_tx_dboard_clock(bool enb); - void enable_codec_clock(bool enb); private: usrp_e_iface::sptr _iface; diff --git a/host/lib/usrp/usrp_e/codec_ctrl.cpp b/host/lib/usrp/usrp_e/codec_ctrl.cpp index daa6ed3e3..a430f2c6f 100644 --- a/host/lib/usrp/usrp_e/codec_ctrl.cpp +++ b/host/lib/usrp/usrp_e/codec_ctrl.cpp @@ -17,34 +17,16 @@ #include "codec_ctrl.hpp" #include "ad9862_regs.hpp" +#include +#include +#include #include +#include +#include #include "usrp_e_regs.hpp" //spi slave constants #include -//#include -//#include #include - //test out codec ls dac/adc - //ad9862_regs_t ad9862_regs; - //ad9862_regs.select_a = ad9862_regs_t::SELECT_A_AUX_ADC1; - //ad9862_regs.aux_dac_a = 0xff/2; - //_iface->transact_spi( - // UE_SPI_SS_AD9862, - // spi_config_t::EDGE_RISE, - // ad9862_regs.get_write_reg(34), 16, false /*no rb*/ - //); - //_iface->transact_spi( - // UE_SPI_SS_AD9862, - // spi_config_t::EDGE_RISE, - // ad9862_regs.get_write_reg(36), 16, false /*no rb*/ - //); - //boost::uint32_t val = _iface->transact_spi( - // UE_SPI_SS_AD9862, - // spi_config_t::EDGE_RISE, - // ad9862_regs.get_read_reg(29), 16, true - //); - //std::cout << "value: " << std::hex << val << std::endl; - using namespace uhd; /*********************************************************************** @@ -58,16 +40,18 @@ public: //aux adc and dac control float read_aux_adc(aux_adc_t which); - void read_aux_adc(aux_dac_t which, float volts); + void write_aux_dac(aux_dac_t which, float volts); private: usrp_e_iface::sptr _iface; ad9862_regs_t _ad9862_regs; + aux_adc_t _last_aux_adc_a, _last_aux_adc_b; void send_reg(boost::uint8_t addr); + void recv_reg(boost::uint8_t addr); }; /*********************************************************************** - * Codec Control Methods + * Codec Control Structors **********************************************************************/ codec_ctrl_impl::codec_ctrl_impl(usrp_e_iface::sptr iface){ _iface = iface; @@ -88,6 +72,13 @@ codec_ctrl_impl::codec_ctrl_impl(usrp_e_iface::sptr iface){ } codec_ctrl_impl::~codec_ctrl_impl(void){ + //set aux dacs to zero + this->write_aux_dac(AUX_DAC_A, 0); + this->write_aux_dac(AUX_DAC_B, 0); + this->write_aux_dac(AUX_DAC_C, 0); + this->write_aux_dac(AUX_DAC_D, 0); + + //power down _ad9862_regs.all_rx_pd = 1; this->send_reg(1); _ad9862_regs.tx_digital_pd = 1; @@ -95,23 +86,119 @@ codec_ctrl_impl::~codec_ctrl_impl(void){ this->send_reg(8); } +/*********************************************************************** + * Codec Control AUX ADC Methods + **********************************************************************/ +static float aux_adc_to_volts(boost::uint8_t high, boost::uint8_t low){ + return float((boost::uint16_t(high) << 2) | low)*3.3/0x3ff; +} + float codec_ctrl_impl::read_aux_adc(aux_adc_t which){ - return 0; + //check to see if the switch needs to be set + bool write_switch = false; + switch(which){ + + case AUX_ADC_A1: + case AUX_ADC_A2: + if (which != _last_aux_adc_a){ + _ad9862_regs.select_a = (which == AUX_ADC_A1)? + ad9862_regs_t::SELECT_A_AUX_ADC1: ad9862_regs_t::SELECT_A_AUX_ADC2; + _last_aux_adc_a = which; + write_switch = true; + } + break; + + case AUX_ADC_B1: + case AUX_ADC_B2: + if (which != _last_aux_adc_b){ + _ad9862_regs.select_b = (which == AUX_ADC_B1)? + ad9862_regs_t::SELECT_B_AUX_ADC1: ad9862_regs_t::SELECT_B_AUX_ADC2; + _last_aux_adc_b = which; + write_switch = true; + } + break; + + } + //write the switch if it changed + if(write_switch) this->send_reg(34); + + //map aux adcs to register values to read + static const uhd::dict aux_dac_to_addr = boost::assign::map_list_of + (AUX_ADC_A2, 26) (AUX_ADC_A1, 28) + (AUX_ADC_B2, 30) (AUX_ADC_B1, 32) + ; + + //read the value + this->recv_reg(aux_dac_to_addr[which]+0); + this->recv_reg(aux_dac_to_addr[which]+1); + + //return the value scaled to volts + switch(which){ + case AUX_ADC_A1: return aux_adc_to_volts(_ad9862_regs.aux_adc_a1_9_2, _ad9862_regs.aux_adc_a1_1_0); + case AUX_ADC_A2: return aux_adc_to_volts(_ad9862_regs.aux_adc_a2_9_2, _ad9862_regs.aux_adc_a2_1_0); + case AUX_ADC_B1: return aux_adc_to_volts(_ad9862_regs.aux_adc_b1_9_2, _ad9862_regs.aux_adc_b1_1_0); + case AUX_ADC_B2: return aux_adc_to_volts(_ad9862_regs.aux_adc_b2_9_2, _ad9862_regs.aux_adc_b2_1_0); + } + UHD_ASSERT_THROW(false); } -void codec_ctrl_impl::read_aux_adc(aux_dac_t which, float volts){ - +/*********************************************************************** + * Codec Control AUX DAC Methods + **********************************************************************/ +void codec_ctrl_impl::write_aux_dac(aux_dac_t which, float volts){ + //special case for aux dac d (aka sigma delta word) + if (which == AUX_DAC_D){ + boost::uint16_t dac_word = std::clip(boost::math::iround(volts*0xfff/3.3), 0, 0xfff); + _ad9862_regs.sig_delt_11_4 = boost::uint8_t(dac_word >> 4); + _ad9862_regs.sig_delt_3_0 = boost::uint8_t(dac_word & 0xf); + this->send_reg(42); + this->send_reg(43); + return; + } + + //calculate the dac word for aux dac a, b, c + boost::uint8_t dac_word = std::clip(boost::math::iround(volts*0xff/3.3), 0, 0xff); + + //setup a lookup table for the aux dac params (reg ref, reg addr) + typedef boost::tuple dac_params_t; + uhd::dict aux_dac_to_params = boost::assign::map_list_of + (AUX_DAC_A, dac_params_t(&_ad9862_regs.aux_dac_a, 36)) + (AUX_DAC_B, dac_params_t(&_ad9862_regs.aux_dac_b, 37)) + (AUX_DAC_C, dac_params_t(&_ad9862_regs.aux_dac_c, 38)) + ; + + //set the aux dac register + UHD_ASSERT_THROW(aux_dac_to_params.has_key(which)); + boost::uint8_t *reg_ref, reg_addr; + boost::tie(reg_ref, reg_addr) = aux_dac_to_params[which]; + *reg_ref = dac_word; + this->send_reg(reg_addr); } +/*********************************************************************** + * Codec Control SPI Methods + **********************************************************************/ void codec_ctrl_impl::send_reg(boost::uint8_t addr){ boost::uint32_t reg = _ad9862_regs.get_write_reg(addr); //std::cout << "codec control write reg: " << std::hex << reg << std::endl; _iface->transact_spi( UE_SPI_SS_AD9862, spi_config_t::EDGE_RISE, - reg, 24, false /*no rb*/ + reg, 16, false /*no rb*/ + ); +} + +void codec_ctrl_impl::recv_reg(boost::uint8_t addr){ + boost::uint32_t reg = _ad9862_regs.get_read_reg(addr); + //std::cout << "codec control read reg: " << std::hex << reg << std::endl; + boost::uint32_t ret = _iface->transact_spi( + UE_SPI_SS_AD9862, + spi_config_t::EDGE_RISE, + reg, 16, true /*rb*/ ); + //std::cout << "codec control read ret: " << std::hex << ret << std::endl; + _ad9862_regs.set_reg(addr, boost::uint16_t(ret)); } /*********************************************************************** diff --git a/host/lib/usrp/usrp_e/codec_ctrl.hpp b/host/lib/usrp/usrp_e/codec_ctrl.hpp index 0fe70c4a2..efdcd7142 100644 --- a/host/lib/usrp/usrp_e/codec_ctrl.hpp +++ b/host/lib/usrp/usrp_e/codec_ctrl.hpp @@ -47,7 +47,9 @@ public: }; /*! - * Read the aux adc. + * Read an auxiliary adc: + * The internals remember which aux adc was read last. + * Therefore, the aux adc switch is only changed as needed. * \param which which of the 4 adcs * \return a value in volts */ @@ -58,15 +60,15 @@ public: AUX_DAC_A = 0xA, AUX_DAC_B = 0xB, AUX_DAC_C = 0xC, - AUX_DAC_D = 0xD + AUX_DAC_D = 0xD //really the sigma delta output }; /*! - * Write the aux dac. + * Write an auxiliary dac. * \param which which of the 4 dacs * \param volts the level in in volts */ - virtual void read_aux_adc(aux_dac_t which, float volts) = 0; + virtual void write_aux_dac(aux_dac_t which, float volts) = 0; }; -- cgit v1.2.3 From 45d92a0610582672cea4f1d97d116af00eac7bef Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 7 May 2010 10:27:33 -0700 Subject: SPI passthru for programming clock gen chip on brand new boards --- usrp2/top/u1e_passthru/Makefile | 107 +++++++++++++++ usrp2/top/u1e_passthru/passthru.ucf | 266 ++++++++++++++++++++++++++++++++++++ usrp2/top/u1e_passthru/passthru.v | 18 +++ 3 files changed, 391 insertions(+) create mode 100644 usrp2/top/u1e_passthru/Makefile create mode 100644 usrp2/top/u1e_passthru/passthru.ucf create mode 100644 usrp2/top/u1e_passthru/passthru.v diff --git a/usrp2/top/u1e_passthru/Makefile b/usrp2/top/u1e_passthru/Makefile new file mode 100644 index 000000000..62923f87f --- /dev/null +++ b/usrp2/top/u1e_passthru/Makefile @@ -0,0 +1,107 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# xtclsh Shell and tcl Script Path +################################################## +#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh +XTCLSH := xtclsh +ISE_HELPER := ../tcl/ise_helper.tcl + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := passthru +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +export SOURCE_ROOT := ../../../ +export SOURCES := \ +top/u1e_passthru/passthru.ucf \ +top/u1e_passthru/passthru.v + +################################################## +# Process Properties +################################################## +export SYNTHESIZE_PROPERTIES := \ +"Number of Clock Buffers" 6 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +export TRANSLATE_PROPERTIES := \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +export MAP_PROPERTIES := \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +export PLACE_ROUTE_PROPERTIES := \ +"Place & Route Effort Level (Overall)" High + +export STATIC_TIMING_PROPERTIES := \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +export GEN_PROG_FILE_PROPERTIES := \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +export SIM_MODEL_PROPERTIES := "" + +################################################## +# Make Options +################################################## +all: + @echo make proj, check, synth, bin, or clean + +proj: + PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) + +check: + PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) + +synth: + PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) + +bin: + PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) + +clean: + rm -rf $(BUILD_DIR) + + diff --git a/usrp2/top/u1e_passthru/passthru.ucf b/usrp2/top/u1e_passthru/passthru.ucf new file mode 100644 index 000000000..1672132a2 --- /dev/null +++ b/usrp2/top/u1e_passthru/passthru.ucf @@ -0,0 +1,266 @@ + +#NET "CLK_FPGA_P" LOC = "Y11" ; +#NET "CLK_FPGA_N" LOC = "Y10" ; + +## GPMC +#NET "EM_D<15>" LOC = "D13" ; +#NET "EM_D<14>" LOC = "D15" ; +#NET "EM_D<13>" LOC = "C16" ; +#NET "EM_D<12>" LOC = "B20" ; +#NET "EM_D<11>" LOC = "A19" ; +#NET "EM_D<10>" LOC = "A17" ; +#NET "EM_D<9>" LOC = "E15" ; +#NET "EM_D<8>" LOC = "F15" ; +#NET "EM_D<7>" LOC = "E16" ; +#NET "EM_D<6>" LOC = "F16" ; +#NET "EM_D<5>" LOC = "B17" ; +#NET "EM_D<4>" LOC = "C17" ; +#NET "EM_D<3>" LOC = "B19" ; +#NET "EM_D<2>" LOC = "D19" ; +#NET "EM_D<1>" LOC = "C19" ; +#NET "EM_D<0>" LOC = "A20" ; + +#NET "EM_A<10>" LOC = "C14" ; +#NET "EM_A<9>" LOC = "C10" ; +#NET "EM_A<8>" LOC = "C5" ; +#NET "EM_A<7>" LOC = "A18" ; +#NET "EM_A<6>" LOC = "A15" ; +#NET "EM_A<5>" LOC = "A12" ; +#NET "EM_A<4>" LOC = "A10" ; +#NET "EM_A<3>" LOC = "E7" ; +#NET "EM_A<2>" LOC = "A7" ; +#NET "EM_A<1>" LOC = "C15" ; + +#NET "EM_NCS6" LOC = "E17" ; +##NET "EM_NCS5" LOC = "E10" ; +#NET "EM_NCS4" LOC = "E6" ; +##NET "EM_NCS1" LOC = "D18" ; +##NET "EM_NCS0" LOC = "D17" ; + +#NET "EM_CLK" LOC = "F11" ; +#NET "EM_WAIT0" LOC = "F14" ; +#NET "EM_NBE<1>" LOC = "D14" ; +#NET "EM_NBE<0>" LOC = "A13" ; +#NET "EM_NWE" LOC = "B13" ; +#NET "EM_NOE" LOC = "A14" ; +##NET "EM_NADV_ALE" LOC = "B15" ; +##NET "EM_NWP" LOC = "F13" ; + +## Overo GPIO +NET "overo_gpio0" LOC = "F9" ; # MISC GPIO for debug +#NET "overo_gpio14" LOC = "C4" ; # MISC GPIO for debug +#NET "overo_gpio21" LOC = "D5" ; # MISC GPIO for debug +#NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug +#NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug +#NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug +#NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug +#NET "overo_gpio127" LOC = "C8" ; # MISC GPIO for debug +#NET "overo_gpio128" LOC = "G8" ; # MISC GPIO for debug +#NET "overo_gpio144" LOC = "A5" ; # tx_have_space +#NET "overo_gpio145" LOC = "C7" ; # tx_underrun +#NET "overo_gpio146" LOC = "A6" ; # rx_have_data +#NET "overo_gpio147" LOC = "B6" ; # rx_overrun +#NET "overo_gpio163" LOC = "D7" ; # MISC GPIO for debug +#NET "overo_gpio170" LOC = "E8" ; # MISC GPIO for debug +#NET "overo_gpio176" LOC = "B4" ; # MISC GPIO for debug + +## Overo UART +##NET "overo_txd1" LOC = "C6" ; +##NET "overo_rxd1" LOC = "D6" ; + +## FTDI UART to USB converter +#NET "FPGA_TXD" LOC = "U1" ; +#NET "FPGA_RXD" LOC = "T6" ; + +##NET "SYSEN" LOC = "C11" ; + +## I2C +#NET "db_scl" LOC = "U4" ; +#NET "db_sda" LOC = "U5" ; + +## SPI +### DBoard SPI +#NET "db_sclk_rx" LOC = "W3" ; +#NET "db_miso_rx" LOC = "W2" ; +#NET "db_mosi_rx" LOC = "V4" ; +#NET "db_sen_rx" LOC = "V3" ; +#NET "db_sclk_tx" LOC = "Y1" ; +#NET "db_miso_tx" LOC = "W1" ; +#NET "db_mosi_tx" LOC = "R3" ; +#NET "db_sen_tx" LOC = "T4" ; + +### AD9862 SPI and aux SPI Interfaces +##NET "aux_sdi_codec" LOC = "F19" ; +##NET "aux_sdo_codec" LOC = "F18" ; +##NET "aux_sclk_codec" LOC = "D21" ; +#NET "sen_codec" LOC = "D20" ; +#NET "mosi_codec" LOC = "E19" ; +#NET "miso_codec" LOC = "F21" ; +#NET "sclk_codec" LOC = "E20" ; + +### Clock Gen SPI +#NET "cgen_miso" LOC = "U2" ; +NET "cgen_mosi" LOC = "V1" ; +NET "cgen_sclk" LOC = "R5" ; +NET "cgen_sen_b" LOC = "T1" ; + +## Clock gen control +#NET "cgen_st_status" LOC = "D4" ; +#NET "cgen_st_ld" LOC = "D1" ; +#NET "cgen_st_refmon" LOC = "E1" ; +#NET "cgen_sync_b" LOC = "M1" ; +#NET "cgen_ref_sel" LOC = "J1" ; + +## Debug pins +#NET "debug_led<2>" LOC = "T5" ; +#NET "debug_led<1>" LOC = "R2" ; +#NET "debug_led<0>" LOC = "R1" ; +#NET "debug<0>" LOC = "P6" ; +#NET "debug<1>" LOC = "R6" ; +#NET "debug<2>" LOC = "P1" ; +#NET "debug<3>" LOC = "P2" ; +#NET "debug<4>" LOC = "N6" ; +#NET "debug<5>" LOC = "N5" ; +#NET "debug<6>" LOC = "N1" ; +#NET "debug<7>" LOC = "K2" ; +#NET "debug<8>" LOC = "K3" ; +#NET "debug<9>" LOC = "K6" ; +#NET "debug<10>" LOC = "L5" ; +#NET "debug<11>" LOC = "H2" ; +#NET "debug<12>" LOC = "K4" ; +#NET "debug<13>" LOC = "K5" ; +#NET "debug<14>" LOC = "G1" ; +#NET "debug<15>" LOC = "H1" ; +#NET "debug<16>" LOC = "H5" ; +#NET "debug<17>" LOC = "H6" ; +#NET "debug<18>" LOC = "E3" ; +#NET "debug<19>" LOC = "E4" ; +#NET "debug<20>" LOC = "G5" ; +#NET "debug<21>" LOC = "G6" ; +#NET "debug<22>" LOC = "F2" ; +#NET "debug<23>" LOC = "F1" ; +#NET "debug<24>" LOC = "H3" ; +#NET "debug<25>" LOC = "H4" ; +#NET "debug<26>" LOC = "F4" ; +#NET "debug<27>" LOC = "F5" ; +#NET "debug<28>" LOC = "C2" ; +#NET "debug<29>" LOC = "C1" ; +#NET "debug<30>" LOC = "F3" ; +#NET "debug<31>" LOC = "G3" ; +#NET "debug_clk<0>" LOC = "L6" ; +#NET "debug_clk<1>" LOC = "M5" ; + +#NET "debug_pb<2>" LOC = "Y2" ; +#NET "debug_pb<1>" LOC = "AA1" ; +#NET "debug_pb<0>" LOC = "N3" ; + +#NET "dip_sw<7>" LOC = "T3" ; +#NET "dip_sw<6>" LOC = "U3" ; +#NET "dip_sw<5>" LOC = "M3" ; +#NET "dip_sw<4>" LOC = "N4" ; +#NET "dip_sw<3>" LOC = "J3" ; +#NET "dip_sw<2>" LOC = "J4" ; +#NET "dip_sw<1>" LOC = "J6" ; +#NET "dip_sw<0>" LOC = "J7" ; + +##NET "RXSYNC" LOC = "F22" ; +##NET "reset_codec" LOC = "D22" ; + +##NET "DB<11>" LOC = "E22" ; +##NET "DB<10>" LOC = "J19" ; +##NET "DB<9>" LOC = "H20" ; +##NET "DB<8>" LOC = "G19" ; +##NET "DB<7>" LOC = "F20" ; +##NET "DB<6>" LOC = "K16" ; +##NET "DB<5>" LOC = "J17" ; +##NET "DB<4>" LOC = "H22" ; +##NET "DB<3>" LOC = "G22" ; +##NET "DB<2>" LOC = "H17" ; +##NET "DB<1>" LOC = "H18" ; +##NET "DB<0>" LOC = "K20" ; +##NET "DA<11>" LOC = "J20" ; +##NET "DA<10>" LOC = "K19" ; +##NET "DA<9>" LOC = "K18" ; +##NET "DA<8>" LOC = "L22" ; +##NET "DA<7>" LOC = "K22" ; +##NET "DA<6>" LOC = "N22" ; +##NET "DA<5>" LOC = "M22" ; +##NET "DA<4>" LOC = "N20" ; +##NET "DA<3>" LOC = "N19" ; +##NET "DA<2>" LOC = "R22" ; +##NET "DA<1>" LOC = "P22" ; +##NET "DA<0>" LOC = "N17" ; + +#NET "TX<13>" LOC = "P19" ; +#NET "TX<12>" LOC = "R18" ; +#NET "TX<11>" LOC = "U20" ; +#NET "TX<10>" LOC = "T20" ; +#NET "TX<9>" LOC = "R19" ; +#NET "TX<8>" LOC = "R20" ; +#NET "TX<7>" LOC = "W22" ; +#NET "TX<6>" LOC = "Y22" ; +#NET "TX<5>" LOC = "T18" ; +#NET "TX<4>" LOC = "T17" ; +#NET "TX<3>" LOC = "W19" ; +#NET "TX<2>" LOC = "V20" ; +#NET "TX<1>" LOC = "Y21" ; +#NET "TX<0>" LOC = "AA22" ; +#NET "TXSYNC" LOC = "U18" ; +#NET "TXBLANK" LOC = "U19" ; + +#NET "PPS_IN" LOC = "M17" ; + +#NET "io_tx<0>" LOC = "AB20" ; +#NET "io_tx<1>" LOC = "Y17" ; +#NET "io_tx<2>" LOC = "Y16" ; +#NET "io_tx<3>" LOC = "U16" ; +#NET "io_tx<4>" LOC = "V16" ; +#NET "io_tx<5>" LOC = "AB19" ; +#NET "io_tx<6>" LOC = "AA19" ; +#NET "io_tx<7>" LOC = "U14" ; +#NET "io_tx<8>" LOC = "U15" ; +#NET "io_tx<9>" LOC = "AB17" ; +#NET "io_tx<10>" LOC = "AB18" ; +#NET "io_tx<11>" LOC = "Y13" ; +#NET "io_tx<12>" LOC = "W14" ; +#NET "io_tx<13>" LOC = "U13" ; +#NET "io_tx<14>" LOC = "AA15" ; +#NET "io_tx<15>" LOC = "AB14" ; + +#NET "io_rx<0>" LOC = "Y8" ; +#NET "io_rx<1>" LOC = "Y9" ; +#NET "io_rx<2>" LOC = "V7" ; +#NET "io_rx<3>" LOC = "U8" ; +#NET "io_rx<4>" LOC = "V10" ; +#NET "io_rx<5>" LOC = "U9" ; +#NET "io_rx<6>" LOC = "AB7" ; +#NET "io_rx<7>" LOC = "AA8" ; +#NET "io_rx<8>" LOC = "W8" ; +#NET "io_rx<9>" LOC = "V8" ; +#NET "io_rx<10>" LOC = "AB5" ; +#NET "io_rx<11>" LOC = "AB6" ; +#NET "io_rx<12>" LOC = "AB4" ; +#NET "io_rx<13>" LOC = "AA4" ; +#NET "io_rx<14>" LOC = "W5" ; +#NET "io_rx<15>" LOC = "Y4" ; + +##NET "CLKOUT2_CODEC" LOC = "U12" ; +##NET "CLKOUT1_CODEC" LOC = "V12" ; + +## FPGA Config Pins +##NET "fpga_cfg_prog_b" LOC = "A2" ; +##NET "fpga_cfg_done" LOC = "AB21" ; +NET "fpga_cfg_din" LOC = "W17" ; +NET "fpga_cfg_cclk" LOC = "V17" ; +##NET "fpga_cfg_init_b" LOC = "W15" ; + +## Unused +##NET "unnamed_net37" LOC = "B1" ; # TMS +##NET "unnamed_net36" LOC = "B22" ; # TDO +##NET "unnamed_net35" LOC = "D2" ; # TDI +##NET "unnamed_net34" LOC = "A21" ; # TCK +##NET "unnamed_net45" LOC = "F7" ; # PUDC_B +##NET "unnamed_net44" LOC = "V6" ; # M2 +##NET "unnamed_net43" LOC = "AA3" ; # M1 +##NET "unnamed_net42" LOC = "AB3" ; # M0 +##NET "GND" LOC = "V19" ; # Suspend, unused diff --git a/usrp2/top/u1e_passthru/passthru.v b/usrp2/top/u1e_passthru/passthru.v new file mode 100644 index 000000000..459c226ee --- /dev/null +++ b/usrp2/top/u1e_passthru/passthru.v @@ -0,0 +1,18 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module passthru + (input overo_gpio0, + output cgen_sclk, + output cgen_sen_b, + output cgen_mosi, + input fpga_cfg_din, + input fpga_cfg_cclk + ); + + assign cgen_sclk = fpga_cfg_cclk; + assign cgen_sen_b = overo_gpio0; + assign cgen_mosi = fpga_cfg_din; + + +endmodule // passthru -- cgit v1.2.3 From b47920906bd1b0480bbcd8427b2d703889cb78e3 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Fri, 7 May 2010 19:23:58 +0000 Subject: Print an error and exit if open fails for some programs. --- host/apps/omap_debug/usrp-e-debug-pins.c | 4 ++++ host/apps/omap_debug/usrp-e-i2c.c | 6 ++++++ host/apps/omap_debug/usrp-e-spi.c | 7 +++++++ 3 files changed, 17 insertions(+) diff --git a/host/apps/omap_debug/usrp-e-debug-pins.c b/host/apps/omap_debug/usrp-e-debug-pins.c index d4e3f5223..d18bbf990 100644 --- a/host/apps/omap_debug/usrp-e-debug-pins.c +++ b/host/apps/omap_debug/usrp-e-debug-pins.c @@ -46,6 +46,10 @@ int main(int argc, char *argv[]) fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); + if (fp < 0) { + perror("Open failed"); + return -1; + } if (strcmp(argv[1], "0") == 0) { printf("Selected 0 based on %s\n", argv[1]); diff --git a/host/apps/omap_debug/usrp-e-i2c.c b/host/apps/omap_debug/usrp-e-i2c.c index 615dc557b..da8709ae1 100644 --- a/host/apps/omap_debug/usrp-e-i2c.c +++ b/host/apps/omap_debug/usrp-e-i2c.c @@ -37,6 +37,12 @@ int main(int argc, char *argv[]) fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); + if (fp < 0) { + perror("Open failed"); + return -1; + } + +// sleep(1); if (direction) { count = argc - 3; diff --git a/host/apps/omap_debug/usrp-e-spi.c b/host/apps/omap_debug/usrp-e-spi.c index d2c38e524..c353c409b 100644 --- a/host/apps/omap_debug/usrp-e-spi.c +++ b/host/apps/omap_debug/usrp-e-spi.c @@ -28,6 +28,13 @@ int main(int argc, char *argv[]) fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); + if (fp < 0) { + perror("Open failed"); + return -1; + } + +// sleep(1); + spi_dat.slave = slave; spi_dat.data = data; -- cgit v1.2.3 From 8df3a38c3be477a02c4b9d636a3ddd647e55e4a5 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Fri, 7 May 2010 15:45:31 -0400 Subject: First pass at data transfer program that uses CRC. --- host/apps/omap_debug/Makefile | 6 +- host/apps/omap_debug/usrp-e-crc-rw.c | 195 +++++++++++++++++++++++++++++++++++ 2 files changed, 200 insertions(+), 1 deletion(-) create mode 100644 host/apps/omap_debug/usrp-e-crc-rw.c diff --git a/host/apps/omap_debug/Makefile b/host/apps/omap_debug/Makefile index 14be592ff..9b590b9f7 100644 --- a/host/apps/omap_debug/Makefile +++ b/host/apps/omap_debug/Makefile @@ -1,6 +1,6 @@ CFLAGS=-Wall -I../../lib/usrp/usrp_e/ -all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio usrp-e-debug-pins usrp-e-rw-random usrp-e-fpga-rw usrp-e-lb-test +all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio usrp-e-debug-pins usrp-e-rw-random usrp-e-fpga-rw usrp-e-lb-test usrp-e-crc-rw usrp-e-spi : usrp-e-spi.c @@ -15,6 +15,9 @@ usrp-e-fpga-rw : usrp-e-fpga-rw.c usrp-e-rw-random : usrp-e-rw-random.c gcc -o $@ $< -lpthread +usrp-e-crc-rw : usrp-e-crc-rw.c + gcc -o $@ $< -lpthread + usrp-e-uart : usrp-e-uart.c usrp-e-uart-rx : usrp-e-uart-rx.c @@ -47,3 +50,4 @@ clean : rm -f usrp-e-gpio rm -f usrp-e-debug-pins rm -f usrp-e-lb-test + rm -f usrp-e-crc-rw diff --git a/host/apps/omap_debug/usrp-e-crc-rw.c b/host/apps/omap_debug/usrp-e-crc-rw.c new file mode 100644 index 000000000..1f23c8d54 --- /dev/null +++ b/host/apps/omap_debug/usrp-e-crc-rw.c @@ -0,0 +1,195 @@ +#include +#include +#include +#include +#include +#include +#include +#include "usrp_e.h" + +// max length #define PKT_DATA_LENGTH 1016 +static int packet_data_length; + +static int fp; +static u_int32_t crc_tab[256]; + +// CRC code from http://www.koders.com/c/fid699AFE0A656F0022C9D6B9D1743E697B69CE5815.aspx +// GPLv2 + +static u_int32_t chksum_crc32_gentab(void) +{ + unsigned long crc, poly; + unsigned long i, j; + + poly = 0xEDB88320L; + + for (i = 0; i < 256; i++) { + crc = i; + for (j = 8; j > 0; j--) { + if (crc & 1) { + crc = (crc >> 1) ^ poly; + } else { + crc >>= 1; + } + } + crc_tab[i] = crc; + } +} + +static void *read_thread(void *threadid) +{ + int cnt; + struct usrp_transfer_frame *rx_data; + int rx_pkt_cnt; + int i; + unsigned long crc; + unsigned int rx_crc; + + printf("Greetings from the reading thread!\n"); + + // IMPORTANT: must assume max length packet from fpga + rx_data = malloc(2048); + + rx_pkt_cnt = 0; + + while (1) { + + cnt = read(fp, rx_data, 2048); + if (cnt < 0) + printf("Error returned from read: %d\n", cnt); + + rx_pkt_cnt++; + + if (rx_pkt_cnt == 512) { + printf("."); + fflush(stdout); + rx_pkt_cnt = 0; + } + + if (rx_data->flags & RB_OVERRUN) + printf("O"); + + crc = 0xFFFFFFFF; + for (i = 0; i < rx_data->len - 4; i++) { + crc = ((crc >> 8) & 0x00FFFFFF) ^ + crc_tab[(crc ^ rx_data->buf[i]) & 0xFF]; + } + + rx_crc = *((int *) &rx_data[rx_data->len - 4]); + + if (rx_crc != (crc & 0xFFFFFFFF)) { + printf("CRC Error, sent: %d, rx: %d\n", + rx_crc, (crc & 0xFFFFFFFF)); + } + + } +} + +static void *write_thread(void *threadid) +{ + int seq_number, i, cnt, tx_pkt_cnt; + int tx_len; + unsigned long crc; + struct usrp_transfer_frame *tx_data; + struct pkt *p; + + printf("Greetings from the write thread!\n"); + + tx_data = malloc(2048); + + while (1) { + + tx_pkt_cnt++; + if (tx_pkt_cnt == 512) { + printf("."); + fflush(stdout); + } + if (tx_pkt_cnt == 1024) { + printf("'"); + fflush(stdout); + } + if (tx_pkt_cnt == 1536) { + printf(":"); + fflush(stdout); + tx_pkt_cnt = 0; + } + + tx_len = 2048 - sizeof(struct usrp_transfer_frame) - sizeof(int); + crc = 0xFFFFFFFF; + for (i = 0; i < tx_len; i++) { + tx_data->buf[i] = rand() & 0xFF; + + crc = ((crc >> 8) & 0x00FFFFFF) ^ + crc_tab[(crc ^ tx_data->buf[i]) & 0xFF]; + + } + *((int *) &tx_data[tx_len]) = crc; + + cnt = write(fp, tx_data, 2048); + if (cnt < 0) + printf("Error returned from write: %d\n", cnt); +// sleep(1); + } +} + + +int main(int argc, char *argv[]) +{ + pthread_t tx, rx; + long int t; + int fpga_config_flag ,decimation; + struct usrp_e_ctl16 d; + struct sched_param s = { + .sched_priority = 1 + }; + + if (argc < 4) { + printf("%s t|w|rw decimation data_size\n", argv[0]); + return -1; + } + + decimation = atoi(argv[2]); + packet_data_length = atoi(argv[3]); + + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); + + fpga_config_flag = 0; + if (strcmp(argv[1], "w") == 0) + fpga_config_flag |= (1 << 15); + else if (strcmp(argv[1], "r") == 0) + fpga_config_flag |= (1 << 14); + else if (strcmp(argv[1], "rw") == 0) + fpga_config_flag |= ((1 << 15) | (1 << 14)); + + fpga_config_flag |= decimation; + + d.offset = 14; + d.count = 1; + d.buf[0] = fpga_config_flag; + ioctl(fp, USRP_E_WRITE_CTL16, &d); + + sleep(1); // in case the kernel threads need time to start. FIXME if so + + sched_setscheduler(0, SCHED_RR, &s); + + if (fpga_config_flag & (1 << 14)) { + if (pthread_create(&rx, NULL, read_thread, (void *) t)) { + printf("Failed to create rx thread\n"); + exit(-1); + } + } + + sleep(1); + + if (fpga_config_flag & (1 << 15)) { + if (pthread_create(&tx, NULL, write_thread, (void *) t)) { + printf("Failed to create tx thread\n"); + exit(-1); + } + } + + sleep(10000); + + printf("Done sleeping\n"); +} -- cgit v1.2.3 From 6c306995a733622a0b0c3fb8c13c23dc8301d926 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Fri, 7 May 2010 16:14:28 -0400 Subject: Update usrp_e.h file from kernel header. --- host/apps/omap_debug/usrp_e.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/host/apps/omap_debug/usrp_e.h b/host/apps/omap_debug/usrp_e.h index 0b582f59b..fd74e6e9e 100644 --- a/host/apps/omap_debug/usrp_e.h +++ b/host/apps/omap_debug/usrp_e.h @@ -34,13 +34,8 @@ struct usrp_e_ctl32 { #define UE_SPI_TXRX 1 // Defines for spi ctrl register -#define UE_SPI_CTRL_ASS (1<<13) -#define UE_SPI_CTRL_IE (1<<12) -#define UE_SPI_CTRL_LSB (1<<11) #define UE_SPI_CTRL_TXNEG (1<<10) #define UE_SPI_CTRL_RXNEG (1<<9) -#define UE_SPI_CTRL_GO_BSY (1<<8) -#define UE_SPI_CTRL_CHAR_LEN_MASK 0x7f #define UE_SPI_PUSH_RISE 0 #define UE_SPI_PUSH_FALL UE_SPI_CTRL_TXNEG -- cgit v1.2.3 From 6ef09d18def4afdd6413188ab63ee38dbae4e9d8 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 7 May 2010 21:51:06 +0000 Subject: filled in dboard interface with codec and clock control --- host/lib/usrp/usrp_e/clock_ctrl.cpp | 4 ++ host/lib/usrp/usrp_e/clock_ctrl.hpp | 18 +++++++ host/lib/usrp/usrp_e/dboard_iface.cpp | 88 ++++++++++++++++++++++++----------- host/lib/usrp/usrp_e/dboard_impl.cpp | 6 ++- host/lib/usrp/usrp_e/usrp_e_impl.cpp | 2 - host/lib/usrp/usrp_e/usrp_e_impl.hpp | 8 +++- 6 files changed, 95 insertions(+), 31 deletions(-) diff --git a/host/lib/usrp/usrp_e/clock_ctrl.cpp b/host/lib/usrp/usrp_e/clock_ctrl.cpp index 9c2ddf670..5f7269412 100644 --- a/host/lib/usrp/usrp_e/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e/clock_ctrl.cpp @@ -38,6 +38,10 @@ public: void enable_rx_dboard_clock(bool enb); void enable_tx_dboard_clock(bool enb); + double get_fpga_clock_rate(void){return 64e6;} + double get_rx_dboard_clock_rate(void){return get_fpga_clock_rate();} + double get_tx_dboard_clock_rate(void){return get_fpga_clock_rate();} + private: usrp_e_iface::sptr _iface; ad9522_regs_t _ad9522_regs; diff --git a/host/lib/usrp/usrp_e/clock_ctrl.hpp b/host/lib/usrp/usrp_e/clock_ctrl.hpp index d0b896a8f..994b83564 100644 --- a/host/lib/usrp/usrp_e/clock_ctrl.hpp +++ b/host/lib/usrp/usrp_e/clock_ctrl.hpp @@ -38,6 +38,24 @@ public: */ static sptr make(usrp_e_iface::sptr iface); + /*! + * Get the rate of the fpga clock line. + * \return the fpga clock rate in Hz + */ + virtual double get_fpga_clock_rate(void) = 0; + + /*! + * Get the rate of the dboard clock clock line. + * \return the dboard clock rate in Hz + */ + virtual double get_rx_dboard_clock_rate(void) = 0; + + /*! + * Get the rate of the dboard clock clock line. + * \return the dboard clock rate in Hz + */ + virtual double get_tx_dboard_clock_rate(void) = 0; + /*! * Enable/disable the rx dboard clock. * \param enb true to enable diff --git a/host/lib/usrp/usrp_e/dboard_iface.cpp b/host/lib/usrp/usrp_e/dboard_iface.cpp index 2a3976ba1..e70934b8c 100644 --- a/host/lib/usrp/usrp_e/dboard_iface.cpp +++ b/host/lib/usrp/usrp_e/dboard_iface.cpp @@ -17,6 +17,8 @@ #include "usrp_e_iface.hpp" #include "usrp_e_regs.hpp" +#include "clock_ctrl.hpp" +#include "codec_ctrl.hpp" #include #include #include @@ -25,11 +27,24 @@ using namespace uhd; using namespace uhd::usrp; +using namespace boost::assign; class usrp_e_dboard_iface : public dboard_iface{ public: - usrp_e_dboard_iface(usrp_e_iface::sptr iface); - ~usrp_e_dboard_iface(void); + + usrp_e_dboard_iface( + usrp_e_iface::sptr iface, + clock_ctrl::sptr clock, + codec_ctrl::sptr codec + ){ + _iface = iface; + _clock = clock; + _codec = codec; + } + + ~usrp_e_dboard_iface(void){ + /* NOP */ + } void write_aux_dac(unit_t, int, float); float read_aux_adc(unit_t, int); @@ -60,35 +75,37 @@ public: private: usrp_e_iface::sptr _iface; + clock_ctrl::sptr _clock; + codec_ctrl::sptr _codec; }; /*********************************************************************** * Make Function **********************************************************************/ -dboard_iface::sptr make_usrp_e_dboard_iface(usrp_e_iface::sptr iface){ - return dboard_iface::sptr(new usrp_e_dboard_iface(iface)); -} - -/*********************************************************************** - * Structors - **********************************************************************/ -usrp_e_dboard_iface::usrp_e_dboard_iface(usrp_e_iface::sptr iface){ - _iface = iface; -} - -usrp_e_dboard_iface::~usrp_e_dboard_iface(void){ - /* NOP */ +dboard_iface::sptr make_usrp_e_dboard_iface( + usrp_e_iface::sptr iface, + clock_ctrl::sptr clock, + codec_ctrl::sptr codec +){ + return dboard_iface::sptr(new usrp_e_dboard_iface(iface, clock, codec)); } /*********************************************************************** * Clock Rates **********************************************************************/ -double usrp_e_dboard_iface::get_clock_rate(unit_t){ - throw std::runtime_error("not implemented"); +double usrp_e_dboard_iface::get_clock_rate(unit_t unit){ + switch(unit){ + case UNIT_RX: return _clock->get_rx_dboard_clock_rate(); + case UNIT_TX: return _clock->get_tx_dboard_clock_rate(); + } + UHD_ASSERT_THROW(false); } -void usrp_e_dboard_iface::set_clock_enabled(unit_t, bool){ - throw std::runtime_error("not implemented"); +void usrp_e_dboard_iface::set_clock_enabled(unit_t unit, bool enb){ + switch(unit){ + case UNIT_RX: return _clock->enable_rx_dboard_clock(enb); + case UNIT_TX: return _clock->enable_tx_dboard_clock(enb); + } } /*********************************************************************** @@ -96,7 +113,7 @@ void usrp_e_dboard_iface::set_clock_enabled(unit_t, bool){ **********************************************************************/ void usrp_e_dboard_iface::set_gpio_ddr(unit_t bank, boost::uint16_t value){ //define mapping of gpio bank to register address - static const uhd::dict bank_to_addr = boost::assign::map_list_of + static const uhd::dict bank_to_addr = map_list_of (UNIT_RX, UE_REG_GPIO_RX_DDR) (UNIT_TX, UE_REG_GPIO_TX_DDR) ; @@ -105,7 +122,7 @@ void usrp_e_dboard_iface::set_gpio_ddr(unit_t bank, boost::uint16_t value){ boost::uint16_t usrp_e_dboard_iface::read_gpio(unit_t bank){ //define mapping of gpio bank to register address - static const uhd::dict bank_to_addr = boost::assign::map_list_of + static const uhd::dict bank_to_addr = map_list_of (UNIT_RX, UE_REG_GPIO_RX_IO) (UNIT_TX, UE_REG_GPIO_TX_IO) ; @@ -116,14 +133,14 @@ void usrp_e_dboard_iface::set_atr_reg(unit_t bank, atr_reg_t atr, boost::uint16_ //define mapping of bank to atr regs to register address static const uhd::dict< unit_t, uhd::dict - > bank_to_atr_to_addr = boost::assign::map_list_of - (UNIT_RX, boost::assign::map_list_of + > bank_to_atr_to_addr = map_list_of + (UNIT_RX, map_list_of (ATR_REG_IDLE, UE_REG_ATR_IDLE_RXSIDE) (ATR_REG_TX_ONLY, UE_REG_ATR_INTX_RXSIDE) (ATR_REG_RX_ONLY, UE_REG_ATR_INRX_RXSIDE) (ATR_REG_FULL_DUPLEX, UE_REG_ATR_FULL_RXSIDE) ) - (UNIT_TX, boost::assign::map_list_of + (UNIT_TX, map_list_of (ATR_REG_IDLE, UE_REG_ATR_IDLE_TXSIDE) (ATR_REG_TX_ONLY, UE_REG_ATR_INTX_TXSIDE) (ATR_REG_RX_ONLY, UE_REG_ATR_INRX_TXSIDE) @@ -181,10 +198,27 @@ byte_vector_t usrp_e_dboard_iface::read_i2c(boost::uint8_t addr, size_t num_byte /*********************************************************************** * Aux DAX/ADC **********************************************************************/ -void usrp_e_dboard_iface::write_aux_dac(dboard_iface::unit_t unit, int which, float value){ - throw std::runtime_error("not implemented"); +void usrp_e_dboard_iface::write_aux_dac(dboard_iface::unit_t, int which, float value){ + //same aux dacs for each unit + static const uhd::dict which_to_aux_dac = map_list_of + (0, codec_ctrl::AUX_DAC_A) (1, codec_ctrl::AUX_DAC_B) + (2, codec_ctrl::AUX_DAC_C) (3, codec_ctrl::AUX_DAC_D) + ; + _codec->write_aux_dac(which_to_aux_dac[which], value); } float usrp_e_dboard_iface::read_aux_adc(dboard_iface::unit_t unit, int which){ - throw std::runtime_error("not implemented"); + static const uhd::dict< + unit_t, uhd::dict + > unit_to_which_to_aux_adc = map_list_of + (UNIT_RX, map_list_of + (0, codec_ctrl::AUX_ADC_A1) + (1, codec_ctrl::AUX_ADC_B1) + ) + (UNIT_TX, map_list_of + (0, codec_ctrl::AUX_ADC_A2) + (1, codec_ctrl::AUX_ADC_B2) + ) + ; + return _codec->read_aux_adc(unit_to_which_to_aux_adc[unit][which]); } diff --git a/host/lib/usrp/usrp_e/dboard_impl.cpp b/host/lib/usrp/usrp_e/dboard_impl.cpp index 00b5d77d7..31f792306 100644 --- a/host/lib/usrp/usrp_e/dboard_impl.cpp +++ b/host/lib/usrp/usrp_e/dboard_impl.cpp @@ -17,6 +17,7 @@ #include #include "usrp_e_impl.hpp" +#include using namespace uhd::usrp; @@ -27,9 +28,12 @@ void usrp_e_impl::dboard_init(void){ _rx_db_eeprom = dboard_eeprom_t(_iface->read_eeprom(I2C_ADDR_RX_DB, 0, dboard_eeprom_t::num_bytes())); _tx_db_eeprom = dboard_eeprom_t(_iface->read_eeprom(I2C_ADDR_TX_DB, 0, dboard_eeprom_t::num_bytes())); + std::cout << _rx_db_eeprom.id.to_pp_string() << std::endl; + std::cout << _tx_db_eeprom.id.to_pp_string() << std::endl; + //create a new dboard interface and manager dboard_iface::sptr dboard_iface( - make_usrp_e_dboard_iface(_iface) + make_usrp_e_dboard_iface(_iface, _clock_ctrl, _codec_ctrl) ); _dboard_manager = dboard_manager::make( _rx_db_eeprom.id, _tx_db_eeprom.id, dboard_iface diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.cpp b/host/lib/usrp/usrp_e/usrp_e_impl.cpp index b6fed6a74..5861be102 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.cpp @@ -83,8 +83,6 @@ usrp_e_impl::usrp_e_impl(const std::string &node){ )); } - sleep(1); //FIXME sleep here until the kernel driver stops hanging - //setup various interfaces into hardware _iface = usrp_e_iface::make(_node_fd); _clock_ctrl = clock_ctrl::make(_iface); diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index 6746e012a..bde0f87c3 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -29,9 +29,15 @@ /*! * Make a usrp-e dboard interface. * \param iface the usrp-e interface object + * \param clock the clock control interface + * \param codec the codec control interface * \return a sptr to a new dboard interface */ -uhd::usrp::dboard_iface::sptr make_usrp_e_dboard_iface(usrp_e_iface::sptr iface); +uhd::usrp::dboard_iface::sptr make_usrp_e_dboard_iface( + usrp_e_iface::sptr iface, + clock_ctrl::sptr clock, + codec_ctrl::sptr codec +); /*! * Simple wax obj proxy class: -- cgit v1.2.3 From 29809e9697b052fa1d0cd2109c8bd5f9af178cfa Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sat, 8 May 2010 01:58:10 +0000 Subject: moved open/close into iface, work on codec tx --- host/lib/usrp/usrp_e/codec_ctrl.cpp | 35 ++++++++++++++++++++++++++++++++--- host/lib/usrp/usrp_e/usrp_e_iface.cpp | 17 ++++++++++++----- host/lib/usrp/usrp_e/usrp_e_iface.hpp | 4 ++-- host/lib/usrp/usrp_e/usrp_e_impl.cpp | 13 ++----------- host/lib/usrp/usrp_e/usrp_e_impl.hpp | 1 - 5 files changed, 48 insertions(+), 22 deletions(-) diff --git a/host/lib/usrp/usrp_e/codec_ctrl.cpp b/host/lib/usrp/usrp_e/codec_ctrl.cpp index a430f2c6f..3f3523ddf 100644 --- a/host/lib/usrp/usrp_e/codec_ctrl.cpp +++ b/host/lib/usrp/usrp_e/codec_ctrl.cpp @@ -29,6 +29,8 @@ using namespace uhd; +static const bool codec_debug = true; + /*********************************************************************** * Codec Control Implementation **********************************************************************/ @@ -56,6 +58,9 @@ private: codec_ctrl_impl::codec_ctrl_impl(usrp_e_iface::sptr iface){ _iface = iface; + //FIXME temp poke !!! + _iface->poke16(UE_REG_MISC_TEST, 0x0f00); + //soft reset _ad9862_regs.soft_reset = 1; this->send_reg(0); @@ -65,6 +70,28 @@ codec_ctrl_impl::codec_ctrl_impl(usrp_e_iface::sptr iface){ _ad9862_regs.lsb_first = ad9862_regs_t::LSB_FIRST_MSB; _ad9862_regs.soft_reset = 0; + //setup rx side of codec + _ad9862_regs.byp_buffer_a = 1; + _ad9862_regs.byp_buffer_b = 1; + _ad9862_regs.buffer_a_pd = 1; + _ad9862_regs.buffer_b_pd = 1; + _ad9862_regs.rx_pga_a = 0x1f; //TODO bring under api control + _ad9862_regs.rx_pga_b = 0x1f; //TODO bring under api control + _ad9862_regs.rx_twos_comp = 1; + _ad9862_regs.rx_hilbert = ad9862_regs_t::RX_HILBERT_DIS; + + //setup tx side of codec + _ad9862_regs.two_data_paths = ad9862_regs_t::TWO_DATA_PATHS_BOTH; + _ad9862_regs.interleaved = ad9862_regs_t::INTERLEAVED_SINGLE; //FIXME should be interleaved + _ad9862_regs.tx_pga_gain = 199; //TODO bring under api control + _ad9862_regs.tx_hilbert = ad9862_regs_t::TX_HILBERT_DIS; + _ad9862_regs.interp = ad9862_regs_t::INTERP_4; + _ad9862_regs.tx_twos_comp = 1; + _ad9862_regs.fine_mode = ad9862_regs_t::FINE_MODE_BYPASS; + _ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_BYPASS; + _ad9862_regs.dac_a_coarse_gain = 0x3; + _ad9862_regs.dac_b_coarse_gain = 0x3; + //write the register settings to the codec for (uint8_t addr = 0; addr <= 50; addr++){ this->send_reg(addr); @@ -72,6 +99,8 @@ codec_ctrl_impl::codec_ctrl_impl(usrp_e_iface::sptr iface){ } codec_ctrl_impl::~codec_ctrl_impl(void){ + return; //FIXME remove this later + //set aux dacs to zero this->write_aux_dac(AUX_DAC_A, 0); this->write_aux_dac(AUX_DAC_B, 0); @@ -181,7 +210,7 @@ void codec_ctrl_impl::write_aux_dac(aux_dac_t which, float volts){ **********************************************************************/ void codec_ctrl_impl::send_reg(boost::uint8_t addr){ boost::uint32_t reg = _ad9862_regs.get_write_reg(addr); - //std::cout << "codec control write reg: " << std::hex << reg << std::endl; + if (codec_debug) std::cout << "codec control write reg: " << std::hex << reg << std::endl; _iface->transact_spi( UE_SPI_SS_AD9862, spi_config_t::EDGE_RISE, @@ -191,13 +220,13 @@ void codec_ctrl_impl::send_reg(boost::uint8_t addr){ void codec_ctrl_impl::recv_reg(boost::uint8_t addr){ boost::uint32_t reg = _ad9862_regs.get_read_reg(addr); - //std::cout << "codec control read reg: " << std::hex << reg << std::endl; + if (codec_debug) std::cout << "codec control read reg: " << std::hex << reg << std::endl; boost::uint32_t ret = _iface->transact_spi( UE_SPI_SS_AD9862, spi_config_t::EDGE_RISE, reg, 16, true /*rb*/ ); - //std::cout << "codec control read ret: " << std::hex << ret << std::endl; + if (codec_debug) std::cout << "codec control read ret: " << std::hex << ret << std::endl; _ad9862_regs.set_reg(addr, boost::uint16_t(ret)); } diff --git a/host/lib/usrp/usrp_e/usrp_e_iface.cpp b/host/lib/usrp/usrp_e/usrp_e_iface.cpp index 1dbe383fa..98d8ef478 100644 --- a/host/lib/usrp/usrp_e/usrp_e_iface.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_iface.cpp @@ -18,6 +18,7 @@ #include "usrp_e_iface.hpp" #include #include //ioctl +#include //open, close #include //ioctl structures and constants #include #include //mutex @@ -31,12 +32,18 @@ public: /******************************************************************* * Structors ******************************************************************/ - usrp_e_iface_impl(int node_fd){ - _node_fd = node_fd; + usrp_e_iface_impl(const std::string &node){ + //open the device node and check file descriptor + if ((_node_fd = ::open(node.c_str(), O_RDWR)) < 0){ + throw std::runtime_error(str( + boost::format("Failed to open %s") % node + )); + } } ~usrp_e_iface_impl(void){ - /* NOP */ + //close the device node file descriptor + ::close(_node_fd); } /******************************************************************* @@ -178,6 +185,6 @@ private: /*********************************************************************** * Public Make Function **********************************************************************/ -usrp_e_iface::sptr usrp_e_iface::make(int node_fd){ - return sptr(new usrp_e_iface_impl(node_fd)); +usrp_e_iface::sptr usrp_e_iface::make(const std::string &node){ + return sptr(new usrp_e_iface_impl(node)); } diff --git a/host/lib/usrp/usrp_e/usrp_e_iface.hpp b/host/lib/usrp/usrp_e/usrp_e_iface.hpp index 016d7448f..6363a24b2 100644 --- a/host/lib/usrp/usrp_e/usrp_e_iface.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_iface.hpp @@ -44,10 +44,10 @@ public: /*! * Make a new usrp-e interface with the control transport. - * \param node_fd the file descriptor for the kernel module node + * \param node the device node name * \return a new usrp-e interface object */ - static sptr make(int node_fd); + static sptr make(const std::string &node); /*! * Perform an ioctl call on the device node file descriptor. diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.cpp b/host/lib/usrp/usrp_e/usrp_e_impl.cpp index 5861be102..4f7361eca 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.cpp @@ -22,7 +22,6 @@ #include #include #include -#include //open using namespace uhd; using namespace uhd::usrp; @@ -76,15 +75,8 @@ device::sptr usrp_e::make(const device_addr_t &device_addr){ usrp_e_impl::usrp_e_impl(const std::string &node){ std::cout << boost::format("Opening USRP-E on %s") % node << std::endl; - //open the device node and check file descriptor - if ((_node_fd = ::open(node.c_str(), O_RDWR)) < 0){ - throw std::runtime_error(str( - boost::format("Failed to open %s") % node - )); - } - //setup various interfaces into hardware - _iface = usrp_e_iface::make(_node_fd); + _iface = usrp_e_iface::make(node); _clock_ctrl = clock_ctrl::make(_iface); _codec_ctrl = codec_ctrl::make(_iface); @@ -100,8 +92,7 @@ usrp_e_impl::usrp_e_impl(const std::string &node){ } usrp_e_impl::~usrp_e_impl(void){ - //close the device node file descriptor - ::close(_node_fd); + /* NOP */ } /*********************************************************************** diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index bde0f87c3..59f80c70c 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -95,7 +95,6 @@ public: private: static const size_t _max_num_samples = 2048/sizeof(boost::uint32_t); usrp_e_iface::sptr _iface; - int _node_fd; uhd::clock_config_t _clock_config; -- cgit v1.2.3 From 3a26c45c69ea61bb1e2cc4dbfb7a605abbd7ca4b Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 10 May 2010 19:00:56 +0000 Subject: ad9862 transmit working --- host/lib/ic_reg_maps/gen_ad9862_regs.py | 2 +- host/lib/usrp/usrp_e/codec_ctrl.cpp | 13 +++++++++++-- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/host/lib/ic_reg_maps/gen_ad9862_regs.py b/host/lib/ic_reg_maps/gen_ad9862_regs.py index 4444c6240..00340224c 100755 --- a/host/lib/ic_reg_maps/gen_ad9862_regs.py +++ b/host/lib/ic_reg_maps/gen_ad9862_regs.py @@ -123,7 +123,7 @@ ftw_23_16 23[0:7] 0 ######################################################################## ## DLL ######################################################################## -input_clk_ctrl 24[6] 0 external, internal +input_clk_ctrl 24[6] 0 internal, external adc_div2 24[5] 0 normal, div2 dll_mult 24[3:4] 0 1, 2, 4 dll_pd 24[2] 0 diff --git a/host/lib/usrp/usrp_e/codec_ctrl.cpp b/host/lib/usrp/usrp_e/codec_ctrl.cpp index 3f3523ddf..ce05ac9eb 100644 --- a/host/lib/usrp/usrp_e/codec_ctrl.cpp +++ b/host/lib/usrp/usrp_e/codec_ctrl.cpp @@ -82,7 +82,7 @@ codec_ctrl_impl::codec_ctrl_impl(usrp_e_iface::sptr iface){ //setup tx side of codec _ad9862_regs.two_data_paths = ad9862_regs_t::TWO_DATA_PATHS_BOTH; - _ad9862_regs.interleaved = ad9862_regs_t::INTERLEAVED_SINGLE; //FIXME should be interleaved + _ad9862_regs.interleaved = ad9862_regs_t::INTERLEAVED_INTERLEAVED; _ad9862_regs.tx_pga_gain = 199; //TODO bring under api control _ad9862_regs.tx_hilbert = ad9862_regs_t::TX_HILBERT_DIS; _ad9862_regs.interp = ad9862_regs_t::INTERP_4; @@ -92,10 +92,19 @@ codec_ctrl_impl::codec_ctrl_impl(usrp_e_iface::sptr iface){ _ad9862_regs.dac_a_coarse_gain = 0x3; _ad9862_regs.dac_b_coarse_gain = 0x3; + //setup the dll + _ad9862_regs.input_clk_ctrl = ad9862_regs_t::INPUT_CLK_CTRL_EXTERNAL; + _ad9862_regs.dll_mult = ad9862_regs_t::DLL_MULT_2; + _ad9862_regs.dll_mode = ad9862_regs_t::DLL_MODE_FAST; + //write the register settings to the codec - for (uint8_t addr = 0; addr <= 50; addr++){ + for (uint8_t addr = 0; addr <= 25; addr++){ this->send_reg(addr); } + + //aux adc clock + _ad9862_regs.clk_4 = ad9862_regs_t::CLK_4_1_4; + this->send_reg(34); } codec_ctrl_impl::~codec_ctrl_impl(void){ -- cgit v1.2.3 From 4a573b5dcc78f9a13162efce09f0bc31f298a818 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 10 May 2010 13:23:48 -0700 Subject: proper signal level for 24 bit data --- usrp2/top/u1e/u1e_core.v | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 74ffc4657..a262184a8 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -349,15 +349,20 @@ module u1e_core cordic_z24 #(.bitwidth(24)) tx_cordic (.clock(wb_clk), .reset(wb_rst), .enable(1), - .xi(24'd15000), .yi(24'd0), .zi(phase), .xo(tx_i), .yo(tx_q), .zo()); + .xi(24'd2500000), .yi(24'd0), .zi(phase), .xo(tx_i), .yo(tx_q), .zo()); // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry assign debug_clk = { EM_CLK, clk_fpga }; - assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, +/* + assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, { EM_D } }; +*/ + assign debug = { phase[23:8], txsync, txblank, tx }; + + assign debug_gpio_0 = { debug_gpmc }; assign debug_gpio_1 = { {rx_enable, rx_strobe, rx_fifo_rdy, rx_strobe & ~rx_fifo_rdy}, {tx_enable, tx_strobe, tx_fifo_rdy, tx_strobe & ~tx_fifo_rdy}, -- cgit v1.2.3 From 57114cf6579a0c6f8fc4626d4c20e8fc09cddb72 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 10 May 2010 14:56:14 -0700 Subject: switched passthru of cgen_sen_b to gpio127, made a note of it. No more safe_u1e necessary. --- usrp2/top/safe_u1e/.gitignore | 4 - usrp2/top/safe_u1e/Makefile | 246 --------------------------------- usrp2/top/safe_u1e/safe_u1e.ucf | 262 ------------------------------------ usrp2/top/safe_u1e/safe_u1e.v | 41 ------ usrp2/top/u1e/u1e.ucf | 2 +- usrp2/top/u1e_passthru/.gitignore | 1 + usrp2/top/u1e_passthru/passthru.ucf | 4 +- usrp2/top/u1e_passthru/passthru.v | 10 +- 8 files changed, 9 insertions(+), 561 deletions(-) delete mode 100644 usrp2/top/safe_u1e/.gitignore delete mode 100644 usrp2/top/safe_u1e/Makefile delete mode 100644 usrp2/top/safe_u1e/safe_u1e.ucf delete mode 100644 usrp2/top/safe_u1e/safe_u1e.v create mode 100644 usrp2/top/u1e_passthru/.gitignore diff --git a/usrp2/top/safe_u1e/.gitignore b/usrp2/top/safe_u1e/.gitignore deleted file mode 100644 index f8b57ea21..000000000 --- a/usrp2/top/safe_u1e/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -*~ -build -*.log -*.cmd diff --git a/usrp2/top/safe_u1e/Makefile b/usrp2/top/safe_u1e/Makefile deleted file mode 100644 index d28cc2b89..000000000 --- a/usrp2/top/safe_u1e/Makefile +++ /dev/null @@ -1,246 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -################################################## -# xtclsh Shell and tcl Script Path -################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl - -################################################## -# Project Setup -################################################## -BUILD_DIR := build/ -export TOP_MODULE := safe_u1e -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd1800a \ -package cs484 \ -speed -4 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ -control_lib/bin2gray.v \ -control_lib/dcache.v \ -control_lib/decoder_3_8.v \ -control_lib/dpram32.v \ -control_lib/gray2bin.v \ -control_lib/gray_send.v \ -control_lib/icache.v \ -control_lib/mux4.v \ -control_lib/mux8.v \ -control_lib/nsgpio.v \ -control_lib/ram_2port.v \ -control_lib/ram_harv_cache.v \ -control_lib/ram_loader.v \ -control_lib/setting_reg.v \ -control_lib/settings_bus.v \ -control_lib/srl.v \ -control_lib/system_control.v \ -control_lib/wb_1master.v \ -control_lib/wb_readback_mux.v \ -control_lib/simple_uart.v \ -control_lib/simple_uart_tx.v \ -control_lib/simple_uart_rx.v \ -control_lib/oneshot_2clk.v \ -control_lib/sd_spi.v \ -control_lib/sd_spi_wb.v \ -control_lib/wb_bridge_16_32.v \ -control_lib/reset_sync.v \ -simple_gemac/simple_gemac_wrapper.v \ -simple_gemac/simple_gemac.v \ -simple_gemac/simple_gemac_wb.v \ -simple_gemac/simple_gemac_tx.v \ -simple_gemac/simple_gemac_rx.v \ -simple_gemac/crc.v \ -simple_gemac/delay_line.v \ -simple_gemac/flow_ctrl_tx.v \ -simple_gemac/flow_ctrl_rx.v \ -simple_gemac/address_filter.v \ -simple_gemac/ll8_to_txmac.v \ -simple_gemac/rxmac_to_ll8.v \ -simple_gemac/miim/eth_miim.v \ -simple_gemac/miim/eth_clockgen.v \ -simple_gemac/miim/eth_outputcontrol.v \ -simple_gemac/miim/eth_shiftreg.v \ -control_lib/newfifo/buffer_int.v \ -control_lib/newfifo/buffer_pool.v \ -control_lib/newfifo/fifo_2clock.v \ -control_lib/newfifo/fifo_2clock_cascade.v \ -control_lib/newfifo/ll8_shortfifo.v \ -control_lib/newfifo/ll8_to_fifo36.v \ -control_lib/newfifo/fifo_short.v \ -control_lib/newfifo/fifo_long.v \ -control_lib/newfifo/fifo_cascade.v \ -control_lib/newfifo/fifo36_to_ll8.v \ -control_lib/longfifo.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ -coregen/fifo_xlnx_2Kx36_2clk.v \ -coregen/fifo_xlnx_2Kx36_2clk.xco \ -coregen/fifo_xlnx_512x36_2clk.v \ -coregen/fifo_xlnx_512x36_2clk.xco \ -coregen/fifo_xlnx_64x36_2clk.v \ -coregen/fifo_xlnx_64x36_2clk.xco \ -extram/wb_zbt16_b.v \ -opencores/8b10b/decode_8b10b.v \ -opencores/8b10b/encode_8b10b.v \ -opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -opencores/aemb/rtl/verilog/aeMB_core_BE.v \ -opencores/aemb/rtl/verilog/aeMB_ctrl.v \ -opencores/aemb/rtl/verilog/aeMB_edk32.v \ -opencores/aemb/rtl/verilog/aeMB_ibuf.v \ -opencores/aemb/rtl/verilog/aeMB_regf.v \ -opencores/aemb/rtl/verilog/aeMB_xecu.v \ -opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_defines.v \ -opencores/i2c/rtl/verilog/i2c_master_top.v \ -opencores/i2c/rtl/verilog/timescale.v \ -opencores/simple_pic/rtl/simple_pic.v \ -opencores/spi/rtl/verilog/spi_clgen.v \ -opencores/spi/rtl/verilog/spi_defines.v \ -opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ -sdr_lib/acc.v \ -sdr_lib/add2.v \ -sdr_lib/add2_and_round.v \ -sdr_lib/add2_and_round_reg.v \ -sdr_lib/add2_reg.v \ -sdr_lib/cic_dec_shifter.v \ -sdr_lib/cic_decim.v \ -sdr_lib/cic_int_shifter.v \ -sdr_lib/cic_interp.v \ -sdr_lib/cic_strober.v \ -sdr_lib/clip.v \ -sdr_lib/clip_reg.v \ -sdr_lib/cordic.v \ -sdr_lib/cordic_z24.v \ -sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_rx.v \ -sdr_lib/dsp_core_tx.v \ -sdr_lib/hb_dec.v \ -sdr_lib/hb_interp.v \ -sdr_lib/round.v \ -sdr_lib/round_reg.v \ -sdr_lib/rx_control.v \ -sdr_lib/rx_dcoffset.v \ -sdr_lib/sign_extend.v \ -sdr_lib/small_hb_dec.v \ -sdr_lib/small_hb_int.v \ -sdr_lib/tx_control.v \ -serdes/serdes.v \ -serdes/serdes_fc_rx.v \ -serdes/serdes_fc_tx.v \ -serdes/serdes_rx.v \ -serdes/serdes_tx.v \ -timing/time_receiver.v \ -timing/time_sender.v \ -timing/time_sync.v \ -timing/timer.v \ -top/u2_core/u2_core.v \ -top/safe_u1e/safe_u1e.ucf \ -top/safe_u1e/safe_u1e.v - -################################################## -# Process Properties -################################################## -export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -export TRANSLATE_PROPERTIES := \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -export MAP_PROPERTIES := \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -export PLACE_ROUTE_PROPERTIES := \ -"Place & Route Effort Level (Overall)" High - -export STATIC_TIMING_PROPERTIES := \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -export GEN_PROG_FILE_PROPERTIES := \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 \ -"Unused IOB Pins" "Pull Up" - -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -clean: - rm -rf $(BUILD_DIR) - - diff --git a/usrp2/top/safe_u1e/safe_u1e.ucf b/usrp2/top/safe_u1e/safe_u1e.ucf deleted file mode 100644 index cb6d6372e..000000000 --- a/usrp2/top/safe_u1e/safe_u1e.ucf +++ /dev/null @@ -1,262 +0,0 @@ - -NET "CLK_FPGA_P" LOC = "Y11" ; -NET "CLK_FPGA_N" LOC = "Y10" ; - -## GPMC -NET "EM_CLK" LOC = "F11" ; - -NET "EM_D<15>" LOC = "D13" ; -NET "EM_D<14>" LOC = "D15" ; -NET "EM_D<13>" LOC = "C16" ; -NET "EM_D<12>" LOC = "B20" ; -NET "EM_D<11>" LOC = "A19" ; -NET "EM_D<10>" LOC = "A17" ; -NET "EM_D<9>" LOC = "E15" ; -NET "EM_D<8>" LOC = "F15" ; -NET "EM_D<7>" LOC = "E16" ; -NET "EM_D<6>" LOC = "F16" ; -NET "EM_D<5>" LOC = "B17" ; -NET "EM_D<4>" LOC = "C17" ; -NET "EM_D<3>" LOC = "B19" ; -NET "EM_D<2>" LOC = "D19" ; -NET "EM_D<1>" LOC = "C19" ; -NET "EM_D<0>" LOC = "A20" ; - -NET "EM_A<10>" LOC = "C14" ; -NET "EM_A<9>" LOC = "C10" ; -NET "EM_A<8>" LOC = "C5" ; -NET "EM_A<7>" LOC = "A18" ; -NET "EM_A<6>" LOC = "A15" ; -NET "EM_A<5>" LOC = "A12" ; -NET "EM_A<4>" LOC = "A10" ; -NET "EM_A<3>" LOC = "E7" ; -NET "EM_A<2>" LOC = "A7" ; -NET "EM_A<1>" LOC = "C15" ; - -#NET "EM_NCS6" LOC = "E17" ; -#NET "EM_NCS5" LOC = "E10" ; -NET "EM_NCS4" LOC = "E6" ; -#NET "EM_NCS1" LOC = "D18" ; -#NET "EM_NCS0" LOC = "D17" ; - -NET "EM_WAIT0" LOC = "F14" ; -#NET "EM_NBE1" LOC = "D14" ; -#NET "EM_NBE0" LOC = "A13" ; -NET "EM_NWP" LOC = "F13" ; -NET "EM_NWE" LOC = "B13" ; -NET "EM_NOE" LOC = "A14" ; -NET "EM_NADV_ALE" LOC = "B15" ; - - -## Overo GPIO -#NET "overo_gpio0" LOC = "F9" ; -#NET "overo_gpio14" LOC = "C4" ; -#NET "overo_gpio21" LOC = "D5" ; -#NET "overo_gpio22" LOC = "A3" ; -#NET "overo_gpio23" LOC = "B3" ; -#NET "overo_gpio64" LOC = "A4" ; -#NET "overo_gpio65" LOC = "F8" ; -#NET "overo_gpio127" LOC = "C8" ; -#NET "overo_gpio128" LOC = "G8" ; -#NET "overo_gpio144" LOC = "A5" ; -#NET "overo_gpio145" LOC = "C7" ; -#NET "overo_gpio146" LOC = "A6" ; -#NET "overo_gpio147" LOC = "B6" ; -#NET "overo_gpio163" LOC = "D7" ; -#NET "overo_gpio170" LOC = "E8" ; -#NET "overo_gpio176" LOC = "B4" ; - -## Overo UART -#NET "overo_txd1" LOC = "C6" ; -#NET "overo_rxd1" LOC = "D6" ; - -#NET "FPGA_TXD" LOC = "U1" ; -#NET "FPGA_RXD" LOC = "T6" ; - -#NET "SYSEN" LOC = "C11" ; - -#NET "db_scl" LOC = "U4" ; -#NET "db_sda" LOC = "U5" ; -#NET "db_sclk_rx" LOC = "W3" ; -#NET "db_miso_rx" LOC = "W2" ; -#NET "db_mosi_rx" LOC = "V4" ; -#NET "db_sen_rx" LOC = "V3" ; -#NET "db_sclk_tx" LOC = "Y1" ; -#NET "db_miso_tx" LOC = "W1" ; -#NET "db_mosi_tx" LOC = "R3" ; -#NET "db_sen_tx" LOC = "T4" ; - -## Clock Gen -#NET "cgen_miso" LOC = "U2" ; -#NET "cgen_mosi" LOC = "V1" ; -#NET "cgen_sclk" LOC = "R5" ; -#NET "cgen_sen_b" LOC = "T1" ; -#NET "cgen_st_status" LOC = "D4" ; -#NET "cgen_st_ld" LOC = "D1" ; -#NET "cgen_st_refmon" LOC = "E1" ; -#NET "cgen_sync_b" LOC = "M1" ; -#NET "cgen_ref_sel" LOC = "J1" ; - -## Debug pins -NET "debug_led<2>" LOC = "T5" ; -NET "debug_led<1>" LOC = "R2" ; -NET "debug_led<0>" LOC = "R1" ; -NET "debug<0>" LOC = "P6" ; -NET "debug<1>" LOC = "R6" ; -NET "debug<2>" LOC = "P1" ; -NET "debug<3>" LOC = "P2" ; -NET "debug<4>" LOC = "N6" ; -NET "debug<5>" LOC = "N5" ; -NET "debug<6>" LOC = "N1" ; -NET "debug<7>" LOC = "K2" ; -NET "debug<8>" LOC = "K3" ; -NET "debug<9>" LOC = "K6" ; -NET "debug<10>" LOC = "L5" ; -NET "debug<11>" LOC = "H2" ; -NET "debug<12>" LOC = "K4" ; -NET "debug<13>" LOC = "K5" ; -NET "debug<14>" LOC = "G1" ; -NET "debug<15>" LOC = "H1" ; -NET "debug<16>" LOC = "H5" ; -NET "debug<17>" LOC = "H6" ; -NET "debug<18>" LOC = "E3" ; -NET "debug<19>" LOC = "E4" ; -NET "debug<20>" LOC = "G5" ; -NET "debug<21>" LOC = "G6" ; -NET "debug<22>" LOC = "F2" ; -NET "debug<23>" LOC = "F1" ; -NET "debug<24>" LOC = "H3" ; -NET "debug<25>" LOC = "H4" ; -NET "debug<26>" LOC = "F4" ; -NET "debug<27>" LOC = "F5" ; -NET "debug<28>" LOC = "C2" ; -NET "debug<29>" LOC = "C1" ; -NET "debug<30>" LOC = "F3" ; -NET "debug<31>" LOC = "G3" ; -NET "debug_clk<0>" LOC = "L6" ; -NET "debug_clk<1>" LOC = "M5" ; - -#NET "debug_pb<2>" LOC = "Y2" ; -#NET "debug_pb<1>" LOC = "AA1" ; -#NET "debug_pb<0>" LOC = "N3" ; - -#NET "dip_sw<7>" LOC = "T3" ; -#NET "dip_sw<6>" LOC = "U3" ; -#NET "dip_sw<5>" LOC = "M3" ; -#NET "dip_sw<4>" LOC = "N4" ; -#NET "dip_sw<3>" LOC = "J3" ; -#NET "dip_sw<2>" LOC = "J4" ; -#NET "dip_sw<1>" LOC = "J6" ; -#NET "dip_sw<0>" LOC = "J7" ; - -## AD9862 Interface -#NET "aux_sdi_codec" LOC = "F19" ; -#NET "aux_sdo_codec" LOC = "F18" ; -#NET "aux_sclk_codec" LOC = "D21" ; -#NET "reset_codec" LOC = "D22" ; -#NET "sen_codec" LOC = "D20" ; -#NET "mosi_codec" LOC = "E19" ; -#NET "miso_codec" LOC = "F21" ; -#NET "sclk_codec" LOC = "E20" ; - -#NET "RXSYNC" LOC = "F22" ; - -#NET "DB<11>" LOC = "E22" ; -#NET "DB<10>" LOC = "J19" ; -#NET "DB<9>" LOC = "H20" ; -#NET "DB<8>" LOC = "G19" ; -#NET "DB<7>" LOC = "F20" ; -#NET "DB<6>" LOC = "K16" ; -#NET "DB<5>" LOC = "J17" ; -#NET "DB<4>" LOC = "H22" ; -#NET "DB<3>" LOC = "G22" ; -#NET "DB<2>" LOC = "H17" ; -#NET "DB<1>" LOC = "H18" ; -#NET "DB<0>" LOC = "K20" ; -#NET "DA<11>" LOC = "J20" ; -#NET "DA<10>" LOC = "K19" ; -#NET "DA<9>" LOC = "K18" ; -#NET "DA<8>" LOC = "L22" ; -#NET "DA<7>" LOC = "K22" ; -#NET "DA<6>" LOC = "N22" ; -#NET "DA<5>" LOC = "M22" ; -#NET "DA<4>" LOC = "N20" ; -#NET "DA<3>" LOC = "N19" ; -#NET "DA<2>" LOC = "R22" ; -#NET "DA<1>" LOC = "P22" ; -#NET "DA<0>" LOC = "N17" ; - -#NET "TX<13>" LOC = "P19" ; -#NET "TX<12>" LOC = "R18" ; -#NET "TX<11>" LOC = "U20" ; -#NET "TX<10>" LOC = "T20" ; -#NET "TX<9>" LOC = "R19" ; -#NET "TX<8>" LOC = "R20" ; -#NET "TX<7>" LOC = "W22" ; -#NET "TX<6>" LOC = "Y22" ; -#NET "TX<5>" LOC = "T18" ; -#NET "TX<4>" LOC = "T17" ; -#NET "TX<3>" LOC = "W19" ; -#NET "TX<2>" LOC = "V20" ; -#NET "TX<1>" LOC = "Y21" ; -#NET "TX<0>" LOC = "AA22" ; -#NET "TXSYNC" LOC = "U18" ; -#NET "TXBLANK" LOC = "U19" ; - -#NET "PPS_IN" LOC = "M17" ; - -#NET "io_tx<0>" LOC = "AB20" ; -#NET "io_tx<1>" LOC = "Y17" ; -#NET "io_tx<2>" LOC = "Y16" ; -#NET "io_tx<3>" LOC = "U16" ; -#NET "io_tx<4>" LOC = "V16" ; -#NET "io_tx<5>" LOC = "AB19" ; -#NET "io_tx<6>" LOC = "AA19" ; -#NET "io_tx<7>" LOC = "U14" ; -#NET "io_tx<8>" LOC = "U15" ; -#NET "io_tx<9>" LOC = "AB17" ; -#NET "io_tx<10>" LOC = "AB18" ; -#NET "io_tx<11>" LOC = "Y13" ; -#NET "io_tx<12>" LOC = "W14" ; -#NET "io_tx<13>" LOC = "U13" ; -#NET "io_tx<14>" LOC = "AA15" ; -#NET "io_tx<15>" LOC = "AB14" ; - -#NET "io_rx<0>" LOC = "Y8" ; -#NET "io_rx<1>" LOC = "Y9" ; -#NET "io_rx<2>" LOC = "V7" ; -#NET "io_rx<3>" LOC = "U8" ; -#NET "io_rx<4>" LOC = "V10" ; -#NET "io_rx<5>" LOC = "U9" ; -#NET "io_rx<6>" LOC = "AB7" ; -#NET "io_rx<7>" LOC = "AA8" ; -#NET "io_rx<8>" LOC = "W8" ; -#NET "io_rx<9>" LOC = "V8" ; -#NET "io_rx<10>" LOC = "AB5" ; -#NET "io_rx<11>" LOC = "AB6" ; -#NET "io_rx<12>" LOC = "AB4" ; -#NET "io_rx<13>" LOC = "AA4" ; -#NET "io_rx<14>" LOC = "W5" ; -#NET "io_rx<15>" LOC = "Y4" ; - -#NET "CLKOUT2_CODEC" LOC = "U12" ; -#NET "CLKOUT1_CODEC" LOC = "V12" ; - -## FPGA Config Pins -#NET "fpga_cfg_prog_b" LOC = "A2" ; -#NET "fpga_cfg_done" LOC = "AB21" ; -#NET "fpga_cfg_din" LOC = "W17" ; -#NET "fpga_cfg_cclk" LOC = "V17" ; -#NET "fpga_cfg_init_b" LOC = "W15" ; - -## Unnamed, need to figure out what they do -#NET "unnamed_net37" LOC = "B1" ; -#NET "unnamed_net36" LOC = "B22" ; -#NET "unnamed_net35" LOC = "D2" ; -#NET "unnamed_net34" LOC = "A21" ; -#NET "unnamed_net45" LOC = "F7" ; -#NET "unnamed_net44" LOC = "V6" ; -#NET "unnamed_net43" LOC = "AA3" ; -#NET "unnamed_net42" LOC = "AB3" ; - -#NET "GND" LOC = "V19" ; diff --git a/usrp2/top/safe_u1e/safe_u1e.v b/usrp2/top/safe_u1e/safe_u1e.v deleted file mode 100644 index dee9c6067..000000000 --- a/usrp2/top/safe_u1e/safe_u1e.v +++ /dev/null @@ -1,41 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module safe_u1e - ( - input CLK_FPGA_P, input CLK_FPGA_N, // Diff - output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - - // GPMC - input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, - input EM_WAIT0, input EM_NCS4, input EM_NWP, input EM_NWE, input EM_NOE, input EM_NADV_ALE - ); - - // FPGA-specific pins connections - wire clk_fpga; - - IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) - clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - - // Debug circuitry - reg [31:0] ctr; - always @(posedge clk_fpga) - ctr <= ctr + 1; - - - assign debug_led = ctr[27:25]; - assign debug_clk = { EM_CLK, clk_fpga }; - assign debug = { { EM_WAIT0, EM_NADV_ALE, EM_NWP, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, - { EM_D } }; - - wire EM_output_enable = (~EM_NOE & ~EM_NCS4); - wire [15:0] EM_D_out; - - assign EM_D = EM_output_enable ? EM_D_out : 16'bz; - - ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port - (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_out), - .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob()); - - -endmodule // safe_u2plus diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index a73ebceb8..2caa46639 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -54,7 +54,7 @@ NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug -NET "overo_gpio127" LOC = "C8" ; # MISC GPIO for debug +NET "overo_gpio127" LOC = "C8" ; # MISC GPIO for debug, also used on the passthru image as the cgen_sen_b pin NET "overo_gpio128" LOC = "G8" ; # MISC GPIO for debug NET "overo_gpio144" LOC = "A5" ; # tx_have_space NET "overo_gpio145" LOC = "C7" ; # tx_underrun diff --git a/usrp2/top/u1e_passthru/.gitignore b/usrp2/top/u1e_passthru/.gitignore new file mode 100644 index 000000000..1b2211df0 --- /dev/null +++ b/usrp2/top/u1e_passthru/.gitignore @@ -0,0 +1 @@ +build* diff --git a/usrp2/top/u1e_passthru/passthru.ucf b/usrp2/top/u1e_passthru/passthru.ucf index 1672132a2..3ffe33882 100644 --- a/usrp2/top/u1e_passthru/passthru.ucf +++ b/usrp2/top/u1e_passthru/passthru.ucf @@ -47,14 +47,14 @@ ##NET "EM_NWP" LOC = "F13" ; ## Overo GPIO -NET "overo_gpio0" LOC = "F9" ; # MISC GPIO for debug +#NET "overo_gpio0" LOC = "F9" ; # MISC GPIO for debug #NET "overo_gpio14" LOC = "C4" ; # MISC GPIO for debug #NET "overo_gpio21" LOC = "D5" ; # MISC GPIO for debug #NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug #NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug #NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug #NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug -#NET "overo_gpio127" LOC = "C8" ; # MISC GPIO for debug +NET "overo_gpio127" LOC = "C8" ; # passed through as cgen_sen_b #NET "overo_gpio128" LOC = "G8" ; # MISC GPIO for debug #NET "overo_gpio144" LOC = "A5" ; # tx_have_space #NET "overo_gpio145" LOC = "C7" ; # tx_underrun diff --git a/usrp2/top/u1e_passthru/passthru.v b/usrp2/top/u1e_passthru/passthru.v index 459c226ee..d846f2cf6 100644 --- a/usrp2/top/u1e_passthru/passthru.v +++ b/usrp2/top/u1e_passthru/passthru.v @@ -2,16 +2,16 @@ ////////////////////////////////////////////////////////////////////////////////// module passthru - (input overo_gpio0, - output cgen_sclk, - output cgen_sen_b, - output cgen_mosi, + (input overo_gpio127, + output cgen_sclk, + output cgen_sen_b, + output cgen_mosi, input fpga_cfg_din, input fpga_cfg_cclk ); assign cgen_sclk = fpga_cfg_cclk; - assign cgen_sen_b = overo_gpio0; + assign cgen_sen_b = overo_gpio127; assign cgen_mosi = fpga_cfg_din; -- cgit v1.2.3 From 019be7444989b977de9e94677bc259bad9eb6843 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Mon, 10 May 2010 21:43:43 -0400 Subject: Add program to do initial configuration of the clkgen chip. --- host/apps/omap_debug/Makefile | 5 +- host/apps/omap_debug/clkgen-config.cc | 294 ++++++++++++++++++++++++++++++++++ 2 files changed, 298 insertions(+), 1 deletion(-) create mode 100644 host/apps/omap_debug/clkgen-config.cc diff --git a/host/apps/omap_debug/Makefile b/host/apps/omap_debug/Makefile index 9b590b9f7..e2aa384f2 100644 --- a/host/apps/omap_debug/Makefile +++ b/host/apps/omap_debug/Makefile @@ -1,6 +1,6 @@ CFLAGS=-Wall -I../../lib/usrp/usrp_e/ -all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio usrp-e-debug-pins usrp-e-rw-random usrp-e-fpga-rw usrp-e-lb-test usrp-e-crc-rw +all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio usrp-e-debug-pins usrp-e-rw-random usrp-e-fpga-rw usrp-e-lb-test usrp-e-crc-rw clkgen-config usrp-e-spi : usrp-e-spi.c @@ -30,6 +30,8 @@ usrp-e-button : usrp-e-button.c fpga-downloader : fpga-downloader.cc +clkgen-config : clkgen-config.cc + usrp-e-gpio : usrp-e-gpio.c usrp-e-lb-test : usrp-e-lb-test.c @@ -51,3 +53,4 @@ clean : rm -f usrp-e-debug-pins rm -f usrp-e-lb-test rm -f usrp-e-crc-rw + rm -f clkgen-config diff --git a/host/apps/omap_debug/clkgen-config.cc b/host/apps/omap_debug/clkgen-config.cc new file mode 100644 index 000000000..c21f54a60 --- /dev/null +++ b/host/apps/omap_debug/clkgen-config.cc @@ -0,0 +1,294 @@ +/* -*- c++ -*- */ +/* + * Copyright 2003,2004,2008,2009 Free Software Foundation, Inc. + * + * This file is part of UHD + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. +*/ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + + +// Programming data for clock gen chip +static const unsigned int config_data[] = { + 0x000024, + 0x023201, + 0x000081, + 0x000400, + 0x00104c, + 0x001101, + 0x001200, + 0x001300, + 0x001414, + 0x001500, + 0x001604, + 0x001704, + 0x001807, + 0x001900, + 0x001a32, + 0x001b12, + 0x001c44, + 0x001d00, + 0x001e00, + 0x00f062, + 0x00f162, + 0x00f262, + 0x00f362, + 0x00f462, + 0x00f562, + 0x00f662, + 0x00f762, + 0x00f862, + 0x00f962, + 0x00fa62, + 0x00fb62, + 0x00fc00, + 0x00fd00, + 0x019021, + 0x019100, + 0x019200, + 0x019333, + 0x019400, + 0x019500, + 0x019611, + 0x019700, + 0x019800, + 0x019900, + 0x019a00, + 0x019b00, + 0x01e003, + 0x01e102, + 0x023000, + 0x023201, + 0x0b0201, + 0x0b0300, + 0x001fff, + 0x0a0000, + 0x0a0100, + 0x0a0200, + 0x0a0302, + 0x0a0400, + 0x0a0504, + 0x0a060e, + 0x0a0700, + 0x0a0810, + 0x0a090e, + 0x0a0a00, + 0x0a0bf0, + 0x0a0c0b, + 0x0a0d01, + 0x0a0e90, + 0x0a0f01, + 0x0a1001, + 0x0a11e0, + 0x0a1201, + 0x0a1302, + 0x0a1430, + 0x0a1580, + 0x0a16ff, + 0x023201, + 0x0b0301, + 0x023201, +}; + + +const unsigned int CLKGEN_SELECT = 145; + + +enum gpio_direction {IN, OUT}; + +class gpio { + public: + + gpio(unsigned int gpio_num, gpio_direction pin_direction, bool close_action); + ~gpio(); + + bool get_value(); + void set_value(bool state); + + private: + + unsigned int gpio_num; + + std::stringstream base_path; + std::fstream value_file; + std::fstream direction_file; + bool close_action; // True set to input and release, false do nothing +}; + +class spidev { + public: + + spidev(std::string dev_name); + ~spidev(); + + void send(char *wbuf, char *rbuf, unsigned int nbytes); + + private: + + int fd; + +}; + +gpio::gpio(unsigned int _gpio_num, gpio_direction pin_direction, bool close_action) +{ + std::fstream export_file; + + gpio_num = _gpio_num; + + export_file.open("/sys/class/gpio/export", std::ios::out); + if (!export_file.is_open()) ///\todo Poor error handling + std::cout << "Failed to open gpio export file." << std::endl; + + export_file << gpio_num << std::endl; + + base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush; + + std::string direction_file_name; + + direction_file_name = base_path.str() + "/direction"; + + direction_file.open(direction_file_name.c_str()); + if (!direction_file.is_open()) + std::cout << "Failed to open direction file." << std::endl; + if (pin_direction == OUT) + direction_file << "out" << std::endl; + else + direction_file << "in" << std::endl; + + std::string value_file_name; + + value_file_name = base_path.str() + "/value"; + + value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out); + if (!value_file.is_open()) + std::cout << "Failed to open value file." << std::endl; +} + +bool gpio::get_value() +{ + + std::string val; + + std::getline(value_file, val); + value_file.seekg(0); + + if (val == "0") + return false; + else if (val == "1") + return true; + else + std::cout << "Data read from value file|" << val << "|" << std::endl; + + return false; +} + +void gpio::set_value(bool state) +{ + + if (state) + value_file << "1" << std::endl; + else + value_file << "0" << std::endl; +} + +gpio::~gpio() +{ + if (close_action) { + std::fstream unexport_file; + + direction_file << "in" << std::endl; + + unexport_file.open("/sys/class/gpio/unexport", std::ios::out); + if (!unexport_file.is_open()) ///\todo Poor error handling + std::cout << "Failed to open gpio export file." << std::endl; + + unexport_file << gpio_num << std::endl; + + } + +} + +spidev::spidev(std::string fname) +{ + int ret; + int mode = 0; + int speed = 12000000; + int bits = 32; + + fd = open(fname.c_str(), O_RDWR); + + ret = ioctl(fd, SPI_IOC_WR_MODE, &mode); + ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed); + ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits); +} + + +spidev::~spidev() +{ + close(fd); +} + +void spidev::send(char *buf, char *rbuf, unsigned int nbytes) +{ + int ret; + + struct spi_ioc_transfer tr; + tr.tx_buf = (unsigned long) buf; + tr.rx_buf = (unsigned long) rbuf; + tr.len = nbytes; + tr.delay_usecs = 0; + tr.speed_hz = 12000000; + tr.bits_per_word = 32; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + +} + +static void send_config_to_clkgen(gpio &chip_select, const unsigned int data[], unsigned int data_size) +{ + spidev spi("/dev/spidev1.0"); + unsigned int rbuf; + + for (unsigned int i = 0; i < data_size; i++) { + + chip_select.set_value(1); + spi.send((char *)&data[i], (char *)&rbuf, 4); + chip_select.set_value(0); + + }; +} + +int main(int argc, char *argv[]) +{ + + gpio clkgen_select(CLKGEN_SELECT, OUT, true); + + send_config_to_clkgen(clkgen_select, config_data, sizeof(config_data)/sizeof(unsigned int)); +} + -- cgit v1.2.3 From 9251c115b302b7b5773e2e16bbd7a7dfd6c18b74 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 12 May 2010 14:11:10 -0400 Subject: Add calculation for data trasnfer rates. --- host/apps/omap_debug/usrp-e-crc-rw.c | 46 +++++++++++++++++++++++++++++++++--- 1 file changed, 43 insertions(+), 3 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-crc-rw.c b/host/apps/omap_debug/usrp-e-crc-rw.c index 1f23c8d54..f99654781 100644 --- a/host/apps/omap_debug/usrp-e-crc-rw.c +++ b/host/apps/omap_debug/usrp-e-crc-rw.c @@ -44,6 +44,8 @@ static void *read_thread(void *threadid) int i; unsigned long crc; unsigned int rx_crc; + unsigned long bytes_transfered, elapsed_seconds; + struct timeval start_time, finish_time; printf("Greetings from the reading thread!\n"); @@ -51,7 +53,10 @@ static void *read_thread(void *threadid) rx_data = malloc(2048); rx_pkt_cnt = 0; - + + bytes_transfered = 0; + gettimeofday(&start_time, NULL); + while (1) { cnt = read(fp, rx_data, 2048); @@ -81,7 +86,20 @@ static void *read_thread(void *threadid) printf("CRC Error, sent: %d, rx: %d\n", rx_crc, (crc & 0xFFFFFFFF)); } - + + bytes_transfered += rx_data->len; + + if (bytes_transfered > (100 * 1000000)) { + gettimeofday(&finish_time, NULL); + elapsed_seconds = start_time.tv_sec - finish_time.tv_sec; + + printf("RX data transfer rate = %f K Bps\n", + (float) bytes_transfered / (float) elapsed_seconds / 1000); + + + start_time = finish_time; + bytes_transfered = 0; + } } } @@ -91,12 +109,16 @@ static void *write_thread(void *threadid) int tx_len; unsigned long crc; struct usrp_transfer_frame *tx_data; - struct pkt *p; + unsigned long bytes_transfered, elapsed_seconds; + struct timeval start_time, finish_time; printf("Greetings from the write thread!\n"); tx_data = malloc(2048); + bytes_transfered = 0; + gettimeofday(&start_time, NULL); + while (1) { tx_pkt_cnt++; @@ -115,6 +137,8 @@ static void *write_thread(void *threadid) } tx_len = 2048 - sizeof(struct usrp_transfer_frame) - sizeof(int); + tx_data->len = tx_len + sizeof(int); + crc = 0xFFFFFFFF; for (i = 0; i < tx_len; i++) { tx_data->buf[i] = rand() & 0xFF; @@ -128,6 +152,22 @@ static void *write_thread(void *threadid) cnt = write(fp, tx_data, 2048); if (cnt < 0) printf("Error returned from write: %d\n", cnt); + + + bytes_transfered += tx_data->len; + + if (bytes_transfered > (100 * 1000000)) { + gettimeofday(&finish_time, NULL); + elapsed_seconds = start_time.tv_sec - finish_time.tv_sec; + + printf("TX data transfer rate = %f K Bps\n", + (float) bytes_transfered / (float) elapsed_seconds / 1000); + + + start_time = finish_time; + bytes_transfered = 0; + } + // sleep(1); } } -- cgit v1.2.3 From 247e36dcbace9ef06763c2c537b44c8225a9d6a7 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 12 May 2010 16:12:00 -0700 Subject: packet generator and verifier, to test gpmc and other data transfer stuff --- usrp2/control_lib/newfifo/.gitignore | 2 + usrp2/control_lib/newfifo/packet_generator.v | 59 ++++++++++++++++++++++++++ usrp2/control_lib/newfifo/packet_tb.v | 29 +++++++++++++ usrp2/control_lib/newfifo/packet_verifier.v | 63 ++++++++++++++++++++++++++++ 4 files changed, 153 insertions(+) create mode 100644 usrp2/control_lib/newfifo/packet_generator.v create mode 100644 usrp2/control_lib/newfifo/packet_tb.v create mode 100644 usrp2/control_lib/newfifo/packet_verifier.v diff --git a/usrp2/control_lib/newfifo/.gitignore b/usrp2/control_lib/newfifo/.gitignore index cba7efc8e..866f1faad 100644 --- a/usrp2/control_lib/newfifo/.gitignore +++ b/usrp2/control_lib/newfifo/.gitignore @@ -1 +1,3 @@ +*.vcd +*.lxt a.out diff --git a/usrp2/control_lib/newfifo/packet_generator.v b/usrp2/control_lib/newfifo/packet_generator.v new file mode 100644 index 000000000..e5bfe5b26 --- /dev/null +++ b/usrp2/control_lib/newfifo/packet_generator.v @@ -0,0 +1,59 @@ + + +module packet_generator + (input clk, input reset, input clear, + output reg [7:0] data_o, output sof_o, output eof_o, + output src_rdy_o, input dst_rdy_i); + + localparam len = 32'd100; + + reg [31:0] state; + reg [31:0] seq; + wire [31:0] crc_out; + wire calc_crc = src_rdy_o & dst_rdy_i & ~(state[31:2] == 30'h3FFF_FFFF); + + + always @(posedge clk) + if(reset | clear) + seq <= 0; + else + if(eof_o & src_rdy_o & dst_rdy_i) + seq <= seq + 1; + + always @(posedge clk) + if(reset | clear) + state <= 0; + else + if(src_rdy_o & dst_rdy_i) + if(state == (len - 1)) + state <= 32'hFFFF_FFFC; + else + state <= state + 1; + + always @* + case(state) + 0 : data_o <= len[7:0]; + 1 : data_o <= len[15:8]; + 2 : data_o <= len[23:16]; + 3 : data_o <= len[31:24]; + 4 : data_o <= seq[7:0]; + 5 : data_o <= seq[15:8]; + 6 : data_o <= seq[23:16]; + 7 : data_o <= seq[31:24]; + 32'hFFFF_FFFC : data_o <= crc_out[31:24]; + 32'hFFFF_FFFD : data_o <= crc_out[23:16]; + 32'hFFFF_FFFE : data_o <= crc_out[15:8]; + 32'hFFFF_FFFF : data_o <= crc_out[7:0]; + default : data_o <= state[7:0]; + endcase // case (state) + + assign src_rdy_o = 1; + assign sof_o = (state == 0); + assign eof_o = (state == 32'hFFFF_FFFF); + + wire clear_crc = eof_o & src_rdy_o & dst_rdy_i; + + crc crc(.clk(clk), .reset(reset), .clear(clear_crc), .data(data_o), + .calc(calc_crc), .crc_out(crc_out), .match()); + +endmodule // packet_generator diff --git a/usrp2/control_lib/newfifo/packet_tb.v b/usrp2/control_lib/newfifo/packet_tb.v new file mode 100644 index 000000000..3c423d2ba --- /dev/null +++ b/usrp2/control_lib/newfifo/packet_tb.v @@ -0,0 +1,29 @@ + + +module packet_tb(); + + wire [7:0] data; + wire sof, eof, src_rdy, dst_rdy; + + wire clear = 0; + reg clk = 0; + reg reset = 1; + + always #10 clk <= ~clk; + initial #1000 reset <= 0; + + initial $dumpfile("packet_tb.vcd"); + initial $dumpvars(0,packet_tb); + + wire [31:0] total, crc_err, seq_err, len_err; + + packet_generator pkt_gen (.clk(clk), .reset(reset), .clear(clear), + .data_o(data), .sof_o(sof), .eof_o(eof), + .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); + + packet_verifier pkt_ver (.clk(clk), .reset(reset), .clear(clear), + .data_i(data), .sof_i(sof), .eof_i(eof), + .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + +endmodule // packet_tb diff --git a/usrp2/control_lib/newfifo/packet_verifier.v b/usrp2/control_lib/newfifo/packet_verifier.v new file mode 100644 index 000000000..22c924198 --- /dev/null +++ b/usrp2/control_lib/newfifo/packet_verifier.v @@ -0,0 +1,63 @@ + + +// Packet format -- +// Line 1 -- Length, 32 bits +// Line 2 -- Sequence number, 32 bits +// Last line -- CRC, 32 bits + +module packet_verifier + (input clk, input reset, input clear, + input [7:0] data_i, input sof_i, output eof_i, input src_rdy_i, output dst_rdy_o, + + output reg [31:0] total, + output reg [31:0] crc_err, + output reg [31:0] seq_err, + output reg [31:0] len_err); + + assign dst_rdy_o = ~last_byte_d1; + + reg [31:0] seq_num; + reg [31:0] length; + + wire calc_crc = src_rdy_i & dst_rdy_o; + + crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i), + .calc(calc_crc), .crc_out(), .match(match_crc)); + + wire first_byte, last_byte; + reg second_byte, last_byte_d1; + + assign first_byte = src_rdy_i & dst_rdy_o & sof_i; + assign last_byte = src_rdy_i & dst_rdy_o & eof_i; + + // stubs for now + wire match_seq = 1; + wire match_len = 1; + + always @(posedge clk) + if(reset | clear) + last_byte_d1 <= 0; + else + last_byte_d1 <= last_byte; + + always @(posedge clk) + if(reset | clear) + begin + total <= 0; + crc_err <= 0; + seq_err <= 0; + len_err <= 0; + end + else + if(last_byte_d1) + begin + total <= total + 1; + if(~match_crc) + crc_err <= crc_err + 1; + else if(~match_seq) + seq_err <= seq_err + 1; + else if(~match_len) + seq_err <= len_err + 1; + end + +endmodule // packet_verifier -- cgit v1.2.3 From ed48630974fb8cbdc3b863b13d4e7d7e8fe31434 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 12 May 2010 16:16:18 -0700 Subject: add missing signal from sensitivity list --- usrp2/control_lib/nsgpio16LE.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/control_lib/nsgpio16LE.v b/usrp2/control_lib/nsgpio16LE.v index d6d7dcf56..514b003ce 100644 --- a/usrp2/control_lib/nsgpio16LE.v +++ b/usrp2/control_lib/nsgpio16LE.v @@ -111,7 +111,7 @@ module nsgpio16LE integer n; reg [31:0] igpio; // temporary internal signal - always @(ctrl or line or debug_1 or debug_0 or atr) + always @(ctrl or line or debug_1 or debug_0 or atr or ddr) for(n=0;n<32;n=n+1) igpio[n] <= ddr[n] ? (dbg[n] ? (ctrl[n] ? debug_1[n] : debug_0[n]) : (ctrl[n] ? atr[n] : line[n]) ) -- cgit v1.2.3 From b04a1beaab300000ce2d8a5814bd2e37af48286c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 12 May 2010 18:51:33 -0700 Subject: moved fifos into gpmc_async, reorganized top level a bit, added in crc packet gen and test --- usrp2/control_lib/newfifo/packet_generator32.v | 21 ++++++ usrp2/control_lib/newfifo/packet_verifier.v | 10 ++- usrp2/control_lib/newfifo/packet_verifier32.v | 23 +++++++ usrp2/gpmc/gpmc_async.v | 91 +++++++++++++++----------- usrp2/top/u1e/Makefile | 4 ++ usrp2/top/u1e/u1e_core.v | 61 ++++++++++------- 6 files changed, 144 insertions(+), 66 deletions(-) create mode 100644 usrp2/control_lib/newfifo/packet_generator32.v create mode 100644 usrp2/control_lib/newfifo/packet_verifier32.v diff --git a/usrp2/control_lib/newfifo/packet_generator32.v b/usrp2/control_lib/newfifo/packet_generator32.v new file mode 100644 index 000000000..6f8004964 --- /dev/null +++ b/usrp2/control_lib/newfifo/packet_generator32.v @@ -0,0 +1,21 @@ + + +module packet_generator32 + (input clk, input reset, input clear, + output [35:0] data_o, output src_rdy_o, input dst_rdy_i); + + wire [7:0] ll_data; + wire ll_sof, ll_eof, ll_src_rdy, ll_dst_rdy_n; + + packet_generator pkt_gen + (.clk(clk), .reset(reset), .clear(clear), + .data_o(ll_data), .sof_o(ll_sof), .eof_o(ll_eof), + .src_rdy_o(ll_src_rdy), .dst_rdy_i(~ll_dst_rdy_n)); + + ll8_to_fifo36 ll8_to_f36 + (.clk(clk), .reset(reset), .clear(clear), + .ll_data(ll_data), .ll_sof_n(~ll_sof), .ll_eof_n(~ll_eof), + .ll_src_rdy_n(~ll_src_rdy), .ll_dst_rdy_n(ll_dst_rdy_n), + .f36_data(data_o), .f36_src_rdy_o(src_rdy_o), .f36_dst_rdy_i(dst_rdy_i)); + +endmodule // packet_generator32 diff --git a/usrp2/control_lib/newfifo/packet_verifier.v b/usrp2/control_lib/newfifo/packet_verifier.v index 22c924198..b49ad1bbb 100644 --- a/usrp2/control_lib/newfifo/packet_verifier.v +++ b/usrp2/control_lib/newfifo/packet_verifier.v @@ -7,28 +7,26 @@ module packet_verifier (input clk, input reset, input clear, - input [7:0] data_i, input sof_i, output eof_i, input src_rdy_i, output dst_rdy_o, + input [7:0] data_i, input sof_i, input eof_i, input src_rdy_i, output dst_rdy_o, output reg [31:0] total, output reg [31:0] crc_err, output reg [31:0] seq_err, output reg [31:0] len_err); - assign dst_rdy_o = ~last_byte_d1; - reg [31:0] seq_num; reg [31:0] length; + wire first_byte, last_byte; + reg second_byte, last_byte_d1; wire calc_crc = src_rdy_i & dst_rdy_o; crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i), .calc(calc_crc), .crc_out(), .match(match_crc)); - wire first_byte, last_byte; - reg second_byte, last_byte_d1; - assign first_byte = src_rdy_i & dst_rdy_o & sof_i; assign last_byte = src_rdy_i & dst_rdy_o & eof_i; + assign dst_rdy_o = ~last_byte_d1; // stubs for now wire match_seq = 1; diff --git a/usrp2/control_lib/newfifo/packet_verifier32.v b/usrp2/control_lib/newfifo/packet_verifier32.v new file mode 100644 index 000000000..065607b6c --- /dev/null +++ b/usrp2/control_lib/newfifo/packet_verifier32.v @@ -0,0 +1,23 @@ + + +module packet_verifier32 + (input clk, input reset, input clear, + input [35:0] data_i, input src_rdy_i, output dst_rdy_o, + output [31:0] total, output [31:0] crc_err, output [31:0] seq_err, output [31:0] len_err); + + wire [7:0] ll_data; + wire ll_sof_n, ll_eof_n, ll_src_rdy_n, ll_dst_rdy; + + fifo36_to_ll8 f36_to_ll8 + (.clk(clk), .reset(reset), .clear(clear), + .f36_data(data_i), .f36_src_rdy_i(src_rdy_i), .f36_dst_rdy_o(dst_rdy_o), + .ll_data(ll_data), .ll_sof_n(ll_sof_n), .ll_eof_n(ll_eof_n), + .ll_src_rdy_n(ll_src_rdy_n), .ll_dst_rdy_n(~ll_dst_rdy)); + + packet_verifier pkt_ver + (.clk(clk), .reset(reset), .clear(clear), + .data_i(ll_data), .sof_i(~ll_sof_n), .eof_i(~ll_eof_n), + .src_rdy_i(~ll_src_rdy_n), .dst_rdy_o(ll_dst_rdy), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + +endmodule // packet_verifier32 diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index dd06478b3..380689c62 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -1,37 +1,38 @@ ////////////////////////////////////////////////////////////////////////////////// module gpmc_async - (// GPMC signals - input arst, - input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, - input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, - - // GPIOs for FIFO signalling - output rx_have_data, output tx_have_space, output reg bus_error, input bus_reset, - - // Wishbone signals - input wb_clk, input wb_rst, - output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, - output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + #(parameter TXFIFOSIZE = 11, parameter RXFIFOSIZE = 11) + (// GPMC signals + input arst, + input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + + // GPIOs for FIFO signalling + output rx_have_data, output tx_have_space, output reg bus_error, input bus_reset, + + // Wishbone signals + input wb_clk, input wb_rst, + output [10:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + + // FIFO interface + input fifo_clk, input fifo_rst, + output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, + input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, + + input [15:0] tx_frame_len, output [15:0] rx_frame_len, + + output [31:0] debug + ); - // FIFO interface - input fifo_clk, input fifo_rst, - output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, - input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, - - input [15:0] tx_frame_len, output [15:0] rx_frame_len, + wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); + wire [15:0] EM_D_fifo; + wire [15:0] EM_D_wb; - output [31:0] debug - ); - - wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); - wire [15:0] EM_D_fifo; - wire [15:0] EM_D_wb; - assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_fifo : EM_D_wb; - - wire bus_error_tx, bus_error_rx; - + + wire bus_error_tx, bus_error_rx; + always @(posedge fifo_clk) if(fifo_rst) bus_error <= 0; @@ -45,9 +46,11 @@ module gpmc_async // //////////////////////////////////////////// // TX Data Path - wire [17:0] tx18_data, tx18b_data; - wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; - wire [15:0] tx_fifo_space; + wire [17:0] tx18_data, tx18b_data; + wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy; + wire [15:0] tx_fifo_space; + wire [35:0] tx36_data; + wire tx36_src_rdy, tx36_dst_rdy; gpmc_to_fifo_async gpmc_to_fifo_async (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), @@ -64,18 +67,30 @@ module gpmc_async fifo19_to_fifo36 f19_to_f36 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), - .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i)); + .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); + fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy), + .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i)); + // //////////////////////////////////////////// // RX Data Path - - wire [17:0] rx18_data, rx18b_data; - wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; - wire [15:0] rx_fifo_space; + wire [17:0] rx18_data, rx18b_data; + wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; + wire [15:0] rx_fifo_space; + wire [35:0] rx36_data; + wire rx36_src_rdy, rx36_dst_rdy; + + fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), + .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); + fifo36_to_fifo18 f18_to_f36 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o), + .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) ); fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo @@ -106,6 +121,6 @@ module gpmc_async .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), .wb_ack_i(wb_ack_i) ); - assign debug = 0; + assign debug = 0; endmodule // gpmc_async diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 2aebb33f9..8622b8480 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -111,6 +111,10 @@ control_lib/newfifo/fifo_cascade.v \ control_lib/newfifo/fifo36_to_ll8.v \ control_lib/newfifo/fifo36_to_fifo18.v \ control_lib/newfifo/fifo19_to_fifo36.v \ +control_lib/newfifo/packet_generator.v \ +control_lib/newfifo/packet_verifier.v \ +control_lib/newfifo/packet_generator32.v \ +control_lib/newfifo/packet_verifier32.v \ control_lib/longfifo.v \ control_lib/shortfifo.v \ control_lib/medfifo.v \ diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index a262184a8..903121832 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -1,4 +1,9 @@ + +//`define LOOPBACK 1 +//`define TIMED 1 +`define CRC 1 + module u1e_core (input clk_fpga, input rst_fpga, output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, @@ -61,47 +66,59 @@ module u1e_core .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), .debug(debug_gpmc)); -/* + +`ifdef LOOPBACK fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo (.clk(wb_clk), .reset(wb_rst), .clear(0), .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); -*/ - wire tx_strobe, rx_strobe, tx_enable, rx_enable; + wire rx_sof = rx_data[32]; + wire rx_eof = rx_data[33]; +`endif // LOOPBACK + +`ifdef TIMED wire [7:0] rate; - wire tx_fifo_rdy, rx_fifo_rdy; - + + // TX side + wire tx_enable; cic_strober tx_strober (.clock(wb_clk), .reset(wb_rst), .enable(tx_enable), - .rate(rate), .strobe_fast(1), .strobe_slow(tx_strobe)); - - fifo_cascade #(.WIDTH(36), .SIZE(11)) tx_fifo - (.clk(wb_clk), .reset(wb_rst), .clear(0), - .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), - .dataout(), .src_rdy_o(tx_fifo_rdy), .dst_rdy_i(tx_strobe)); + .rate(rate), .strobe_fast(1), .strobe_slow(tx_dst_rdy)); - + // RX side + wire rx_enable; reg [15:0] ctr; wire [15:0] rx_pkt_len = 480; wire rx_eof = (ctr == rx_pkt_len); wire rx_sof = (ctr == 0); cic_strober rx_strober (.clock(wb_clk), .reset(wb_rst), .enable(rx_enable), - .rate(rate), .strobe_fast(1), .strobe_slow(rx_strobe)); + .rate(rate), .strobe_fast(1), .strobe_slow(rx_src_rdy)); - fifo_cascade #(.WIDTH(36), .SIZE(11)) rx_fifo - (.clk(wb_clk), .reset(wb_rst), .clear(0), - .datain({2'b00,rx_eof,rx_sof,16'd0,ctr}), .src_rdy_i(rx_strobe), .dst_rdy_o(rx_fifo_rdy), - .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); - always @(posedge wb_clk) if(wb_rst) ctr <= 0; - else if(rx_strobe & rx_fifo_rdy) + else if(rx_dst_rdy & rx_src_rdy) if(ctr == rx_pkt_len) ctr <= 0; else ctr <= ctr + 1; - + + assign rx_data = {2'b00,rx_eof,rx_sof,~ctr,ctr}; +`endif // TIMED + +`ifdef CRC + packet_generator32 pktgen32 + (.clk(wb_clk), .reset(wb_rst), .clear(clear), + .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + + packet_verifier32 pktver32 + (.clk(wb_clk), .reset(wb_rst), .clear(clear), + .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + + wire rx_sof = rx_data[32]; + wire rx_eof = rx_data[33]; +`endif // CRC // ///////////////////////////////////////////////////////////////////////////////////// // Wishbone Intercon, single master @@ -364,8 +381,8 @@ module u1e_core assign debug_gpio_0 = { debug_gpmc }; - assign debug_gpio_1 = { {rx_enable, rx_strobe, rx_fifo_rdy, rx_strobe & ~rx_fifo_rdy}, - {tx_enable, tx_strobe, tx_fifo_rdy, tx_strobe & ~tx_fifo_rdy}, + assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy}, + {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy}, {rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0}, {3'b0, bus_error, misc_gpio[11:0]} }; -- cgit v1.2.3 From 89d6cb12a03153934b68d51e69bfdb3b9af43872 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 13 May 2010 18:25:36 +0000 Subject: Print a . for every packet received. --- host/apps/omap_debug/usrp-e-rw-random.c | 2 ++ host/apps/omap_debug/usrp-e-rw.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/host/apps/omap_debug/usrp-e-rw-random.c b/host/apps/omap_debug/usrp-e-rw-random.c index c6a838067..43f1571cb 100644 --- a/host/apps/omap_debug/usrp-e-rw-random.c +++ b/host/apps/omap_debug/usrp-e-rw-random.c @@ -76,6 +76,8 @@ static void *read_thread(void *threadid) if (calc_checksum(p) != p->checksum) printf("Checksum fail packet = %d, expected = %d\n", calc_checksum(p), p->checksum); + printf("."); + fflush(stdout); // printf("\n"); } diff --git a/host/apps/omap_debug/usrp-e-rw.c b/host/apps/omap_debug/usrp-e-rw.c index edfcea92a..7fba8cd2a 100644 --- a/host/apps/omap_debug/usrp-e-rw.c +++ b/host/apps/omap_debug/usrp-e-rw.c @@ -68,6 +68,9 @@ static void *read_thread(void *threadid) if (calc_checksum(p) != p->checksum) printf("Checksum fail packet = %X, expected = %X\n", calc_checksum(p), p->checksum); + + printf("."); + fflush(stdout); // printf("\n"); } -- cgit v1.2.3 From 41928cd9ff513f1e6d753e02a74db15bda4b1ba8 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 13 May 2010 15:51:28 -0400 Subject: Change to 24 bit transfers. --- host/apps/omap_debug/clkgen-config.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/host/apps/omap_debug/clkgen-config.cc b/host/apps/omap_debug/clkgen-config.cc index c21f54a60..70c63c6e8 100644 --- a/host/apps/omap_debug/clkgen-config.cc +++ b/host/apps/omap_debug/clkgen-config.cc @@ -239,7 +239,7 @@ spidev::spidev(std::string fname) int ret; int mode = 0; int speed = 12000000; - int bits = 32; + int bits = 24; fd = open(fname.c_str(), O_RDWR); @@ -264,7 +264,7 @@ void spidev::send(char *buf, char *rbuf, unsigned int nbytes) tr.len = nbytes; tr.delay_usecs = 0; tr.speed_hz = 12000000; - tr.bits_per_word = 32; + tr.bits_per_word = 24; ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); -- cgit v1.2.3 From d4a75cef3ed64a305b8c4ef3001ed34c9d47d287 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 13 May 2010 17:46:53 -0400 Subject: Connect enable to the correct gpio. --- host/apps/omap_debug/clkgen-config.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/host/apps/omap_debug/clkgen-config.cc b/host/apps/omap_debug/clkgen-config.cc index 70c63c6e8..85371c5d1 100644 --- a/host/apps/omap_debug/clkgen-config.cc +++ b/host/apps/omap_debug/clkgen-config.cc @@ -117,7 +117,7 @@ static const unsigned int config_data[] = { }; -const unsigned int CLKGEN_SELECT = 145; +const unsigned int CLKGEN_SELECT = 127; enum gpio_direction {IN, OUT}; -- cgit v1.2.3 From bb3c5d65561bbd720085d8c0bac2ac5cb978773e Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 13 May 2010 22:49:42 +0000 Subject: got clock gen config working and tested --- host/apps/omap_debug/clkgen-config.cc | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/host/apps/omap_debug/clkgen-config.cc b/host/apps/omap_debug/clkgen-config.cc index 85371c5d1..e8279b4ae 100644 --- a/host/apps/omap_debug/clkgen-config.cc +++ b/host/apps/omap_debug/clkgen-config.cc @@ -50,6 +50,7 @@ static const unsigned int config_data[] = { 0x001704, 0x001807, 0x001900, + //0x001a00,//for debug 0x001a32, 0x001b12, 0x001c44, @@ -117,7 +118,7 @@ static const unsigned int config_data[] = { }; -const unsigned int CLKGEN_SELECT = 127; +const unsigned int CLKGEN_SELECT = 145; enum gpio_direction {IN, OUT}; @@ -238,7 +239,7 @@ spidev::spidev(std::string fname) { int ret; int mode = 0; - int speed = 12000000; + int speed = 12000; int bits = 24; fd = open(fname.c_str(), O_RDWR); @@ -277,9 +278,10 @@ static void send_config_to_clkgen(gpio &chip_select, const unsigned int data[], for (unsigned int i = 0; i < data_size; i++) { - chip_select.set_value(1); - spi.send((char *)&data[i], (char *)&rbuf, 4); + std::cout << "sending " << std::hex << data[i] << std::endl; chip_select.set_value(0); + spi.send((char *)&data[i], (char *)&rbuf, 4); + chip_select.set_value(1); }; } -- cgit v1.2.3 From 4d82cabe938b398bc42cab3d316983d2bbe40d06 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Fri, 14 May 2010 10:05:54 -0400 Subject: Update test program to reflect what is in the FPGA image. --- host/apps/omap_debug/usrp-e-crc-rw.c | 41 ++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 21 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-crc-rw.c b/host/apps/omap_debug/usrp-e-crc-rw.c index f99654781..e32cf2c59 100644 --- a/host/apps/omap_debug/usrp-e-crc-rw.c +++ b/host/apps/omap_debug/usrp-e-crc-rw.c @@ -177,43 +177,42 @@ int main(int argc, char *argv[]) { pthread_t tx, rx; long int t; - int fpga_config_flag ,decimation; struct usrp_e_ctl16 d; struct sched_param s = { .sched_priority = 1 }; + int read, write; - if (argc < 4) { - printf("%s t|w|rw decimation data_size\n", argv[0]); + if (argc < 2) { + printf("%s r|w|rw tx_data_size\n", argv[0]); return -1; } - decimation = atoi(argv[2]); - packet_data_length = atoi(argv[3]); + packet_data_length = atoi(argv[2]); - fp = open("/dev/usrp_e0", O_RDWR); - printf("fp = %d\n", fp); + if (strcmp(argv[1], "r") == 0) { + read = 1; + write = 0; + } - fpga_config_flag = 0; - if (strcmp(argv[1], "w") == 0) - fpga_config_flag |= (1 << 15); - else if (strcmp(argv[1], "r") == 0) - fpga_config_flag |= (1 << 14); - else if (strcmp(argv[1], "rw") == 0) - fpga_config_flag |= ((1 << 15) | (1 << 14)); + if (strcmp(argv[1], "w") == 0) { + read = 0; + write = 1; + } - fpga_config_flag |= decimation; + if (strcmp(argv[1], "rw") == 0) { + read = 1; + write = 1; + } - d.offset = 14; - d.count = 1; - d.buf[0] = fpga_config_flag; - ioctl(fp, USRP_E_WRITE_CTL16, &d); + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); sleep(1); // in case the kernel threads need time to start. FIXME if so sched_setscheduler(0, SCHED_RR, &s); - if (fpga_config_flag & (1 << 14)) { + if (read) { if (pthread_create(&rx, NULL, read_thread, (void *) t)) { printf("Failed to create rx thread\n"); exit(-1); @@ -222,7 +221,7 @@ int main(int argc, char *argv[]) sleep(1); - if (fpga_config_flag & (1 << 15)) { + if (write) { if (pthread_create(&tx, NULL, write_thread, (void *) t)) { printf("Failed to create tx thread\n"); exit(-1); -- cgit v1.2.3 From 47230fadfbbde3b45fbf57e8ff506f4fac812ca2 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 17 May 2010 20:59:55 -0700 Subject: better debug pins --- usrp2/top/u1e/u1e_core.v | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 903121832..4637df0cc 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -1,8 +1,8 @@ -//`define LOOPBACK 1 +`define LOOPBACK 1 //`define TIMED 1 -`define CRC 1 +//`define CRC 1 module u1e_core (input clk_fpga, input rst_fpga, @@ -372,12 +372,10 @@ module u1e_core // Debug circuitry assign debug_clk = { EM_CLK, clk_fpga }; -/* - assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, + assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, { EM_D } }; -*/ - assign debug = { phase[23:8], txsync, txblank, tx }; + //assign debug = { phase[23:8], txsync, txblank, tx }; assign debug_gpio_0 = { debug_gpmc }; -- cgit v1.2.3 From 7d0a98fc33c17457c9f4cd8e03eddb0d559457f0 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Tue, 18 May 2010 10:26:21 -0400 Subject: Revert "Update test program to reflect what is in the FPGA image." This reverts commit 4d82cabe938b398bc42cab3d316983d2bbe40d06. Now sure where I got the idea this image did not contain the rate setting code. --- host/apps/omap_debug/usrp-e-crc-rw.c | 41 ++++++++++++++++++------------------ 1 file changed, 21 insertions(+), 20 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-crc-rw.c b/host/apps/omap_debug/usrp-e-crc-rw.c index e32cf2c59..f99654781 100644 --- a/host/apps/omap_debug/usrp-e-crc-rw.c +++ b/host/apps/omap_debug/usrp-e-crc-rw.c @@ -177,42 +177,43 @@ int main(int argc, char *argv[]) { pthread_t tx, rx; long int t; + int fpga_config_flag ,decimation; struct usrp_e_ctl16 d; struct sched_param s = { .sched_priority = 1 }; - int read, write; - if (argc < 2) { - printf("%s r|w|rw tx_data_size\n", argv[0]); + if (argc < 4) { + printf("%s t|w|rw decimation data_size\n", argv[0]); return -1; } - packet_data_length = atoi(argv[2]); + decimation = atoi(argv[2]); + packet_data_length = atoi(argv[3]); - if (strcmp(argv[1], "r") == 0) { - read = 1; - write = 0; - } + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); - if (strcmp(argv[1], "w") == 0) { - read = 0; - write = 1; - } + fpga_config_flag = 0; + if (strcmp(argv[1], "w") == 0) + fpga_config_flag |= (1 << 15); + else if (strcmp(argv[1], "r") == 0) + fpga_config_flag |= (1 << 14); + else if (strcmp(argv[1], "rw") == 0) + fpga_config_flag |= ((1 << 15) | (1 << 14)); - if (strcmp(argv[1], "rw") == 0) { - read = 1; - write = 1; - } + fpga_config_flag |= decimation; - fp = open("/dev/usrp_e0", O_RDWR); - printf("fp = %d\n", fp); + d.offset = 14; + d.count = 1; + d.buf[0] = fpga_config_flag; + ioctl(fp, USRP_E_WRITE_CTL16, &d); sleep(1); // in case the kernel threads need time to start. FIXME if so sched_setscheduler(0, SCHED_RR, &s); - if (read) { + if (fpga_config_flag & (1 << 14)) { if (pthread_create(&rx, NULL, read_thread, (void *) t)) { printf("Failed to create rx thread\n"); exit(-1); @@ -221,7 +222,7 @@ int main(int argc, char *argv[]) sleep(1); - if (write) { + if (fpga_config_flag & (1 << 15)) { if (pthread_create(&tx, NULL, write_thread, (void *) t)) { printf("Failed to create tx thread\n"); exit(-1); -- cgit v1.2.3 From 3689cdd36c43656edc93cfee25d3bee1837f8bbd Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Tue, 18 May 2010 14:27:57 +0000 Subject: Remove rand for now. Fix bug in data rate calculation. --- host/apps/omap_debug/usrp-e-crc-rw.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-crc-rw.c b/host/apps/omap_debug/usrp-e-crc-rw.c index f99654781..b3f8ccc90 100644 --- a/host/apps/omap_debug/usrp-e-crc-rw.c +++ b/host/apps/omap_debug/usrp-e-crc-rw.c @@ -114,6 +114,7 @@ static void *write_thread(void *threadid) printf("Greetings from the write thread!\n"); + tx_pkt_cnt = 0; tx_data = malloc(2048); bytes_transfered = 0; @@ -141,7 +142,7 @@ static void *write_thread(void *threadid) crc = 0xFFFFFFFF; for (i = 0; i < tx_len; i++) { - tx_data->buf[i] = rand() & 0xFF; + tx_data->buf[i] = i & 0xFF; crc = ((crc >> 8) & 0x00FFFFFF) ^ crc_tab[(crc ^ tx_data->buf[i]) & 0xFF]; @@ -158,8 +159,9 @@ static void *write_thread(void *threadid) if (bytes_transfered > (100 * 1000000)) { gettimeofday(&finish_time, NULL); - elapsed_seconds = start_time.tv_sec - finish_time.tv_sec; + elapsed_seconds = finish_time.tv_sec - start_time.tv_sec; + printf("%d bytes transfered in %d seconds.\n", bytes_transfered, elapsed_seconds); printf("TX data transfer rate = %f K Bps\n", (float) bytes_transfered / (float) elapsed_seconds / 1000); -- cgit v1.2.3 From b5dfe74e991d240f0e666dfd521726ec61128eb8 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Tue, 18 May 2010 13:56:57 -0400 Subject: Revert "Revert "Update test program to reflect what is in the FPGA image."" This reverts commit 7d0a98fc33c17457c9f4cd8e03eddb0d559457f0. Must make filenames more different. --- host/apps/omap_debug/usrp-e-crc-rw.c | 41 ++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 21 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-crc-rw.c b/host/apps/omap_debug/usrp-e-crc-rw.c index b3f8ccc90..d47dfef5e 100644 --- a/host/apps/omap_debug/usrp-e-crc-rw.c +++ b/host/apps/omap_debug/usrp-e-crc-rw.c @@ -179,43 +179,42 @@ int main(int argc, char *argv[]) { pthread_t tx, rx; long int t; - int fpga_config_flag ,decimation; struct usrp_e_ctl16 d; struct sched_param s = { .sched_priority = 1 }; + int read, write; - if (argc < 4) { - printf("%s t|w|rw decimation data_size\n", argv[0]); + if (argc < 2) { + printf("%s r|w|rw tx_data_size\n", argv[0]); return -1; } - decimation = atoi(argv[2]); - packet_data_length = atoi(argv[3]); + packet_data_length = atoi(argv[2]); - fp = open("/dev/usrp_e0", O_RDWR); - printf("fp = %d\n", fp); + if (strcmp(argv[1], "r") == 0) { + read = 1; + write = 0; + } - fpga_config_flag = 0; - if (strcmp(argv[1], "w") == 0) - fpga_config_flag |= (1 << 15); - else if (strcmp(argv[1], "r") == 0) - fpga_config_flag |= (1 << 14); - else if (strcmp(argv[1], "rw") == 0) - fpga_config_flag |= ((1 << 15) | (1 << 14)); + if (strcmp(argv[1], "w") == 0) { + read = 0; + write = 1; + } - fpga_config_flag |= decimation; + if (strcmp(argv[1], "rw") == 0) { + read = 1; + write = 1; + } - d.offset = 14; - d.count = 1; - d.buf[0] = fpga_config_flag; - ioctl(fp, USRP_E_WRITE_CTL16, &d); + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); sleep(1); // in case the kernel threads need time to start. FIXME if so sched_setscheduler(0, SCHED_RR, &s); - if (fpga_config_flag & (1 << 14)) { + if (read) { if (pthread_create(&rx, NULL, read_thread, (void *) t)) { printf("Failed to create rx thread\n"); exit(-1); @@ -224,7 +223,7 @@ int main(int argc, char *argv[]) sleep(1); - if (fpga_config_flag & (1 << 15)) { + if (write) { if (pthread_create(&tx, NULL, write_thread, (void *) t)) { printf("Failed to create tx thread\n"); exit(-1); -- cgit v1.2.3 From e62fd331f37f532e63bdc302236a53dc2e2021e9 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Tue, 18 May 2010 17:58:39 +0000 Subject: Comment out progress indicators. --- host/apps/omap_debug/usrp-e-crc-rw.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-crc-rw.c b/host/apps/omap_debug/usrp-e-crc-rw.c index d47dfef5e..cd95761a2 100644 --- a/host/apps/omap_debug/usrp-e-crc-rw.c +++ b/host/apps/omap_debug/usrp-e-crc-rw.c @@ -64,13 +64,15 @@ static void *read_thread(void *threadid) printf("Error returned from read: %d\n", cnt); rx_pkt_cnt++; - + +#if 0 if (rx_pkt_cnt == 512) { printf("."); fflush(stdout); rx_pkt_cnt = 0; } - +#endif + if (rx_data->flags & RB_OVERRUN) printf("O"); @@ -91,7 +93,7 @@ static void *read_thread(void *threadid) if (bytes_transfered > (100 * 1000000)) { gettimeofday(&finish_time, NULL); - elapsed_seconds = start_time.tv_sec - finish_time.tv_sec; + elapsed_seconds = finish_time.tv_sec - start_time.tv_sec; printf("RX data transfer rate = %f K Bps\n", (float) bytes_transfered / (float) elapsed_seconds / 1000); @@ -123,6 +125,8 @@ static void *write_thread(void *threadid) while (1) { tx_pkt_cnt++; + +#if 0 if (tx_pkt_cnt == 512) { printf("."); fflush(stdout); @@ -136,6 +140,7 @@ static void *write_thread(void *threadid) fflush(stdout); tx_pkt_cnt = 0; } +#endif tx_len = 2048 - sizeof(struct usrp_transfer_frame) - sizeof(int); tx_data->len = tx_len + sizeof(int); @@ -161,7 +166,6 @@ static void *write_thread(void *threadid) gettimeofday(&finish_time, NULL); elapsed_seconds = finish_time.tv_sec - start_time.tv_sec; - printf("%d bytes transfered in %d seconds.\n", bytes_transfered, elapsed_seconds); printf("TX data transfer rate = %f K Bps\n", (float) bytes_transfered / (float) elapsed_seconds / 1000); -- cgit v1.2.3 From ad01832ca5a52d70a5f26de9c45868626b850785 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 19 May 2010 15:01:23 +0000 Subject: Keep repo in sync with my churn ... --- host/apps/omap_debug/usrp-e-crc-rw.c | 3 ++- host/apps/omap_debug/usrp-e-rw.c | 16 ++++++++++------ 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-crc-rw.c b/host/apps/omap_debug/usrp-e-crc-rw.c index cd95761a2..e1d9bf0db 100644 --- a/host/apps/omap_debug/usrp-e-crc-rw.c +++ b/host/apps/omap_debug/usrp-e-crc-rw.c @@ -211,12 +211,13 @@ int main(int argc, char *argv[]) write = 1; } + printf("About to open /dev/usrp_e0"); fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); sleep(1); // in case the kernel threads need time to start. FIXME if so - sched_setscheduler(0, SCHED_RR, &s); +// sched_setscheduler(0, SCHED_RR, &s); if (read) { if (pthread_create(&rx, NULL, read_thread, (void *) t)) { diff --git a/host/apps/omap_debug/usrp-e-rw.c b/host/apps/omap_debug/usrp-e-rw.c index 7fba8cd2a..1b12fa889 100644 --- a/host/apps/omap_debug/usrp-e-rw.c +++ b/host/apps/omap_debug/usrp-e-rw.c @@ -35,7 +35,7 @@ static int calc_checksum(struct pkt *p) static void *read_thread(void *threadid) { - int cnt, prev_seq_num; + int cnt, prev_seq_num, pkt_count; struct usrp_transfer_frame *rx_data; struct pkt *p; @@ -50,6 +50,7 @@ static void *read_thread(void *threadid) printf("sizeof rx data = %d\n", sizeof(struct usrp_transfer_frame) + sizeof(struct pkt)); prev_seq_num = 0; + pkt_count = 0; while (1) { @@ -60,14 +61,17 @@ static void *read_thread(void *threadid) // printf("Packet received, flags = %X, len = %d\n", rx_data->flags, rx_data->len); // printf("p->seq_num = %d\n", p->seq_num); + + pkt_count++; + if (p->seq_num != prev_seq_num + 1) - printf("Sequence number fail, current = %X, previous = %X\n", - p->seq_num, prev_seq_num); + printf("Sequence number fail, current = %X, previous = %X, pkt_count = %d\n", + p->seq_num, prev_seq_num, pkt_count); prev_seq_num = p->seq_num; if (calc_checksum(p) != p->checksum) - printf("Checksum fail packet = %X, expected = %X\n", - calc_checksum(p), p->checksum); + printf("Checksum fail packet = %X, expected = %X, pkt_count = %d\n", + calc_checksum(p), p->checksum, pkt_count); printf("."); fflush(stdout); @@ -108,7 +112,7 @@ static void *write_thread(void *threadid) cnt = write(fp, tx_data, 2048); if (cnt < 0) printf("Error returned from write: %d\n", cnt); - // sleep(1); + sleep(1); } } -- cgit v1.2.3 From 88b2a958f0a3a593230ca6b17e7c4aac3fba35e7 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 19 May 2010 13:21:45 -0400 Subject: Rename test program to match FPGA bin file name and add data rate calculation. --- host/apps/omap_debug/Makefile | 6 +- host/apps/omap_debug/usrp-e-fpga-rw.c | 207 ------------------------------- host/apps/omap_debug/usrp-e-timed.c | 227 ++++++++++++++++++++++++++++++++++ 3 files changed, 230 insertions(+), 210 deletions(-) delete mode 100644 host/apps/omap_debug/usrp-e-fpga-rw.c create mode 100644 host/apps/omap_debug/usrp-e-timed.c diff --git a/host/apps/omap_debug/Makefile b/host/apps/omap_debug/Makefile index e2aa384f2..40e04e377 100644 --- a/host/apps/omap_debug/Makefile +++ b/host/apps/omap_debug/Makefile @@ -1,6 +1,6 @@ CFLAGS=-Wall -I../../lib/usrp/usrp_e/ -all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio usrp-e-debug-pins usrp-e-rw-random usrp-e-fpga-rw usrp-e-lb-test usrp-e-crc-rw clkgen-config +all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio usrp-e-debug-pins usrp-e-rw-random usrp-e-timed usrp-e-lb-test usrp-e-crc-rw clkgen-config usrp-e-spi : usrp-e-spi.c @@ -9,7 +9,7 @@ usrp-e-i2c : usrp-e-i2c.c usrp-e-rw : usrp-e-rw.c gcc -o $@ $< -lpthread -usrp-e-fpga-rw : usrp-e-fpga-rw.c +usrp-e-timed : usrp-e-timed.c gcc -o $@ $< -lpthread usrp-e-rw-random : usrp-e-rw-random.c @@ -41,7 +41,7 @@ clean : rm -f usrp-e-spi rm -f usrp-e-i2c rm -f usrp-e-rw - rm -f usrp-e-fpga-rw + rm -f usrp-e-timed rm -f usrp-e-rw-random rm -f usrp-e-uart rm -f usrp-e-uart-rx diff --git a/host/apps/omap_debug/usrp-e-fpga-rw.c b/host/apps/omap_debug/usrp-e-fpga-rw.c deleted file mode 100644 index 6b585913e..000000000 --- a/host/apps/omap_debug/usrp-e-fpga-rw.c +++ /dev/null @@ -1,207 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include "usrp_e.h" - -// max length #define PKT_DATA_LENGTH 1016 -static int packet_data_length; - -struct pkt { - int checksum; - int seq_num; - short data[]; -}; - -static int fp; - -static int calc_checksum(struct pkt *p) -{ - int i, sum; - - i = 0; - sum = 0; - - for (i=0; i < packet_data_length; i++) - sum += p->data[i]; - - sum += p->seq_num; - - return sum; -} - -static void *read_thread(void *threadid) -{ - int cnt, prev_seq_num; - struct usrp_transfer_frame *rx_data; - struct pkt *p; - int rx_pkt_cnt; - int i; - - printf("Greetings from the reading thread!\n"); - - // IMPORTANT: must assume max length packet from fpga - rx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (1016 * 2)); - p = (struct pkt *) ((void *)rx_data + offsetof(struct usrp_transfer_frame, buf)); - //p = &(rx_data->buf[0]); - printf("Address of rx_data = %p, p = %p\n", rx_data, p); - printf("offsetof = %d\n", offsetof(struct usrp_transfer_frame, buf)); - printf("sizeof rx data = %d\n", sizeof(struct usrp_transfer_frame) + sizeof(struct pkt)); - - prev_seq_num = 0; - - rx_pkt_cnt = 0; - - while (1) { - - cnt = read(fp, rx_data, 2048); - if (cnt < 0) - printf("Error returned from read: %d\n", cnt); - rx_pkt_cnt++; - - if (rx_pkt_cnt == 512) { - printf("."); - fflush(stdout); - rx_pkt_cnt = 0; - } - - if (rx_data->flags & RB_OVERRUN) - printf("O"); - -// for (i = 0; i < 10; i++) -// printf(" %d", p->data[i]); -// printf("\n"); - -// printf("Packet received, flags = %X, len = %d\n", rx_data->flags, rx_data->len); -// printf("p->seq_num = %d\n", p->seq_num); - -// if (p->seq_num != prev_seq_num + 1) -// printf("Sequence number fail, current = %X, previous = %X\n", -// p->seq_num, prev_seq_num); -// prev_seq_num = p->seq_num; - -// if (calc_checksum(p) != p->checksum) -// printf("Checksum fail packet = %X, expected = %X\n", -// calc_checksum(p), p->checksum); -// printf("\n"); - } - -} - -static void *write_thread(void *threadid) -{ - int seq_number, i, cnt, tx_pkt_cnt; - struct usrp_transfer_frame *tx_data; - struct pkt *p; - - printf("Greetings from the write thread!\n"); - - tx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (packet_data_length * 2)); - p = (struct pkt *) ((void *)tx_data + offsetof(struct usrp_transfer_frame, buf)); - printf("Address of tx_data = %p, p = %p\n", tx_data, p); - - printf("sizeof rp_transfer_frame = %d, sizeof pkt = %d\n", sizeof(struct usrp_transfer_frame), sizeof(struct pkt)); - - for (i=0; i < packet_data_length; i++) -// p->data[i] = random() >> 16; - p->data[i] = i; - - tx_data->flags = 0; - tx_data->len = 8 + packet_data_length * 2; - - printf("tx_data->len = %d\n", tx_data->len); - - seq_number = 1; - tx_pkt_cnt = 0; - - while (1) { - - tx_pkt_cnt++; - if (tx_pkt_cnt == 512) { - printf("."); - fflush(stdout); - } - if (tx_pkt_cnt == 1024) { - printf("'"); - fflush(stdout); - } - if (tx_pkt_cnt == 1536) { - printf(":"); - fflush(stdout); - tx_pkt_cnt = 0; - } - -// printf("tx flags = %X, len = %d\n", tx_data->flags, tx_data->len); - p->seq_num = seq_number++; - p->checksum = calc_checksum(p); - cnt = write(fp, tx_data, 2048); - if (cnt < 0) - printf("Error returned from write: %d\n", cnt); -// sleep(1); - } -} - - -int main(int argc, char *argv[]) -{ - pthread_t tx, rx; - long int t; - int fpga_config_flag ,decimation; - struct usrp_e_ctl16 d; - struct sched_param s = { - .sched_priority = 1 - }; - - if (argc < 4) { - printf("%s t|w|rw decimation data_size\n", argv[0]); - return -1; - } - - decimation = atoi(argv[2]); - packet_data_length = atoi(argv[3]); - - fp = open("/dev/usrp_e0", O_RDWR); - printf("fp = %d\n", fp); - - fpga_config_flag = 0; - if (strcmp(argv[1], "w") == 0) - fpga_config_flag |= (1 << 15); - else if (strcmp(argv[1], "r") == 0) - fpga_config_flag |= (1 << 14); - else if (strcmp(argv[1], "rw") == 0) - fpga_config_flag |= ((1 << 15) | (1 << 14)); - - fpga_config_flag |= decimation; - - d.offset = 14; - d.count = 1; - d.buf[0] = fpga_config_flag; - ioctl(fp, USRP_E_WRITE_CTL16, &d); - - sleep(1); // in case the kernel threads need time to start. FIXME if so - - sched_setscheduler(0, SCHED_RR, &s); - - if (fpga_config_flag & (1 << 14)) { - if (pthread_create(&rx, NULL, read_thread, (void *) t)) { - printf("Failed to create rx thread\n"); - exit(-1); - } - } - - sleep(1); - - if (fpga_config_flag & (1 << 15)) { - if (pthread_create(&tx, NULL, write_thread, (void *) t)) { - printf("Failed to create tx thread\n"); - exit(-1); - } - } - - sleep(10000); - - printf("Done sleeping\n"); -} diff --git a/host/apps/omap_debug/usrp-e-timed.c b/host/apps/omap_debug/usrp-e-timed.c new file mode 100644 index 000000000..69e6c07ca --- /dev/null +++ b/host/apps/omap_debug/usrp-e-timed.c @@ -0,0 +1,227 @@ +#include +#include +#include +#include +#include +#include +#include +#include "usrp_e.h" + +// max length #define PKT_DATA_LENGTH 1016 +static int packet_data_length; + +struct pkt { + int checksum; + int seq_num; + short data[]; +}; + +static int fp; + +static int calc_checksum(struct pkt *p) +{ + int i, sum; + + i = 0; + sum = 0; + + for (i=0; i < packet_data_length; i++) + sum += p->data[i]; + + sum += p->seq_num; + + return sum; +} + +static void *read_thread(void *threadid) +{ + int cnt, prev_seq_num; + struct usrp_transfer_frame *rx_data; + struct pkt *p; + int rx_pkt_cnt; + int i; + unsigned long bytes_transfered, elapsed_seconds; + struct timeval start_time, finish_time; + + printf("Greetings from the reading thread!\n"); + + // IMPORTANT: must assume max length packet from fpga + rx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (1016 * 2)); + p = (struct pkt *) ((void *)rx_data + offsetof(struct usrp_transfer_frame, buf)); + //p = &(rx_data->buf[0]); + printf("Address of rx_data = %p, p = %p\n", rx_data, p); + printf("offsetof = %d\n", offsetof(struct usrp_transfer_frame, buf)); + printf("sizeof rx data = %d\n", sizeof(struct usrp_transfer_frame) + sizeof(struct pkt)); + + prev_seq_num = 0; + + rx_pkt_cnt = 0; + + while (1) { + + cnt = read(fp, rx_data, 2048); + if (cnt < 0) + printf("Error returned from read: %d\n", cnt); + rx_pkt_cnt++; + +#if 0 + if (rx_pkt_cnt == 512) { + printf("."); + fflush(stdout); + rx_pkt_cnt = 0; + } +#endif + + if (rx_data->flags & RB_OVERRUN) + printf("O"); + + bytes_transfered += rx_data->len; + + if (bytes_transfered > (100 * 1000000)) { + gettimeofday(&finish_time, NULL); + elapsed_seconds = finish_time.tv_sec - start_time.tv_sec; + + printf("RX data transfer rate = %f K Bps\n", + (float) bytes_transfered / (float) elapsed_seconds / 1000); + + + start_time = finish_time; + bytes_transfered = 0; + } + } + +} + +static void *write_thread(void *threadid) +{ + int seq_number, i, cnt, tx_pkt_cnt; + struct usrp_transfer_frame *tx_data; + struct pkt *p; + unsigned long bytes_transfered, elapsed_seconds; + struct timeval start_time, finish_time; + + printf("Greetings from the write thread!\n"); + + tx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (packet_data_length * 2)); + p = (struct pkt *) ((void *)tx_data + offsetof(struct usrp_transfer_frame, buf)); + printf("Address of tx_data = %p, p = %p\n", tx_data, p); + + printf("sizeof rp_transfer_frame = %d, sizeof pkt = %d\n", sizeof(struct usrp_transfer_frame), sizeof(struct pkt)); + + for (i=0; i < packet_data_length; i++) +// p->data[i] = random() >> 16; + p->data[i] = i; + + tx_data->flags = 0; + tx_data->len = 8 + packet_data_length * 2; + + printf("tx_data->len = %d\n", tx_data->len); + + seq_number = 1; + tx_pkt_cnt = 0; + + while (1) { + + tx_pkt_cnt++; + +#if 0 + if (tx_pkt_cnt == 512) { + printf("."); + fflush(stdout); + } + if (tx_pkt_cnt == 1024) { + printf("'"); + fflush(stdout); + } + if (tx_pkt_cnt == 1536) { + printf(":"); + fflush(stdout); + tx_pkt_cnt = 0; + } +#endif + +// printf("tx flags = %X, len = %d\n", tx_data->flags, tx_data->len); + p->seq_num = seq_number++; + p->checksum = calc_checksum(p); + cnt = write(fp, tx_data, 2048); + if (cnt < 0) + printf("Error returned from write: %d\n", cnt); + + bytes_transfered += tx_data->len; + + if (bytes_transfered > (100 * 1000000)) { + gettimeofday(&finish_time, NULL); + elapsed_seconds = finish_time.tv_sec - start_time.tv_sec; + + printf("TX data transfer rate = %f K Bps\n", + (float) bytes_transfered / (float) elapsed_seconds / 1000); + + + start_time = finish_time; + bytes_transfered = 0; + } +// sleep(1); + } +} + + +int main(int argc, char *argv[]) +{ + pthread_t tx, rx; + long int t; + int fpga_config_flag ,decimation; + struct usrp_e_ctl16 d; + struct sched_param s = { + .sched_priority = 1 + }; + + if (argc < 4) { + printf("%s t|w|rw decimation data_size\n", argv[0]); + return -1; + } + + decimation = atoi(argv[2]); + packet_data_length = atoi(argv[3]); + + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); + + fpga_config_flag = 0; + if (strcmp(argv[1], "w") == 0) + fpga_config_flag |= (1 << 15); + else if (strcmp(argv[1], "r") == 0) + fpga_config_flag |= (1 << 14); + else if (strcmp(argv[1], "rw") == 0) + fpga_config_flag |= ((1 << 15) | (1 << 14)); + + fpga_config_flag |= decimation; + + d.offset = 14; + d.count = 1; + d.buf[0] = fpga_config_flag; + ioctl(fp, USRP_E_WRITE_CTL16, &d); + + sleep(1); // in case the kernel threads need time to start. FIXME if so + + sched_setscheduler(0, SCHED_RR, &s); + + if (fpga_config_flag & (1 << 14)) { + if (pthread_create(&rx, NULL, read_thread, (void *) t)) { + printf("Failed to create rx thread\n"); + exit(-1); + } + } + + sleep(1); + + if (fpga_config_flag & (1 << 15)) { + if (pthread_create(&tx, NULL, write_thread, (void *) t)) { + printf("Failed to create tx thread\n"); + exit(-1); + } + } + + sleep(10000); + + printf("Done sleeping\n"); +} -- cgit v1.2.3 From d6fc36cb7aa39cbe3f6dde1b6bc4606a2e686279 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 19 May 2010 17:41:11 +0000 Subject: Fix initialization bug. --- host/apps/omap_debug/usrp-e-timed.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/host/apps/omap_debug/usrp-e-timed.c b/host/apps/omap_debug/usrp-e-timed.c index 69e6c07ca..cfc70f724 100644 --- a/host/apps/omap_debug/usrp-e-timed.c +++ b/host/apps/omap_debug/usrp-e-timed.c @@ -45,6 +45,9 @@ static void *read_thread(void *threadid) printf("Greetings from the reading thread!\n"); + bytes_transfered = 0; + gettimeofday(&start_time, NULL); + // IMPORTANT: must assume max length packet from fpga rx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (1016 * 2)); p = (struct pkt *) ((void *)rx_data + offsetof(struct usrp_transfer_frame, buf)); @@ -102,6 +105,9 @@ static void *write_thread(void *threadid) printf("Greetings from the write thread!\n"); + bytes_transfered = 0; + gettimeofday(&start_time, NULL); + tx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (packet_data_length * 2)); p = (struct pkt *) ((void *)tx_data + offsetof(struct usrp_transfer_frame, buf)); printf("Address of tx_data = %p, p = %p\n", tx_data, p); -- cgit v1.2.3 From fe753af7e62e55668cb331b7b74ea14d6e45a0ec Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 19 May 2010 22:25:29 +0000 Subject: Use better optimization settings. --- host/apps/omap_debug/Makefile | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/host/apps/omap_debug/Makefile b/host/apps/omap_debug/Makefile index 40e04e377..295d40979 100644 --- a/host/apps/omap_debug/Makefile +++ b/host/apps/omap_debug/Makefile @@ -1,4 +1,5 @@ -CFLAGS=-Wall -I../../lib/usrp/usrp_e/ +CFLAGS=-Wall -I../../lib/usrp/usrp_e/ -march=armv7-a -mtune=cortex-a8 -mfpu=neon -O3 +CXXFLAGS=-Wall -I../../lib/usrp/usrp_e/ -march=armv7-a -mtune=cortex-a8 -mfpu=neon -O3 all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio usrp-e-debug-pins usrp-e-rw-random usrp-e-timed usrp-e-lb-test usrp-e-crc-rw clkgen-config @@ -7,16 +8,16 @@ usrp-e-spi : usrp-e-spi.c usrp-e-i2c : usrp-e-i2c.c usrp-e-rw : usrp-e-rw.c - gcc -o $@ $< -lpthread + gcc -o $@ $< -lpthread ${CFLAGS} usrp-e-timed : usrp-e-timed.c - gcc -o $@ $< -lpthread + gcc -o $@ $< -lpthread ${CFLAGS} usrp-e-rw-random : usrp-e-rw-random.c - gcc -o $@ $< -lpthread + gcc -o $@ $< -lpthread ${CFLAGS} usrp-e-crc-rw : usrp-e-crc-rw.c - gcc -o $@ $< -lpthread + gcc -o $@ $< -lpthread ${CFLAGS} usrp-e-uart : usrp-e-uart.c -- cgit v1.2.3 From 090d066570993f068f2e3b3a6c6bd25986fc92b7 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 19 May 2010 22:26:14 +0000 Subject: Calculate received sample rate for loopback test. --- host/apps/omap_debug/usrp-e-rw.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-rw.c b/host/apps/omap_debug/usrp-e-rw.c index 1b12fa889..f96e4e25b 100644 --- a/host/apps/omap_debug/usrp-e-rw.c +++ b/host/apps/omap_debug/usrp-e-rw.c @@ -38,9 +38,14 @@ static void *read_thread(void *threadid) int cnt, prev_seq_num, pkt_count; struct usrp_transfer_frame *rx_data; struct pkt *p; + unsigned long bytes_transfered, elapsed_seconds; + struct timeval start_time, finish_time; printf("Greetings from the reading thread!\n"); + bytes_transfered = 0; + gettimeofday(&start_time, NULL); + // IMPORTANT: must assume max length packet from fpga rx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (1016 * 2)); p = (struct pkt *) ((void *)rx_data + offsetof(struct usrp_transfer_frame, buf)); @@ -73,8 +78,24 @@ static void *read_thread(void *threadid) printf("Checksum fail packet = %X, expected = %X, pkt_count = %d\n", calc_checksum(p), p->checksum, pkt_count); - printf("."); - fflush(stdout); + + bytes_transfered += rx_data->len; + + if (bytes_transfered > (100 * 1000000)) { + gettimeofday(&finish_time, NULL); + elapsed_seconds = finish_time.tv_sec - start_time.tv_sec; + + printf("RX data transfer rate = %f K Samples/second\n", + (float) bytes_transfered / (float) elapsed_seconds / 250); + + + start_time = finish_time; + bytes_transfered = 0; + } + + +// printf("."); +// fflush(stdout); // printf("\n"); } @@ -112,7 +133,7 @@ static void *write_thread(void *threadid) cnt = write(fp, tx_data, 2048); if (cnt < 0) printf("Error returned from write: %d\n", cnt); - sleep(1); +// sleep(1); } } -- cgit v1.2.3 From 3bb874f8061f203d8adf6f07e61fd50a154e9906 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 19 May 2010 22:27:06 +0000 Subject: Display data rate in samples/second and fix typo. --- host/apps/omap_debug/usrp-e-timed.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-timed.c b/host/apps/omap_debug/usrp-e-timed.c index cfc70f724..c71651741 100644 --- a/host/apps/omap_debug/usrp-e-timed.c +++ b/host/apps/omap_debug/usrp-e-timed.c @@ -84,8 +84,8 @@ static void *read_thread(void *threadid) gettimeofday(&finish_time, NULL); elapsed_seconds = finish_time.tv_sec - start_time.tv_sec; - printf("RX data transfer rate = %f K Bps\n", - (float) bytes_transfered / (float) elapsed_seconds / 1000); + printf("RX data transfer rate = %f K Samples/second\n", + (float) bytes_transfered / (float) elapsed_seconds / 4000); start_time = finish_time; @@ -159,8 +159,8 @@ static void *write_thread(void *threadid) gettimeofday(&finish_time, NULL); elapsed_seconds = finish_time.tv_sec - start_time.tv_sec; - printf("TX data transfer rate = %f K Bps\n", - (float) bytes_transfered / (float) elapsed_seconds / 1000); + printf("TX data transfer rate = %f K Samples/second\n", + (float) bytes_transfered / (float) elapsed_seconds / 4000); start_time = finish_time; @@ -182,7 +182,7 @@ int main(int argc, char *argv[]) }; if (argc < 4) { - printf("%s t|w|rw decimation data_size\n", argv[0]); + printf("%s r|w|rw decimation data_size\n", argv[0]); return -1; } -- cgit v1.2.3 From c94256034819feb26d739e57e8cf7d3f60539e9c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 20 May 2010 00:30:49 -0700 Subject: combined timed and crc cases. fifo pacer produces/consumes at a fixed rate --- usrp2/control_lib/newfifo/fifo_pacer.v | 24 ++++++++++++++ usrp2/top/u1e/Makefile | 1 + usrp2/top/u1e/u1e_core.v | 57 ++++++++++++++-------------------- 3 files changed, 48 insertions(+), 34 deletions(-) create mode 100644 usrp2/control_lib/newfifo/fifo_pacer.v diff --git a/usrp2/control_lib/newfifo/fifo_pacer.v b/usrp2/control_lib/newfifo/fifo_pacer.v new file mode 100644 index 000000000..1bf03ab6e --- /dev/null +++ b/usrp2/control_lib/newfifo/fifo_pacer.v @@ -0,0 +1,24 @@ + + +module fifo_pacer + (input clk, + input reset, + input [7:0] rate, + input enable, + input src1_rdy_i, output dst1_rdy_o, + output src2_rdy_o, input dst2_rdy_i, + output underrun, overrun); + + wire strobe; + + cic_strober strober (.clock(clk), .reset(reset), .enable(enable), + .rate(rate), .strobe_fast(1), .strobe_slow(strobe)); + + wire all_ready = src1_rdy_i & dst2_rdy_i; + assign dst1_rdy_o = all_ready & strobe; + assign src2_rdy_o = dst1_rdy_o; + + assign underrun = strobe & ~src1_rdy_i; + assign overrun = strobe & ~dst2_rdy_i; + +endmodule // fifo_pacer diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 8622b8480..0277ef4f2 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -115,6 +115,7 @@ control_lib/newfifo/packet_generator.v \ control_lib/newfifo/packet_verifier.v \ control_lib/newfifo/packet_generator32.v \ control_lib/newfifo/packet_verifier32.v \ +control_lib/newfifo/fifo_pacer.v \ control_lib/longfifo.v \ control_lib/shortfifo.v \ control_lib/medfifo.v \ diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 903121832..21ac97dbd 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -1,8 +1,7 @@ //`define LOOPBACK 1 -//`define TIMED 1 -`define CRC 1 +`define TIMED 1 module u1e_core (input clk_fpga, input rst_fpga, @@ -80,45 +79,35 @@ module u1e_core wire [7:0] rate; // TX side - wire tx_enable; - cic_strober tx_strober (.clock(wb_clk), .reset(wb_rst), .enable(tx_enable), - .rate(rate), .strobe_fast(1), .strobe_slow(tx_dst_rdy)); - - // RX side - wire rx_enable; - reg [15:0] ctr; - wire [15:0] rx_pkt_len = 480; - wire rx_eof = (ctr == rx_pkt_len); - wire rx_sof = (ctr == 0); + wire tx_enable, tx_src_rdy_int, tx_dst_rdy_int; - cic_strober rx_strober (.clock(wb_clk), .reset(wb_rst), .enable(rx_enable), - .rate(rate), .strobe_fast(1), .strobe_slow(rx_src_rdy)); + fifo_pacer tx_pacer + (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(tx_enable), + .src1_rdy_i(tx_src_rdy), .dst1_rdy_o(tx_dst_rdy), + .src2_rdy_o(tx_src_rdy_int), .dst2_rdy_i(tx_dst_rdy_int), + .underrun(tx_underrun), .overrun()); - always @(posedge wb_clk) - if(wb_rst) - ctr <= 0; - else if(rx_dst_rdy & rx_src_rdy) - if(ctr == rx_pkt_len) - ctr <= 0; - else - ctr <= ctr + 1; - - assign rx_data = {2'b00,rx_eof,rx_sof,~ctr,ctr}; -`endif // TIMED - -`ifdef CRC - packet_generator32 pktgen32 - (.clk(wb_clk), .reset(wb_rst), .clear(clear), - .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); - packet_verifier32 pktver32 (.clk(wb_clk), .reset(wb_rst), .clear(clear), - .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), + .data_i(tx_data), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int), .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + // RX side + wire rx_enable, rx_src_rdy_int, rx_dst_rdy_int; wire rx_sof = rx_data[32]; wire rx_eof = rx_data[33]; -`endif // CRC + + packet_generator32 pktgen32 + (.clk(wb_clk), .reset(wb_rst), .clear(clear), + .data_o(rx_data), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int)); + + fifo_pacer rx_pacer + (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(rx_enable), + .src1_rdy_i(rx_src_rdy_int), .dst1_rdy_o(rx_dst_rdy_int), + .src2_rdy_o(rx_src_rdy), .dst2_rdy_i(rx_dst_rdy), + .underrun(), .overrun(rx_overrun)); + +`endif // `ifdef TIMED // ///////////////////////////////////////////////////////////////////////////////////// // Wishbone Intercon, single master @@ -233,7 +222,7 @@ module u1e_core assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; - assign { rx_overrun, tx_underrun } = 0; // reg_test; + //assign { rx_overrun, tx_underrun } = 0; // reg_test; assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : -- cgit v1.2.3 From 3b96b1f0f443acb9412b40592de5dc13e1f840d6 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 20 May 2010 00:34:35 -0700 Subject: put over/underrun on debug bus, remove high order address bits --- usrp2/top/u1e/u1e_core.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 71b9b8712..48b5bd010 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -361,7 +361,8 @@ module u1e_core // Debug circuitry assign debug_clk = { EM_CLK, clk_fpga }; - assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, + assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, rx_overrun, tx_underrun }, + { EM_A[8:1] }, { EM_D } }; //assign debug = { phase[23:8], txsync, txblank, tx }; -- cgit v1.2.3 From a9fefde874503c0c4e0c542846c1dd1c74156d07 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 20 May 2010 15:05:04 +0000 Subject: Enable realtime scheduling in loopback test to prevent overruns. --- host/apps/omap_debug/usrp-e-rw.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/host/apps/omap_debug/usrp-e-rw.c b/host/apps/omap_debug/usrp-e-rw.c index f96e4e25b..798bc4b45 100644 --- a/host/apps/omap_debug/usrp-e-rw.c +++ b/host/apps/omap_debug/usrp-e-rw.c @@ -142,6 +142,9 @@ int main(int argc, char *argv[]) { pthread_t tx, rx; long int t; + struct sched_param s = { + .sched_priority = 1 + }; if (argc < 2) { printf("%s data_size\n", argv[0]); @@ -153,6 +156,8 @@ int main(int argc, char *argv[]) fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); + sched_setscheduler(0, SCHED_RR, &s); + if (pthread_create(&rx, NULL, read_thread, (void *) t)) { printf("Failed to create rx thread\n"); exit(-1); -- cgit v1.2.3 From 64276eabd8d88f7d72763f8b500c13a9a689cd21 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 20 May 2010 15:10:32 +0000 Subject: Rename loopback test program to match bin file name. --- host/apps/omap_debug/Makefile | 6 +- host/apps/omap_debug/usrp-e-loopback.c | 176 +++++++++++++++++++++++++++++++++ host/apps/omap_debug/usrp-e-rw.c | 176 --------------------------------- 3 files changed, 179 insertions(+), 179 deletions(-) create mode 100644 host/apps/omap_debug/usrp-e-loopback.c delete mode 100644 host/apps/omap_debug/usrp-e-rw.c diff --git a/host/apps/omap_debug/Makefile b/host/apps/omap_debug/Makefile index 295d40979..17a3858cf 100644 --- a/host/apps/omap_debug/Makefile +++ b/host/apps/omap_debug/Makefile @@ -1,13 +1,13 @@ CFLAGS=-Wall -I../../lib/usrp/usrp_e/ -march=armv7-a -mtune=cortex-a8 -mfpu=neon -O3 CXXFLAGS=-Wall -I../../lib/usrp/usrp_e/ -march=armv7-a -mtune=cortex-a8 -mfpu=neon -O3 -all : usrp-e-spi usrp-e-i2c usrp-e-rw usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio usrp-e-debug-pins usrp-e-rw-random usrp-e-timed usrp-e-lb-test usrp-e-crc-rw clkgen-config +all : usrp-e-spi usrp-e-i2c usrp-e-loopback usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio usrp-e-debug-pins usrp-e-rw-random usrp-e-timed usrp-e-lb-test usrp-e-crc-rw clkgen-config usrp-e-spi : usrp-e-spi.c usrp-e-i2c : usrp-e-i2c.c -usrp-e-rw : usrp-e-rw.c +usrp-e-loopback : usrp-e-loopback.c gcc -o $@ $< -lpthread ${CFLAGS} usrp-e-timed : usrp-e-timed.c @@ -41,7 +41,7 @@ usrp-e-debug-pins : usrp-e-debug-pins.c clean : rm -f usrp-e-spi rm -f usrp-e-i2c - rm -f usrp-e-rw + rm -f usrp-e-loopback rm -f usrp-e-timed rm -f usrp-e-rw-random rm -f usrp-e-uart diff --git a/host/apps/omap_debug/usrp-e-loopback.c b/host/apps/omap_debug/usrp-e-loopback.c new file mode 100644 index 000000000..798bc4b45 --- /dev/null +++ b/host/apps/omap_debug/usrp-e-loopback.c @@ -0,0 +1,176 @@ +#include +#include +#include +#include +#include +#include +#include +#include "usrp_e.h" + +// max length #define PKT_DATA_LENGTH 1016 +static int packet_data_length; + +struct pkt { + int checksum; + int seq_num; + short data[]; +}; + +static int fp; + +static int calc_checksum(struct pkt *p) +{ + int i, sum; + + i = 0; + sum = 0; + + for (i=0; i < packet_data_length; i++) + sum += p->data[i]; + + sum += p->seq_num; + + return sum; +} + +static void *read_thread(void *threadid) +{ + int cnt, prev_seq_num, pkt_count; + struct usrp_transfer_frame *rx_data; + struct pkt *p; + unsigned long bytes_transfered, elapsed_seconds; + struct timeval start_time, finish_time; + + printf("Greetings from the reading thread!\n"); + + bytes_transfered = 0; + gettimeofday(&start_time, NULL); + + // IMPORTANT: must assume max length packet from fpga + rx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (1016 * 2)); + p = (struct pkt *) ((void *)rx_data + offsetof(struct usrp_transfer_frame, buf)); + //p = &(rx_data->buf[0]); + printf("Address of rx_data = %p, p = %p\n", rx_data, p); + printf("offsetof = %d\n", offsetof(struct usrp_transfer_frame, buf)); + printf("sizeof rx data = %d\n", sizeof(struct usrp_transfer_frame) + sizeof(struct pkt)); + + prev_seq_num = 0; + pkt_count = 0; + + while (1) { + + cnt = read(fp, rx_data, 2048); + if (cnt < 0) + printf("Error returned from read: %d\n", cnt); + +// printf("Packet received, flags = %X, len = %d\n", rx_data->flags, rx_data->len); +// printf("p->seq_num = %d\n", p->seq_num); + + + pkt_count++; + + if (p->seq_num != prev_seq_num + 1) + printf("Sequence number fail, current = %X, previous = %X, pkt_count = %d\n", + p->seq_num, prev_seq_num, pkt_count); + prev_seq_num = p->seq_num; + + if (calc_checksum(p) != p->checksum) + printf("Checksum fail packet = %X, expected = %X, pkt_count = %d\n", + calc_checksum(p), p->checksum, pkt_count); + + + bytes_transfered += rx_data->len; + + if (bytes_transfered > (100 * 1000000)) { + gettimeofday(&finish_time, NULL); + elapsed_seconds = finish_time.tv_sec - start_time.tv_sec; + + printf("RX data transfer rate = %f K Samples/second\n", + (float) bytes_transfered / (float) elapsed_seconds / 250); + + + start_time = finish_time; + bytes_transfered = 0; + } + + +// printf("."); +// fflush(stdout); +// printf("\n"); + } + +} + +static void *write_thread(void *threadid) +{ + int seq_number, i, cnt; + struct usrp_transfer_frame *tx_data; + struct pkt *p; + + printf("Greetings from the write thread!\n"); + + tx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (packet_data_length * 2)); + p = (struct pkt *) ((void *)tx_data + offsetof(struct usrp_transfer_frame, buf)); + printf("Address of tx_data = %p, p = %p\n", tx_data, p); + + printf("sizeof rp_transfer_frame = %d, sizeof pkt = %d\n", sizeof(struct usrp_transfer_frame), sizeof(struct pkt)); + + for (i=0; i < packet_data_length; i++) +// p->data[i] = random() >> 16; + p->data[i] = i; + + tx_data->flags = 0xdeadbeef; + tx_data->len = 8 + packet_data_length * 2; + + printf("tx_data->len = %d\n", tx_data->len); + + seq_number = 1; + + while (1) { +// printf("tx flags = %X, len = %d\n", tx_data->flags, tx_data->len); + p->seq_num = seq_number++; + p->checksum = calc_checksum(p); + cnt = write(fp, tx_data, 2048); + if (cnt < 0) + printf("Error returned from write: %d\n", cnt); +// sleep(1); + } +} + + +int main(int argc, char *argv[]) +{ + pthread_t tx, rx; + long int t; + struct sched_param s = { + .sched_priority = 1 + }; + + if (argc < 2) { + printf("%s data_size\n", argv[0]); + return -1; + } + + packet_data_length = atoi(argv[1]); + + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); + + sched_setscheduler(0, SCHED_RR, &s); + + if (pthread_create(&rx, NULL, read_thread, (void *) t)) { + printf("Failed to create rx thread\n"); + exit(-1); + } + + sleep(1); + + if (pthread_create(&tx, NULL, write_thread, (void *) t)) { + printf("Failed to create tx thread\n"); + exit(-1); + } + + sleep(10000); + + printf("Done sleeping\n"); +} diff --git a/host/apps/omap_debug/usrp-e-rw.c b/host/apps/omap_debug/usrp-e-rw.c deleted file mode 100644 index 798bc4b45..000000000 --- a/host/apps/omap_debug/usrp-e-rw.c +++ /dev/null @@ -1,176 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include "usrp_e.h" - -// max length #define PKT_DATA_LENGTH 1016 -static int packet_data_length; - -struct pkt { - int checksum; - int seq_num; - short data[]; -}; - -static int fp; - -static int calc_checksum(struct pkt *p) -{ - int i, sum; - - i = 0; - sum = 0; - - for (i=0; i < packet_data_length; i++) - sum += p->data[i]; - - sum += p->seq_num; - - return sum; -} - -static void *read_thread(void *threadid) -{ - int cnt, prev_seq_num, pkt_count; - struct usrp_transfer_frame *rx_data; - struct pkt *p; - unsigned long bytes_transfered, elapsed_seconds; - struct timeval start_time, finish_time; - - printf("Greetings from the reading thread!\n"); - - bytes_transfered = 0; - gettimeofday(&start_time, NULL); - - // IMPORTANT: must assume max length packet from fpga - rx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (1016 * 2)); - p = (struct pkt *) ((void *)rx_data + offsetof(struct usrp_transfer_frame, buf)); - //p = &(rx_data->buf[0]); - printf("Address of rx_data = %p, p = %p\n", rx_data, p); - printf("offsetof = %d\n", offsetof(struct usrp_transfer_frame, buf)); - printf("sizeof rx data = %d\n", sizeof(struct usrp_transfer_frame) + sizeof(struct pkt)); - - prev_seq_num = 0; - pkt_count = 0; - - while (1) { - - cnt = read(fp, rx_data, 2048); - if (cnt < 0) - printf("Error returned from read: %d\n", cnt); - -// printf("Packet received, flags = %X, len = %d\n", rx_data->flags, rx_data->len); -// printf("p->seq_num = %d\n", p->seq_num); - - - pkt_count++; - - if (p->seq_num != prev_seq_num + 1) - printf("Sequence number fail, current = %X, previous = %X, pkt_count = %d\n", - p->seq_num, prev_seq_num, pkt_count); - prev_seq_num = p->seq_num; - - if (calc_checksum(p) != p->checksum) - printf("Checksum fail packet = %X, expected = %X, pkt_count = %d\n", - calc_checksum(p), p->checksum, pkt_count); - - - bytes_transfered += rx_data->len; - - if (bytes_transfered > (100 * 1000000)) { - gettimeofday(&finish_time, NULL); - elapsed_seconds = finish_time.tv_sec - start_time.tv_sec; - - printf("RX data transfer rate = %f K Samples/second\n", - (float) bytes_transfered / (float) elapsed_seconds / 250); - - - start_time = finish_time; - bytes_transfered = 0; - } - - -// printf("."); -// fflush(stdout); -// printf("\n"); - } - -} - -static void *write_thread(void *threadid) -{ - int seq_number, i, cnt; - struct usrp_transfer_frame *tx_data; - struct pkt *p; - - printf("Greetings from the write thread!\n"); - - tx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (packet_data_length * 2)); - p = (struct pkt *) ((void *)tx_data + offsetof(struct usrp_transfer_frame, buf)); - printf("Address of tx_data = %p, p = %p\n", tx_data, p); - - printf("sizeof rp_transfer_frame = %d, sizeof pkt = %d\n", sizeof(struct usrp_transfer_frame), sizeof(struct pkt)); - - for (i=0; i < packet_data_length; i++) -// p->data[i] = random() >> 16; - p->data[i] = i; - - tx_data->flags = 0xdeadbeef; - tx_data->len = 8 + packet_data_length * 2; - - printf("tx_data->len = %d\n", tx_data->len); - - seq_number = 1; - - while (1) { -// printf("tx flags = %X, len = %d\n", tx_data->flags, tx_data->len); - p->seq_num = seq_number++; - p->checksum = calc_checksum(p); - cnt = write(fp, tx_data, 2048); - if (cnt < 0) - printf("Error returned from write: %d\n", cnt); -// sleep(1); - } -} - - -int main(int argc, char *argv[]) -{ - pthread_t tx, rx; - long int t; - struct sched_param s = { - .sched_priority = 1 - }; - - if (argc < 2) { - printf("%s data_size\n", argv[0]); - return -1; - } - - packet_data_length = atoi(argv[1]); - - fp = open("/dev/usrp_e0", O_RDWR); - printf("fp = %d\n", fp); - - sched_setscheduler(0, SCHED_RR, &s); - - if (pthread_create(&rx, NULL, read_thread, (void *) t)) { - printf("Failed to create rx thread\n"); - exit(-1); - } - - sleep(1); - - if (pthread_create(&tx, NULL, write_thread, (void *) t)) { - printf("Failed to create tx thread\n"); - exit(-1); - } - - sleep(10000); - - printf("Done sleeping\n"); -} -- cgit v1.2.3 From c6e8d0658dc66e9a24a87d4574c649b77ec4075d Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 20 May 2010 13:43:13 -0700 Subject: removes the icache and pipelines the reads --- usrp2/control_lib/ram_harvard.v | 71 +++++++++++++++++++++++++ usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v | 5 +- usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v | 27 ++++++---- usrp2/top/u2_core/u2_core.v | 10 ++-- usrp2/top/u2_rev3/Makefile | 1 + 5 files changed, 98 insertions(+), 16 deletions(-) create mode 100644 usrp2/control_lib/ram_harvard.v diff --git a/usrp2/control_lib/ram_harvard.v b/usrp2/control_lib/ram_harvard.v new file mode 100644 index 000000000..6711da366 --- /dev/null +++ b/usrp2/control_lib/ram_harvard.v @@ -0,0 +1,71 @@ + + +// Dual ported, Harvard architecture, cached ram + +module ram_harvard + #(parameter AWIDTH=15, + parameter RAM_SIZE=16384, + parameter ICWIDTH=6, + parameter DCWIDTH=6) + + (input wb_clk_i, + input wb_rst_i, + // Firmware download port. + input [AWIDTH-1:0] ram_loader_adr_i, + input [31:0] ram_loader_dat_i, + input ram_loader_stb_i, + input [3:0] ram_loader_sel_i, + input ram_loader_we_i, + output ram_loader_ack_o, + input ram_loader_done_i, + // Instruction fetch port. + input [AWIDTH-1:0] if_adr, + output [31:0] if_data, + // Data access port. + input [AWIDTH-1:0] dwb_adr_i, + input [31:0] dwb_dat_i, + output [31:0] dwb_dat_o, + input dwb_we_i, + output dwb_ack_o, + input dwb_stb_i, + input [3:0] dwb_sel_i, + + input flush_icache ); + + reg ack_d1; + reg stb_d1; + + + dpram32 #(.AWIDTH(AWIDTH),.RAM_SIZE(RAM_SIZE)) + sys_ram + (.clk(wb_clk_i), + .adr1_i(ram_loader_done_i ? if_adr : ram_loader_adr_i), + .dat1_i(ram_loader_dat_i), + .dat1_o(if_data), + .we1_i(ram_loader_done_i ? 1'b0 : ram_loader_we_i), + .en1_i(ram_loader_done_i ? 1'b1 : ram_loader_stb_i), + .sel1_i(ram_loader_done_i ? 4'hF : ram_loader_sel_i), + .adr2_i(dwb_adr_i), + .dat2_i(dwb_dat_i), + .dat2_o(dwb_dat_o), + .we2_i(dwb_we_i), + .en2_i(dwb_stb_i), + .sel2_i(dwb_sel_i) + ); + + assign dwb_ack_o = dwb_stb_i & (dwb_we_i | (stb_d1 & ~ack_d1)); + + always @(posedge wb_clk_i) + if(wb_rst_i) + ack_d1 <= 1'b0; + else + ack_d1 <= dwb_ack_o; + + always @(posedge wb_clk_i) + if(wb_rst_i) + stb_d1 <= 0; + else + stb_d1 <= dwb_stb_i; + + +endmodule // ram_harv_cache diff --git a/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v b/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v index a7c686e7e..81587e25c 100644 --- a/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v +++ b/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v @@ -125,7 +125,7 @@ module aeMB_bpcu (/*AUTOARG*/ reg [31:2] rPC, xPC; reg [31:2] rPCLNK, xPCLNK; - assign iwb_adr_o = rIPC[IW-1:2]; + assign iwb_adr_o = gena ? xIPC[IW-1:2] : rIPC[IW-1:2]; //IJB always @(/*AUTOSENSE*/rBRA or rIPC or rPC or rRESULT) begin //xPCLNK <= (^rATOM) ? rPC : rPC; @@ -168,7 +168,8 @@ module aeMB_bpcu (/*AUTOARG*/ rATOM <= 2'h0; rBRA <= 1'h0; rDLY <= 1'h0; - rIPC <= 30'h0; +// rIPC <= 30'h0; + rIPC <= 30'h3fffffff; // DWORD aligned address rPC <= 30'h0; rPCLNK <= 30'h0; // End of automatics diff --git a/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v b/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v index 9ffa20ff2..38ca3a023 100644 --- a/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v +++ b/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v @@ -10,12 +10,10 @@ module aeMB_core_BE parameter MUL=0, parameter BSF=0) (input sys_clk_i, input sys_rst_i, - - output iwb_stb_o, - output [ISIZ-1:0] iwb_adr_o, - input [31:0] iwb_dat_i, - input iwb_ack_i, - + // Instruction port + output [14:0] if_adr, + input [31:0] if_dat, + // Data port output dwb_we_o, output dwb_stb_o, output [DSIZ-1:0] dwb_adr_o, @@ -28,17 +26,28 @@ module aeMB_core_BE input sys_int_i, input sys_exc_i); - assign dwb_cyc_o = dwb_stb_o; + wire [ISIZ-1:0] iwb_adr_o; + wire [31:0] iwb_dat_i; + wire iwb_ack_i; + wire iwb_stb_o; + + assign dwb_cyc_o = dwb_stb_o; + assign iwb_ack_i = 1'b1; + assign if_adr = iwb_adr_o[14:0]; + assign iwb_dat_i = if_dat; + + // Note some "wishbone" instruction fetch signals pruned on external interface + // but not propogated change deep into aeMB. aeMB_edk32 #(.IW(ISIZ),.DW(DSIZ),.MUL(MUL),.BSF(BSF)) aeMB_edk32 (.sys_clk_i(sys_clk_i), .sys_rst_i(sys_rst_i), - + // Instruction Port .iwb_stb_o(iwb_stb_o), .iwb_adr_o(iwb_adr_o[ISIZ-1:2]), .iwb_ack_i(iwb_ack_i), .iwb_dat_i(iwb_dat_i), - + // Data port .dwb_wre_o(dwb_we_o), .dwb_stb_o(dwb_stb_o), .dwb_adr_o(dwb_adr_o[DSIZ-1:2]), diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v index df74c7dba..5e0b569cc 100755 --- a/usrp2/top/u2_core/u2_core.v +++ b/usrp2/top/u2_core/u2_core.v @@ -284,8 +284,8 @@ module u2_core aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), // Instruction Wishbone bus to I-RAM - .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), - .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), + .if_adr(if_adr), + .if_dat(if_dat), // Data Wishbone bus to system bus fabric .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), @@ -299,7 +299,7 @@ module u2_core // I-port connects directly to processor and ram loader wire flush_icache; - ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) + ram_harvard #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), @@ -307,8 +307,8 @@ module u2_core .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), .ram_loader_done_i(ram_loader_done), - .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), - .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), + .if_adr(if_adr), + .if_data(if_dat), .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile index 80d09acb7..bfebcac8b 100644 --- a/usrp2/top/u2_rev3/Makefile +++ b/usrp2/top/u2_rev3/Makefile @@ -66,6 +66,7 @@ control_lib/mux4.v \ control_lib/mux8.v \ control_lib/nsgpio.v \ control_lib/ram_2port.v \ +control_lib/ram_harvard.v \ control_lib/ram_harv_cache.v \ control_lib/ram_loader.v \ control_lib/setting_reg.v \ -- cgit v1.2.3 From 1d38c098122746ff34c0c1f16668b44d7337175d Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 20 May 2010 16:48:59 -0700 Subject: send bigger packets to reduce cpu load --- usrp2/control_lib/newfifo/packet_generator.v | 2 +- usrp2/top/u1e/u1e_core.v | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/usrp2/control_lib/newfifo/packet_generator.v b/usrp2/control_lib/newfifo/packet_generator.v index e5bfe5b26..6e8b45ccd 100644 --- a/usrp2/control_lib/newfifo/packet_generator.v +++ b/usrp2/control_lib/newfifo/packet_generator.v @@ -5,7 +5,7 @@ module packet_generator output reg [7:0] data_o, output sof_o, output eof_o, output src_rdy_o, input dst_rdy_i); - localparam len = 32'd100; + localparam len = 32'd2000; reg [31:0] state; reg [31:0] seq; diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 48b5bd010..ee193ffb9 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -43,6 +43,7 @@ module u1e_core wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy; reg [15:0] tx_frame_len; wire [15:0] rx_frame_len; + wire [7:0] rate; wire bus_error; @@ -76,7 +77,6 @@ module u1e_core `endif // LOOPBACK `ifdef TIMED - wire [7:0] rate; // TX side wire tx_enable, tx_src_rdy_int, tx_dst_rdy_int; @@ -362,7 +362,7 @@ module u1e_core assign debug_clk = { EM_CLK, clk_fpga }; assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, rx_overrun, tx_underrun }, - { EM_A[8:1] }, + { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int }, { EM_D } }; //assign debug = { phase[23:8], txsync, txblank, tx }; -- cgit v1.2.3 From 96ef5b171b44956f44e02672af8a734f3c0e38c4 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Fri, 21 May 2010 10:14:03 -0400 Subject: OK, now crc uses the timed interface to set the data rate. Revert "Revert "Revert "Update test program to reflect what is in the FPGA image.""" This reverts commit b5dfe74e991d240f0e666dfd521726ec61128eb8. Conflicts: host/apps/omap_debug/usrp-e-crc-rw.c --- host/apps/omap_debug/usrp-e-crc-rw.c | 42 ++++++++++++++++++------------------ 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-crc-rw.c b/host/apps/omap_debug/usrp-e-crc-rw.c index e1d9bf0db..b0982de86 100644 --- a/host/apps/omap_debug/usrp-e-crc-rw.c +++ b/host/apps/omap_debug/usrp-e-crc-rw.c @@ -183,43 +183,43 @@ int main(int argc, char *argv[]) { pthread_t tx, rx; long int t; + int fpga_config_flag ,decimation; struct usrp_e_ctl16 d; struct sched_param s = { .sched_priority = 1 }; - int read, write; - if (argc < 2) { - printf("%s r|w|rw tx_data_size\n", argv[0]); + if (argc < 4) { + printf("%s t|w|rw decimation data_size\n", argv[0]); return -1; } - packet_data_length = atoi(argv[2]); + decimation = atoi(argv[2]); + packet_data_length = atoi(argv[3]); - if (strcmp(argv[1], "r") == 0) { - read = 1; - write = 0; - } + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); - if (strcmp(argv[1], "w") == 0) { - read = 0; - write = 1; - } + fpga_config_flag = 0; + if (strcmp(argv[1], "w") == 0) + fpga_config_flag |= (1 << 15); + else if (strcmp(argv[1], "r") == 0) + fpga_config_flag |= (1 << 14); + else if (strcmp(argv[1], "rw") == 0) + fpga_config_flag |= ((1 << 15) | (1 << 14)); - if (strcmp(argv[1], "rw") == 0) { - read = 1; - write = 1; - } + fpga_config_flag |= decimation; - printf("About to open /dev/usrp_e0"); - fp = open("/dev/usrp_e0", O_RDWR); - printf("fp = %d\n", fp); + d.offset = 14; + d.count = 1; + d.buf[0] = fpga_config_flag; + ioctl(fp, USRP_E_WRITE_CTL16, &d); sleep(1); // in case the kernel threads need time to start. FIXME if so // sched_setscheduler(0, SCHED_RR, &s); - if (read) { + if (fpga_config_flag & (1 << 14)) { if (pthread_create(&rx, NULL, read_thread, (void *) t)) { printf("Failed to create rx thread\n"); exit(-1); @@ -228,7 +228,7 @@ int main(int argc, char *argv[]) sleep(1); - if (write) { + if (fpga_config_flag & (1 << 15)) { if (pthread_create(&tx, NULL, write_thread, (void *) t)) { printf("Failed to create tx thread\n"); exit(-1); -- cgit v1.2.3 From 85e32e298217a16102d25a455d605c55a05e369c Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Fri, 21 May 2010 21:13:25 +0000 Subject: Work on crc testing program. Currently dumps first received packet to the screen. Started to reduce teh number of warnings. --- host/apps/omap_debug/usrp-e-crc-rw.c | 46 ++++++++++++++++++++++++++++-------- 1 file changed, 36 insertions(+), 10 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-crc-rw.c b/host/apps/omap_debug/usrp-e-crc-rw.c index b0982de86..8883366ae 100644 --- a/host/apps/omap_debug/usrp-e-crc-rw.c +++ b/host/apps/omap_debug/usrp-e-crc-rw.c @@ -1,5 +1,8 @@ #include #include +#include +#include +#include #include #include #include @@ -34,6 +37,8 @@ static u_int32_t chksum_crc32_gentab(void) } crc_tab[i] = crc; } + + return 0; } static void *read_thread(void *threadid) @@ -47,6 +52,9 @@ static void *read_thread(void *threadid) unsigned long bytes_transfered, elapsed_seconds; struct timeval start_time, finish_time; + __u8 *p; + __u32 *pi; + printf("Greetings from the reading thread!\n"); // IMPORTANT: must assume max length packet from fpga @@ -81,12 +89,24 @@ static void *read_thread(void *threadid) crc = ((crc >> 8) & 0x00FFFFFF) ^ crc_tab[(crc ^ rx_data->buf[i]) & 0xFF]; } - - rx_crc = *((int *) &rx_data[rx_data->len - 4]); - + + p = &rx_data->buf[rx_data->len - 4]; + pi = (__u32 *) p; + rx_crc = *pi; + +#if 1 + printf("rx_data->len = %d\n", rx_data->len); + printf("rx_data->flags = %d\n", rx_data->flags); + for (i = 0; i < rx_data->len; i++) + printf("idx = %d, data = %X\n", i, rx_data->buf[i]); + printf("calc crc = %lX, rx crc = %X\n", crc, rx_crc); + fflush(stdout); + break; +#endif + if (rx_crc != (crc & 0xFFFFFFFF)) { - printf("CRC Error, sent: %d, rx: %d\n", - rx_crc, (crc & 0xFFFFFFFF)); + printf("CRC Error, calc crc: %X, rx_crc: %X\n", + (crc & 0xFFFFFFFF), rx_crc); } bytes_transfered += rx_data->len; @@ -95,8 +115,9 @@ static void *read_thread(void *threadid) gettimeofday(&finish_time, NULL); elapsed_seconds = finish_time.tv_sec - start_time.tv_sec; - printf("RX data transfer rate = %f K Bps\n", - (float) bytes_transfered / (float) elapsed_seconds / 1000); + printf("Bytes transfered = %ld, elapsed seconds = %ld\n", bytes_transfered, elapsed_seconds); + printf("RX data transfer rate = %f K Samples/second\n", + (float) bytes_transfered / (float) elapsed_seconds / 250); start_time = finish_time; @@ -166,8 +187,9 @@ static void *write_thread(void *threadid) gettimeofday(&finish_time, NULL); elapsed_seconds = finish_time.tv_sec - start_time.tv_sec; - printf("TX data transfer rate = %f K Bps\n", - (float) bytes_transfered / (float) elapsed_seconds / 1000); + printf("Bytes transfered = %d, elapsed seconds = %d\n", bytes_transfered, elapsed_seconds); + printf("TX data transfer rate = %f K Samples/second\n", + (float) bytes_transfered / (float) elapsed_seconds / 250); start_time = finish_time; @@ -194,6 +216,8 @@ int main(int argc, char *argv[]) return -1; } + chksum_crc32_gentab(); + decimation = atoi(argv[2]); packet_data_length = atoi(argv[3]); @@ -217,7 +241,7 @@ int main(int argc, char *argv[]) sleep(1); // in case the kernel threads need time to start. FIXME if so -// sched_setscheduler(0, SCHED_RR, &s); + sched_setscheduler(0, SCHED_RR, &s); if (fpga_config_flag & (1 << 14)) { if (pthread_create(&rx, NULL, read_thread, (void *) t)) { @@ -238,4 +262,6 @@ int main(int argc, char *argv[]) sleep(10000); printf("Done sleeping\n"); + + return 0; } -- cgit v1.2.3 From 268324b62898a916c0ef01e9336c34cd4ae1ff93 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 21 May 2010 15:56:01 -0700 Subject: fix double declaration --- usrp2/control_lib/newfifo/fifo36_to_ll8.v | 1 - 1 file changed, 1 deletion(-) diff --git a/usrp2/control_lib/newfifo/fifo36_to_ll8.v b/usrp2/control_lib/newfifo/fifo36_to_ll8.v index 0dee1dfc6..9604d0e38 100644 --- a/usrp2/control_lib/newfifo/fifo36_to_ll8.v +++ b/usrp2/control_lib/newfifo/fifo36_to_ll8.v @@ -55,6 +55,5 @@ module fifo36_to_ll8 assign advance = ll_src_rdy & ll_dst_rdy; assign f36_dst_rdy_o = advance & ((state==3)|ll_eof); - assign debug = state; endmodule // ll8_to_fifo36 -- cgit v1.2.3 From d3e6f630945076cc9d5fb91e86e1caf0b554ac89 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 21 May 2010 15:56:18 -0700 Subject: fifo36_to_ll8 and fifo pacer need a real fifo between them or they deadlock (by design) --- usrp2/control_lib/newfifo/packet_verifier32.v | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/usrp2/control_lib/newfifo/packet_verifier32.v b/usrp2/control_lib/newfifo/packet_verifier32.v index 065607b6c..06a13d242 100644 --- a/usrp2/control_lib/newfifo/packet_verifier32.v +++ b/usrp2/control_lib/newfifo/packet_verifier32.v @@ -7,10 +7,17 @@ module packet_verifier32 wire [7:0] ll_data; wire ll_sof_n, ll_eof_n, ll_src_rdy_n, ll_dst_rdy; + wire [35:0] data_int; + wire src_rdy_int, dst_rdy_int; + + fifo_short #(.WIDTH(36)) fifo_short + (.clk(clk), .reset(reset), .clear(clear), + .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), + .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int)); fifo36_to_ll8 f36_to_ll8 (.clk(clk), .reset(reset), .clear(clear), - .f36_data(data_i), .f36_src_rdy_i(src_rdy_i), .f36_dst_rdy_o(dst_rdy_o), + .f36_data(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int), .ll_data(ll_data), .ll_sof_n(ll_sof_n), .ll_eof_n(ll_eof_n), .ll_src_rdy_n(ll_src_rdy_n), .ll_dst_rdy_n(~ll_dst_rdy)); -- cgit v1.2.3 From f113ae17863729f05b6ada815b9817cd16001211 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Sun, 23 May 2010 12:58:58 +0000 Subject: Divide by 4 to convert byts/sec to samples/sec. Multiply by 4 is right out. --- host/apps/omap_debug/usrp-e-loopback.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/host/apps/omap_debug/usrp-e-loopback.c b/host/apps/omap_debug/usrp-e-loopback.c index 798bc4b45..177394947 100644 --- a/host/apps/omap_debug/usrp-e-loopback.c +++ b/host/apps/omap_debug/usrp-e-loopback.c @@ -86,7 +86,7 @@ static void *read_thread(void *threadid) elapsed_seconds = finish_time.tv_sec - start_time.tv_sec; printf("RX data transfer rate = %f K Samples/second\n", - (float) bytes_transfered / (float) elapsed_seconds / 250); + (float) bytes_transfered / (float) elapsed_seconds / 4000); start_time = finish_time; -- cgit v1.2.3 From 6f63773d7425dd952c5ca24da618c22c486ae294 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 24 May 2010 11:34:42 -0700 Subject: test full width packets --- usrp2/control_lib/newfifo/packet32_tb.v | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 usrp2/control_lib/newfifo/packet32_tb.v diff --git a/usrp2/control_lib/newfifo/packet32_tb.v b/usrp2/control_lib/newfifo/packet32_tb.v new file mode 100644 index 000000000..82bb09c29 --- /dev/null +++ b/usrp2/control_lib/newfifo/packet32_tb.v @@ -0,0 +1,27 @@ + + +module packet32_tb(); + + wire [35:0] data; + wire src_rdy, dst_rdy; + + wire clear = 0; + reg clk = 0; + reg reset = 1; + + always #10 clk <= ~clk; + initial #1000 reset <= 0; + + initial $dumpfile("packet32_tb.vcd"); + initial $dumpvars(0,packet32_tb); + + wire [31:0] total, crc_err, seq_err, len_err; + + packet_generator32 pkt_gen (.clk(clk), .reset(reset), .clear(clear), + .data_o(data), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); + + packet_verifier32 pkt_ver (.clk(clk), .reset(reset), .clear(clear), + .data_i(data), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + +endmodule // packet32_tb -- cgit v1.2.3 From d32cedbf00eb342d999832737f9f1ba2109ef2ad Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 24 May 2010 14:21:03 -0700 Subject: fixes from IJB from 5/24. Basically connect unconnected wires. --- usrp2/control_lib/ram_harvard.v | 2 ++ usrp2/top/u2_core/u2_core.v | 5 +++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/usrp2/control_lib/ram_harvard.v b/usrp2/control_lib/ram_harvard.v index 6711da366..3c00f87c7 100644 --- a/usrp2/control_lib/ram_harvard.v +++ b/usrp2/control_lib/ram_harvard.v @@ -36,6 +36,8 @@ module ram_harvard reg stb_d1; + assign ram_loader_ack_o = ram_loader_stb_i; + dpram32 #(.AWIDTH(AWIDTH),.RAM_SIZE(RAM_SIZE)) sys_ram (.clk(wb_clk_i), diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v index 5e0b569cc..600bd7f3f 100755 --- a/usrp2/top/u2_core/u2_core.v +++ b/usrp2/top/u2_core/u2_core.v @@ -259,8 +259,9 @@ module u2_core // /////////////////////////////////////////////////////////////////// // RAM Loader - wire [31:0] ram_loader_dat, iwb_dat; - wire [15:0] ram_loader_adr, iwb_adr; + wire [31:0] ram_loader_dat, if_dat; + wire [15:0] ram_loader_adr; + wire [14:0] if_adr; wire [3:0] ram_loader_sel; wire ram_loader_stb, ram_loader_we, ram_loader_ack; wire iwb_ack, iwb_stb; -- cgit v1.2.3 From a1284e5d02fbb9e0b7cf541a9ffe501707d37c8c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 26 May 2010 18:45:01 -0700 Subject: experimental mods to make ram loader fully synchronous. Based on IJB's work --- usrp2/control_lib/ram_harvard.v | 12 +- usrp2/control_lib/ram_loader.v | 460 ++++++++++++++++++++++------------------ usrp2/top/u2_core/u2_core.v | 29 ++- 3 files changed, 266 insertions(+), 235 deletions(-) diff --git a/usrp2/control_lib/ram_harvard.v b/usrp2/control_lib/ram_harvard.v index 3c00f87c7..948f9b36f 100644 --- a/usrp2/control_lib/ram_harvard.v +++ b/usrp2/control_lib/ram_harvard.v @@ -13,10 +13,9 @@ module ram_harvard // Firmware download port. input [AWIDTH-1:0] ram_loader_adr_i, input [31:0] ram_loader_dat_i, - input ram_loader_stb_i, input [3:0] ram_loader_sel_i, + input ram_loader_stb_i, input ram_loader_we_i, - output ram_loader_ack_o, input ram_loader_done_i, // Instruction fetch port. input [AWIDTH-1:0] if_adr, @@ -35,9 +34,6 @@ module ram_harvard reg ack_d1; reg stb_d1; - - assign ram_loader_ack_o = ram_loader_stb_i; - dpram32 #(.AWIDTH(AWIDTH),.RAM_SIZE(RAM_SIZE)) sys_ram (.clk(wb_clk_i), @@ -46,7 +42,8 @@ module ram_harvard .dat1_o(if_data), .we1_i(ram_loader_done_i ? 1'b0 : ram_loader_we_i), .en1_i(ram_loader_done_i ? 1'b1 : ram_loader_stb_i), - .sel1_i(ram_loader_done_i ? 4'hF : ram_loader_sel_i), + //.sel1_i(ram_loader_done_i ? 4'hF : ram_loader_sel_i), + .sel1_i(ram_loader_sel_i), // Sel is only for writes anyway .adr2_i(dwb_adr_i), .dat2_i(dwb_dat_i), .dat2_o(dwb_dat_o), @@ -68,6 +65,5 @@ module ram_harvard stb_d1 <= 0; else stb_d1 <= dwb_stb_i; - -endmodule // ram_harv_cache +endmodule // ram_harvard diff --git a/usrp2/control_lib/ram_loader.v b/usrp2/control_lib/ram_loader.v index cb67de739..c53ea7aa7 100644 --- a/usrp2/control_lib/ram_loader.v +++ b/usrp2/control_lib/ram_loader.v @@ -1,225 +1,261 @@ +module ram_loader + #(parameter AWIDTH=16, RAM_SIZE=16384) + ( + // Wishbone I/F and clock domain + input wb_clk, + input dsp_clk, + input ram_loader_rst, + output wire [31:0] wb_dat, + output wire [AWIDTH-1:0] wb_adr, + output wb_stb, + output reg [3:0] wb_sel, + output wb_we, + output reg ram_loader_done, + // CPLD signals and clock domain + input cpld_clk, + input cpld_din, + output reg cpld_start, + output reg cpld_mode, + output reg cpld_done, + input cpld_detached + ); -// Adapted from VHDL code in spi_boot by Arnim Legauer -// Added a full wishbone master interface (32-bit) - -module ram_loader #(parameter AWIDTH=16, RAM_SIZE=16384) - (input clk_i, input rst_i, - // CPLD Interface - input cfg_clk_i, input cfg_data_i, - output start_o, output mode_o, output done_o, - input detached_i, - // Wishbone interface - output wire [31:0] wb_dat_o, - output reg [AWIDTH-1:0] wb_adr_o, - output wb_stb_o, - output wb_cyc_o, - output reg [3:0] wb_sel_o, - output reg wb_we_o, - input wb_ack_i, - output ram_loader_done_o); + localparam S0 = 0; + localparam S1 = 1; + localparam S2 = 2; + localparam S3 = 3; + localparam S4 = 4; + localparam S5 = 5; + localparam S6 = 6; + localparam RESET = 7; - // FSM to control start signal, clocked on main clock - localparam FSM1_WAIT_DETACH = 2'b00; - localparam FSM1_CHECK_NO_DONE = 2'b01; - localparam FSM1_WAIT_DONE = 2'b10; - - reg [1:0] start_fsm_q, start_fsm_s; - reg start_q, enable_q, start_s, enable_s; - reg done_q, done_s; + localparam WB_IDLE = 0; + localparam WB_WRITE = 1; + + + reg [AWIDTH+2:0] count; // 3 LSB's count bits in, the MSB's generate the Wishbone address + reg [6:0] shift_reg; + reg [7:0] data_reg; + reg sampled_clk; + reg sampled_clk_meta; + reg sampled_din; + reg inc_count; + reg load_data_reg; + reg shift; + reg wb_state, wb_next_state; + reg [2:0] state, next_state; + + // + // CPLD clock doesn't free run and is approximately 12.5MHz. + // Use 50MHz Wishbone clock to sample it as a signal and avoid having + // an extra clock domain for no reason. + // + + always @(posedge dsp_clk or posedge ram_loader_rst) + if (ram_loader_rst) + begin + sampled_clk_meta <= 1'b0; + sampled_clk <= 1'b0; + sampled_din <= 1'b0; + count <= 'h7FFF8; // Initialize so that address will be 0 when first byte fully received. + data_reg <= 0; + shift_reg <= 0; + end + else + begin + sampled_clk_meta <= cpld_clk; + sampled_clk <= sampled_clk_meta; + sampled_din <= cpld_din; + if (inc_count) + count <= count + 1'b1; + if (load_data_reg) + data_reg <= {shift_reg,sampled_din}; + if (shift) + shift_reg <= {shift_reg[5:0],sampled_din}; + end // else: !if(ram_loader_rst) - always @(posedge clk_i or posedge rst_i) - if(rst_i) - begin - start_fsm_q <= FSM1_WAIT_DETACH; - start_q <= 1'b0; - enable_q <= 1'b0; - end + + always @(posedge dsp_clk or posedge ram_loader_rst) + if (ram_loader_rst) + state <= RESET; else - begin - start_fsm_q <= start_fsm_s; - enable_q <= enable_s; - start_q <= start_s; - end // else: !if(rst_i) - + state <= next_state; + + always @* - case(start_fsm_q) - FSM1_WAIT_DETACH: - if(detached_i == 1'b1) - begin - start_fsm_s <= FSM1_CHECK_NO_DONE; - enable_s <= 1'b1; - start_s <= 1'b1; - end - else - begin - start_fsm_s <= FSM1_WAIT_DETACH; - enable_s <= enable_q; - start_s <= start_q; - end // else: !if(detached_i == 1'b1) - FSM1_CHECK_NO_DONE: - if(~done_q) - begin - start_fsm_s <= FSM1_WAIT_DONE; - enable_s <= enable_q; - start_s <= start_q; - end - else - begin - start_fsm_s <= FSM1_CHECK_NO_DONE; - enable_s <= enable_q; - start_s <= start_q; - end // else: !if(~done_q) - FSM1_WAIT_DONE: - if(done_q) - begin - start_fsm_s <= FSM1_WAIT_DETACH; - enable_s <= 1'b0; - start_s <= 1'b0; - end - else - begin - start_fsm_s <= FSM1_WAIT_DONE; - enable_s <= enable_q; - start_s <= start_q; - end // else: !if(done_q) - default: - begin - start_fsm_s <= FSM1_WAIT_DETACH; - enable_s <= enable_q; - start_s <= start_q; - end // else: !if(done_q) - endcase // case(start_fsm_q) - - // FSM running on data clock - - localparam FSM2_IDLE = 3'b000; - localparam FSM2_WE_ON = 3'b001; - localparam FSM2_WE_OFF = 3'b010; - localparam FSM2_INC_ADDR1 = 3'b011; - localparam FSM2_INC_ADDR2 = 3'b100; - localparam FSM2_FINISHED = 3'b101; - - reg [AWIDTH-1:0] addr_q; - reg [7:0] shift_dat_q, ser_dat_q; - reg [2:0] bit_q, fsm_q, fsm_s; - reg bit_ovfl_q, ram_we_s, ram_we_q, mode_q, mode_s, inc_addr_s; - - always @(posedge cfg_clk_i or posedge rst_i) - if(rst_i) - begin - addr_q <= 0; - shift_dat_q <= 8'd0; - ser_dat_q <= 8'd0; - bit_q <= 3'd0; - bit_ovfl_q <= 1'b0; - fsm_q <= FSM2_IDLE; - ram_we_q <= 1'b0; - done_q <= 1'b0; - mode_q <= 1'b0; - end + begin + // Defaults + next_state = state; + cpld_start = 1'b0; + shift = 1'b0; + inc_count = 0; + load_data_reg = 1'b0; + ram_loader_done = 1'b0; + cpld_mode = 1'b0; + cpld_done = 1'b1; + + + + case (state) //synthesis parallel_case full_case + // After reset wait until CPLD indicates its detached. + RESET: begin + if (cpld_detached) + next_state = S0; + else + next_state = RESET; + end + + // Assert cpld_start to signal the CPLD its to start sending serial clock and data. + // Assume cpld_clk is low as we transition into search for first rising edge + S0: begin + cpld_start = 1'b1; + cpld_done = 1'b0; + if (~cpld_detached) + next_state = S2; + else + next_state = S0; + end + + // + S1: begin + cpld_start = 1'b1; + cpld_done = 1'b0; + if (sampled_clk) + begin + // Found rising edge on cpld_clk. + if (count[2:0] == 3'b111) + // Its the last bit of a byte, send it out to the Wishbone bus. + begin + load_data_reg = 1'b1; + inc_count = 1'b1; + end + else + // Shift databit into LSB of shift register and increment count + begin + shift = 1'b1; + inc_count = 1'b1; + end // else: !if(count[2:0] == 3'b111) + next_state = S2; + end // if (sampled_clk) + else + next_state = S1; + end // case: S1 + + // + S2: begin + cpld_start = 1'b1; + cpld_done = 1'b0; + if (~sampled_clk) + // Found negative edge of clock + if (count[AWIDTH+2:3] == RAM_SIZE-1) // NOTE need to change this constant + // All firmware now downloaded + next_state = S3; + else + next_state = S1; + else + next_state = S2; + end // case: S2 + + // Now that terminal count is reached and all firmware is downloaded signal CPLD that download is done + // and that mode is now SPI mode. + S3: begin + if (sampled_clk) + begin + cpld_mode = 1'b1; + cpld_done = 1'b1; + next_state = S4; + end + else + next_state = S3; + end + + // Search for negedge of cpld_clk whilst keeping done sequence asserted. + // Keep done assserted + S4: begin + cpld_mode = 1'b1; + cpld_done = 1'b1; + if (~sampled_clk) + next_state = S5; + else + next_state = S4; + end + + // Search for posedge of cpld_clk whilst keeping done sequence asserted. + S5: begin + cpld_mode = 1'b1; + cpld_done = 1'b1; + if (sampled_clk) + next_state = S6; + else + next_state = S5; + end + + // Stay in this state until reset/power down + S6: begin + ram_loader_done = 1'b1; + cpld_done = 1'b1; + cpld_mode = 1'b1; + next_state = S6; + end + + endcase // case(state) + end + + always @(posedge dsp_clk or posedge ram_loader_rst) + if (ram_loader_rst) + wb_state <= WB_IDLE; else - begin - if(inc_addr_s) - addr_q <= addr_q + 1; - if(enable_q) - begin - bit_q <= bit_q + 1; - bit_ovfl_q <= (bit_q == 3'd7); - shift_dat_q[0] <= cfg_data_i; - shift_dat_q[7:1] <= shift_dat_q[6:0]; - end - if(bit_ovfl_q) - ser_dat_q <= shift_dat_q; - - fsm_q <= fsm_s; - - ram_we_q <= ram_we_s; - - if(done_s) - done_q <= 1'b1; - mode_q <= mode_s; - end // else: !if(rst_i) + wb_state <= wb_next_state; + reg do_write; + wire empty, full; + always @* begin - inc_addr_s <= 1'b0; - ram_we_s <= 1'b0; - done_s <= 1'b0; - fsm_s <= FSM2_IDLE; - mode_s <= 1'b0; - - case(fsm_q) - FSM2_IDLE : - if(start_q) - if(bit_ovfl_q) - fsm_s <= FSM2_WE_ON; - FSM2_WE_ON: - begin - ram_we_s <= 1'b1; - fsm_s <= FSM2_WE_OFF; - end - FSM2_WE_OFF: - begin - ram_we_s <= 1'b1; - fsm_s <= FSM2_INC_ADDR1; - end - FSM2_INC_ADDR1: - fsm_s <= FSM2_INC_ADDR2; - FSM2_INC_ADDR2: - if(addr_q == (RAM_SIZE-1)) - //if(&addr_q) - begin - fsm_s <= FSM2_FINISHED; - done_s <= 1'b1; - mode_s <= 1'b1; - end - else - begin - inc_addr_s <= 1'b1; - fsm_s <= FSM2_IDLE; - end // else: !if(&addr_q) - FSM2_FINISHED: - begin - fsm_s <= FSM2_FINISHED; - mode_s <= 1'b1; - end - endcase // case(fsm_q) + wb_next_state = wb_state; + do_write = 1'b0; + + case (wb_state) //synthesis full_case parallel_case + // + WB_IDLE: begin + if (load_data_reg) + // Data reg will load ready to write wishbone @ next clock edge + wb_next_state = WB_WRITE; + else + wb_next_state = WB_IDLE; + end + + // Drive address and data onto wishbone. + WB_WRITE: begin + do_write = 1'b1; + if (~full) + wb_next_state = WB_IDLE; + else + wb_next_state = WB_WRITE; + end + + endcase // case(wb_state) end // always @ * - assign start_o = start_q; - assign mode_o = mode_q; - assign done_o = start_q ? done_q : 1'b1; - wire [AWIDTH-1:0] ram_addr = addr_q; - wire [7:0] ram_data = ser_dat_q; - assign ram_loader_done_o = (fsm_q == FSM2_FINISHED); - - // wishbone master, only writes - reg [7:0] dat_holder; - assign wb_dat_o = {4{dat_holder}}; - assign wb_stb_o = wb_we_o; - assign wb_cyc_o = wb_we_o; + wire [1:0] count_out; + wire [7:0] data_out; + + fifo_xlnx_16x40_2clk crossclk + (.rst(ram_loader_rst), + .wr_clk(dsp_clk), .din({count[4:3],count[AWIDTH+2:3],data_reg}), .wr_en(do_write), .full(full), + .rd_clk(wb_clk), .dout({count_out,wb_adr,data_out}), .rd_en(~empty), .empty(empty)); + + assign wb_dat = {4{data_out}}; + + always @* + case(count_out[1:0]) //synthesis parallel_case full_case + 2'b00 : wb_sel = 4'b1000; + 2'b01 : wb_sel = 4'b0100; + 2'b10 : wb_sel = 4'b0010; + 2'b11 : wb_sel = 4'b0001; + endcase + + assign wb_we = ~empty; + assign wb_stb = ~empty; - always @(posedge clk_i or posedge rst_i) - if(rst_i) - begin - dat_holder <= 8'd0; - wb_adr_o <= 0; - wb_sel_o <= 4'b0000; - wb_we_o <= 1'b0; - end - else if(ram_we_q) - begin - dat_holder <= ram_data; - wb_adr_o <= ram_addr; - wb_we_o <= 1'b1; - case(ram_addr[1:0]) // Big Endian - 2'b00 : wb_sel_o <= 4'b1000; - 2'b01 : wb_sel_o <= 4'b0100; - 2'b10 : wb_sel_o <= 4'b0010; - 2'b11 : wb_sel_o <= 4'b0001; - endcase // case(ram_addr[1:0]) - end // if (ram_we_q) - else if(wb_ack_i) - wb_we_o <= 1'b0; - endmodule // ram_loader diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v index 600bd7f3f..a90e2ced6 100755 --- a/usrp2/top/u2_core/u2_core.v +++ b/usrp2/top/u2_core/u2_core.v @@ -263,23 +263,22 @@ module u2_core wire [15:0] ram_loader_adr; wire [14:0] if_adr; wire [3:0] ram_loader_sel; - wire ram_loader_stb, ram_loader_we, ram_loader_ack; + wire ram_loader_stb, ram_loader_we; wire iwb_ack, iwb_stb; ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) - ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), + ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst), + .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr), + .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel), + .wb_we(ram_loader_we), + .ram_loader_done(ram_loader_done), // CPLD Interface - .cfg_clk_i(cpld_clk), - .cfg_data_i(cpld_din), - .start_o(cpld_start_int), - .mode_o(cpld_mode_int), - .done_o(cpld_done_int), - .detached_i(cpld_detached), - // Wishbone Interface - .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), - .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), - .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), - .ram_loader_done_o(ram_loader_done)); - + .cpld_clk(cpld_clk), + .cpld_din(cpld_din), + .cpld_start(cpld_start_int), + .cpld_mode(cpld_mode_int), + .cpld_done(cpld_done_int), + .cpld_detached(cpld_detached)); + // ///////////////////////////////////////////////////////////////////////// // Processor aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) @@ -305,7 +304,7 @@ module u2_core .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), - .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), + .ram_loader_we_i(ram_loader_we), .ram_loader_done_i(ram_loader_done), .if_adr(if_adr), -- cgit v1.2.3 From 1c8fc02f8787b8f809335d18a6691c2d7510be9a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 26 May 2010 18:45:46 -0700 Subject: change the debug pins, which makes it more reliable. This is unnerving. --- usrp2/top/u2_core/u2_core.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_core/u2_core.v index 600bd7f3f..fc2e10d52 100755 --- a/usrp2/top/u2_core/u2_core.v +++ b/usrp2/top/u2_core/u2_core.v @@ -683,7 +683,8 @@ module u2_core { wr2_flags, rd2_flags }, { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; - assign debug_gpio_0 = debug_mac; //eth_mac_debug; + assign debug_gpio_0 = 0; + //debug_mac; //eth_mac_debug; assign debug_gpio_1 = 0; endmodule // u2_core -- cgit v1.2.3 From ac62d187cc7a4adde65c1e6fb1807ec5a967f966 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 28 May 2010 17:41:01 +0000 Subject: reverted usrp-e-led sorry --- host/apps/omap_debug/usrp-e-led.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-led.c b/host/apps/omap_debug/usrp-e-led.c index 30fbb66e0..d1b6c8996 100644 --- a/host/apps/omap_debug/usrp-e-led.c +++ b/host/apps/omap_debug/usrp-e-led.c @@ -20,16 +20,16 @@ int main(int argc, char *argv[]) fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); - d.offset = UE_REG_MISC_BASE+14; + d.offset = UE_REG_MISC_BASE; d.count = 1; - d.buf[0] = 0x4020; - ret = ioctl(fp, USRP_E_WRITE_CTL16, &d); - - sleep(10); - - d.buf[0] = 0x0; - ret = ioctl(fp, USRP_E_WRITE_CTL16, &d); + while (1) { + for (i=0; i<8; i++) { + d.buf[0] = i; + ret = ioctl(fp, USRP_E_WRITE_CTL16, &d); + sleep(1); + } + } return 0; } -- cgit v1.2.3 From 2d45c8537171f8a82baf13674fbe9ccefa2cc0c0 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 1 Jun 2010 10:18:13 -0700 Subject: zero out debug pins. helps timing a little bit. --- usrp2/top/u2_core/u2_core_udp.v | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/usrp2/top/u2_core/u2_core_udp.v b/usrp2/top/u2_core/u2_core_udp.v index 1fe3aafd8..d2e842b1c 100644 --- a/usrp2/top/u2_core/u2_core_udp.v +++ b/usrp2/top/u2_core/u2_core_udp.v @@ -729,7 +729,15 @@ module u2_core // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins + + assign debug_clk[1:0] = 2'b00; + assign debug = 32'd0; + assign debug_gpio_0 = 32'd0; + assign debug_gpio_1 = 32'd0; +endmodule // u2_core + + /* // FIFO Level Debugging reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo; @@ -756,15 +764,12 @@ module u2_core assign debug_clk[0] = GMII_RX_CLK; // wb_clk; assign debug_clk[1] = dsp_clk; -/* - wire mdio_cpy = MDIO; assign debug = { { 1'b0, s6_stb, s6_ack, s6_we, s6_sel[3:0] }, { s6_adr[15:8] }, { s6_adr[7:0] }, { 6'd0, mdio_cpy, MDC } }; -*/ -/* + assign debug = { { GMII_TXD }, { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK }, { wr2_flags, rd2_flags }, @@ -773,9 +778,8 @@ module u2_core { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK }, { wr2_flags, rd2_flags }, { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } }; - */ -// assign debug = debug_udp; + assign debug = debug_udp; assign debug = vrc_debug; assign debug_gpio_0 = { {pps_in, pps_int, 2'd0, vita_state}, {2'd0, rx_dst_rdy, rx_src_rdy, rx_data[99:96]}, @@ -784,14 +788,12 @@ module u2_core assign debug_gpio_1 = {vita_time[63:32] }; -/* - assign debug_gpio_1 = { { tx_f19_data[15:8] }, + assign debug_gpio_1 = { { tx_f19_data[15:8] }, { tx_f19_data[7:0] }, { 3'd0, tx_f19_src_rdy, tx_f19_dst_rdy, tx_f19_data[18:16] }, { 2'b0, rd2_ready_i, rd2_ready_o, rd2_flags } }; */ -endmodule // u2_core // wire debug_mux; // setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), -- cgit v1.2.3 From e5bc7a493252753ad9ddf6799e986fa19841221a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 1 Jun 2010 15:50:06 -0700 Subject: vita49 tx and rx added in, all sample rates now at main system clock rate. --- usrp2/top/u1e/Makefile | 5 ++ usrp2/top/u1e/u1e.ucf | 50 ++++++------ usrp2/top/u1e/u1e.v | 68 ++++++++++++++-- usrp2/top/u1e/u1e_core.v | 204 ++++++++++++++++++++++++++++++----------------- 4 files changed, 220 insertions(+), 107 deletions(-) diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 0277ef4f2..7f5085275 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -189,6 +189,11 @@ gpmc/gpmc_to_fifo_async.v \ gpmc/fifo_to_gpmc_async.v \ gpmc/fifo_watcher.v \ gpmc/gpmc_wb.v \ +vrt/vita_rx_control.v \ +vrt/vita_rx_framer.v \ +vrt/vita_tx_control.v \ +vrt/vita_tx_deframer.v \ +timing/time_compare.v \ top/u1e/u1e_core.v \ top/u1e/u1e.ucf \ top/u1e/timing.ucf \ diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 2caa46639..659a9dce5 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -163,33 +163,33 @@ NET "dip_sw<2>" LOC = "J4" ; NET "dip_sw<1>" LOC = "J6" ; NET "dip_sw<0>" LOC = "J7" ; -#NET "RXSYNC" LOC = "F22" ; #NET "reset_codec" LOC = "D22" ; -#NET "DB<11>" LOC = "E22" ; -#NET "DB<10>" LOC = "J19" ; -#NET "DB<9>" LOC = "H20" ; -#NET "DB<8>" LOC = "G19" ; -#NET "DB<7>" LOC = "F20" ; -#NET "DB<6>" LOC = "K16" ; -#NET "DB<5>" LOC = "J17" ; -#NET "DB<4>" LOC = "H22" ; -#NET "DB<3>" LOC = "G22" ; -#NET "DB<2>" LOC = "H17" ; -#NET "DB<1>" LOC = "H18" ; -#NET "DB<0>" LOC = "K20" ; -#NET "DA<11>" LOC = "J20" ; -#NET "DA<10>" LOC = "K19" ; -#NET "DA<9>" LOC = "K18" ; -#NET "DA<8>" LOC = "L22" ; -#NET "DA<7>" LOC = "K22" ; -#NET "DA<6>" LOC = "N22" ; -#NET "DA<5>" LOC = "M22" ; -#NET "DA<4>" LOC = "N20" ; -#NET "DA<3>" LOC = "N19" ; -#NET "DA<2>" LOC = "R22" ; -#NET "DA<1>" LOC = "P22" ; -#NET "DA<0>" LOC = "N17" ; +NET "RXSYNC" LOC = "F22" ; +NET "DB<11>" LOC = "E22" ; +NET "DB<10>" LOC = "J19" ; +NET "DB<9>" LOC = "H20" ; +NET "DB<8>" LOC = "G19" ; +NET "DB<7>" LOC = "F20" ; +NET "DB<6>" LOC = "K16" ; +NET "DB<5>" LOC = "J17" ; +NET "DB<4>" LOC = "H22" ; +NET "DB<3>" LOC = "G22" ; +NET "DB<2>" LOC = "H17" ; +NET "DB<1>" LOC = "H18" ; +NET "DB<0>" LOC = "K20" ; +NET "DA<11>" LOC = "J20" ; +NET "DA<10>" LOC = "K19" ; +NET "DA<9>" LOC = "K18" ; +NET "DA<8>" LOC = "L22" ; +NET "DA<7>" LOC = "K22" ; +NET "DA<6>" LOC = "N22" ; +NET "DA<5>" LOC = "M22" ; +NET "DA<4>" LOC = "N20" ; +NET "DA<3>" LOC = "N19" ; +NET "DA<2>" LOC = "R22" ; +NET "DA<1>" LOC = "P22" ; +NET "DA<0>" LOC = "N17" ; NET "TX<13>" LOC = "P19" ; NET "TX<12>" LOC = "R18" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 35818e8c8..3018ff100 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -26,18 +26,46 @@ module u1e inout [15:0] io_tx, inout [15:0] io_rx, - output [13:0] TX, output TXSYNC, output TXBLANK, - + output reg [13:0] TX, output reg TXSYNC, output TXBLANK, + input [11:0] DA, input [11:0] DB, input RXSYNC, + input PPS_IN ); - // FPGA-specific pins connections - wire clk_fpga; + // ///////////////////////////////////////////////////////////////////////// + // Clocking + wire clk_fpga, clk_fpga_in, clk_2x, dcm_rst, dcm_locked; IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) - clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + + DCM #(.CLK_FEEDBACK ( "1X" ), + .CLKDV_DIVIDE ( 2.0 ), + .CLKFX_DIVIDE ( 1 ), + .CLKFX_MULTIPLY ( 2 ), + .CLKIN_DIVIDE_BY_2 ( "FALSE" ), + .CLKIN_PERIOD ( 15.625 ), + .CLKOUT_PHASE_SHIFT ( "NONE" ), + .DESKEW_ADJUST ( "SYSTEM_SYNCHRONOUS" ), + .DFS_FREQUENCY_MODE ( "LOW" ), + .DLL_FREQUENCY_MODE ( "LOW" ), + .DUTY_CYCLE_CORRECTION ( "TRUE" ), + .FACTORY_JF ( 16'h8080 ), + .PHASE_SHIFT ( 0 ), + .STARTUP_WAIT ( "FALSE" )) + clk_doubler (.CLKFB(clk_fpga), .CLKIN(clk_fpga_in), .RST(dcm_rst), + .DSSEN(0), .PSCLK(0), .PSEN(0), .PSINCDEC(0), .PSDONE(), + .CLKDV(), .CLKFX(), .CLKFX180(), + .CLK2X(clk_2x), .CLK2X180(), + .CLK0(clk_fpga), .CLK90(), .CLK180(), .CLK270(), + .LOCKED(dcm_locked), .STATUS()); + + //BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); + //BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); + - // SPI pins + // ///////////////////////////////////////////////////////////////////////// + // SPI wire mosi, sclk, miso; assign { db_sclk_tx, db_mosi_tx } = ~db_sen_tx ? {sclk,mosi} : 2'b0; assign { db_sclk_rx, db_mosi_rx } = ~db_sen_rx ? {sclk,mosi} : 2'b0; @@ -45,7 +73,27 @@ module u1e assign { cgen_sclk, cgen_mosi } = ~cgen_sen_b ? {sclk,mosi} : 2'b0; assign miso = (~db_sen_tx & db_miso_tx) | (~db_sen_rx & db_miso_rx) | (~sen_codec & miso_codec) | (~cgen_sen_b & cgen_miso); + + // ///////////////////////////////////////////////////////////////////////// + // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL + + assign TXBLANK = 0; + wire [13:0] tx_i, tx_q; + always @(posedge clk_2x) + if(clk_fpga) + begin + TX <= tx_i; + TXSYNC <= 0; // Low indicates first data item + end + else + begin + TX <= tx_q; + TXSYNC <= 1; + end + + // ///////////////////////////////////////////////////////////////////////// + // Main U1E Core u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb[2]), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), .debug_pb(~debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), @@ -59,10 +107,16 @@ module u1e .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145), .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147), .io_tx(io_tx), .io_rx(io_rx), - .tx(TX), .txsync(TXSYNC), .txblank(TXBLANK), + .tx_i(tx_i), .tx_q(tx_q), + .rx_i(DA), .rx_q(DB), .misc_gpio( {{overo_gpio128,overo_gpio163,overo_gpio170,overo_gpio176}, {overo_gpio0,overo_gpio14,overo_gpio21,overo_gpio22}, {overo_gpio23,overo_gpio64,overo_gpio65,overo_gpio127}}), .pps_in(PPS_IN) ); + + // ///////////////////////////////////////////////////////////////////////// + // Local Debug + // assign debug_clk = {clk_fpga, clk_2x }; + // assign debug = { TXSYNC, TXBLANK, TX }; endmodule // u1e diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index ee193ffb9..002b28f7a 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -1,7 +1,8 @@ //`define LOOPBACK 1 -`define TIMED 1 +//`define TIMED 1 +`define DSP 1 module u1e_core (input clk_fpga, input rst_fpga, @@ -18,14 +19,31 @@ module u1e_core input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, inout [15:0] io_tx, inout [15:0] io_rx, - output reg [13:0] tx, output reg txsync, output txblank, + output [13:0] tx_i, output [13:0] tx_q, + input [11:0] rx_i, input [11:0] rx_q, input [11:0] misc_gpio, input pps_in ); - + + localparam TXFIFOSIZE = 11; + localparam RXFIFOSIZE = 11; + localparam SR_TIME64 = 0; + localparam SR_RX_DSP = 0; + localparam SR_RX_CTRL = 0; + localparam SR_TX_DSP = 0; + localparam SR_TX_CTRL = 0; + wire wb_clk = clk_fpga; wire wb_rst = rst_fpga; + wire pps_int; + wire [63:0] vita_time; + reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; + + wire [7:0] set_addr; + wire [31:0] set_data; + wire set_stb; + // ///////////////////////////////////////////////////////////////////////////////////// // GPMC Slave to Wishbone Master localparam dw = 16; @@ -47,33 +65,36 @@ module u1e_core wire bus_error; - gpmc_async gpmc (.arst(wb_rst), - .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), - .EM_NOE(EM_NOE), - - .rx_have_data(rx_have_data), .tx_have_space(tx_have_space), - .bus_error(bus_error), .bus_reset(0), - - .wb_clk(wb_clk), .wb_rst(wb_rst), - .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), - .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), - .wb_ack_i(m0_ack), - - .fifo_clk(wb_clk), .fifo_rst(wb_rst), - .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), - .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), - - .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), - .debug(debug_gpmc)); + gpmc_async #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE)) + gpmc (.arst(wb_rst), + .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), + .EM_NOE(EM_NOE), + + .rx_have_data(rx_have_data), .tx_have_space(tx_have_space), + .bus_error(bus_error), .bus_reset(0), + + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), + .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), + .wb_ack_i(m0_ack), + + .fifo_clk(wb_clk), .fifo_rst(wb_rst), + .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), + .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), + + .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len), + .debug(debug_gpmc)); + wire rx_sof = rx_data[32]; + wire rx_eof = rx_data[33]; + wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int; + `ifdef LOOPBACK fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo (.clk(wb_clk), .reset(wb_rst), .clear(0), .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); - wire rx_sof = rx_data[32]; - wire rx_eof = rx_data[33]; `endif // LOOPBACK `ifdef TIMED @@ -93,9 +114,7 @@ module u1e_core .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); // RX side - wire rx_enable, rx_src_rdy_int, rx_dst_rdy_int; - wire rx_sof = rx_data[32]; - wire rx_eof = rx_data[33]; + wire rx_enable; packet_generator32 pktgen32 (.clk(wb_clk), .reset(wb_rst), .clear(clear), @@ -108,7 +127,90 @@ module u1e_core .underrun(), .overrun(rx_overrun)); `endif // `ifdef TIMED + +`ifdef DSP + wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug; + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX + wire [31:0] sample_rx, sample_tx; + wire strobe_rx, strobe_tx; + wire rx1_dst_rdy, rx1_src_rdy; + wire [99:0] rx1_data; + + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx + (.clk(wb_clk),.rst(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a({rx_i,2'b0}),.adc_ovf_a(0),.adc_b({rx_q,2'b0}),.adc_ovf_b(0), + .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time), .overrun(overrun), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy), + .debug_rx(vrc_debug)); + + vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy), + .data_o(rx_data), .dst_rdy_i(rx_dst_rdy), .src_rdy_o(rx_src_rdy), + .fifo_occupied(), .fifo_full(), .fifo_empty(), + .debug_rx(vrf_debug) ); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [99:0] tx1_data; + wire tx1_src_rdy, tx1_dst_rdy; + wire [15:0] tx_i_int, tx_q_int; + wire [31:0] debug_vtc, debug_vtd, debug_vt; + + vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), + .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), + .debug(debug_vtd) ); + + vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time),.underrun(underrun), + .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .debug(debug_vtc) ); + + dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx + (.clk(wb_clk),.rst(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .dac_a(tx_i_int),.dac_b(tx_q_int), + .debug(debug_tx_dsp) ); + + assign tx_i = tx_i_int[15:2]; + assign tx_q = tx_q_int[15:2]; + +`else // !`ifdef DSP + // Dummy DSP signal generator for test purposes + wire [23:0] tx_i_int, tx_q_int; + wire [23:0] freq = {reg_test,8'd0}; + reg [23:0] phase; + + always @(posedge wb_clk) + phase <= phase + freq; + cordic_z24 #(.bitwidth(24)) tx_cordic + (.clock(wb_clk), .reset(wb_rst), .enable(1), + .xi(24'd2500000), .yi(24'd0), .zi(phase), .xo(tx_i_int), .yo(tx_q_int), .zo()); + + assign tx_i = tx_i_int[23:10]; + assign tx_q = tx_q_int[23:10]; +`endif // !`ifdef DSP + // ///////////////////////////////////////////////////////////////////////////////////// // Wishbone Intercon, single master wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, @@ -181,8 +283,6 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////////////////// // Slave 0, Misc LEDs, Switches, controls - reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; - localparam REG_LEDS = 7'd0; // out localparam REG_SWITCHES = 7'd2; // in localparam REG_CGEN_CTRL = 7'd4; // out @@ -288,10 +388,6 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #5 - wire [7:0] set_addr; - wire [31:0] set_data; - wire set_stb; - // only have 32 regs, 32 bits each with current setup... settings_bus_16LE #(.AWIDTH(11),.RWIDTH(11-4-2)) settings_bus_16LE (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s5_adr),.wb_dat_i(s5_dat_mosi), @@ -311,51 +407,9 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////// // VITA Timing - localparam SR_TIME64 = 0; - wire pps_int; - wire [63:0] vita_time; - time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int)); - - - // ///////////////////////////////////////////////////////////////////////// - // TX - - assign txblank = 0; - - wire [23:0] freq = {reg_test,8'd0}; - - reg [23:0] tx_q_hold; - wire [23:0] tx_i, tx_q; - - reg tx_stb; - always @(posedge wb_clk) - tx_stb <= ~tx_stb; - - always @(posedge wb_clk) - if(tx_stb) - tx <= tx_i[23:10]; - else - tx <= tx_q_hold[23:10]; - - always @(posedge wb_clk) - if(tx_stb) - tx_q_hold <= tx_q; - - always @(posedge wb_clk) - txsync <= ~tx_stb; // TX Sync low indicates first data item - // We invert here if we don't use inv_txsync in the 9862 - - reg [23:0] phase; - always @(posedge wb_clk) - if(tx_stb) - phase <= phase + freq; - - cordic_z24 #(.bitwidth(24)) tx_cordic - (.clock(wb_clk), .reset(wb_rst), .enable(1), - .xi(24'd2500000), .yi(24'd0), .zi(phase), .xo(tx_i), .yo(tx_q), .zo()); // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry -- cgit v1.2.3 From 552c3477734c6c302c53fe039d6e85134fcf210c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 1 Jun 2010 16:20:24 -0700 Subject: assign addresses for the settings regs --- usrp2/top/u1e/u1e_core.v | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 002b28f7a..ed4176ca5 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -27,11 +27,12 @@ module u1e_core localparam TXFIFOSIZE = 11; localparam RXFIFOSIZE = 11; - localparam SR_TIME64 = 0; - localparam SR_RX_DSP = 0; - localparam SR_RX_CTRL = 0; - localparam SR_TX_DSP = 0; - localparam SR_TX_CTRL = 0; + + localparam SR_RX_DSP = 0; // 7 regs + localparam SR_RX_CTRL = 8; // 9 regs + localparam SR_TX_DSP = 17; // 5 regs + localparam SR_TX_CTRL = 24; // 2 regs + localparam SR_TIME64 = 28; // 4 regs wire wb_clk = clk_fpga; wire wb_rst = rst_fpga; -- cgit v1.2.3 From 7a776f9fce357b298566d0a417a1417c4484723c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 1 Jun 2010 18:23:09 -0700 Subject: use DDR regs instead of a 2nd clock --- usrp2/top/u1e/u1e.v | 54 +++++++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 46 insertions(+), 8 deletions(-) diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 3018ff100..523aae1b9 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -1,6 +1,8 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// +//`define DCM 1 + module u1e (input CLK_FPGA_P, input CLK_FPGA_N, // Diff output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, @@ -26,7 +28,7 @@ module u1e inout [15:0] io_tx, inout [15:0] io_rx, - output reg [13:0] TX, output reg TXSYNC, output TXBLANK, + output [13:0] TX, output TXSYNC, output TXBLANK, input [11:0] DA, input [11:0] DB, input RXSYNC, input PPS_IN @@ -34,11 +36,13 @@ module u1e // ///////////////////////////////////////////////////////////////////////// // Clocking - wire clk_fpga, clk_fpga_in, clk_2x, dcm_rst, dcm_locked; + wire clk_fpga, clk_fpga_in; IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); +`ifdef DCM + wire clk_2x, dcm_rst, dcm_locked; DCM #(.CLK_FEEDBACK ( "1X" ), .CLKDV_DIVIDE ( 2.0 ), .CLKFX_DIVIDE ( 1 ), @@ -59,11 +63,10 @@ module u1e .CLK2X(clk_2x), .CLK2X180(), .CLK0(clk_fpga), .CLK90(), .CLK180(), .CLK270(), .LOCKED(dcm_locked), .STATUS()); - - //BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk)); - //BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk)); - - +`else // !`ifdef DCM + BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga)); +`endif // !`ifdef DCM + // ///////////////////////////////////////////////////////////////////////// // SPI wire mosi, sclk, miso; @@ -79,6 +82,10 @@ module u1e assign TXBLANK = 0; wire [13:0] tx_i, tx_q; + +`ifdef DCM + reg [13:0] TX; + reg TXSYNC; always @(posedge clk_2x) if(clk_fpga) @@ -91,7 +98,38 @@ module u1e TX <= tx_q; TXSYNC <= 1; end - +`else // !`ifdef DCM + genvar i; + generate + for(i=0;i<14;i=i+1) + begin : gen_dacout + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_inst (.Q(TX[i]), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(tx_i[i]), // 1-bit data input (associated with C0) + .D1(tx_q[i]), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + end // block: gen_dacout + endgenerate + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(1'b0), // 1-bit data input (associated with C0) + .D1(1'b1), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + +`endif // !`ifdef DCM + // ///////////////////////////////////////////////////////////////////////// // Main U1E Core u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb[2]), -- cgit v1.2.3 From b96282d6d9d7aad94d82f2ac6487460f4850a55c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 1 Jun 2010 18:23:35 -0700 Subject: connect the rx run lines so it doesn't get optimized out --- usrp2/top/u1e/u1e_core.v | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index ed4176ca5..7307a0299 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -138,12 +138,14 @@ module u1e_core wire strobe_rx, strobe_tx; wire rx1_dst_rdy, rx1_src_rdy; wire [99:0] rx1_data; + wire run_rx; + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx (.clk(wb_clk),.rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .adc_a({rx_i,2'b0}),.adc_ovf_a(0),.adc_b({rx_q,2'b0}),.adc_ovf_b(0), - .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), .debug(debug_rx_dsp) ); vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control @@ -169,6 +171,7 @@ module u1e_core wire tx1_src_rdy, tx1_dst_rdy; wire [15:0] tx_i_int, tx_q_int; wire [31:0] debug_vtc, debug_vtd, debug_vt; + wire run_tx; vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer (.clk(wb_clk), .reset(wb_rst), .clear(0), -- cgit v1.2.3 From 66deed6015f2a2bc67f17f6630ca62a41b596090 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 1 Jun 2010 18:50:15 -0700 Subject: added sr registers to u1e --- host/lib/usrp/usrp_e/usrp_e_regs.hpp | 78 +++++++++++++++++++++++++++++++++++- 1 file changed, 76 insertions(+), 2 deletions(-) diff --git a/host/lib/usrp/usrp_e/usrp_e_regs.hpp b/host/lib/usrp/usrp_e/usrp_e_regs.hpp index 51a47f061..67c174208 100644 --- a/host/lib/usrp/usrp_e/usrp_e_regs.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_regs.hpp @@ -17,6 +17,7 @@ // Slave pointers #define UE_REG_SLAVE(n) ((n)<<7) +#define UE_REG_SR_ADDR(n) ((UE_REG_SLAVE(5)) + (4*(n))) ///////////////////////////////////////////////////// // Slave 0 -- Misc Regs @@ -102,8 +103,8 @@ #define UE_REG_ATR_BASE UE_REG_SLAVE(6) -#define UE_REG_ATR_IDLE_RXSIDE UE_REG_ATR_BASE + 0 -#define UE_REG_ATR_IDLE_TXSIDE UE_REG_ATR_BASE + 2 +#define UE_REG_ATR_IDLE_RXSIDE UE_REG_ATR_BASE + 0 +#define UE_REG_ATR_IDLE_TXSIDE UE_REG_ATR_BASE + 2 #define UE_REG_ATR_INTX_RXSIDE UE_REG_ATR_BASE + 4 #define UE_REG_ATR_INTX_TXSIDE UE_REG_ATR_BASE + 6 #define UE_REG_ATR_INRX_RXSIDE UE_REG_ATR_BASE + 8 @@ -111,5 +112,78 @@ #define UE_REG_ATR_FULL_RXSIDE UE_REG_ATR_BASE + 12 #define UE_REG_ATR_FULL_TXSIDE UE_REG_ATR_BASE + 14 +///////////////////////////////////////////////// +// DSP RX Regs +//////////////////////////////////////////////// +#define UE_REG_DSP_RX_FREQ UE_REG_SR_ADDR(0) +#define UE_REG_DSP_RX_SCALE_IQ UE_REG_SR_ADDR(1) // {scale_i,scale_q} +#define UE_REG_DSP_RX_DECIM_RATE UE_REG_SR_ADDR(2) // hb and decim rate +#define UE_REG_DSP_RX_DCOFFSET_I UE_REG_SR_ADDR(3) // Bit 31 high sets fixed offset mode, using lower 14 bits, // otherwise it is automatic +#define UE_REG_DSP_RX_DCOFFSET_Q UE_REG_SR_ADDR(4) // Bit 31 high sets fixed offset mode, using lower 14 bits +#define UE_REG_DSP_RX_MUX UE_REG_SR_ADDR(5) + +/////////////////////////////////////////////////// +// VITA RX CTRL regs +/////////////////////////////////////////////////// +// The following 3 are logically a single command register. +// They are clocked into the underlying fifo when time_ticks is written. +#define UE_REG_CTRL_RX_STREAM_CMD UE_REG_SR_ADDR(8) // {now, chain, num_samples(30) +#define UE_REG_CTRL_RX_TIME_SECS UE_REG_SR_ADDR(9) +#define UE_REG_CTRL_RX_TIME_TICKS UE_REG_SR_ADDR(10) +#define UE_REG_CTRL_RX_CLEAR_OVERRUN UE_REG_SR_ADDR(11) // write anything to clear overrun +#define UE_REG_CTRL_RX_VRT_HEADER UE_REG_SR_ADDR(12) // word 0 of packet. FPGA fills in packet counter +#define UE_REG_CTRL_RX_VRT_STREAM_ID UE_REG_SR_ADDR(13) // word 1 of packet. +#define UE_REG_CTRL_RX_VRT_TRAILER UE_REG_SR_ADDR(14) +#define UE_REG_CTRL_RX_NSAMPS_PER_PKT UE_REG_SR_ADDR(15) +#define UE_REG_CTRL_RX_NCHANNELS UE_REG_SR_ADDR(16) // 1 in basic case, up to 4 for vector sources + +///////////////////////////////////////////////// +// DSP TX Regs +//////////////////////////////////////////////// +#define UE_REG_DSP_TX_FREQ UE_REG_SR_ADDR(17) +#define UE_REG_DSP_TX_SCALE_IQ UE_REG_SR_ADDR(18) // {scale_i,scale_q} +#define UE_REG_DSP_TX_INTERP_RATE UE_REG_SR_ADDR(19) +#define UE_REG_DSP_TX_UNUSED UE_REG_SR_ADDR(20) +#define UE_REG_DSP_TX_MUX UE_REG_SR_ADDR(21) + +///////////////////////////////////////////////// +// VITA TX CTRL regs +//////////////////////////////////////////////// +#define UE_REG_CTRL_TX_NCHANNELS UE_REG_SR_ADDR(24) +#define UE_REG_CTRL_TX_CLEAR_UNDERRUN UE_REG_SR_ADDR(25) + +///////////////////////////////////////////////// +// VITA49 64 bit time (write only) +//////////////////////////////////////////////// + /*! + * \brief Time 64 flags + * + * 
+   *
+   *    3                   2                   1
+   *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   * +-----------------------------------------------------------+-+-+
+   * |                                                           |S|P|
+   * +-----------------------------------------------------------+-+-+
+   *
+   * P - PPS edge selection (0=negedge, 1=posedge, default=0)
+   * S - Source (0=sma, 1=mimo, 0=default)
+   *
+   *
+ */ +#define UE_REG_TIME64_SECS UE_REG_SR_ADDR(28) // value to set absolute secs to on next PPS +#define UE_REG_TIME64_TICKS UE_REG_SR_ADDR(29) // value to set absolute ticks to on next PPS +#define UE_REG_TIME64_FLAGS UE_REG_SR_ADDR(30) // flags - see chart above +#define UE_REG_TIME64_IMM UE_REG_SR_ADDR(31) // set immediate (0=latch on next pps, 1=latch immediate, default=0) + +//pps flags (see above) +#define UE_FLAG_TIME64_PPS_NEGEDGE (0 << 0) +#define UE_FLAG_TIME64_PPS_POSEDGE (1 << 0) +#define UE_FLAG_TIME64_PPS_SMA (0 << 1) +#define UE_FLAG_TIME64_PPS_MIMO (1 << 1) + +#define UE_FLAG_TIME64_LATCH_NOW 1 +#define UE_FLAG_TIME64_LATCH_NEXT_PPS 0 + #endif -- cgit v1.2.3 From d2163a256d55692c19b0a717e382850a6546f80f Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 1 Jun 2010 18:56:44 -0700 Subject: use same version as usrp2-udp, so regs are same place in memory map --- usrp2/top/u1e/Makefile | 2 +- usrp2/top/u1e/u1e_core.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 7f5085275..edfc47c53 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -160,7 +160,7 @@ sdr_lib/clip_reg.v \ sdr_lib/cordic.v \ sdr_lib/cordic_z24.v \ sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_rx.v \ +sdr_lib/dsp_core_rx_udp.v \ sdr_lib/dsp_core_tx.v \ sdr_lib/hb_dec.v \ sdr_lib/hb_interp.v \ diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 7307a0299..12ce41c23 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -28,7 +28,7 @@ module u1e_core localparam TXFIFOSIZE = 11; localparam RXFIFOSIZE = 11; - localparam SR_RX_DSP = 0; // 7 regs + localparam SR_RX_DSP = 0; // 5 regs localparam SR_RX_CTRL = 8; // 9 regs localparam SR_TX_DSP = 17; // 5 regs localparam SR_TX_CTRL = 24; // 2 regs -- cgit v1.2.3 From 4f1b2441c0250a61f691c038f8bd9cfb229bd103 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 3 Jun 2010 08:44:13 -0700 Subject: Phil wants gpio #145 --- usrp2/top/u1e_passthru/passthru.ucf | 4 ++-- usrp2/top/u1e_passthru/passthru.v | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/usrp2/top/u1e_passthru/passthru.ucf b/usrp2/top/u1e_passthru/passthru.ucf index 3ffe33882..fcfce61b2 100644 --- a/usrp2/top/u1e_passthru/passthru.ucf +++ b/usrp2/top/u1e_passthru/passthru.ucf @@ -54,10 +54,10 @@ #NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug #NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug #NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug -NET "overo_gpio127" LOC = "C8" ; # passed through as cgen_sen_b +#NET "overo_gpio127" LOC = "C8" ; # passed through as cgen_sen_b #NET "overo_gpio128" LOC = "G8" ; # MISC GPIO for debug #NET "overo_gpio144" LOC = "A5" ; # tx_have_space -#NET "overo_gpio145" LOC = "C7" ; # tx_underrun +NET "overo_gpio145" LOC = "C7" ; # tx_underrun #NET "overo_gpio146" LOC = "A6" ; # rx_have_data #NET "overo_gpio147" LOC = "B6" ; # rx_overrun #NET "overo_gpio163" LOC = "D7" ; # MISC GPIO for debug diff --git a/usrp2/top/u1e_passthru/passthru.v b/usrp2/top/u1e_passthru/passthru.v index d846f2cf6..12e4db017 100644 --- a/usrp2/top/u1e_passthru/passthru.v +++ b/usrp2/top/u1e_passthru/passthru.v @@ -2,7 +2,7 @@ ////////////////////////////////////////////////////////////////////////////////// module passthru - (input overo_gpio127, + (input overo_gpio145, output cgen_sclk, output cgen_sen_b, output cgen_mosi, @@ -11,7 +11,7 @@ module passthru ); assign cgen_sclk = fpga_cfg_cclk; - assign cgen_sen_b = overo_gpio127; + assign cgen_sen_b = overo_gpio145; assign cgen_mosi = fpga_cfg_din; -- cgit v1.2.3 From f1529463174883f6c830acbfd52cd52ed4755971 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 3 Jun 2010 17:09:06 +0000 Subject: added headers to cmakelists for completeness --- host/lib/usrp/usrp_e/CMakeLists.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/host/lib/usrp/usrp_e/CMakeLists.txt b/host/lib/usrp/usrp_e/CMakeLists.txt index c25b2cba4..6035d4ff2 100644 --- a/host/lib/usrp/usrp_e/CMakeLists.txt +++ b/host/lib/usrp/usrp_e/CMakeLists.txt @@ -42,14 +42,19 @@ IF(HAVE_USRP_E_REQUIRED_HEADERS) MESSAGE(STATUS " Building usrp-e support.") LIBUHD_APPEND_SOURCES( ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/clock_ctrl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/clock_ctrl.hpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/codec_ctrl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/codec_ctrl.hpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/dboard_impl.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/dboard_iface.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/dsp_impl.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/fpga-downloader.cc ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/mboard_impl.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_impl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_impl.hpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_iface.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_iface.hpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_regs.hpp ) ELSE(HAVE_USRP_E_REQUIRED_HEADERS) MESSAGE(STATUS " Skipping usrp-e support.") -- cgit v1.2.3 From 551426b72672379faa56302eb3d3e19d12c41aec Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 3 Jun 2010 19:30:00 +0000 Subject: work on io impl for usrp-e using read/write --- host/lib/usrp/usrp_e/CMakeLists.txt | 1 + host/lib/usrp/usrp_e/io_impl.cpp | 137 ++++++++++++++++++++++++++++++++++ host/lib/usrp/usrp_e/usrp_e_iface.cpp | 4 + host/lib/usrp/usrp_e/usrp_e_iface.hpp | 6 ++ host/lib/usrp/usrp_e/usrp_e_impl.cpp | 30 +------- host/lib/usrp/usrp_e/usrp_e_impl.hpp | 35 ++++----- 6 files changed, 166 insertions(+), 47 deletions(-) create mode 100644 host/lib/usrp/usrp_e/io_impl.cpp diff --git a/host/lib/usrp/usrp_e/CMakeLists.txt b/host/lib/usrp/usrp_e/CMakeLists.txt index 6035d4ff2..568fbd132 100644 --- a/host/lib/usrp/usrp_e/CMakeLists.txt +++ b/host/lib/usrp/usrp_e/CMakeLists.txt @@ -49,6 +49,7 @@ IF(HAVE_USRP_E_REQUIRED_HEADERS) ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/dboard_iface.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/dsp_impl.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/fpga-downloader.cc + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/io_impl.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/mboard_impl.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_impl.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_impl.hpp diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp new file mode 100644 index 000000000..5bb40723e --- /dev/null +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -0,0 +1,137 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "usrp_e_impl.hpp" +#include "../../transport/vrt_packet_handler.hpp" +#include +#include //read, write +#include //transfer frame struct +#include //offsetof + +using namespace uhd; + +/*********************************************************************** + * Data Transport (phony zero-copy with read/write) + **********************************************************************/ +class data_transport: + public transport::phony_zero_copy_recv_if, + public transport::phony_zero_copy_send_if +{ +public: + data_transport(int fd): + transport::phony_zero_copy_recv_if(2048), //FIXME magic # + transport::phony_zero_copy_send_if(2048), //FIXME magic # + _fd(fd) + { + /* NOP */ + } + + size_t get_num_recv_frames(void) const{ + return 10; //FIXME no idea! + } + + size_t get_num_send_frames(void) const{ + return 10; //FIXME no idea! + } + +private: + int _fd; + size_t send(const boost::asio::const_buffer &buff){ + return write( + _fd, + boost::asio::buffer_cast(buff), + boost::asio::buffer_size(buff) + ); + } + size_t recv(const boost::asio::mutable_buffer &buff){ + return read( + _fd, + boost::asio::buffer_cast(buff), + boost::asio::buffer_size(buff) + ); + } +}; + +/*********************************************************************** + * IO Implementation Details + **********************************************************************/ +struct usrp_e_impl::io_impl{ + vrt_packet_handler::recv_state recv_state; + vrt_packet_handler::send_state send_state; + data_transport transport; + io_impl(int fd): transport(fd){} +}; + +void usrp_e_impl::io_init(void){ + _io_impl = UHD_PIMPL_MAKE(io_impl, (_iface->get_file_descriptor())); +} + +/*********************************************************************** + * Data Send + **********************************************************************/ +size_t usrp_e_impl::send( + const boost::asio::const_buffer &buff, + const uhd::tx_metadata_t &metadata, + const io_type_t & io_type, + send_mode_t send_mode +){ + otw_type_t send_otw_type; + send_otw_type.width = 16; + send_otw_type.shift = 0; + send_otw_type.byteorder = otw_type_t::BO_NATIVE; + + return vrt_packet_handler::send( + _io_impl->send_state, + buff, + metadata, + send_mode, + io_type, + send_otw_type, //TODO + 64e6, //TODO + boost::bind(&data_transport::get_send_buff, &_io_impl->transport), + _max_num_samples, //TODO + offsetof(usrp_transfer_frame, buf) + //TODO probably need callback to fill in frame size + ); +} + +/*********************************************************************** + * Data Recv + **********************************************************************/ +size_t usrp_e_impl::recv( + const boost::asio::mutable_buffer &buff, + uhd::rx_metadata_t &metadata, + const io_type_t &io_type, + recv_mode_t recv_mode +){ + otw_type_t recv_otw_type; + recv_otw_type.width = 16; + recv_otw_type.shift = 0; + recv_otw_type.byteorder = otw_type_t::BO_NATIVE; + + return vrt_packet_handler::recv( + _io_impl->recv_state, + buff, + metadata, + recv_mode, + io_type, + recv_otw_type, //TODO + 64e6, //TODO + boost::bind(&data_transport::get_recv_buff, &_io_impl->transport), + offsetof(usrp_transfer_frame, buf) + ); +} diff --git a/host/lib/usrp/usrp_e/usrp_e_iface.cpp b/host/lib/usrp/usrp_e/usrp_e_iface.cpp index 98d8ef478..21e91452f 100644 --- a/host/lib/usrp/usrp_e/usrp_e_iface.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_iface.cpp @@ -29,6 +29,10 @@ using namespace uhd; class usrp_e_iface_impl : public usrp_e_iface{ public: + int get_file_descriptor(void){ + return _node_fd; + } + /******************************************************************* * Structors ******************************************************************/ diff --git a/host/lib/usrp/usrp_e/usrp_e_iface.hpp b/host/lib/usrp/usrp_e/usrp_e_iface.hpp index 6363a24b2..59aac43d9 100644 --- a/host/lib/usrp/usrp_e/usrp_e_iface.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_iface.hpp @@ -49,6 +49,12 @@ public: */ static sptr make(const std::string &node); + /*! + * Get the underlying file descriptor. + * \return the file descriptor + */ + virtual int get_file_descriptor(void) = 0; + /*! * Perform an ioctl call on the device node file descriptor. * This will throw when the internal ioctl call fails. diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.cpp b/host/lib/usrp/usrp_e/usrp_e_impl.cpp index 4a398e21c..f9af36887 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.cpp @@ -89,6 +89,9 @@ usrp_e_impl::usrp_e_impl(const std::string &node){ //initialize the dsps rx_ddc_init(); tx_duc_init(); + + //init the io send/recv + io_init(); } usrp_e_impl::~usrp_e_impl(void){ @@ -127,30 +130,3 @@ void usrp_e_impl::get(const wax::obj &key_, wax::obj &val){ void usrp_e_impl::set(const wax::obj &, const wax::obj &){ UHD_THROW_PROP_SET_ERROR(); } - -/*********************************************************************** - * Device IO (TODO) - **********************************************************************/ -size_t usrp_e_impl::send( - const boost::asio::const_buffer &, - const uhd::tx_metadata_t &, - const io_type_t &, - send_mode_t -){ - if (true){ - throw std::runtime_error(str(boost::format("usrp-e send: cannot handle type \"%s\"") % "")); - } - return 0; -} - -size_t usrp_e_impl::recv( - const boost::asio::mutable_buffer &, - uhd::rx_metadata_t &, - const io_type_t &, - recv_mode_t -){ - if (true){ - throw std::runtime_error(str(boost::format("usrp-e recv: cannot handle type \"%s\"") % "")); - } - return 0; -} diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index a2cdbc31e..12d4c9d9e 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -18,6 +18,7 @@ #include "usrp_e_iface.hpp" #include "clock_ctrl.hpp" #include "codec_ctrl.hpp" +#include #include #include #include @@ -55,26 +56,11 @@ public: return sptr(new wax_obj_proxy(get, set)); } - ~wax_obj_proxy(void){ - /* NOP */ - } - private: - get_t _get; - set_t _set; - - wax_obj_proxy(const get_t &get, const set_t &set){ - _get = get; - _set = set; - }; - - void get(const wax::obj &key, wax::obj &val){ - return _get(key, val); - } - - void set(const wax::obj &key, const wax::obj &val){ - return _set(key, val); - } + get_t _get; set_t _set; + wax_obj_proxy(const get_t &get, const set_t &set): _get(get), _set(set){}; + void get(const wax::obj &key, wax::obj &val){return _get(key, val);} + void set(const wax::obj &key, const wax::obj &val){return _set(key, val);} }; /*! @@ -95,10 +81,19 @@ public: size_t get_max_recv_samps_per_packet(void) const{return _max_num_samples;} private: - static const size_t _max_num_samples = 2048/sizeof(boost::uint32_t); + //interface to ioctls and file descriptor usrp_e_iface::sptr _iface; + //FIXME fetch from ioctl? + static const size_t _max_num_samples = 2048/sizeof(boost::uint32_t); + + //handle io stuff + UHD_PIMPL_DECL(io_impl) _io_impl; + void io_init(void); + + //configuration shadows uhd::clock_config_t _clock_config; + //TODO otw type recv/send //ad9522 clock control clock_ctrl::sptr _clock_ctrl; -- cgit v1.2.3 From fcdbea4f089db2405820ad598979e639cf131ff5 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 4 Jun 2010 01:58:12 +0000 Subject: io impl tweaks, renamed clock control and codec control implementation to avoid collision with usrp2 (those need to be renamed as well) --- host/lib/usrp/usrp_e/clock_ctrl.cpp | 18 +++++++++--------- host/lib/usrp/usrp_e/codec_ctrl.cpp | 20 ++++++++++---------- host/lib/usrp/usrp_e/dsp_impl.cpp | 24 ++++++++++++++++++++++++ host/lib/usrp/usrp_e/io_impl.cpp | 16 ++++++++++++---- 4 files changed, 55 insertions(+), 23 deletions(-) diff --git a/host/lib/usrp/usrp_e/clock_ctrl.cpp b/host/lib/usrp/usrp_e/clock_ctrl.cpp index 5f7269412..7947930a0 100644 --- a/host/lib/usrp/usrp_e/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e/clock_ctrl.cpp @@ -29,11 +29,11 @@ using namespace uhd; /*********************************************************************** * Clock Control Implementation **********************************************************************/ -class clock_ctrl_impl : public clock_ctrl{ +class usrp_e_clock_ctrl_impl : public clock_ctrl{ public: //structors - clock_ctrl_impl(usrp_e_iface::sptr iface); - ~clock_ctrl_impl(void); + usrp_e_clock_ctrl_impl(usrp_e_iface::sptr iface); + ~usrp_e_clock_ctrl_impl(void); void enable_rx_dboard_clock(bool enb); void enable_tx_dboard_clock(bool enb); @@ -56,7 +56,7 @@ private: /*********************************************************************** * Clock Control Methods **********************************************************************/ -clock_ctrl_impl::clock_ctrl_impl(usrp_e_iface::sptr iface){ +usrp_e_clock_ctrl_impl::usrp_e_clock_ctrl_impl(usrp_e_iface::sptr iface){ _iface = iface; //init the clock gen registers @@ -126,12 +126,12 @@ clock_ctrl_impl::clock_ctrl_impl(usrp_e_iface::sptr iface){ this->enable_tx_dboard_clock(false); } -clock_ctrl_impl::~clock_ctrl_impl(void){ +usrp_e_clock_ctrl_impl::~usrp_e_clock_ctrl_impl(void){ this->enable_rx_dboard_clock(false); this->enable_tx_dboard_clock(false); } -void clock_ctrl_impl::enable_rx_dboard_clock(bool enb){ +void usrp_e_clock_ctrl_impl::enable_rx_dboard_clock(bool enb){ _ad9522_regs.out9_format = ad9522_regs_t::OUT9_FORMAT_CMOS; _ad9522_regs.out9_cmos_configuration = (enb)? ad9522_regs_t::OUT9_CMOS_CONFIGURATION_B_ON : @@ -144,7 +144,7 @@ void clock_ctrl_impl::enable_rx_dboard_clock(bool enb){ this->latch_regs(); } -void clock_ctrl_impl::enable_tx_dboard_clock(bool enb){ +void usrp_e_clock_ctrl_impl::enable_tx_dboard_clock(bool enb){ _ad9522_regs.out6_format = ad9522_regs_t::OUT6_FORMAT_CMOS; _ad9522_regs.out6_cmos_configuration = (enb)? ad9522_regs_t::OUT6_CMOS_CONFIGURATION_B_ON : @@ -157,7 +157,7 @@ void clock_ctrl_impl::enable_tx_dboard_clock(bool enb){ this->latch_regs(); } -void clock_ctrl_impl::send_reg(boost::uint16_t addr){ +void usrp_e_clock_ctrl_impl::send_reg(boost::uint16_t addr){ boost::uint32_t reg = _ad9522_regs.get_write_reg(addr); //std::cout << "clock control write reg: " << std::hex << reg << std::endl; _iface->transact_spi( @@ -171,5 +171,5 @@ void clock_ctrl_impl::send_reg(boost::uint16_t addr){ * Clock Control Make **********************************************************************/ clock_ctrl::sptr clock_ctrl::make(usrp_e_iface::sptr iface){ - return sptr(new clock_ctrl_impl(iface)); + return sptr(new usrp_e_clock_ctrl_impl(iface)); } diff --git a/host/lib/usrp/usrp_e/codec_ctrl.cpp b/host/lib/usrp/usrp_e/codec_ctrl.cpp index ce05ac9eb..e86fde346 100644 --- a/host/lib/usrp/usrp_e/codec_ctrl.cpp +++ b/host/lib/usrp/usrp_e/codec_ctrl.cpp @@ -34,11 +34,11 @@ static const bool codec_debug = true; /*********************************************************************** * Codec Control Implementation **********************************************************************/ -class codec_ctrl_impl : public codec_ctrl{ +class usrp_e_codec_ctrl_impl : public codec_ctrl{ public: //structors - codec_ctrl_impl(usrp_e_iface::sptr iface); - ~codec_ctrl_impl(void); + usrp_e_codec_ctrl_impl(usrp_e_iface::sptr iface); + ~usrp_e_codec_ctrl_impl(void); //aux adc and dac control float read_aux_adc(aux_adc_t which); @@ -55,7 +55,7 @@ private: /*********************************************************************** * Codec Control Structors **********************************************************************/ -codec_ctrl_impl::codec_ctrl_impl(usrp_e_iface::sptr iface){ +usrp_e_codec_ctrl_impl::usrp_e_codec_ctrl_impl(usrp_e_iface::sptr iface){ _iface = iface; //FIXME temp poke !!! @@ -107,7 +107,7 @@ codec_ctrl_impl::codec_ctrl_impl(usrp_e_iface::sptr iface){ this->send_reg(34); } -codec_ctrl_impl::~codec_ctrl_impl(void){ +usrp_e_codec_ctrl_impl::~usrp_e_codec_ctrl_impl(void){ return; //FIXME remove this later //set aux dacs to zero @@ -131,7 +131,7 @@ static float aux_adc_to_volts(boost::uint8_t high, boost::uint8_t low){ return float((boost::uint16_t(high) << 2) | low)*3.3/0x3ff; } -float codec_ctrl_impl::read_aux_adc(aux_adc_t which){ +float usrp_e_codec_ctrl_impl::read_aux_adc(aux_adc_t which){ //check to see if the switch needs to be set bool write_switch = false; switch(which){ @@ -184,7 +184,7 @@ float codec_ctrl_impl::read_aux_adc(aux_adc_t which){ /*********************************************************************** * Codec Control AUX DAC Methods **********************************************************************/ -void codec_ctrl_impl::write_aux_dac(aux_dac_t which, float volts){ +void usrp_e_codec_ctrl_impl::write_aux_dac(aux_dac_t which, float volts){ //special case for aux dac d (aka sigma delta word) if (which == AUX_DAC_D){ boost::uint16_t dac_word = std::clip(boost::math::iround(volts*0xfff/3.3), 0, 0xfff); @@ -217,7 +217,7 @@ void codec_ctrl_impl::write_aux_dac(aux_dac_t which, float volts){ /*********************************************************************** * Codec Control SPI Methods **********************************************************************/ -void codec_ctrl_impl::send_reg(boost::uint8_t addr){ +void usrp_e_codec_ctrl_impl::send_reg(boost::uint8_t addr){ boost::uint32_t reg = _ad9862_regs.get_write_reg(addr); if (codec_debug) std::cout << "codec control write reg: " << std::hex << reg << std::endl; _iface->transact_spi( @@ -227,7 +227,7 @@ void codec_ctrl_impl::send_reg(boost::uint8_t addr){ ); } -void codec_ctrl_impl::recv_reg(boost::uint8_t addr){ +void usrp_e_codec_ctrl_impl::recv_reg(boost::uint8_t addr){ boost::uint32_t reg = _ad9862_regs.get_read_reg(addr); if (codec_debug) std::cout << "codec control read reg: " << std::hex << reg << std::endl; boost::uint32_t ret = _iface->transact_spi( @@ -243,5 +243,5 @@ void codec_ctrl_impl::recv_reg(boost::uint8_t addr){ * Codec Control Make **********************************************************************/ codec_ctrl::sptr codec_ctrl::make(usrp_e_iface::sptr iface){ - return sptr(new codec_ctrl_impl(iface)); + return sptr(new usrp_e_codec_ctrl_impl(iface)); } diff --git a/host/lib/usrp/usrp_e/dsp_impl.cpp b/host/lib/usrp/usrp_e/dsp_impl.cpp index 272ac71b3..e61f529ab 100644 --- a/host/lib/usrp/usrp_e/dsp_impl.cpp +++ b/host/lib/usrp/usrp_e/dsp_impl.cpp @@ -20,6 +20,30 @@ using namespace uhd::usrp; +/*********************************************************************** + * Helper Functions + **********************************************************************/ +// Check if requested decim/interp rate is: +// multiple of 4, enable two halfband filters +// multiple of 2, enable one halfband filter +// handle remainder in CIC +static boost::uint32_t calculate_cic_word(size_t rate){ + int hb0 = 0, hb1 = 0; + if (not (rate & 0x1)){ + hb0 = 1; + rate /= 2; + } + if (not (rate & 0x1)){ + hb1 = 1; + rate /= 2; + } + return (hb1 << 9) | (hb0 << 8) | (rate & 0xff); +} + +static boost::uint32_t calculate_iq_scale_word(boost::int16_t i, boost::int16_t q){ + return (boost::uint16_t(i) << 16) | (boost::uint16_t(q) << 0); +} + /*********************************************************************** * RX DDC Initialization **********************************************************************/ diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index 5bb40723e..f83829cb8 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -24,6 +24,8 @@ using namespace uhd; +static const size_t MAX_BUFF_SIZE = 2048; + /*********************************************************************** * Data Transport (phony zero-copy with read/write) **********************************************************************/ @@ -33,8 +35,8 @@ class data_transport: { public: data_transport(int fd): - transport::phony_zero_copy_recv_if(2048), //FIXME magic # - transport::phony_zero_copy_send_if(2048), //FIXME magic # + transport::phony_zero_copy_recv_if(MAX_BUFF_SIZE), + transport::phony_zero_copy_send_if(MAX_BUFF_SIZE), _fd(fd) { /* NOP */ @@ -51,6 +53,13 @@ public: private: int _fd; size_t send(const boost::asio::const_buffer &buff){ + //Set the frame length in the frame header. + //This is technically bad to write to a const buffer, + //but this will go away when the ring gets implemented, + //and the send buffer commit method will set the length. + const_cast( + boost::asio::buffer_cast(buff) + )->len = boost::asio::buffer_size(buff); return write( _fd, boost::asio::buffer_cast(buff), @@ -103,9 +112,8 @@ size_t usrp_e_impl::send( send_otw_type, //TODO 64e6, //TODO boost::bind(&data_transport::get_send_buff, &_io_impl->transport), - _max_num_samples, //TODO + (MAX_BUFF_SIZE - sizeof(usrp_transfer_frame))/send_otw_type.get_sample_size(), offsetof(usrp_transfer_frame, buf) - //TODO probably need callback to fill in frame size ); } -- cgit v1.2.3 From 685cf432a373ee7556db507f7958f51e6ccf581a Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 4 Jun 2010 21:13:27 +0000 Subject: prefixed helper classes with usrp_e to avoid collision --- host/lib/usrp/usrp_e/clock_ctrl.cpp | 4 ++-- host/lib/usrp/usrp_e/clock_ctrl.hpp | 4 ++-- host/lib/usrp/usrp_e/codec_ctrl.cpp | 4 ++-- host/lib/usrp/usrp_e/codec_ctrl.hpp | 4 ++-- host/lib/usrp/usrp_e/dboard_iface.cpp | 28 ++++++++++++++-------------- host/lib/usrp/usrp_e/usrp_e_impl.cpp | 4 ++-- host/lib/usrp/usrp_e/usrp_e_impl.hpp | 8 ++++---- 7 files changed, 28 insertions(+), 28 deletions(-) diff --git a/host/lib/usrp/usrp_e/clock_ctrl.cpp b/host/lib/usrp/usrp_e/clock_ctrl.cpp index 7947930a0..e37b17a54 100644 --- a/host/lib/usrp/usrp_e/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e/clock_ctrl.cpp @@ -29,7 +29,7 @@ using namespace uhd; /*********************************************************************** * Clock Control Implementation **********************************************************************/ -class usrp_e_clock_ctrl_impl : public clock_ctrl{ +class usrp_e_clock_ctrl_impl : public usrp_e_clock_ctrl{ public: //structors usrp_e_clock_ctrl_impl(usrp_e_iface::sptr iface); @@ -170,6 +170,6 @@ void usrp_e_clock_ctrl_impl::send_reg(boost::uint16_t addr){ /*********************************************************************** * Clock Control Make **********************************************************************/ -clock_ctrl::sptr clock_ctrl::make(usrp_e_iface::sptr iface){ +usrp_e_clock_ctrl::sptr usrp_e_clock_ctrl::make(usrp_e_iface::sptr iface){ return sptr(new usrp_e_clock_ctrl_impl(iface)); } diff --git a/host/lib/usrp/usrp_e/clock_ctrl.hpp b/host/lib/usrp/usrp_e/clock_ctrl.hpp index 994b83564..692b9eb0e 100644 --- a/host/lib/usrp/usrp_e/clock_ctrl.hpp +++ b/host/lib/usrp/usrp_e/clock_ctrl.hpp @@ -27,9 +27,9 @@ * - Setup system clocks. * - Disable/enable clock lines. */ -class clock_ctrl : boost::noncopyable{ +class usrp_e_clock_ctrl : boost::noncopyable{ public: - typedef boost::shared_ptr sptr; + typedef boost::shared_ptr sptr; /*! * Make a new clock control object. diff --git a/host/lib/usrp/usrp_e/codec_ctrl.cpp b/host/lib/usrp/usrp_e/codec_ctrl.cpp index e86fde346..b19606020 100644 --- a/host/lib/usrp/usrp_e/codec_ctrl.cpp +++ b/host/lib/usrp/usrp_e/codec_ctrl.cpp @@ -34,7 +34,7 @@ static const bool codec_debug = true; /*********************************************************************** * Codec Control Implementation **********************************************************************/ -class usrp_e_codec_ctrl_impl : public codec_ctrl{ +class usrp_e_codec_ctrl_impl : public usrp_e_codec_ctrl{ public: //structors usrp_e_codec_ctrl_impl(usrp_e_iface::sptr iface); @@ -242,6 +242,6 @@ void usrp_e_codec_ctrl_impl::recv_reg(boost::uint8_t addr){ /*********************************************************************** * Codec Control Make **********************************************************************/ -codec_ctrl::sptr codec_ctrl::make(usrp_e_iface::sptr iface){ +usrp_e_codec_ctrl::sptr usrp_e_codec_ctrl::make(usrp_e_iface::sptr iface){ return sptr(new usrp_e_codec_ctrl_impl(iface)); } diff --git a/host/lib/usrp/usrp_e/codec_ctrl.hpp b/host/lib/usrp/usrp_e/codec_ctrl.hpp index efdcd7142..b9005a82d 100644 --- a/host/lib/usrp/usrp_e/codec_ctrl.hpp +++ b/host/lib/usrp/usrp_e/codec_ctrl.hpp @@ -27,9 +27,9 @@ * - Init/power down codec. * - Read aux adc, write aux dac. */ -class codec_ctrl : boost::noncopyable{ +class usrp_e_codec_ctrl : boost::noncopyable{ public: - typedef boost::shared_ptr sptr; + typedef boost::shared_ptr sptr; /*! * Make a new clock control object. diff --git a/host/lib/usrp/usrp_e/dboard_iface.cpp b/host/lib/usrp/usrp_e/dboard_iface.cpp index 23255b58c..594f2a23e 100644 --- a/host/lib/usrp/usrp_e/dboard_iface.cpp +++ b/host/lib/usrp/usrp_e/dboard_iface.cpp @@ -34,8 +34,8 @@ public: usrp_e_dboard_iface( usrp_e_iface::sptr iface, - clock_ctrl::sptr clock, - codec_ctrl::sptr codec + usrp_e_clock_ctrl::sptr clock, + usrp_e_codec_ctrl::sptr codec ){ _iface = iface; _clock = clock; @@ -77,8 +77,8 @@ public: private: usrp_e_iface::sptr _iface; - clock_ctrl::sptr _clock; - codec_ctrl::sptr _codec; + usrp_e_clock_ctrl::sptr _clock; + usrp_e_codec_ctrl::sptr _codec; }; /*********************************************************************** @@ -86,8 +86,8 @@ private: **********************************************************************/ dboard_iface::sptr make_usrp_e_dboard_iface( usrp_e_iface::sptr iface, - clock_ctrl::sptr clock, - codec_ctrl::sptr codec + usrp_e_clock_ctrl::sptr clock, + usrp_e_codec_ctrl::sptr codec ){ return dboard_iface::sptr(new usrp_e_dboard_iface(iface, clock, codec)); } @@ -214,24 +214,24 @@ byte_vector_t usrp_e_dboard_iface::read_i2c(boost::uint8_t addr, size_t num_byte **********************************************************************/ void usrp_e_dboard_iface::write_aux_dac(dboard_iface::unit_t, int which, float value){ //same aux dacs for each unit - static const uhd::dict which_to_aux_dac = map_list_of - (0, codec_ctrl::AUX_DAC_A) (1, codec_ctrl::AUX_DAC_B) - (2, codec_ctrl::AUX_DAC_C) (3, codec_ctrl::AUX_DAC_D) + static const uhd::dict which_to_aux_dac = map_list_of + (0, usrp_e_codec_ctrl::AUX_DAC_A) (1, usrp_e_codec_ctrl::AUX_DAC_B) + (2, usrp_e_codec_ctrl::AUX_DAC_C) (3, usrp_e_codec_ctrl::AUX_DAC_D) ; _codec->write_aux_dac(which_to_aux_dac[which], value); } float usrp_e_dboard_iface::read_aux_adc(dboard_iface::unit_t unit, int which){ static const uhd::dict< - unit_t, uhd::dict + unit_t, uhd::dict > unit_to_which_to_aux_adc = map_list_of (UNIT_RX, map_list_of - (0, codec_ctrl::AUX_ADC_A1) - (1, codec_ctrl::AUX_ADC_B1) + (0, usrp_e_codec_ctrl::AUX_ADC_A1) + (1, usrp_e_codec_ctrl::AUX_ADC_B1) ) (UNIT_TX, map_list_of - (0, codec_ctrl::AUX_ADC_A2) - (1, codec_ctrl::AUX_ADC_B2) + (0, usrp_e_codec_ctrl::AUX_ADC_A2) + (1, usrp_e_codec_ctrl::AUX_ADC_B2) ) ; return _codec->read_aux_adc(unit_to_which_to_aux_adc[unit][which]); diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.cpp b/host/lib/usrp/usrp_e/usrp_e_impl.cpp index f9af36887..226825510 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.cpp @@ -77,8 +77,8 @@ usrp_e_impl::usrp_e_impl(const std::string &node){ //setup various interfaces into hardware _iface = usrp_e_iface::make(node); - _clock_ctrl = clock_ctrl::make(_iface); - _codec_ctrl = codec_ctrl::make(_iface); + _clock_ctrl = usrp_e_clock_ctrl::make(_iface); + _codec_ctrl = usrp_e_codec_ctrl::make(_iface); //initialize the mboard mboard_init(); diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index 12d4c9d9e..bdb1a675b 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -36,8 +36,8 @@ */ uhd::usrp::dboard_iface::sptr make_usrp_e_dboard_iface( usrp_e_iface::sptr iface, - clock_ctrl::sptr clock, - codec_ctrl::sptr codec + usrp_e_clock_ctrl::sptr clock, + usrp_e_codec_ctrl::sptr codec ); /*! @@ -96,10 +96,10 @@ private: //TODO otw type recv/send //ad9522 clock control - clock_ctrl::sptr _clock_ctrl; + usrp_e_clock_ctrl::sptr _clock_ctrl; //ad9862 codec control - codec_ctrl::sptr _codec_ctrl; + usrp_e_codec_ctrl::sptr _codec_ctrl; //device functions and settings void get(const wax::obj &, wax::obj &); -- cgit v1.2.3 From a5dca07971587e3b20e57924227c020f13bfd700 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 4 Jun 2010 22:44:06 +0000 Subject: implemented dsp and rx control --- host/lib/usrp/usrp_e/dsp_impl.cpp | 137 ++++++++++++++++++++++++++++++++--- host/lib/usrp/usrp_e/io_impl.cpp | 40 +++++++++- host/lib/usrp/usrp_e/mboard_impl.cpp | 12 ++- host/lib/usrp/usrp_e/usrp_e_impl.hpp | 6 ++ 4 files changed, 182 insertions(+), 13 deletions(-) diff --git a/host/lib/usrp/usrp_e/dsp_impl.cpp b/host/lib/usrp/usrp_e/dsp_impl.cpp index e61f529ab..11d22d15f 100644 --- a/host/lib/usrp/usrp_e/dsp_impl.cpp +++ b/host/lib/usrp/usrp_e/dsp_impl.cpp @@ -15,14 +15,34 @@ // along with this program. If not, see . // -#include #include "usrp_e_impl.hpp" +#include "usrp_e_regs.hpp" +#include +#include +#include +#include + +#define rint boost::math::iround +using namespace uhd; using namespace uhd::usrp; /*********************************************************************** * Helper Functions **********************************************************************/ +static boost::uint32_t calculate_freq_word_and_update_actual_freq(double &freq, double clock_freq){ + UHD_ASSERT_THROW(std::abs(freq) < clock_freq/2.0); + static const double scale_factor = std::pow(2.0, 32); + + //calculate the freq register word + boost::uint32_t freq_word = rint((freq / clock_freq) * scale_factor); + + //update the actual frequency + freq = (double(freq_word) / scale_factor) * clock_freq; + + return freq_word; +} + // Check if requested decim/interp rate is: // multiple of 4, enable two halfband filters // multiple of 2, enable one halfband filter @@ -57,15 +77,62 @@ void usrp_e_impl::rx_ddc_init(void){ /*********************************************************************** * RX DDC Get **********************************************************************/ -void usrp_e_impl::rx_ddc_get(const wax::obj &, wax::obj &){ - UHD_THROW_PROP_GET_ERROR(); +void usrp_e_impl::rx_ddc_get(const wax::obj &key, wax::obj &val){ + switch(key.as()){ + case DSP_PROP_NAME: + val = std::string("usrp-e ddc0"); + return; + + case DSP_PROP_OTHERS: + val = prop_names_t(); //empty + return; + + case DSP_PROP_FREQ_SHIFT: + val = _ddc_freq; + return; + + case DSP_PROP_CODEC_RATE: + val = MASTER_CLOCK_RATE; + return; + + case DSP_PROP_HOST_RATE: + val = MASTER_CLOCK_RATE/_ddc_decim; + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } } /*********************************************************************** * RX DDC Set **********************************************************************/ -void usrp_e_impl::rx_ddc_set(const wax::obj &, const wax::obj &){ - UHD_THROW_PROP_SET_ERROR(); +void usrp_e_impl::rx_ddc_set(const wax::obj &key, const wax::obj &val){ + switch(key.as()){ + + case DSP_PROP_FREQ_SHIFT:{ + double new_freq = val.as(); + _iface->poke32(UE_REG_DSP_RX_FREQ, + calculate_freq_word_and_update_actual_freq(new_freq, MASTER_CLOCK_RATE) + ); + _ddc_freq = new_freq; //shadow + } + return; + + case DSP_PROP_HOST_RATE:{ + //set the decimation + _ddc_decim = rint(MASTER_CLOCK_RATE/val.as()); + _iface->poke32(UE_REG_DSP_RX_DECIM_RATE, calculate_cic_word(_ddc_decim)); + + //set the scaling + static const boost::int16_t default_rx_scale_iq = 1024; + _iface->poke32(UE_REG_DSP_RX_SCALE_IQ, + calculate_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq) + ); + } + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } } /*********************************************************************** @@ -81,13 +148,65 @@ void usrp_e_impl::tx_duc_init(void){ /*********************************************************************** * TX DUC Get **********************************************************************/ -void usrp_e_impl::tx_duc_get(const wax::obj &, wax::obj &){ - UHD_THROW_PROP_GET_ERROR(); +void usrp_e_impl::tx_duc_get(const wax::obj &key, wax::obj &val){ + switch(key.as()){ + case DSP_PROP_NAME: + val = std::string("usrp-e duc0"); + return; + + case DSP_PROP_OTHERS: + val = prop_names_t(); //empty + return; + + case DSP_PROP_FREQ_SHIFT: + val = _duc_freq; + return; + + case DSP_PROP_CODEC_RATE: + val = MASTER_CLOCK_RATE; + return; + + case DSP_PROP_HOST_RATE: + val = MASTER_CLOCK_RATE/_duc_interp; + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } } /*********************************************************************** * TX DUC Set **********************************************************************/ -void usrp_e_impl::tx_duc_set(const wax::obj &, const wax::obj &){ - UHD_THROW_PROP_SET_ERROR(); +void usrp_e_impl::tx_duc_set(const wax::obj &key, const wax::obj &val){ + switch(key.as()){ + + case DSP_PROP_FREQ_SHIFT:{ + double new_freq = val.as(); + _iface->poke32(UE_REG_DSP_TX_FREQ, + calculate_freq_word_and_update_actual_freq(new_freq, MASTER_CLOCK_RATE) + ); + _duc_freq = new_freq; //shadow + } + return; + + case DSP_PROP_HOST_RATE:{ + _duc_interp = rint(MASTER_CLOCK_RATE/val.as()); + + // Calculate CIC interpolation (i.e., without halfband interpolators) + size_t tmp_interp = calculate_cic_word(_duc_interp) & 0xff; + + // Calculate closest multiplier constant to reverse gain absent scale multipliers + double interp_cubed = std::pow(double(tmp_interp), 3); + boost::int16_t scale = rint((4096*std::pow(2, ceil(log2(interp_cubed))))/(1.65*interp_cubed)); + + //set the interpolation + _iface->poke32(UE_REG_DSP_TX_INTERP_RATE, calculate_cic_word(_duc_interp)); + + //set the scaling + _iface->poke32(UE_REG_DSP_TX_SCALE_IQ, calculate_iq_scale_word(scale, scale)); + } + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } } diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index f83829cb8..5914bc613 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -16,6 +16,7 @@ // #include "usrp_e_impl.hpp" +#include "usrp_e_regs.hpp" #include "../../transport/vrt_packet_handler.hpp" #include #include //read, write @@ -86,9 +87,44 @@ struct usrp_e_impl::io_impl{ }; void usrp_e_impl::io_init(void){ + //setup rx data path + _iface->poke32(UE_REG_CTRL_RX_NSAMPS_PER_PKT, 1000); //FIXME magic number + _iface->poke32(UE_REG_CTRL_RX_NCHANNELS, 1); + _iface->poke32(UE_REG_CTRL_RX_CLEAR_OVERRUN, 1); //reset + _iface->poke32(UE_REG_CTRL_RX_VRT_HEADER, 0 + | (0x1 << 28) //if data with stream id + | (0x1 << 26) //has trailer + | (0x3 << 22) //integer time other + | (0x1 << 20) //fractional time sample count + ); + _iface->poke32(UE_REG_CTRL_RX_VRT_STREAM_ID, 0); + _iface->poke32(UE_REG_CTRL_RX_VRT_TRAILER, 0); + _io_impl = UHD_PIMPL_MAKE(io_impl, (_iface->get_file_descriptor())); } +static boost::uint32_t make_stream_cmd(bool now, bool chain, boost::uint32_t nsamps){ + return (((now)? 1 : 0) << 31) | (((chain)? 1 : 0) << 30) | nsamps; +} + +void usrp_e_impl::issue_stream_cmd(const stream_cmd_t &stream_cmd){ + boost::uint32_t cmd = 0; + switch(stream_cmd.stream_mode){ + case stream_cmd_t::STREAM_MODE_NUM_SAMPS_AND_DONE: + cmd = make_stream_cmd(stream_cmd.stream_now, false, stream_cmd.num_samps); + break; + + case stream_cmd_t::STREAM_MODE_NUM_SAMPS_AND_MORE: + cmd = make_stream_cmd(stream_cmd.stream_now, true, stream_cmd.num_samps); + break; + + default: throw std::runtime_error("stream mode not implemented"); + } + _iface->poke32(UE_REG_CTRL_RX_STREAM_CMD, cmd); + _iface->poke32(UE_REG_CTRL_RX_TIME_SECS, stream_cmd.time_spec.secs); + _iface->poke32(UE_REG_CTRL_RX_TIME_TICKS, stream_cmd.time_spec.get_ticks(MASTER_CLOCK_RATE)); +} + /*********************************************************************** * Data Send **********************************************************************/ @@ -110,7 +146,7 @@ size_t usrp_e_impl::send( send_mode, io_type, send_otw_type, //TODO - 64e6, //TODO + MASTER_CLOCK_RATE, boost::bind(&data_transport::get_send_buff, &_io_impl->transport), (MAX_BUFF_SIZE - sizeof(usrp_transfer_frame))/send_otw_type.get_sample_size(), offsetof(usrp_transfer_frame, buf) @@ -138,7 +174,7 @@ size_t usrp_e_impl::recv( recv_mode, io_type, recv_otw_type, //TODO - 64e6, //TODO + MASTER_CLOCK_RATE, boost::bind(&data_transport::get_recv_buff, &_io_impl->transport), offsetof(usrp_transfer_frame, buf) ); diff --git a/host/lib/usrp/usrp_e/mboard_impl.cpp b/host/lib/usrp/usrp_e/mboard_impl.cpp index 00ce4b782..efbde38ce 100644 --- a/host/lib/usrp/usrp_e/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e/mboard_impl.cpp @@ -108,6 +108,14 @@ void usrp_e_impl::mboard_get(const wax::obj &key_, wax::obj &val){ /*********************************************************************** * Mboard Set **********************************************************************/ -void usrp_e_impl::mboard_set(const wax::obj &, const wax::obj &){ - UHD_THROW_PROP_SET_ERROR(); +void usrp_e_impl::mboard_set(const wax::obj &key, const wax::obj &val){ + //handle the get request conditioned on the key + switch(key.as()){ + + case MBOARD_PROP_STREAM_CMD: + issue_stream_cmd(val.as()); + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } } diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index bdb1a675b..a9fd856fe 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -22,11 +22,14 @@ #include #include #include +#include #include #ifndef INCLUDED_USRP_E_IMPL_HPP #define INCLUDED_USRP_E_IMPL_HPP +static const double MASTER_CLOCK_RATE = 64e6; + /*! * Make a usrp-e dboard interface. * \param iface the usrp-e interface object @@ -90,6 +93,7 @@ private: //handle io stuff UHD_PIMPL_DECL(io_impl) _io_impl; void io_init(void); + void issue_stream_cmd(const uhd::stream_cmd_t &stream_cmd); //configuration shadows uhd::clock_config_t _clock_config; @@ -131,12 +135,14 @@ private: void rx_ddc_init(void); void rx_ddc_get(const wax::obj &, wax::obj &); void rx_ddc_set(const wax::obj &, const wax::obj &); + double _ddc_freq; size_t _ddc_decim; wax_obj_proxy::sptr _rx_ddc_proxy; //tx duc functions and settings void tx_duc_init(void); void tx_duc_get(const wax::obj &, wax::obj &); void tx_duc_set(const wax::obj &, const wax::obj &); + double _duc_freq; size_t _duc_interp; wax_obj_proxy::sptr _tx_duc_proxy; }; -- cgit v1.2.3 From a5cdd7a311edcb3afdc9673bd7f6ec84bf8e7b6c Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sat, 5 Jun 2010 00:24:16 +0000 Subject: usrp-e more implementation, rx timed samples runs w/o error (no workie though) --- host/lib/usrp/usrp_e/dboard_impl.cpp | 116 +++++++++++++++++++++++++++++++---- host/lib/usrp/usrp_e/io_impl.cpp | 5 ++ host/lib/usrp/usrp_e/mboard_impl.cpp | 23 ++++--- host/lib/usrp/usrp_e/usrp_e_impl.hpp | 3 + 4 files changed, 128 insertions(+), 19 deletions(-) diff --git a/host/lib/usrp/usrp_e/dboard_impl.cpp b/host/lib/usrp/usrp_e/dboard_impl.cpp index 31f792306..22c4ac8b7 100644 --- a/host/lib/usrp/usrp_e/dboard_impl.cpp +++ b/host/lib/usrp/usrp_e/dboard_impl.cpp @@ -17,8 +17,11 @@ #include #include "usrp_e_impl.hpp" +#include +#include #include +using namespace uhd; using namespace uhd::usrp; /*********************************************************************** @@ -32,11 +35,11 @@ void usrp_e_impl::dboard_init(void){ std::cout << _tx_db_eeprom.id.to_pp_string() << std::endl; //create a new dboard interface and manager - dboard_iface::sptr dboard_iface( - make_usrp_e_dboard_iface(_iface, _clock_ctrl, _codec_ctrl) + _dboard_iface = make_usrp_e_dboard_iface( + _iface, _clock_ctrl, _codec_ctrl ); _dboard_manager = dboard_manager::make( - _rx_db_eeprom.id, _tx_db_eeprom.id, dboard_iface + _rx_db_eeprom.id, _tx_db_eeprom.id, _dboard_iface ); //setup the dboard proxies @@ -48,32 +51,123 @@ void usrp_e_impl::dboard_init(void){ boost::bind(&usrp_e_impl::tx_dboard_get, this, _1, _2), boost::bind(&usrp_e_impl::tx_dboard_set, this, _1, _2) ); + + //init the subdevs in use (use the first subdevice) + _rx_subdevs_in_use = prop_names_t(1, _dboard_manager->get_rx_subdev_names().at(0)); + //TODO update_rx_mux_config(); + + _tx_subdevs_in_use = prop_names_t(1, _dboard_manager->get_tx_subdev_names().at(0)); + //TODO update_tx_mux_config(); } /*********************************************************************** * RX Dboard Get **********************************************************************/ -void usrp_e_impl::rx_dboard_get(const wax::obj &, wax::obj &){ - UHD_THROW_PROP_GET_ERROR(); +void usrp_e_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){ + wax::obj key; std::string name; + boost::tie(key, name) = extract_named_prop(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case DBOARD_PROP_NAME: + val = std::string("usrp-e dboard (rx unit)"); + return; + + case DBOARD_PROP_SUBDEV: + val = _dboard_manager->get_rx_subdev(name); + return; + + case DBOARD_PROP_SUBDEV_NAMES: + val = _dboard_manager->get_rx_subdev_names(); + return; + + case DBOARD_PROP_USED_SUBDEVS: + val = _rx_subdevs_in_use; + return; + + case DBOARD_PROP_DBOARD_ID: + val = _rx_db_eeprom.id; + return; + + case DBOARD_PROP_DBOARD_IFACE: + val = _dboard_iface; + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } } /*********************************************************************** * RX Dboard Set **********************************************************************/ -void usrp_e_impl::rx_dboard_set(const wax::obj &, const wax::obj &){ - UHD_THROW_PROP_SET_ERROR(); +void usrp_e_impl::rx_dboard_set(const wax::obj &key, const wax::obj &val){ + switch(key.as()){ + case DBOARD_PROP_USED_SUBDEVS: + _rx_subdevs_in_use = val.as(); + //TODO update_rx_mux_config(); //if the val is bad, this will throw + return; + + case DBOARD_PROP_DBOARD_ID: + _rx_db_eeprom.id = val.as(); + _iface->write_eeprom(I2C_ADDR_RX_DB, 0, _rx_db_eeprom.get_eeprom_bytes()); + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } } /*********************************************************************** * TX Dboard Get **********************************************************************/ -void usrp_e_impl::tx_dboard_get(const wax::obj &, wax::obj &){ - UHD_THROW_PROP_GET_ERROR(); +void usrp_e_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){ + wax::obj key; std::string name; + boost::tie(key, name) = extract_named_prop(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case DBOARD_PROP_NAME: + val = std::string("usrp-e dboard (tx unit)"); + return; + + case DBOARD_PROP_SUBDEV: + val = _dboard_manager->get_tx_subdev(name); + return; + + case DBOARD_PROP_SUBDEV_NAMES: + val = _dboard_manager->get_tx_subdev_names(); + return; + + case DBOARD_PROP_USED_SUBDEVS: + val = _tx_subdevs_in_use; + return; + + case DBOARD_PROP_DBOARD_ID: + val = _tx_db_eeprom.id; + return; + + case DBOARD_PROP_DBOARD_IFACE: + val = _dboard_iface; + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } } /*********************************************************************** * TX Dboard Set **********************************************************************/ -void usrp_e_impl::tx_dboard_set(const wax::obj &, const wax::obj &){ - UHD_THROW_PROP_SET_ERROR(); +void usrp_e_impl::tx_dboard_set(const wax::obj &key, const wax::obj &val){ + switch(key.as()){ + case DBOARD_PROP_USED_SUBDEVS: + _tx_subdevs_in_use = val.as(); + //TODO update_tx_mux_config(); //if the val is bad, this will throw + return; + + case DBOARD_PROP_DBOARD_ID: + _tx_db_eeprom.id = val.as(); + _iface->write_eeprom(I2C_ADDR_TX_DB, 0, _tx_db_eeprom.get_eeprom_bytes()); + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } } diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index 5914bc613..9ebc5b560 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -22,6 +22,8 @@ #include //read, write #include //transfer frame struct #include //offsetof +#include +#include using namespace uhd; @@ -68,6 +70,9 @@ private: ); } size_t recv(const boost::asio::mutable_buffer &buff){ + std::cout << boost::format( + "calling read on fd %d, buff size is %d" + ) % _fd % boost::asio::buffer_size(buff) << std::endl; return read( _fd, boost::asio::buffer_cast(buff), diff --git a/host/lib/usrp/usrp_e/mboard_impl.cpp b/host/lib/usrp/usrp_e/mboard_impl.cpp index efbde38ce..e4a0e81af 100644 --- a/host/lib/usrp/usrp_e/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e/mboard_impl.cpp @@ -16,6 +16,7 @@ // #include "usrp_e_impl.hpp" +#include "usrp_e_regs.hpp" #include #include #include @@ -75,26 +76,22 @@ void usrp_e_impl::mboard_get(const wax::obj &key_, wax::obj &val){ val = prop_names_t(1, ""); //vector of size 1 with empty string return; - case MBOARD_PROP_STREAM_CMD: - //val = TODO - return; - case MBOARD_PROP_RX_DSP: - UHD_ASSERT_THROW(name == "ddc0"); + UHD_ASSERT_THROW(name == ""); val = _rx_ddc_proxy->get_link(); return; case MBOARD_PROP_RX_DSP_NAMES: - val = prop_names_t(1, "ddc0"); + val = prop_names_t(1, ""); return; case MBOARD_PROP_TX_DSP: - UHD_ASSERT_THROW(name == "duc0"); + UHD_ASSERT_THROW(name == ""); val = _tx_duc_proxy->get_link(); return; case MBOARD_PROP_TX_DSP_NAMES: - val = prop_names_t(1, "duc0"); + val = prop_names_t(1, ""); return; case MBOARD_PROP_CLOCK_CONFIG: @@ -116,6 +113,16 @@ void usrp_e_impl::mboard_set(const wax::obj &key, const wax::obj &val){ issue_stream_cmd(val.as()); return; + case MBOARD_PROP_TIME_NOW: + case MBOARD_PROP_TIME_NEXT_PPS:{ + time_spec_t time_spec = val.as(); + _iface->poke32(UE_REG_TIME64_TICKS, time_spec.get_ticks(MASTER_CLOCK_RATE)); + boost::uint32_t imm_flags = (key.as() == MBOARD_PROP_TIME_NOW)? 1 : 0; + _iface->poke32(UE_REG_TIME64_IMM, imm_flags); + _iface->poke32(UE_REG_TIME64_SECS, time_spec.secs); + } + return; + default: UHD_THROW_PROP_SET_ERROR(); } } diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index a9fd856fe..657d2d225 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -118,17 +118,20 @@ private: //xx dboard functions and settings void dboard_init(void); uhd::usrp::dboard_manager::sptr _dboard_manager; + uhd::usrp::dboard_iface::sptr _dboard_iface; //rx dboard functions and settings uhd::usrp::dboard_eeprom_t _rx_db_eeprom; void rx_dboard_get(const wax::obj &, wax::obj &); void rx_dboard_set(const wax::obj &, const wax::obj &); + uhd::prop_names_t _rx_subdevs_in_use; wax_obj_proxy::sptr _rx_dboard_proxy; //tx dboard functions and settings uhd::usrp::dboard_eeprom_t _tx_db_eeprom; void tx_dboard_get(const wax::obj &, wax::obj &); void tx_dboard_set(const wax::obj &, const wax::obj &); + uhd::prop_names_t _tx_subdevs_in_use; wax_obj_proxy::sptr _tx_dboard_proxy; //rx ddc functions and settings -- cgit v1.2.3 From 7332fc3198a81d9f747ea2a033c1cca168858944 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sat, 5 Jun 2010 01:35:19 +0000 Subject: recv giving me something, bad vrt headers though... --- host/lib/usrp/usrp_e/io_impl.cpp | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index 9ebc5b560..7c451a75f 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -73,11 +73,14 @@ private: std::cout << boost::format( "calling read on fd %d, buff size is %d" ) % _fd % boost::asio::buffer_size(buff) << std::endl; - return read( + ssize_t ret = read( _fd, boost::asio::buffer_cast(buff), boost::asio::buffer_size(buff) ); + if (ret < ssize_t(sizeof(usrp_transfer_frame))) return 0; + std::cout << "len " << int(boost::asio::buffer_cast(buff)->len) << std::endl; + return boost::asio::buffer_cast(buff)->len; } }; @@ -93,7 +96,7 @@ struct usrp_e_impl::io_impl{ void usrp_e_impl::io_init(void){ //setup rx data path - _iface->poke32(UE_REG_CTRL_RX_NSAMPS_PER_PKT, 1000); //FIXME magic number + _iface->poke32(UE_REG_CTRL_RX_NSAMPS_PER_PKT, 300); //FIXME magic number _iface->poke32(UE_REG_CTRL_RX_NCHANNELS, 1); _iface->poke32(UE_REG_CTRL_RX_CLEAR_OVERRUN, 1); //reset _iface->poke32(UE_REG_CTRL_RX_VRT_HEADER, 0 @@ -142,7 +145,7 @@ size_t usrp_e_impl::send( otw_type_t send_otw_type; send_otw_type.width = 16; send_otw_type.shift = 0; - send_otw_type.byteorder = otw_type_t::BO_NATIVE; + send_otw_type.byteorder = otw_type_t::BO_BIG_ENDIAN; return vrt_packet_handler::send( _io_impl->send_state, @@ -170,7 +173,7 @@ size_t usrp_e_impl::recv( otw_type_t recv_otw_type; recv_otw_type.width = 16; recv_otw_type.shift = 0; - recv_otw_type.byteorder = otw_type_t::BO_NATIVE; + recv_otw_type.byteorder = otw_type_t::BO_BIG_ENDIAN; return vrt_packet_handler::recv( _io_impl->recv_state, -- cgit v1.2.3 From 761e22013c6715987c411216d012098e60684836 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 6 Jun 2010 02:26:48 -0700 Subject: get rid of redundant fifo18, since we can just use fifo19 and ignore the occ bit --- usrp2/control_lib/newfifo/fifo36_to_fifo18.v | 40 ---------------------------- usrp2/gpmc/gpmc_async.v | 5 ++-- usrp2/gpmc/gpmc_sync.v | 5 ++-- 3 files changed, 6 insertions(+), 44 deletions(-) delete mode 100644 usrp2/control_lib/newfifo/fifo36_to_fifo18.v diff --git a/usrp2/control_lib/newfifo/fifo36_to_fifo18.v b/usrp2/control_lib/newfifo/fifo36_to_fifo18.v deleted file mode 100644 index b636ab9ca..000000000 --- a/usrp2/control_lib/newfifo/fifo36_to_fifo18.v +++ /dev/null @@ -1,40 +0,0 @@ - -module fifo36_to_fifo18 - (input clk, input reset, input clear, - input [35:0] f36_datain, - input f36_src_rdy_i, - output f36_dst_rdy_o, - - output [17:0] f18_dataout, - output f18_src_rdy_o, - input f18_dst_rdy_i ); - - wire f36_sof = f36_datain[32]; - wire f36_eof = f36_datain[33]; - wire f36_occ = f36_datain[35:34]; - - reg phase; - - wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2)); - - assign f18_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16]; - assign f18_dataout[16] = phase ? 0 : f36_sof; - assign f18_dataout[17] = phase ? f36_eof : half_line; - - assign f18_src_rdy_o = f36_src_rdy_i; - assign f36_dst_rdy_o = (phase | half_line) & f18_dst_rdy_i; - - wire f18_xfer = f18_src_rdy_o & f18_dst_rdy_i; - wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o; - - always @(posedge clk) - if(reset) - phase <= 0; - else if(f36_xfer) - phase <= 0; - else if(f18_xfer) - phase <= 1; - - -endmodule // fifo36_to_fifo18 - diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 380689c62..f42b835ed 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -82,16 +82,17 @@ module gpmc_async wire [15:0] rx_fifo_space; wire [35:0] rx36_data; wire rx36_src_rdy, rx36_dst_rdy; + wire dummy; fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 (.clk(wb_clk), .reset(wb_rst), .clear(0), .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); - fifo36_to_fifo18 f18_to_f36 + fifo36_to_fifo19 f36_to_f19 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), - .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) ); + .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo (.clk(fifo_clk), .reset(fifo_rst), .clear(0), diff --git a/usrp2/gpmc/gpmc_sync.v b/usrp2/gpmc/gpmc_sync.v index 825d131d8..bac489ca0 100644 --- a/usrp2/gpmc/gpmc_sync.v +++ b/usrp2/gpmc/gpmc_sync.v @@ -68,11 +68,12 @@ module gpmc_sync wire [17:0] rx18_data, rx18b_data; wire rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy; wire [15:0] rx_fifo_space, rx_frame_len; + wire dummy; - fifo36_to_fifo18 f18_to_f36 + fifo36_to_fifo19 f36_to_f19 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o), - .f18_dataout(rx18_data), .f18_src_rdy_o(rx18_src_rdy), .f18_dst_rdy_i(rx18_dst_rdy) ); + .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) rx_fifo (.wclk(fifo_clk), .datain(rx18_data), -- cgit v1.2.3 From 3122c8c3d9740a2fd5e68b99df627bc632d764da Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 6 Jun 2010 02:50:18 -0700 Subject: added little endian capability for gpmc to fifo and fifo to gpmc, since ARM is LE. --- usrp2/control_lib/newfifo/fifo19_to_fifo36.v | 40 ++++++++++++++----------- usrp2/control_lib/newfifo/fifo36_to_fifo19.v | 44 +++++++++++++++------------- usrp2/gpmc/gpmc_async.v | 4 +-- usrp2/gpmc/gpmc_sync.v | 4 +-- 4 files changed, 51 insertions(+), 41 deletions(-) diff --git a/usrp2/control_lib/newfifo/fifo19_to_fifo36.v b/usrp2/control_lib/newfifo/fifo19_to_fifo36.v index 5f9aeff9b..0e6bcea68 100644 --- a/usrp2/control_lib/newfifo/fifo19_to_fifo36.v +++ b/usrp2/control_lib/newfifo/fifo19_to_fifo36.v @@ -1,26 +1,31 @@ +// Parameter LE tells us if we are little-endian. +// Little-endian means send lower 16 bits first. +// Default is big endian (network order), send upper bits first. + module fifo19_to_fifo36 - (input clk, input reset, input clear, - input [18:0] f19_datain, - input f19_src_rdy_i, - output f19_dst_rdy_o, + #(parameter LE=0) + (input clk, input reset, input clear, + input [18:0] f19_datain, + input f19_src_rdy_i, + output f19_dst_rdy_o, - output [35:0] f36_dataout, - output f36_src_rdy_o, - input f36_dst_rdy_i, - output [31:0] debug - ); + output [35:0] f36_dataout, + output f36_src_rdy_o, + input f36_dst_rdy_i, + output [31:0] debug + ); - reg f36_sof, f36_eof, f36_occ; + reg f36_sof, f36_eof, f36_occ; - reg [1:0] state; - reg [15:0] dat0, dat1; + reg [1:0] state; + reg [15:0] dat0, dat1; - wire f19_sof = f19_datain[16]; - wire f19_eof = f19_datain[17]; - wire f19_occ = f19_datain[18]; + wire f19_sof = f19_datain[16]; + wire f19_eof = f19_datain[17]; + wire f19_occ = f19_datain[18]; - wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i; + wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i; always @(posedge clk) if(f19_src_rdy_i & ((state==0)|xfer_out)) @@ -68,7 +73,8 @@ module fifo19_to_fifo36 dat0 <= f19_datain; assign f19_dst_rdy_o = xfer_out | (state != 2); - assign f36_dataout = {f36_occ,f36_eof,f36_sof,dat0,dat1}; + assign f36_dataout = LE ? {f36_occ,f36_eof,f36_sof,dat1,dat0} : + {f36_occ,f36_eof,f36_sof,dat0,dat1}; assign f36_src_rdy_o = (state == 2); assign debug = state; diff --git a/usrp2/control_lib/newfifo/fifo36_to_fifo19.v b/usrp2/control_lib/newfifo/fifo36_to_fifo19.v index de249aaeb..517a2a476 100644 --- a/usrp2/control_lib/newfifo/fifo36_to_fifo19.v +++ b/usrp2/control_lib/newfifo/fifo36_to_fifo19.v @@ -1,33 +1,38 @@ -module fifo36_to_fifo19 - (input clk, input reset, input clear, - input [35:0] f36_datain, - input f36_src_rdy_i, - output f36_dst_rdy_o, - - output [18:0] f19_dataout, - output f19_src_rdy_o, - input f19_dst_rdy_i ); +// Parameter LE tells us if we are little-endian. +// Little-endian means send lower 16 bits first. +// Default is big endian (network order), send upper bits first. +module fifo36_to_fifo19 + #(parameter LE=0) + (input clk, input reset, input clear, + input [35:0] f36_datain, + input f36_src_rdy_i, + output f36_dst_rdy_o, + + output [18:0] f19_dataout, + output f19_src_rdy_o, + input f19_dst_rdy_i ); + wire f36_sof = f36_datain[32]; wire f36_eof = f36_datain[33]; wire f36_occ = f36_datain[35:34]; - - reg phase; - - wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2)); - assign f19_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16]; + reg phase; + + wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2)); + + assign f19_dataout[15:0] = (LE ^ phase) ? f36_datain[15:0] : f36_datain[31:16]; assign f19_dataout[16] = phase ? 0 : f36_sof; assign f19_dataout[17] = phase ? f36_eof : half_line; assign f19_dataout[18] = f19_dataout[17] & ((f36_occ==1)|(f36_occ==3)); assign f19_src_rdy_o = f36_src_rdy_i; assign f36_dst_rdy_o = (phase | half_line) & f19_dst_rdy_i; - - wire f19_xfer = f19_src_rdy_o & f19_dst_rdy_i; - wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o; - + + wire f19_xfer = f19_src_rdy_o & f19_dst_rdy_i; + wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o; + always @(posedge clk) if(reset) phase <= 0; @@ -36,6 +41,5 @@ module fifo36_to_fifo19 else if(f19_xfer) phase <= 1; - + endmodule // fifo36_to_fifo19 - diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index f42b835ed..1050cef7d 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -64,7 +64,7 @@ module gpmc_async .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied()); - fifo19_to_fifo36 f19_to_f36 + fifo19_to_fifo36 #(.LE(1)) f19_to_f36 // Little endian because ARM is LE (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); @@ -89,7 +89,7 @@ module gpmc_async .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); - fifo36_to_fifo19 f36_to_f19 + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); diff --git a/usrp2/gpmc/gpmc_sync.v b/usrp2/gpmc/gpmc_sync.v index bac489ca0..61c54a793 100644 --- a/usrp2/gpmc/gpmc_sync.v +++ b/usrp2/gpmc/gpmc_sync.v @@ -57,7 +57,7 @@ module gpmc_sync .rclk(fifo_clk), .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied(), .arst(arst)); - fifo19_to_fifo36 f19_to_f36 + fifo19_to_fifo36 #(.LE(1)) f19_to_f36 // Little endian because ARM is LE (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), .f36_dataout(tx_data_o), .f36_src_rdy_o(tx_src_rdy_o), .f36_dst_rdy_i(tx_dst_rdy_i)); @@ -70,7 +70,7 @@ module gpmc_sync wire [15:0] rx_fifo_space, rx_frame_len; wire dummy; - fifo36_to_fifo19 f36_to_f19 + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .f36_datain(rx_data_i), .f36_src_rdy_i(rx_src_rdy_i), .f36_dst_rdy_o(rx_dst_rdy_o), .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); -- cgit v1.2.3 From 2f92808d27efae16368d6dddfbcc74ca181f4d7c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 6 Jun 2010 03:18:39 -0700 Subject: use fifo19 not fifo18 in makefile --- usrp2/top/u1e/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index edfc47c53..cfef1378f 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -109,7 +109,7 @@ control_lib/newfifo/fifo_short.v \ control_lib/newfifo/fifo_long.v \ control_lib/newfifo/fifo_cascade.v \ control_lib/newfifo/fifo36_to_ll8.v \ -control_lib/newfifo/fifo36_to_fifo18.v \ +control_lib/newfifo/fifo36_to_fifo19.v \ control_lib/newfifo/fifo19_to_fifo36.v \ control_lib/newfifo/packet_generator.v \ control_lib/newfifo/packet_verifier.v \ -- cgit v1.2.3 From 552b06b5b281e0953b0268a22357c5f43bd9657c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Sun, 6 Jun 2010 09:53:42 -0700 Subject: remove double declaration --- usrp2/top/u1e/u1e_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 12ce41c23..6dae653ce 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -101,7 +101,7 @@ module u1e_core `ifdef TIMED // TX side - wire tx_enable, tx_src_rdy_int, tx_dst_rdy_int; + wire tx_enable; fifo_pacer tx_pacer (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(tx_enable), -- cgit v1.2.3 From cd84a19214ea03a3615b5ac7997f33fcfc9870ae Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 7 Jun 2010 22:51:02 +0000 Subject: usrp-e: working vrt recv, implemented dsp utils in usrp-e dsp --- host/lib/usrp/usrp_e/codec_ctrl.cpp | 2 +- host/lib/usrp/usrp_e/dsp_impl.cpp | 59 +++++-------------------------------- host/lib/usrp/usrp_e/io_impl.cpp | 27 ++++++++++++----- 3 files changed, 28 insertions(+), 60 deletions(-) diff --git a/host/lib/usrp/usrp_e/codec_ctrl.cpp b/host/lib/usrp/usrp_e/codec_ctrl.cpp index b19606020..ce3458827 100644 --- a/host/lib/usrp/usrp_e/codec_ctrl.cpp +++ b/host/lib/usrp/usrp_e/codec_ctrl.cpp @@ -29,7 +29,7 @@ using namespace uhd; -static const bool codec_debug = true; +static const bool codec_debug = false; /*********************************************************************** * Codec Control Implementation diff --git a/host/lib/usrp/usrp_e/dsp_impl.cpp b/host/lib/usrp/usrp_e/dsp_impl.cpp index 11d22d15f..a87a41ca6 100644 --- a/host/lib/usrp/usrp_e/dsp_impl.cpp +++ b/host/lib/usrp/usrp_e/dsp_impl.cpp @@ -17,53 +17,15 @@ #include "usrp_e_impl.hpp" #include "usrp_e_regs.hpp" +#include "../dsp_utils.hpp" #include -#include #include -#include #define rint boost::math::iround using namespace uhd; using namespace uhd::usrp; -/*********************************************************************** - * Helper Functions - **********************************************************************/ -static boost::uint32_t calculate_freq_word_and_update_actual_freq(double &freq, double clock_freq){ - UHD_ASSERT_THROW(std::abs(freq) < clock_freq/2.0); - static const double scale_factor = std::pow(2.0, 32); - - //calculate the freq register word - boost::uint32_t freq_word = rint((freq / clock_freq) * scale_factor); - - //update the actual frequency - freq = (double(freq_word) / scale_factor) * clock_freq; - - return freq_word; -} - -// Check if requested decim/interp rate is: -// multiple of 4, enable two halfband filters -// multiple of 2, enable one halfband filter -// handle remainder in CIC -static boost::uint32_t calculate_cic_word(size_t rate){ - int hb0 = 0, hb1 = 0; - if (not (rate & 0x1)){ - hb0 = 1; - rate /= 2; - } - if (not (rate & 0x1)){ - hb1 = 1; - rate /= 2; - } - return (hb1 << 9) | (hb0 << 8) | (rate & 0xff); -} - -static boost::uint32_t calculate_iq_scale_word(boost::int16_t i, boost::int16_t q){ - return (boost::uint16_t(i) << 16) | (boost::uint16_t(q) << 0); -} - /*********************************************************************** * RX DDC Initialization **********************************************************************/ @@ -112,7 +74,7 @@ void usrp_e_impl::rx_ddc_set(const wax::obj &key, const wax::obj &val){ case DSP_PROP_FREQ_SHIFT:{ double new_freq = val.as(); _iface->poke32(UE_REG_DSP_RX_FREQ, - calculate_freq_word_and_update_actual_freq(new_freq, MASTER_CLOCK_RATE) + dsp_type1::calc_cordic_word_and_update(new_freq, MASTER_CLOCK_RATE) ); _ddc_freq = new_freq; //shadow } @@ -121,12 +83,12 @@ void usrp_e_impl::rx_ddc_set(const wax::obj &key, const wax::obj &val){ case DSP_PROP_HOST_RATE:{ //set the decimation _ddc_decim = rint(MASTER_CLOCK_RATE/val.as()); - _iface->poke32(UE_REG_DSP_RX_DECIM_RATE, calculate_cic_word(_ddc_decim)); + _iface->poke32(UE_REG_DSP_RX_DECIM_RATE, dsp_type1::calc_cic_filter_word(_ddc_decim)); //set the scaling static const boost::int16_t default_rx_scale_iq = 1024; _iface->poke32(UE_REG_DSP_RX_SCALE_IQ, - calculate_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq) + dsp_type1::calc_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq) ); } return; @@ -183,7 +145,7 @@ void usrp_e_impl::tx_duc_set(const wax::obj &key, const wax::obj &val){ case DSP_PROP_FREQ_SHIFT:{ double new_freq = val.as(); _iface->poke32(UE_REG_DSP_TX_FREQ, - calculate_freq_word_and_update_actual_freq(new_freq, MASTER_CLOCK_RATE) + dsp_type1::calc_cordic_word_and_update(new_freq, MASTER_CLOCK_RATE) ); _duc_freq = new_freq; //shadow } @@ -192,18 +154,11 @@ void usrp_e_impl::tx_duc_set(const wax::obj &key, const wax::obj &val){ case DSP_PROP_HOST_RATE:{ _duc_interp = rint(MASTER_CLOCK_RATE/val.as()); - // Calculate CIC interpolation (i.e., without halfband interpolators) - size_t tmp_interp = calculate_cic_word(_duc_interp) & 0xff; - - // Calculate closest multiplier constant to reverse gain absent scale multipliers - double interp_cubed = std::pow(double(tmp_interp), 3); - boost::int16_t scale = rint((4096*std::pow(2, ceil(log2(interp_cubed))))/(1.65*interp_cubed)); - //set the interpolation - _iface->poke32(UE_REG_DSP_TX_INTERP_RATE, calculate_cic_word(_duc_interp)); + _iface->poke32(UE_REG_DSP_TX_INTERP_RATE, dsp_type1::calc_cic_filter_word(_duc_interp)); //set the scaling - _iface->poke32(UE_REG_DSP_TX_SCALE_IQ, calculate_iq_scale_word(scale, scale)); + _iface->poke32(UE_REG_DSP_TX_SCALE_IQ, dsp_type1::calc_iq_scale_word(_duc_interp)); } return; diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index 7c451a75f..d26f113f5 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -29,6 +29,8 @@ using namespace uhd; static const size_t MAX_BUFF_SIZE = 2048; +static const size_t vrt_header_offset_words32 = offsetof(usrp_transfer_frame, buf)/sizeof(boost::uint32_t); + /*********************************************************************** * Data Transport (phony zero-copy with read/write) **********************************************************************/ @@ -70,17 +72,26 @@ private: ); } size_t recv(const boost::asio::mutable_buffer &buff){ - std::cout << boost::format( - "calling read on fd %d, buff size is %d" - ) % _fd % boost::asio::buffer_size(buff) << std::endl; + //std::cout << boost::format( + // "calling read on fd %d, buff size is %d" + //) % _fd % boost::asio::buffer_size(buff) << std::endl; ssize_t ret = read( _fd, boost::asio::buffer_cast(buff), boost::asio::buffer_size(buff) ); if (ret < ssize_t(sizeof(usrp_transfer_frame))) return 0; - std::cout << "len " << int(boost::asio::buffer_cast(buff)->len) << std::endl; - return boost::asio::buffer_cast(buff)->len; + //overwrite the vrt header length with the transfer frame length + size_t frame_size = boost::asio::buffer_cast(buff)->len; + boost::uint32_t *vrt_header = boost::asio::buffer_cast(buff) + vrt_header_offset_words32; + vrt_header[0] = (vrt_header[0] & ~0xffff) | ((frame_size/sizeof(boost::uint32_t)) & 0xffff); + + //std::cout << "len " << int(boost::asio::buffer_cast(buff)->len) << std::endl; + //for (size_t i = 0; i < 7; i++){ + // std::cout << boost::format(" 0x%08x") % boost::asio::buffer_cast(buff)[i] << std::endl; + //} + + return frame_size; } }; @@ -155,9 +166,10 @@ size_t usrp_e_impl::send( io_type, send_otw_type, //TODO MASTER_CLOCK_RATE, + uhd::transport::vrt::pack_le, boost::bind(&data_transport::get_send_buff, &_io_impl->transport), (MAX_BUFF_SIZE - sizeof(usrp_transfer_frame))/send_otw_type.get_sample_size(), - offsetof(usrp_transfer_frame, buf) + vrt_header_offset_words32 ); } @@ -183,7 +195,8 @@ size_t usrp_e_impl::recv( io_type, recv_otw_type, //TODO MASTER_CLOCK_RATE, + uhd::transport::vrt::unpack_le, boost::bind(&data_transport::get_recv_buff, &_io_impl->transport), - offsetof(usrp_transfer_frame, buf) + vrt_header_offset_words32 ); } -- cgit v1.2.3 From 724af67a222aca01207cda9e0e4a8ce33217b7b8 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 8 Jun 2010 14:16:22 -0700 Subject: debug pins --- usrp2/gpmc/fifo_watcher.v | 4 +++- usrp2/gpmc/gpmc_async.v | 7 +++++-- usrp2/top/u1e/u1e_core.v | 3 ++- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/usrp2/gpmc/fifo_watcher.v b/usrp2/gpmc/fifo_watcher.v index 4bba142b0..fe4e35de3 100644 --- a/usrp2/gpmc/fifo_watcher.v +++ b/usrp2/gpmc/fifo_watcher.v @@ -4,13 +4,15 @@ module fifo_watcher (input clk, input reset, input clear, input src_rdy1, input dst_rdy1, input sof1, input eof1, input src_rdy2, input dst_rdy2, input sof2, input eof2, - output reg have_packet, output [15:0] length, output reg bus_error); + output reg have_packet, output [15:0] length, output reg bus_error, + output [31:0] debug); wire write = src_rdy1 & dst_rdy1 & eof1; wire read = src_rdy2 & dst_rdy2 & eof2; wire have_packet_int; reg [15:0] counter; wire [4:0] pkt_count; + assign debug = pkt_count; fifo_short #(.WIDTH(16)) frame_lengths (.clk(clk), .reset(reset), .clear(clear), diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 1050cef7d..9f7b6dc4c 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -105,11 +105,14 @@ module gpmc_async .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), .frame_len(rx_frame_len) ); + wire [31:0] pkt_count; + fifo_watcher fifo_watcher (.clk(fifo_clk), .reset(fifo_rst), .clear(0), .src_rdy1(rx18_src_rdy), .dst_rdy1(rx18_dst_rdy), .sof1(rx18_data[16]), .eof1(rx18_data[17]), .src_rdy2(rx18b_src_rdy), .dst_rdy2(rx18b_dst_rdy), .sof2(rx18b_data[16]), .eof2(rx18b_data[17]), - .have_packet(rx_have_data), .length(rx_frame_len), .bus_error(bus_error_rx) ); + .have_packet(rx_have_data), .length(rx_frame_len), .bus_error(bus_error_rx), + .debug(pkt_count)); // //////////////////////////////////////////// // Control path on CS6 @@ -122,6 +125,6 @@ module gpmc_async .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), .wb_ack_i(wb_ack_i) ); - assign debug = 0; + assign debug = pkt_count; endmodule // gpmc_async diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 6dae653ce..dde81df6b 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -430,6 +430,7 @@ module u1e_core assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy}, {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy}, {rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0}, - {3'b0, bus_error, misc_gpio[11:0]} }; + {2'b0, bus_error, debug_gpmc[4:0] }, + {misc_gpio[7:0]} }; endmodule // u1e_core -- cgit v1.2.3 From c28838a4ecfc1b3051bb46cf28114eb85a8845c7 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 8 Jun 2010 14:18:27 -0700 Subject: ignores --- usrp2/top/.gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/usrp2/top/.gitignore b/usrp2/top/.gitignore index bf1b77066..0d90f1698 100644 --- a/usrp2/top/.gitignore +++ b/usrp2/top/.gitignore @@ -1 +1,2 @@ /*.sav +build* -- cgit v1.2.3 From c8e2670b63ec4e7dbec1549dbc452dfeacecf07d Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 9 Jun 2010 01:05:14 +0000 Subject: usrp-e: switched otw type to little endian (works now) --- host/lib/usrp/usrp_e/io_impl.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index d26f113f5..a94275b78 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -156,7 +156,7 @@ size_t usrp_e_impl::send( otw_type_t send_otw_type; send_otw_type.width = 16; send_otw_type.shift = 0; - send_otw_type.byteorder = otw_type_t::BO_BIG_ENDIAN; + send_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN; return vrt_packet_handler::send( _io_impl->send_state, @@ -185,7 +185,7 @@ size_t usrp_e_impl::recv( otw_type_t recv_otw_type; recv_otw_type.width = 16; recv_otw_type.shift = 0; - recv_otw_type.byteorder = otw_type_t::BO_BIG_ENDIAN; + recv_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN; return vrt_packet_handler::recv( _io_impl->recv_state, -- cgit v1.2.3 From 71783634c4394e739bbc13a9bb3df7d6ab75c147 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 10 Jun 2010 18:25:42 +0000 Subject: installed mux setting and initing the duc and ddc --- host/lib/usrp/usrp_e/dboard_impl.cpp | 40 ++++++++++++++++++++++-------------- host/lib/usrp/usrp_e/dsp_impl.cpp | 8 ++++++++ host/lib/usrp/usrp_e/usrp_e_regs.hpp | 3 ++- 3 files changed, 35 insertions(+), 16 deletions(-) diff --git a/host/lib/usrp/usrp_e/dboard_impl.cpp b/host/lib/usrp/usrp_e/dboard_impl.cpp index 22c4ac8b7..a384c71a0 100644 --- a/host/lib/usrp/usrp_e/dboard_impl.cpp +++ b/host/lib/usrp/usrp_e/dboard_impl.cpp @@ -15,10 +15,13 @@ // along with this program. If not, see . // -#include #include "usrp_e_impl.hpp" +#include "usrp_e_regs.hpp" +#include "../dsp_utils.hpp" #include #include +#include +#include #include using namespace uhd; @@ -31,9 +34,6 @@ void usrp_e_impl::dboard_init(void){ _rx_db_eeprom = dboard_eeprom_t(_iface->read_eeprom(I2C_ADDR_RX_DB, 0, dboard_eeprom_t::num_bytes())); _tx_db_eeprom = dboard_eeprom_t(_iface->read_eeprom(I2C_ADDR_TX_DB, 0, dboard_eeprom_t::num_bytes())); - std::cout << _rx_db_eeprom.id.to_pp_string() << std::endl; - std::cout << _tx_db_eeprom.id.to_pp_string() << std::endl; - //create a new dboard interface and manager _dboard_iface = make_usrp_e_dboard_iface( _iface, _clock_ctrl, _codec_ctrl @@ -53,11 +53,8 @@ void usrp_e_impl::dboard_init(void){ ); //init the subdevs in use (use the first subdevice) - _rx_subdevs_in_use = prop_names_t(1, _dboard_manager->get_rx_subdev_names().at(0)); - //TODO update_rx_mux_config(); - - _tx_subdevs_in_use = prop_names_t(1, _dboard_manager->get_tx_subdev_names().at(0)); - //TODO update_tx_mux_config(); + rx_dboard_set(DBOARD_PROP_USED_SUBDEVS, prop_names_t(1, _dboard_manager->get_rx_subdev_names().at(0))); + tx_dboard_set(DBOARD_PROP_USED_SUBDEVS, prop_names_t(1, _dboard_manager->get_tx_subdev_names().at(0))); } /*********************************************************************** @@ -102,9 +99,16 @@ void usrp_e_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){ **********************************************************************/ void usrp_e_impl::rx_dboard_set(const wax::obj &key, const wax::obj &val){ switch(key.as()){ - case DBOARD_PROP_USED_SUBDEVS: - _rx_subdevs_in_use = val.as(); - //TODO update_rx_mux_config(); //if the val is bad, this will throw + case DBOARD_PROP_USED_SUBDEVS:{ + _rx_subdevs_in_use = val.as(); + UHD_ASSERT_THROW(_rx_subdevs_in_use.size() == 1); + wax::obj rx_subdev = _dboard_manager->get_rx_subdev(_rx_subdevs_in_use.at(0)); + std::cout << "Using: " << rx_subdev[SUBDEV_PROP_NAME].as() << std::endl; + _iface->poke32(UE_REG_DSP_RX_MUX, dsp_type1::calc_rx_mux_word( + rx_subdev[SUBDEV_PROP_QUADRATURE].as(), + rx_subdev[SUBDEV_PROP_IQ_SWAPPED].as() + )); + } return; case DBOARD_PROP_DBOARD_ID: @@ -158,9 +162,15 @@ void usrp_e_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){ **********************************************************************/ void usrp_e_impl::tx_dboard_set(const wax::obj &key, const wax::obj &val){ switch(key.as()){ - case DBOARD_PROP_USED_SUBDEVS: - _tx_subdevs_in_use = val.as(); - //TODO update_tx_mux_config(); //if the val is bad, this will throw + case DBOARD_PROP_USED_SUBDEVS:{ + _tx_subdevs_in_use = val.as(); + UHD_ASSERT_THROW(_tx_subdevs_in_use.size() == 1); + wax::obj tx_subdev = _dboard_manager->get_tx_subdev(_tx_subdevs_in_use.at(0)); + std::cout << "Using: " << tx_subdev[SUBDEV_PROP_NAME].as() << std::endl; + _iface->poke32(UE_REG_DSP_TX_MUX, dsp_type1::calc_tx_mux_word( + tx_subdev[SUBDEV_PROP_IQ_SWAPPED].as() + )); + } return; case DBOARD_PROP_DBOARD_ID: diff --git a/host/lib/usrp/usrp_e/dsp_impl.cpp b/host/lib/usrp/usrp_e/dsp_impl.cpp index a87a41ca6..58a58706d 100644 --- a/host/lib/usrp/usrp_e/dsp_impl.cpp +++ b/host/lib/usrp/usrp_e/dsp_impl.cpp @@ -34,6 +34,10 @@ void usrp_e_impl::rx_ddc_init(void){ boost::bind(&usrp_e_impl::rx_ddc_get, this, _1, _2), boost::bind(&usrp_e_impl::rx_ddc_set, this, _1, _2) ); + + //initial config and update + rx_ddc_set(DSP_PROP_FREQ_SHIFT, double(0)); + rx_ddc_set(DSP_PROP_HOST_RATE, double(64e6/10)); } /*********************************************************************** @@ -105,6 +109,10 @@ void usrp_e_impl::tx_duc_init(void){ boost::bind(&usrp_e_impl::tx_duc_get, this, _1, _2), boost::bind(&usrp_e_impl::tx_duc_set, this, _1, _2) ); + + //initial config and update + tx_duc_set(DSP_PROP_FREQ_SHIFT, double(0)); + tx_duc_set(DSP_PROP_HOST_RATE, double(64e6/10)); } /*********************************************************************** diff --git a/host/lib/usrp/usrp_e/usrp_e_regs.hpp b/host/lib/usrp/usrp_e/usrp_e_regs.hpp index 67c174208..41cbfa1e2 100644 --- a/host/lib/usrp/usrp_e/usrp_e_regs.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_regs.hpp @@ -174,7 +174,8 @@ #define UE_REG_TIME64_SECS UE_REG_SR_ADDR(28) // value to set absolute secs to on next PPS #define UE_REG_TIME64_TICKS UE_REG_SR_ADDR(29) // value to set absolute ticks to on next PPS #define UE_REG_TIME64_FLAGS UE_REG_SR_ADDR(30) // flags - see chart above -#define UE_REG_TIME64_IMM UE_REG_SR_ADDR(31) // set immediate (0=latch on next pps, 1=latch immediate, default=0) +#define UE_REG_TIME64_IMM UE_REG_SR_ADDR(31) // set immediate (0=latch on next pps, 1=latch immediate, default=0) +#define UE_REG_TIME64_TPS UE_REG_SR_ADDR(31) // clock ticks per second (counter rollover) //pps flags (see above) #define UE_FLAG_TIME64_PPS_NEGEDGE (0 << 0) -- cgit v1.2.3 From aefcb65e7788a9fbb50b443dbd3f248e2d462107 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 10 Jun 2010 12:03:45 -0700 Subject: proper overrun, underrun connections, debug pins. --- usrp2/top/u1e/u1e_core.v | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index dde81df6b..a6654906b 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -96,6 +96,9 @@ module u1e_core (.clk(wb_clk), .reset(wb_rst), .clear(0), .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + + assign tx_underrun = 0; + assign rx_overrun = 0; `endif // LOOPBACK `ifdef TIMED @@ -151,7 +154,7 @@ module u1e_core vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control (.clk(wb_clk), .reset(wb_rst), .clear(0), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time), .overrun(overrun), + .vita_time(vita_time), .overrun(rx_overrun), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy), .debug_rx(vrc_debug)); @@ -183,7 +186,7 @@ module u1e_core vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control (.clk(wb_clk), .reset(wb_rst), .clear(0), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time),.underrun(underrun), + .vita_time(vita_time),.underrun(tx_underrun), .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_vtc) ); @@ -326,7 +329,6 @@ module u1e_core assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; - //assign { rx_overrun, tx_underrun } = 0; // reg_test; assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : @@ -426,7 +428,9 @@ module u1e_core //assign debug = { phase[23:8], txsync, txblank, tx }; - assign debug_gpio_0 = { debug_gpmc }; + assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, rx_i[11:0]}, + {rx1_src_rdy, rx1_dst_rdy, rx_src_rdy, rx_dst_rdy, rx_q[11:0]} }; + assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy}, {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy}, {rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0}, -- cgit v1.2.3 From 7d067d0109d4ee484a65caabcaf173082719f0d4 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 10 Jun 2010 12:19:41 -0700 Subject: left something out of the sensitivity list. --- usrp2/control_lib/nsgpio16LE.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/control_lib/nsgpio16LE.v b/usrp2/control_lib/nsgpio16LE.v index 514b003ce..8aef0c7ae 100644 --- a/usrp2/control_lib/nsgpio16LE.v +++ b/usrp2/control_lib/nsgpio16LE.v @@ -111,7 +111,7 @@ module nsgpio16LE integer n; reg [31:0] igpio; // temporary internal signal - always @(ctrl or line or debug_1 or debug_0 or atr or ddr) + always @(ctrl or line or debug_1 or debug_0 or atr or ddr or dbg) for(n=0;n<32;n=n+1) igpio[n] <= ddr[n] ? (dbg[n] ? (ctrl[n] ? debug_1[n] : debug_0[n]) : (ctrl[n] ? atr[n] : line[n]) ) -- cgit v1.2.3 From b38a1db20233e6d23ffce831c38d67a500e87b51 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 10 Jun 2010 14:50:32 -0700 Subject: much bigger fifos --- usrp2/top/u1e/u1e_core.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index a6654906b..8db995b17 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -25,8 +25,8 @@ module u1e_core input [11:0] misc_gpio, input pps_in ); - localparam TXFIFOSIZE = 11; - localparam RXFIFOSIZE = 11; + localparam TXFIFOSIZE = 13; + localparam RXFIFOSIZE = 13; localparam SR_RX_DSP = 0; // 5 regs localparam SR_RX_CTRL = 8; // 9 regs -- cgit v1.2.3 From a4b11332ab4f6a24bf4645c0b2770f9578a36f45 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 10 Jun 2010 15:45:58 -0700 Subject: debug pins --- usrp2/top/u1e/u1e_core.v | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 8db995b17..64173ef2d 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -428,13 +428,16 @@ module u1e_core //assign debug = { phase[23:8], txsync, txblank, tx }; - assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, rx_i[11:0]}, - {rx1_src_rdy, rx1_dst_rdy, rx_src_rdy, rx_dst_rdy, rx_q[11:0]} }; + assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]}, + {tx1_src_rdy, tx1_dst_rdy, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; + + assign debug_gpio_1 = debug_vtd | debug_vtc; +/* assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy}, {tx_enable, tx_src_rdy, tx_dst_rdy, tx_dst_rdy & ~tx_src_rdy}, {rx_sof, rx_eof, rx_src_rdy, rx_dst_rdy, rx_data[33:32],2'b0}, {2'b0, bus_error, debug_gpmc[4:0] }, {misc_gpio[7:0]} }; - + */ endmodule // u1e_core -- cgit v1.2.3 From 8869208ea8d8dfdd5fe86adc1637b93c4b390c0c Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Fri, 28 May 2010 11:26:40 +0000 Subject: Update usrp_e.h file. Change programs to use struct element status instead of flags. --- host/apps/omap_debug/usrp-e-crc-rw.c | 15 +++++++++++---- host/apps/omap_debug/usrp-e-lb-test.c | 2 +- host/apps/omap_debug/usrp-e-loopback.c | 6 +++--- host/apps/omap_debug/usrp-e-rw-random.c | 4 ++-- host/apps/omap_debug/usrp-e-timed.c | 6 +++--- host/apps/omap_debug/usrp_e.h | 16 +++++++++------- 6 files changed, 29 insertions(+), 20 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-crc-rw.c b/host/apps/omap_debug/usrp-e-crc-rw.c index 8883366ae..c3ae45cc1 100644 --- a/host/apps/omap_debug/usrp-e-crc-rw.c +++ b/host/apps/omap_debug/usrp-e-crc-rw.c @@ -81,13 +81,20 @@ static void *read_thread(void *threadid) } #endif - if (rx_data->flags & RB_OVERRUN) + if (rx_data->status & RB_OVERRUN) printf("O"); - + + printf("rx_data->len = %d\n", rx_data->len); + + crc = 0xFFFFFFFF; - for (i = 0; i < rx_data->len - 4; i++) { + for (i = 0; i < rx_data->len - 4; i+=2) { + crc = ((crc >> 8) & 0x00FFFFFF) ^ + crc_tab[(crc ^ rx_data->buf[i+1]) & 0xFF]; +printf("idx = %d, data = %X, crc = %X\n", i, rx_data->buf[i+1],crc); crc = ((crc >> 8) & 0x00FFFFFF) ^ crc_tab[(crc ^ rx_data->buf[i]) & 0xFF]; +printf("idx = %d, data = %X, crc = %X\n", i, rx_data->buf[i],crc); } p = &rx_data->buf[rx_data->len - 4]; @@ -96,7 +103,7 @@ static void *read_thread(void *threadid) #if 1 printf("rx_data->len = %d\n", rx_data->len); - printf("rx_data->flags = %d\n", rx_data->flags); + printf("rx_data->status = %d\n", rx_data->status); for (i = 0; i < rx_data->len; i++) printf("idx = %d, data = %X\n", i, rx_data->buf[i]); printf("calc crc = %lX, rx crc = %X\n", crc, rx_crc); diff --git a/host/apps/omap_debug/usrp-e-lb-test.c b/host/apps/omap_debug/usrp-e-lb-test.c index 675de8622..68848064e 100644 --- a/host/apps/omap_debug/usrp-e-lb-test.c +++ b/host/apps/omap_debug/usrp-e-lb-test.c @@ -32,7 +32,7 @@ int main(int argc, char *argv[]) tx_data = malloc(2048); rx_data = malloc(2048); - tx_data->flags = 0; + tx_data->status = 0; tx_data->len = sizeof(struct usrp_transfer_frame) + packet_data_length; while (1) { diff --git a/host/apps/omap_debug/usrp-e-loopback.c b/host/apps/omap_debug/usrp-e-loopback.c index 177394947..535ce1025 100644 --- a/host/apps/omap_debug/usrp-e-loopback.c +++ b/host/apps/omap_debug/usrp-e-loopback.c @@ -63,7 +63,7 @@ static void *read_thread(void *threadid) if (cnt < 0) printf("Error returned from read: %d\n", cnt); -// printf("Packet received, flags = %X, len = %d\n", rx_data->flags, rx_data->len); +// printf("Packet received, status = %X, len = %d\n", rx_data->status, rx_data->len); // printf("p->seq_num = %d\n", p->seq_num); @@ -119,7 +119,7 @@ static void *write_thread(void *threadid) // p->data[i] = random() >> 16; p->data[i] = i; - tx_data->flags = 0xdeadbeef; + tx_data->status = 0xdeadbeef; tx_data->len = 8 + packet_data_length * 2; printf("tx_data->len = %d\n", tx_data->len); @@ -127,7 +127,7 @@ static void *write_thread(void *threadid) seq_number = 1; while (1) { -// printf("tx flags = %X, len = %d\n", tx_data->flags, tx_data->len); +// printf("tx status = %X, len = %d\n", tx_data->status, tx_data->len); p->seq_num = seq_number++; p->checksum = calc_checksum(p); cnt = write(fp, tx_data, 2048); diff --git a/host/apps/omap_debug/usrp-e-rw-random.c b/host/apps/omap_debug/usrp-e-rw-random.c index 43f1571cb..5960b8fbd 100644 --- a/host/apps/omap_debug/usrp-e-rw-random.c +++ b/host/apps/omap_debug/usrp-e-rw-random.c @@ -65,7 +65,7 @@ static void *read_thread(void *threadid) while (1) { cnt = read(fp, rx_data, 2048); -// printf("Packet received, flags = %X, len = %d\n", rx_data->flags, rx_data->len); +// printf("Packet received, status = %X, len = %d\n", rx_data->status, rx_data->len); // printf("p->seq_num = %d\n", p->seq_num); if (p->seq_num != prev_seq_num + 1) @@ -102,7 +102,7 @@ static void *write_thread(void *threadid) // p->data[i] = random() >> 16; p->data[i] = i; - tx_data->flags = 0xdeadbeef; + tx_data->status = 0xdeadbeef; tx_data->len = 8 + packet_data_length * 2; printf("tx_data->len = %d\n", tx_data->len); diff --git a/host/apps/omap_debug/usrp-e-timed.c b/host/apps/omap_debug/usrp-e-timed.c index c71651741..3cb33ce2d 100644 --- a/host/apps/omap_debug/usrp-e-timed.c +++ b/host/apps/omap_debug/usrp-e-timed.c @@ -75,7 +75,7 @@ static void *read_thread(void *threadid) } #endif - if (rx_data->flags & RB_OVERRUN) + if (rx_data->status & RB_OVERRUN) printf("O"); bytes_transfered += rx_data->len; @@ -118,7 +118,7 @@ static void *write_thread(void *threadid) // p->data[i] = random() >> 16; p->data[i] = i; - tx_data->flags = 0; + tx_data->status = 0; tx_data->len = 8 + packet_data_length * 2; printf("tx_data->len = %d\n", tx_data->len); @@ -146,7 +146,7 @@ static void *write_thread(void *threadid) } #endif -// printf("tx flags = %X, len = %d\n", tx_data->flags, tx_data->len); +// printf("tx status = %X, len = %d\n", tx_data->status, tx_data->len); p->seq_num = seq_number++; p->checksum = calc_checksum(p); cnt = write(fp, tx_data, 2048); diff --git a/host/apps/omap_debug/usrp_e.h b/host/apps/omap_debug/usrp_e.h index fd74e6e9e..b098ad114 100644 --- a/host/apps/omap_debug/usrp_e.h +++ b/host/apps/omap_debug/usrp_e.h @@ -28,14 +28,14 @@ struct usrp_e_ctl32 { __u32 buf[10]; }; -// SPI interface +/* SPI interface */ #define UE_SPI_TXONLY 0 #define UE_SPI_TXRX 1 -// Defines for spi ctrl register -#define UE_SPI_CTRL_TXNEG (1<<10) -#define UE_SPI_CTRL_RXNEG (1<<9) +/* Defines for spi ctrl register */ +#define UE_SPI_CTRL_TXNEG (1 << 10) +#define UE_SPI_CTRL_RXNEG (1 << 9) #define UE_SPI_PUSH_RISE 0 #define UE_SPI_PUSH_FALL UE_SPI_CTRL_TXNEG @@ -65,20 +65,22 @@ struct usrp_e_i2c { #define USRP_E_I2C_READ _IOWR(USRP_E_IOC_MAGIC, 0x25, struct usrp_e_i2c) #define USRP_E_I2C_WRITE _IOW(USRP_E_IOC_MAGIC, 0x26, struct usrp_e_i2c) -// Data transfer frame definition +/* Data transfer frame definition */ struct usrp_transfer_frame { - __u32 flags; + __u32 status; __u32 len; __u8 buf[]; }; -// Flag defines +/* Flag defines */ #define RB_USER (1 << 0) #define RB_KERNEL (1 << 1) #define RB_OVERRUN (1 << 2) +#define RB_DMA_ACTIVE (1 << 3) struct ring_buffer_entry { + unsigned int flags; unsigned long dma_addr; struct usrp_transfer_frame *frame_addr; }; -- cgit v1.2.3 From 7edefe21d6476e0570313a0bbdeada38ea835b9a Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Sat, 5 Jun 2010 11:43:15 +0000 Subject: Exit on errors. Run until an error occurs. Alloq for up to 2 sequence number errors so program can start with "dirty" fpga contents. --- host/apps/omap_debug/usrp-e-loopback.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-loopback.c b/host/apps/omap_debug/usrp-e-loopback.c index 535ce1025..929d65604 100644 --- a/host/apps/omap_debug/usrp-e-loopback.c +++ b/host/apps/omap_debug/usrp-e-loopback.c @@ -9,6 +9,7 @@ // max length #define PKT_DATA_LENGTH 1016 static int packet_data_length; +static int error; struct pkt { int checksum; @@ -35,7 +36,7 @@ static int calc_checksum(struct pkt *p) static void *read_thread(void *threadid) { - int cnt, prev_seq_num, pkt_count; + int cnt, prev_seq_num, pkt_count, seq_num_failure; struct usrp_transfer_frame *rx_data; struct pkt *p; unsigned long bytes_transfered, elapsed_seconds; @@ -56,12 +57,13 @@ static void *read_thread(void *threadid) prev_seq_num = 0; pkt_count = 0; + seq_num_failure = 0; while (1) { cnt = read(fp, rx_data, 2048); if (cnt < 0) - printf("Error returned from read: %d\n", cnt); + printf("Error returned from read: %d, sequence number = %d\n", cnt, p->seq_num); // printf("Packet received, status = %X, len = %d\n", rx_data->status, rx_data->len); // printf("p->seq_num = %d\n", p->seq_num); @@ -69,15 +71,22 @@ static void *read_thread(void *threadid) pkt_count++; - if (p->seq_num != prev_seq_num + 1) + if (p->seq_num != prev_seq_num + 1) { printf("Sequence number fail, current = %X, previous = %X, pkt_count = %d\n", p->seq_num, prev_seq_num, pkt_count); + + seq_num_failure ++; + if (seq_num_failure > 2) + error = 1; + } + prev_seq_num = p->seq_num; - if (calc_checksum(p) != p->checksum) + if (calc_checksum(p) != p->checksum) { printf("Checksum fail packet = %X, expected = %X, pkt_count = %d\n", calc_checksum(p), p->checksum, pkt_count); - + error = 1; + } bytes_transfered += rx_data->len; @@ -157,6 +166,7 @@ int main(int argc, char *argv[]) printf("fp = %d\n", fp); sched_setscheduler(0, SCHED_RR, &s); + error = 0; if (pthread_create(&rx, NULL, read_thread, (void *) t)) { printf("Failed to create rx thread\n"); @@ -170,7 +180,8 @@ int main(int argc, char *argv[]) exit(-1); } - sleep(10000); + while (!error) + sleep(1); printf("Done sleeping\n"); } -- cgit v1.2.3 From 617488fd6a4f6a2efa0c966a07d6ac1b6201c3aa Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Mon, 7 Jun 2010 14:46:14 +0000 Subject: Rename loopback of random length packets test program so we know it needs loopback fpga image. Needs debug. --- host/apps/omap_debug/Makefile | 4 +- host/apps/omap_debug/usrp-e-random-loopback.c | 149 ++++++++++++++++++++++++++ host/apps/omap_debug/usrp-e-rw-random.c | 149 -------------------------- 3 files changed, 151 insertions(+), 151 deletions(-) create mode 100644 host/apps/omap_debug/usrp-e-random-loopback.c delete mode 100644 host/apps/omap_debug/usrp-e-rw-random.c diff --git a/host/apps/omap_debug/Makefile b/host/apps/omap_debug/Makefile index 17a3858cf..c11609bdd 100644 --- a/host/apps/omap_debug/Makefile +++ b/host/apps/omap_debug/Makefile @@ -1,7 +1,7 @@ CFLAGS=-Wall -I../../lib/usrp/usrp_e/ -march=armv7-a -mtune=cortex-a8 -mfpu=neon -O3 CXXFLAGS=-Wall -I../../lib/usrp/usrp_e/ -march=armv7-a -mtune=cortex-a8 -mfpu=neon -O3 -all : usrp-e-spi usrp-e-i2c usrp-e-loopback usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio usrp-e-debug-pins usrp-e-rw-random usrp-e-timed usrp-e-lb-test usrp-e-crc-rw clkgen-config +all : usrp-e-spi usrp-e-i2c usrp-e-loopback usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio usrp-e-debug-pins usrp-e-random-loopback usrp-e-timed usrp-e-lb-test usrp-e-crc-rw clkgen-config usrp-e-spi : usrp-e-spi.c @@ -13,7 +13,7 @@ usrp-e-loopback : usrp-e-loopback.c usrp-e-timed : usrp-e-timed.c gcc -o $@ $< -lpthread ${CFLAGS} -usrp-e-rw-random : usrp-e-rw-random.c +usrp-e-random-loopback : usrp-e-random-loopback.c gcc -o $@ $< -lpthread ${CFLAGS} usrp-e-crc-rw : usrp-e-crc-rw.c diff --git a/host/apps/omap_debug/usrp-e-random-loopback.c b/host/apps/omap_debug/usrp-e-random-loopback.c new file mode 100644 index 000000000..5960b8fbd --- /dev/null +++ b/host/apps/omap_debug/usrp-e-random-loopback.c @@ -0,0 +1,149 @@ +#include +#include +#include +#include +#include +#include +#include +#include "usrp_e.h" + +// max length #define PKT_DATA_LENGTH 1014 +static int packet_data_length; + +struct pkt { + int checksum; + int seq_num; + int len; + short data[]; +}; + +static int fp; + +static int calc_checksum(struct pkt *p) +{ + int i, sum; + + i = 0; + sum = 0; + + for (i=0; i < p->len; i++) + sum += p->data[i]; + + sum += p->seq_num; + + return sum; +} + +int randN(int n) +{ + long tmp; + + tmp = rand() % n; + + return tmp; +} + +static void *read_thread(void *threadid) +{ + int cnt, prev_seq_num; + struct usrp_transfer_frame *rx_data; + struct pkt *p; + + printf("Greetings from the reading thread!\n"); + + // IMPORTANT: must assume max length packet from fpga + rx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (1014 * 2)); + rx_data = malloc(2048); + p = (struct pkt *) ((void *)rx_data + offsetof(struct usrp_transfer_frame, buf)); + //p = &(rx_data->buf[0]); + printf("Address of rx_data = %p, p = %p\n", rx_data, p); + printf("offsetof = %d\n", offsetof(struct usrp_transfer_frame, buf)); + printf("sizeof rx data = %d\n", sizeof(struct usrp_transfer_frame) + sizeof(struct pkt)); + + prev_seq_num = 0; + + while (1) { + + cnt = read(fp, rx_data, 2048); +// printf("Packet received, status = %X, len = %d\n", rx_data->status, rx_data->len); +// printf("p->seq_num = %d\n", p->seq_num); + + if (p->seq_num != prev_seq_num + 1) + printf("Sequence number fail, current = %d, previous = %d\n", + p->seq_num, prev_seq_num); + prev_seq_num = p->seq_num; + + if (calc_checksum(p) != p->checksum) + printf("Checksum fail packet = %d, expected = %d\n", + calc_checksum(p), p->checksum); + printf("."); + fflush(stdout); +// printf("\n"); + } + +} + +static void *write_thread(void *threadid) +{ + int seq_number, i, cnt, pkt_cnt; + struct usrp_transfer_frame *tx_data; + struct pkt *p; + + printf("Greetings from the write thread!\n"); + + // Allocate max length buffer for frame + tx_data = malloc(2048); + p = (struct pkt *) ((void *)tx_data + offsetof(struct usrp_transfer_frame, buf)); + printf("Address of tx_data = %p, p = %p\n", tx_data, p); + + printf("sizeof rp_transfer_frame = %d, sizeof pkt = %d\n", sizeof(struct usrp_transfer_frame), sizeof(struct pkt)); + + for (i=0; i < 1014; i++) +// p->data[i] = random() >> 16; + p->data[i] = i; + + tx_data->status = 0xdeadbeef; + tx_data->len = 8 + packet_data_length * 2; + + printf("tx_data->len = %d\n", tx_data->len); + + seq_number = 1; + + while (1) { + pkt_cnt = randN(16); + for (i = 0; i < pkt_cnt; i++) { + p->seq_num = seq_number++; + p->len = randN(1013) + 1; + p->checksum = calc_checksum(p); + tx_data->len = 12 + p->len * 2; + cnt = write(fp, tx_data, tx_data->len + 8); + } + sleep(random() >> 31); + } +} + + +int main(int argc, char *argv[]) +{ + pthread_t tx, rx; + long int t; + + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); + + if (pthread_create(&rx, NULL, read_thread, (void *) t)) { + printf("Failed to create rx thread\n"); + exit(-1); + } + + sleep(1); + + if (pthread_create(&tx, NULL, write_thread, (void *) t)) { + printf("Failed to create tx thread\n"); + exit(-1); + } + + sleep(1000000000); + + printf("Done sleeping\n"); +} diff --git a/host/apps/omap_debug/usrp-e-rw-random.c b/host/apps/omap_debug/usrp-e-rw-random.c deleted file mode 100644 index 5960b8fbd..000000000 --- a/host/apps/omap_debug/usrp-e-rw-random.c +++ /dev/null @@ -1,149 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include "usrp_e.h" - -// max length #define PKT_DATA_LENGTH 1014 -static int packet_data_length; - -struct pkt { - int checksum; - int seq_num; - int len; - short data[]; -}; - -static int fp; - -static int calc_checksum(struct pkt *p) -{ - int i, sum; - - i = 0; - sum = 0; - - for (i=0; i < p->len; i++) - sum += p->data[i]; - - sum += p->seq_num; - - return sum; -} - -int randN(int n) -{ - long tmp; - - tmp = rand() % n; - - return tmp; -} - -static void *read_thread(void *threadid) -{ - int cnt, prev_seq_num; - struct usrp_transfer_frame *rx_data; - struct pkt *p; - - printf("Greetings from the reading thread!\n"); - - // IMPORTANT: must assume max length packet from fpga - rx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (1014 * 2)); - rx_data = malloc(2048); - p = (struct pkt *) ((void *)rx_data + offsetof(struct usrp_transfer_frame, buf)); - //p = &(rx_data->buf[0]); - printf("Address of rx_data = %p, p = %p\n", rx_data, p); - printf("offsetof = %d\n", offsetof(struct usrp_transfer_frame, buf)); - printf("sizeof rx data = %d\n", sizeof(struct usrp_transfer_frame) + sizeof(struct pkt)); - - prev_seq_num = 0; - - while (1) { - - cnt = read(fp, rx_data, 2048); -// printf("Packet received, status = %X, len = %d\n", rx_data->status, rx_data->len); -// printf("p->seq_num = %d\n", p->seq_num); - - if (p->seq_num != prev_seq_num + 1) - printf("Sequence number fail, current = %d, previous = %d\n", - p->seq_num, prev_seq_num); - prev_seq_num = p->seq_num; - - if (calc_checksum(p) != p->checksum) - printf("Checksum fail packet = %d, expected = %d\n", - calc_checksum(p), p->checksum); - printf("."); - fflush(stdout); -// printf("\n"); - } - -} - -static void *write_thread(void *threadid) -{ - int seq_number, i, cnt, pkt_cnt; - struct usrp_transfer_frame *tx_data; - struct pkt *p; - - printf("Greetings from the write thread!\n"); - - // Allocate max length buffer for frame - tx_data = malloc(2048); - p = (struct pkt *) ((void *)tx_data + offsetof(struct usrp_transfer_frame, buf)); - printf("Address of tx_data = %p, p = %p\n", tx_data, p); - - printf("sizeof rp_transfer_frame = %d, sizeof pkt = %d\n", sizeof(struct usrp_transfer_frame), sizeof(struct pkt)); - - for (i=0; i < 1014; i++) -// p->data[i] = random() >> 16; - p->data[i] = i; - - tx_data->status = 0xdeadbeef; - tx_data->len = 8 + packet_data_length * 2; - - printf("tx_data->len = %d\n", tx_data->len); - - seq_number = 1; - - while (1) { - pkt_cnt = randN(16); - for (i = 0; i < pkt_cnt; i++) { - p->seq_num = seq_number++; - p->len = randN(1013) + 1; - p->checksum = calc_checksum(p); - tx_data->len = 12 + p->len * 2; - cnt = write(fp, tx_data, tx_data->len + 8); - } - sleep(random() >> 31); - } -} - - -int main(int argc, char *argv[]) -{ - pthread_t tx, rx; - long int t; - - fp = open("/dev/usrp_e0", O_RDWR); - printf("fp = %d\n", fp); - - if (pthread_create(&rx, NULL, read_thread, (void *) t)) { - printf("Failed to create rx thread\n"); - exit(-1); - } - - sleep(1); - - if (pthread_create(&tx, NULL, write_thread, (void *) t)) { - printf("Failed to create tx thread\n"); - exit(-1); - } - - sleep(1000000000); - - printf("Done sleeping\n"); -} -- cgit v1.2.3 From ec451d811c335af672d7a8ffbcfd3d0a1a645b2b Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 14 Jun 2010 22:32:54 +0000 Subject: file option for rx timed samples, misc fixes --- host/examples/rx_timed_samples.cpp | 21 ++++++++++++++++----- host/lib/usrp/usrp_e/codec_ctrl.cpp | 11 +++-------- host/lib/usrp/usrp_e/io_impl.cpp | 4 ++-- host/lib/usrp/usrp_e/usrp_e_impl.hpp | 4 ++-- 4 files changed, 23 insertions(+), 17 deletions(-) diff --git a/host/examples/rx_timed_samples.cpp b/host/examples/rx_timed_samples.cpp index 64da260d5..eb7ef7251 100644 --- a/host/examples/rx_timed_samples.cpp +++ b/host/examples/rx_timed_samples.cpp @@ -20,13 +20,14 @@ #include #include #include +#include #include namespace po = boost::program_options; int UHD_SAFE_MAIN(int argc, char *argv[]){ //variables to be set by po - std::string args; + std::string args, file_path; int seconds_in_future; size_t total_num_samps; double rx_rate, freq; @@ -40,6 +41,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ ("nsamps", po::value(&total_num_samps)->default_value(1000), "total number of samples to receive") ("rxrate", po::value(&rx_rate)->default_value(100e6/16), "rate of incoming samples") ("freq", po::value(&freq)->default_value(0), "rf center frequency in Hz") + ("file", po::value(&file_path)->default_value(""), "write samps to output file") ; po::variables_map vm; po::store(po::parse_command_line(argc, argv, desc), vm); @@ -76,14 +78,20 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ stream_cmd.time_spec = uhd::time_spec_t(seconds_in_future); sdev->issue_stream_cmd(stream_cmd); + std::ofstream outfile; + if(file_path != "") outfile.open (file_path.c_str(), std::ios::out | std::ios::binary); + + //setup recv buffer, io type, and metadata for recv + uhd::rx_metadata_t md; + uhd::io_type_t io_type(uhd::io_type_t::COMPLEX_INT16); + std::vector > recv_mem(dev->get_max_recv_samps_per_packet()); + boost::asio::mutable_buffer buff(boost::asio::buffer(recv_mem)); + //loop until total number of samples reached size_t num_acc_samps = 0; //number of accumulated samples while(num_acc_samps < total_num_samps){ - uhd::rx_metadata_t md; - std::vector > buff(dev->get_max_recv_samps_per_packet()); size_t num_rx_samps = dev->recv( - boost::asio::buffer(buff), - md, uhd::io_type_t::COMPLEX_FLOAT32, + buff, md, io_type, uhd::device::RECV_MODE_ONE_PACKET ); if (num_rx_samps == 0 and num_acc_samps > 0){ @@ -95,11 +103,14 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ std::cout << boost::format("Got packet: %u samples, %u secs, %u nsecs") % num_rx_samps % md.time_spec.secs % md.time_spec.nsecs << std::endl; + if(file_path != "") outfile.write(boost::asio::buffer_cast(buff), num_rx_samps*io_type.size); + num_acc_samps += num_rx_samps; } //finished std::cout << std::endl << "Done!" << std::endl << std::endl; + if(file_path != "") outfile.close(); return 0; } diff --git a/host/lib/usrp/usrp_e/codec_ctrl.cpp b/host/lib/usrp/usrp_e/codec_ctrl.cpp index ce3458827..ac61bc6b4 100644 --- a/host/lib/usrp/usrp_e/codec_ctrl.cpp +++ b/host/lib/usrp/usrp_e/codec_ctrl.cpp @@ -58,9 +58,6 @@ private: usrp_e_codec_ctrl_impl::usrp_e_codec_ctrl_impl(usrp_e_iface::sptr iface){ _iface = iface; - //FIXME temp poke !!! - _iface->poke16(UE_REG_MISC_TEST, 0x0f00); - //soft reset _ad9862_regs.soft_reset = 1; this->send_reg(0); @@ -75,8 +72,8 @@ usrp_e_codec_ctrl_impl::usrp_e_codec_ctrl_impl(usrp_e_iface::sptr iface){ _ad9862_regs.byp_buffer_b = 1; _ad9862_regs.buffer_a_pd = 1; _ad9862_regs.buffer_b_pd = 1; - _ad9862_regs.rx_pga_a = 0x1f; //TODO bring under api control - _ad9862_regs.rx_pga_b = 0x1f; //TODO bring under api control + _ad9862_regs.rx_pga_a = 0;//0x1f; //TODO bring under api control + _ad9862_regs.rx_pga_b = 0;//0x1f; //TODO bring under api control _ad9862_regs.rx_twos_comp = 1; _ad9862_regs.rx_hilbert = ad9862_regs_t::RX_HILBERT_DIS; @@ -85,7 +82,7 @@ usrp_e_codec_ctrl_impl::usrp_e_codec_ctrl_impl(usrp_e_iface::sptr iface){ _ad9862_regs.interleaved = ad9862_regs_t::INTERLEAVED_INTERLEAVED; _ad9862_regs.tx_pga_gain = 199; //TODO bring under api control _ad9862_regs.tx_hilbert = ad9862_regs_t::TX_HILBERT_DIS; - _ad9862_regs.interp = ad9862_regs_t::INTERP_4; + _ad9862_regs.interp = ad9862_regs_t::INTERP_2; _ad9862_regs.tx_twos_comp = 1; _ad9862_regs.fine_mode = ad9862_regs_t::FINE_MODE_BYPASS; _ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_BYPASS; @@ -108,8 +105,6 @@ usrp_e_codec_ctrl_impl::usrp_e_codec_ctrl_impl(usrp_e_iface::sptr iface){ } usrp_e_codec_ctrl_impl::~usrp_e_codec_ctrl_impl(void){ - return; //FIXME remove this later - //set aux dacs to zero this->write_aux_dac(AUX_DAC_A, 0); this->write_aux_dac(AUX_DAC_B, 0); diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index a94275b78..e1c1fe80b 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -107,7 +107,7 @@ struct usrp_e_impl::io_impl{ void usrp_e_impl::io_init(void){ //setup rx data path - _iface->poke32(UE_REG_CTRL_RX_NSAMPS_PER_PKT, 300); //FIXME magic number + _iface->poke32(UE_REG_CTRL_RX_NSAMPS_PER_PKT, get_max_recv_samps_per_packet()); _iface->poke32(UE_REG_CTRL_RX_NCHANNELS, 1); _iface->poke32(UE_REG_CTRL_RX_CLEAR_OVERRUN, 1); //reset _iface->poke32(UE_REG_CTRL_RX_VRT_HEADER, 0 @@ -168,7 +168,7 @@ size_t usrp_e_impl::send( MASTER_CLOCK_RATE, uhd::transport::vrt::pack_le, boost::bind(&data_transport::get_send_buff, &_io_impl->transport), - (MAX_BUFF_SIZE - sizeof(usrp_transfer_frame))/send_otw_type.get_sample_size(), + get_max_send_samps_per_packet(), vrt_header_offset_words32 ); } diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index 657d2d225..487e295cb 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -80,8 +80,8 @@ public: //the io interface size_t send(const boost::asio::const_buffer &, const uhd::tx_metadata_t &, const uhd::io_type_t &, send_mode_t); size_t recv(const boost::asio::mutable_buffer &, uhd::rx_metadata_t &, const uhd::io_type_t &, recv_mode_t); - size_t get_max_send_samps_per_packet(void) const{return _max_num_samples;} - size_t get_max_recv_samps_per_packet(void) const{return _max_num_samples;} + size_t get_max_send_samps_per_packet(void) const{return 300;} + size_t get_max_recv_samps_per_packet(void) const{return 300;} private: //interface to ioctls and file descriptor -- cgit v1.2.3 From 6d43a4e83814c5c325caefb35eb1e07b415d8d37 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 14 Jun 2010 23:15:58 +0000 Subject: fix type, it was supposed to be complex float --- host/examples/rx_timed_samples.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/host/examples/rx_timed_samples.cpp b/host/examples/rx_timed_samples.cpp index eb7ef7251..a7212eba3 100644 --- a/host/examples/rx_timed_samples.cpp +++ b/host/examples/rx_timed_samples.cpp @@ -83,7 +83,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ //setup recv buffer, io type, and metadata for recv uhd::rx_metadata_t md; - uhd::io_type_t io_type(uhd::io_type_t::COMPLEX_INT16); + uhd::io_type_t io_type(uhd::io_type_t::COMPLEX_FLOAT32); std::vector > recv_mem(dev->get_max_recv_samps_per_packet()); boost::asio::mutable_buffer buff(boost::asio::buffer(recv_mem)); -- cgit v1.2.3 From b4b80f1f6e59fa02d508af860f1a572c9224b975 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 15 Jun 2010 01:23:00 +0000 Subject: usrp-e: added poll(...) call before read(...) call --- host/lib/usrp/usrp_e/io_impl.cpp | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index e1c1fe80b..829e923b5 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -22,6 +22,7 @@ #include //read, write #include //transfer frame struct #include //offsetof +#include #include #include @@ -75,12 +76,22 @@ private: //std::cout << boost::format( // "calling read on fd %d, buff size is %d" //) % _fd % boost::asio::buffer_size(buff) << std::endl; + + //setup and call poll on the file descriptor + //return 0 and do not read when poll times out + pollfd pfd; + pfd.fd = _fd; + pfd.events = POLLIN; + if (poll(&pfd, 1, 100 /*ms*/) <= 0) return 0; //timeout + + //perform the blocking read(...) ssize_t ret = read( _fd, boost::asio::buffer_cast(buff), boost::asio::buffer_size(buff) ); if (ret < ssize_t(sizeof(usrp_transfer_frame))) return 0; + //overwrite the vrt header length with the transfer frame length size_t frame_size = boost::asio::buffer_cast(buff)->len; boost::uint32_t *vrt_header = boost::asio::buffer_cast(buff) + vrt_header_offset_words32; -- cgit v1.2.3 From cd537e846af8547b83c4b8f8ca30de4860c7fefb Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Tue, 15 Jun 2010 20:53:28 +0000 Subject: Add gitignore file. --- host/apps/omap_debug/.gitignore | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 host/apps/omap_debug/.gitignore diff --git a/host/apps/omap_debug/.gitignore b/host/apps/omap_debug/.gitignore new file mode 100644 index 000000000..5d6b1c6f5 --- /dev/null +++ b/host/apps/omap_debug/.gitignore @@ -0,0 +1,19 @@ +.gitignore +clkgen-config +fpga-downloader +usrp-e-button +usrp-e-crc-rw +usrp-e-ctl +usrp-e-debug-pins +usrp-e-fpga-rw +usrp-e-gpio +usrp-e-i2c +usrp-e-lb-test +usrp-e-led +usrp-e-loopback +usrp-e-random-loopback +usrp-e-rw +usrp-e-spi +usrp-e-timed +usrp-e-uart +usrp-e-uart-rx -- cgit v1.2.3 From e18a963fb5c35ba9ccf03986e8c82adfe44f0b89 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 16 Jun 2010 17:35:20 +0000 Subject: usrp-e: added type device address argument to usrp-e --- host/lib/usrp/usrp_e/usrp_e_impl.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.cpp b/host/lib/usrp/usrp_e/usrp_e_impl.cpp index 226825510..a534c74b2 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.cpp @@ -44,6 +44,9 @@ static std::string abs_path(const std::string &file_path){ device_addrs_t usrp_e::find(const device_addr_t &hint){ device_addrs_t usrp_e_addrs; + //return an empty list of addresses when type is set to non-usrp-e + if (hint.has_key("type") and hint["type"] != "usrp-e") return usrp_e_addrs; + //device node not provided, assume its 0 if (not hint.has_key("node")){ device_addr_t new_addr = hint; @@ -54,7 +57,7 @@ device_addrs_t usrp_e::find(const device_addr_t &hint){ //use the given device node name if (fs::exists(hint["node"])){ device_addr_t new_addr; - new_addr["name"] = "USRP-E"; + new_addr["type"] = "usrp-e"; new_addr["node"] = abs_path(hint["node"]); usrp_e_addrs.push_back(new_addr); } -- cgit v1.2.3 From 55e0d893e8a596e18c9eeb34e6f518e03c26dd80 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 17 Jun 2010 13:59:51 -0700 Subject: added ability to clear out fifos of tx and rx. --- usrp2/gpmc/gpmc_async.v | 22 +++++++++++----------- usrp2/gpmc/gpmc_to_fifo_async.v | 10 +++++----- usrp2/top/u1e/u1e_core.v | 33 +++++++++++++++++++++------------ 3 files changed, 37 insertions(+), 28 deletions(-) diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 9f7b6dc4c..23bad56ae 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -16,7 +16,7 @@ module gpmc_async output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, // FIFO interface - input fifo_clk, input fifo_rst, + input fifo_clk, input fifo_rst, input clear_tx, input clear_rx, output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, @@ -34,7 +34,7 @@ module gpmc_async wire bus_error_tx, bus_error_rx; always @(posedge fifo_clk) - if(fifo_rst) + if(fifo_rst | clear_tx | clear_rx) bus_error <= 0; else bus_error <= bus_error_tx | bus_error_rx; @@ -54,23 +54,23 @@ module gpmc_async gpmc_to_fifo_async gpmc_to_fifo_async (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE), - .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), + .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), .clear(clear_tx), .data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy), .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space), .bus_error(bus_error_tx) ); fifo_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space), .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied()); fifo19_to_fifo36 #(.LE(1)) f19_to_f36 // Little endian because ARM is LE - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy), .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 - (.clk(wb_clk), .reset(wb_rst), .clear(0), + (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx), .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy), .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i)); @@ -85,22 +85,22 @@ module gpmc_async wire dummy; fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 - (.clk(wb_clk), .reset(wb_rst), .clear(0), + (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), .f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) ); fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), .datain(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space), .dataout(rx18b_data), .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied()); fifo_to_gpmc_async fifo_to_gpmc_async - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy), .EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE), .frame_len(rx_frame_len) ); @@ -108,7 +108,7 @@ module gpmc_async wire [31:0] pkt_count; fifo_watcher fifo_watcher - (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), .src_rdy1(rx18_src_rdy), .dst_rdy1(rx18_dst_rdy), .sof1(rx18_data[16]), .eof1(rx18_data[17]), .src_rdy2(rx18b_src_rdy), .dst_rdy2(rx18b_dst_rdy), .sof2(rx18b_data[16]), .eof2(rx18b_data[17]), .have_packet(rx_have_data), .length(rx_frame_len), .bus_error(bus_error_rx), diff --git a/usrp2/gpmc/gpmc_to_fifo_async.v b/usrp2/gpmc/gpmc_to_fifo_async.v index 3d29745a2..55c0cef50 100644 --- a/usrp2/gpmc/gpmc_to_fifo_async.v +++ b/usrp2/gpmc/gpmc_to_fifo_async.v @@ -2,7 +2,7 @@ module gpmc_to_fifo_async (input [15:0] EM_D, input [1:0] EM_NBE, input EM_NCS, input EM_NWE, - input fifo_clk, input fifo_rst, + input fifo_clk, input fifo_rst, input clear, output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i, input [15:0] frame_len, input [15:0] fifo_space, output reg fifo_ready, @@ -37,7 +37,7 @@ module gpmc_to_fifo_async end always @(posedge fifo_clk) - if(fifo_rst) + if(fifo_rst | clear) src_rdy_o <= 0; else if(do_write) src_rdy_o <= 1; @@ -45,7 +45,7 @@ module gpmc_to_fifo_async src_rdy_o <= 0; // Assume it was taken always @(posedge fifo_clk) - if(fifo_rst) + if(fifo_rst | clear) counter <= 0; else if(do_write) if(last_write) @@ -54,13 +54,13 @@ module gpmc_to_fifo_async counter <= counter + 1; always @(posedge fifo_clk) - if(fifo_rst) + if(fifo_rst | clear) fifo_ready <= 0; else fifo_ready <= /* first_write & */ (fifo_space > 16'd1023); always @(posedge fifo_clk) - if(fifo_rst) + if(fifo_rst | clear) bus_error <= 0; else if(src_rdy_o & ~dst_rdy_i) bus_error <= 1; diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 64173ef2d..787bf016c 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -28,10 +28,11 @@ module u1e_core localparam TXFIFOSIZE = 13; localparam RXFIFOSIZE = 13; - localparam SR_RX_DSP = 0; // 5 regs - localparam SR_RX_CTRL = 8; // 9 regs - localparam SR_TX_DSP = 17; // 5 regs - localparam SR_TX_CTRL = 24; // 2 regs + localparam SR_RX_DSP = 0; // 5 regs + localparam SR_CLEAR_FIFO = 6; // 1 reg + localparam SR_RX_CTRL = 8; // 9 regs + localparam SR_TX_DSP = 17; // 5 regs + localparam SR_TX_CTRL = 24; // 2 regs localparam SR_TIME64 = 28; // 4 regs wire wb_clk = clk_fpga; @@ -65,6 +66,14 @@ module u1e_core wire [7:0] rate; wire bus_error; + + wire clear_rx_int, clear_tx_int, clear_tx, clear_rx, do_clear; + + setting_reg #(.my_addr(SR_CLEAR_FIFO), .width(2)) sr_clear + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out({clear_tx_int,clear_rx_int}),.changed(do_clear)); + assign clear_tx = clear_tx_int & do_clear; + assign clear_rx = clear_rx_int & do_clear; gpmc_async #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE)) gpmc (.arst(wb_rst), @@ -80,7 +89,7 @@ module u1e_core .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), .wb_ack_i(m0_ack), - .fifo_clk(wb_clk), .fifo_rst(wb_rst), + .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx), .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), @@ -93,7 +102,7 @@ module u1e_core `ifdef LOOPBACK fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo - (.clk(wb_clk), .reset(wb_rst), .clear(0), + (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx | clear_rx), .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); @@ -113,7 +122,7 @@ module u1e_core .underrun(tx_underrun), .overrun()); packet_verifier32 pktver32 - (.clk(wb_clk), .reset(wb_rst), .clear(clear), + (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx), .data_i(tx_data), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int), .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); @@ -121,7 +130,7 @@ module u1e_core wire rx_enable; packet_generator32 pktgen32 - (.clk(wb_clk), .reset(wb_rst), .clear(clear), + (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), .data_o(rx_data), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int)); fifo_pacer rx_pacer @@ -152,7 +161,7 @@ module u1e_core .debug(debug_rx_dsp) ); vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control - (.clk(wb_clk), .reset(wb_rst), .clear(0), + (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .vita_time(vita_time), .overrun(rx_overrun), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), @@ -160,7 +169,7 @@ module u1e_core .debug_rx(vrc_debug)); vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer - (.clk(wb_clk), .reset(wb_rst), .clear(0), + (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy), .data_o(rx_data), .dst_rdy_i(rx_dst_rdy), .src_rdy_o(rx_src_rdy), @@ -177,14 +186,14 @@ module u1e_core wire run_tx; vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer - (.clk(wb_clk), .reset(wb_rst), .clear(0), + (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), .debug(debug_vtd) ); vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control - (.clk(wb_clk), .reset(wb_rst), .clear(0), + (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .vita_time(vita_time),.underrun(tx_underrun), .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), -- cgit v1.2.3 From 2f9b6d5530df140a5a03120adc98a5ad32a69cc4 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 17 Jun 2010 22:33:32 +0000 Subject: usrp-e: added verbose for bad poll and read values --- host/lib/usrp/usrp_e/io_impl.cpp | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index 829e923b5..c168d6304 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -28,9 +28,13 @@ using namespace uhd; +/*********************************************************************** + * Constants + **********************************************************************/ static const size_t MAX_BUFF_SIZE = 2048; - static const size_t vrt_header_offset_words32 = offsetof(usrp_transfer_frame, buf)/sizeof(boost::uint32_t); +static const bool usrp_e_io_impl_verbose = true; +static const size_t recv_timeout_ms = 100; /*********************************************************************** * Data Transport (phony zero-copy with read/write) @@ -82,15 +86,28 @@ private: pollfd pfd; pfd.fd = _fd; pfd.events = POLLIN; - if (poll(&pfd, 1, 100 /*ms*/) <= 0) return 0; //timeout + ssize_t poll_ret = poll(&pfd, 1, recv_timeout_ms); + if (poll_ret <= 0){ + if (usrp_e_io_impl_verbose) std::cerr << boost::format( + "usrp-e io impl recv(): poll() returned non-positive value: %d\n" + " -> return 0 for timeout" + ) % poll_ret << std::endl; + return 0; //timeout + } //perform the blocking read(...) - ssize_t ret = read( + ssize_t read_ret = read( _fd, boost::asio::buffer_cast(buff), boost::asio::buffer_size(buff) ); - if (ret < ssize_t(sizeof(usrp_transfer_frame))) return 0; + if (read_ret < ssize_t(sizeof(usrp_transfer_frame))){ + if (usrp_e_io_impl_verbose) std::cerr << boost::format( + "usrp-e io impl recv(): read() returned small value: %d\n" + " -> return 0 for error" + ) % read_ret << std::endl; + return 0; + } //overwrite the vrt header length with the transfer frame length size_t frame_size = boost::asio::buffer_cast(buff)->len; -- cgit v1.2.3 From df6cc603fd5e9dc34665385ac84b94eadf074074 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 21 Jun 2010 19:39:15 +0000 Subject: usrp-e: added clock rate control to dboard iface and clock control impl --- host/lib/usrp/usrp_e/clock_ctrl.cpp | 290 ++++++++++++++++++++-------------- host/lib/usrp/usrp_e/clock_ctrl.hpp | 27 +++- host/lib/usrp/usrp_e/dboard_iface.cpp | 53 +++++-- 3 files changed, 226 insertions(+), 144 deletions(-) diff --git a/host/lib/usrp/usrp_e/clock_ctrl.cpp b/host/lib/usrp/usrp_e/clock_ctrl.cpp index e37b17a54..36799ef63 100644 --- a/host/lib/usrp/usrp_e/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e/clock_ctrl.cpp @@ -17,6 +17,7 @@ #include "clock_ctrl.hpp" #include "ad9522_regs.hpp" +#include #include #include "usrp_e_regs.hpp" //spi slave constants #include @@ -26,21 +27,171 @@ using namespace uhd; +template static void set_clock_divider( + size_t divider, div_type &low, div_type &high +){ + high = divider/2; + low = divider-high; +} + +/*********************************************************************** + * Constants + **********************************************************************/ +static const double master_clock_rate = 320e6; +static const size_t fpga_clock_divider = 5; //64 MHz +static const size_t codec_clock_divider = 5; //64 MHz + /*********************************************************************** * Clock Control Implementation **********************************************************************/ class usrp_e_clock_ctrl_impl : public usrp_e_clock_ctrl{ public: - //structors - usrp_e_clock_ctrl_impl(usrp_e_iface::sptr iface); - ~usrp_e_clock_ctrl_impl(void); + usrp_e_clock_ctrl_impl(usrp_e_iface::sptr iface){ + _iface = iface; + + //init the clock gen registers + //Note: out0 should already be clocking the FPGA or this isnt going to work + _ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO; + _ad9522_regs.status_pin_control = 0x1; //n divider + _ad9522_regs.ld_pin_control = 0x32; //show ref2 + _ad9522_regs.refmon_pin_control = 0x12; //show ref2 + + _ad9522_regs.enable_ref2 = 1; + _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF2; + + _ad9522_regs.r_counter_lsb = 1; + _ad9522_regs.r_counter_msb = 0; + _ad9522_regs.a_counter = 0; + _ad9522_regs.b_counter_lsb = 20; + _ad9522_regs.b_counter_msb = 0; + _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV8_9; + + _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL; + _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_3_0MA; + + _ad9522_regs.vco_calibration_now = 1; //calibrate it! + _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5; + _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_VCO; + + //setup fpga master clock + _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; + set_clock_divider(fpga_clock_divider, + _ad9522_regs.divider0_low_cycles, + _ad9522_regs.divider0_high_cycles + ); + + //setup codec clock + _ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS; + set_clock_divider(codec_clock_divider, + _ad9522_regs.divider1_low_cycles, + _ad9522_regs.divider1_high_cycles + ); + + //setup test clock (same divider as codec clock) + _ad9522_regs.out4_format = ad9522_regs_t::OUT4_FORMAT_CMOS; + _ad9522_regs.out4_cmos_configuration = (true)? + ad9522_regs_t::OUT4_CMOS_CONFIGURATION_A_ON : + ad9522_regs_t::OUT4_CMOS_CONFIGURATION_OFF; + + //setup a list of register ranges to write + typedef std::pair range_t; + static const std::vector ranges = boost::assign::list_of + (range_t(0x000, 0x000)) (range_t(0x010, 0x01F)) + (range_t(0x0F0, 0x0FD)) (range_t(0x190, 0x19B)) + (range_t(0x1E0, 0x1E1)) (range_t(0x230, 0x230)) + ; + + //write initial register values and latch/update + BOOST_FOREACH(const range_t &range, ranges){ + for(boost::uint16_t addr = range.first; addr <= range.second; addr++){ + this->send_reg(addr); + } + } + this->latch_regs(); + //test read: + //boost::uint32_t reg = _ad9522_regs.get_read_reg(0x01b); + //boost::uint32_t result = _iface->transact_spi( + // UE_SPI_SS_AD9522, + // spi_config_t::EDGE_RISE, + // reg, 24, true /*no*/ + //); + //std::cout << "result " << std::hex << result << std::endl; + this->enable_rx_dboard_clock(false); + this->enable_tx_dboard_clock(false); + } + + ~usrp_e_clock_ctrl_impl(void){ + this->enable_rx_dboard_clock(false); + this->enable_tx_dboard_clock(false); + } - void enable_rx_dboard_clock(bool enb); - void enable_tx_dboard_clock(bool enb); + double get_fpga_clock_rate(void){ + return master_clock_rate/fpga_clock_divider; + } - double get_fpga_clock_rate(void){return 64e6;} - double get_rx_dboard_clock_rate(void){return get_fpga_clock_rate();} - double get_tx_dboard_clock_rate(void){return get_fpga_clock_rate();} + /*********************************************************************** + * RX Dboard Clock Control (output 9, divider 3) + **********************************************************************/ + void enable_rx_dboard_clock(bool enb){ + _ad9522_regs.out9_format = ad9522_regs_t::OUT9_FORMAT_CMOS; + _ad9522_regs.out9_cmos_configuration = (enb)? + ad9522_regs_t::OUT9_CMOS_CONFIGURATION_B_ON : + ad9522_regs_t::OUT9_CMOS_CONFIGURATION_OFF; + this->send_reg(0x0F9); + this->latch_regs(); + } + + std::vector get_rx_dboard_clock_rates(void){ + std::vector rates; + for(size_t div = 1; div <= 16+16; div++) rates.push_back(master_clock_rate/div); + return rates; + } + + void set_rx_dboard_clock_rate(double rate){ + assert_has(get_rx_dboard_clock_rates(), rate, "rx dboard clock rate"); + size_t divider = size_t(rate/master_clock_rate); + //bypass when the divider ratio is one + _ad9522_regs.divider3_bypass = (divider == 1)? 1 : 0; + this->send_reg(0x19a); + //set the divider registers + set_clock_divider(divider, + _ad9522_regs.divider3_low_cycles, + _ad9522_regs.divider3_high_cycles + ); + this->send_reg(0x199); + this->latch_regs(); + } + + /*********************************************************************** + * TX Dboard Clock Control (output 6, divider 2) + **********************************************************************/ + void enable_tx_dboard_clock(bool enb){ + _ad9522_regs.out6_format = ad9522_regs_t::OUT6_FORMAT_CMOS; + _ad9522_regs.out6_cmos_configuration = (enb)? + ad9522_regs_t::OUT6_CMOS_CONFIGURATION_B_ON : + ad9522_regs_t::OUT6_CMOS_CONFIGURATION_OFF; + this->send_reg(0x0F6); + this->latch_regs(); + } + + std::vector get_tx_dboard_clock_rates(void){ + return get_rx_dboard_clock_rates(); //same master clock, same dividers... + } + + void set_tx_dboard_clock_rate(double rate){ + assert_has(get_tx_dboard_clock_rates(), rate, "tx dboard clock rate"); + size_t divider = size_t(rate/master_clock_rate); + //bypass when the divider ratio is one + _ad9522_regs.divider2_bypass = (divider == 1)? 1 : 0; + this->send_reg(0x197); + //set the divider registers + set_clock_divider(divider, + _ad9522_regs.divider2_low_cycles, + _ad9522_regs.divider2_high_cycles + ); + this->send_reg(0x196); + this->latch_regs(); + } private: usrp_e_iface::sptr _iface; @@ -50,122 +201,17 @@ private: _ad9522_regs.io_update = 1; this->send_reg(0x232); } - void send_reg(boost::uint16_t addr); -}; -/*********************************************************************** - * Clock Control Methods - **********************************************************************/ -usrp_e_clock_ctrl_impl::usrp_e_clock_ctrl_impl(usrp_e_iface::sptr iface){ - _iface = iface; - - //init the clock gen registers - //Note: out0 should already be clocking the FPGA or this isnt going to work - _ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO; - _ad9522_regs.status_pin_control = 0x1; //n divider - _ad9522_regs.ld_pin_control = 0x32; //show ref2 - _ad9522_regs.refmon_pin_control = 0x12; //show ref2 - - _ad9522_regs.enable_ref2 = 1; - _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF2; - - _ad9522_regs.r_counter_lsb = 1; - _ad9522_regs.r_counter_msb = 0; - _ad9522_regs.a_counter = 0; - _ad9522_regs.b_counter_lsb = 20; - _ad9522_regs.b_counter_msb = 0; - _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV8_9; - - _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL; - _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_3_0MA; - - _ad9522_regs.vco_calibration_now = 1; //calibrate it! - _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5; - _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_VCO; - - //setup fpga master clock - _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; - _ad9522_regs.divider0_low_cycles = 2; //3 low - _ad9522_regs.divider0_high_cycles = 1; //2 high - - //setup codec clock - _ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS; - _ad9522_regs.divider1_low_cycles = 2; //3 low - _ad9522_regs.divider1_high_cycles = 1; //2 high - - //setup test clock (same divider as codec clock) - _ad9522_regs.out4_format = ad9522_regs_t::OUT4_FORMAT_CMOS; - _ad9522_regs.out4_cmos_configuration = (true)? - ad9522_regs_t::OUT4_CMOS_CONFIGURATION_A_ON : - ad9522_regs_t::OUT4_CMOS_CONFIGURATION_OFF; - - //setup a list of register ranges to write - typedef std::pair range_t; - static const std::vector ranges = boost::assign::list_of - (range_t(0x000, 0x000)) (range_t(0x010, 0x01F)) - (range_t(0x0F0, 0x0FD)) (range_t(0x190, 0x19B)) - (range_t(0x1E0, 0x1E1)) (range_t(0x230, 0x230)) - ; - - //write initial register values and latch/update - BOOST_FOREACH(const range_t &range, ranges){ - for(boost::uint16_t addr = range.first; addr <= range.second; addr++){ - this->send_reg(addr); - } + void send_reg(boost::uint16_t addr){ + boost::uint32_t reg = _ad9522_regs.get_write_reg(addr); + //std::cout << "clock control write reg: " << std::hex << reg << std::endl; + _iface->transact_spi( + UE_SPI_SS_AD9522, + spi_config_t::EDGE_RISE, + reg, 24, false /*no rb*/ + ); } - this->latch_regs(); - //test read: - //boost::uint32_t reg = _ad9522_regs.get_read_reg(0x01b); - //boost::uint32_t result = _iface->transact_spi( - // UE_SPI_SS_AD9522, - // spi_config_t::EDGE_RISE, - // reg, 24, true /*no*/ - //); - //std::cout << "result " << std::hex << result << std::endl; - this->enable_rx_dboard_clock(false); - this->enable_tx_dboard_clock(false); -} - -usrp_e_clock_ctrl_impl::~usrp_e_clock_ctrl_impl(void){ - this->enable_rx_dboard_clock(false); - this->enable_tx_dboard_clock(false); -} - -void usrp_e_clock_ctrl_impl::enable_rx_dboard_clock(bool enb){ - _ad9522_regs.out9_format = ad9522_regs_t::OUT9_FORMAT_CMOS; - _ad9522_regs.out9_cmos_configuration = (enb)? - ad9522_regs_t::OUT9_CMOS_CONFIGURATION_B_ON : - ad9522_regs_t::OUT9_CMOS_CONFIGURATION_OFF; - this->send_reg(0x0F9); - - _ad9522_regs.divider3_low_cycles = 2; //3 low - _ad9522_regs.divider3_high_cycles = 1; //2 high - this->send_reg(0x199); - this->latch_regs(); -} - -void usrp_e_clock_ctrl_impl::enable_tx_dboard_clock(bool enb){ - _ad9522_regs.out6_format = ad9522_regs_t::OUT6_FORMAT_CMOS; - _ad9522_regs.out6_cmos_configuration = (enb)? - ad9522_regs_t::OUT6_CMOS_CONFIGURATION_B_ON : - ad9522_regs_t::OUT6_CMOS_CONFIGURATION_OFF; - this->send_reg(0x0F6); - - _ad9522_regs.divider2_low_cycles = 2; //3 low - _ad9522_regs.divider2_high_cycles = 1; //2 high - this->send_reg(0x196); - this->latch_regs(); -} - -void usrp_e_clock_ctrl_impl::send_reg(boost::uint16_t addr){ - boost::uint32_t reg = _ad9522_regs.get_write_reg(addr); - //std::cout << "clock control write reg: " << std::hex << reg << std::endl; - _iface->transact_spi( - UE_SPI_SS_AD9522, - spi_config_t::EDGE_RISE, - reg, 24, false /*no rb*/ - ); -} +}; /*********************************************************************** * Clock Control Make diff --git a/host/lib/usrp/usrp_e/clock_ctrl.hpp b/host/lib/usrp/usrp_e/clock_ctrl.hpp index 692b9eb0e..3b5103ed1 100644 --- a/host/lib/usrp/usrp_e/clock_ctrl.hpp +++ b/host/lib/usrp/usrp_e/clock_ctrl.hpp @@ -21,6 +21,7 @@ #include "usrp_e_iface.hpp" #include #include +#include /*! * The usrp-e clock control: @@ -45,16 +46,30 @@ public: virtual double get_fpga_clock_rate(void) = 0; /*! - * Get the rate of the dboard clock clock line. - * \return the dboard clock rate in Hz + * Get the possible rates of the rx dboard clock. + * \return a vector of clock rates in Hz */ - virtual double get_rx_dboard_clock_rate(void) = 0; + virtual std::vector get_rx_dboard_clock_rates(void) = 0; /*! - * Get the rate of the dboard clock clock line. - * \return the dboard clock rate in Hz + * Get the possible rates of the tx dboard clock. + * \return a vector of clock rates in Hz */ - virtual double get_tx_dboard_clock_rate(void) = 0; + virtual std::vector get_tx_dboard_clock_rates(void) = 0; + + /*! + * Set the rx dboard clock rate to a possible rate. + * \param rate the new clock rate in Hz + * \throw exception when rate cannot be achieved + */ + virtual void set_rx_dboard_clock_rate(double rate) = 0; + + /*! + * Set the tx dboard clock rate to a possible rate. + * \param rate the new clock rate in Hz + * \throw exception when rate cannot be achieved + */ + virtual void set_tx_dboard_clock_rate(double rate) = 0; /*! * Enable/disable the rx dboard clock. diff --git a/host/lib/usrp/usrp_e/dboard_iface.cpp b/host/lib/usrp/usrp_e/dboard_iface.cpp index 594f2a23e..ce00cd40d 100644 --- a/host/lib/usrp/usrp_e/dboard_iface.cpp +++ b/host/lib/usrp/usrp_e/dboard_iface.cpp @@ -40,14 +40,18 @@ public: _iface = iface; _clock = clock; _codec = codec; + + //init the clock rate shadows + this->set_clock_rate(UNIT_RX, _clock->get_fpga_clock_rate()); + this->set_clock_rate(UNIT_TX, _clock->get_fpga_clock_rate()); } ~usrp_e_dboard_iface(void){ /* NOP */ } - void write_aux_dac(unit_t, int, float); - float read_aux_adc(unit_t, int); + void write_aux_dac(unit_t, aux_dac_t, float); + float read_aux_adc(unit_t, aux_adc_t); void set_pin_ctrl(unit_t, boost::uint16_t); void set_atr_reg(unit_t, atr_reg_t, boost::uint16_t); @@ -72,6 +76,8 @@ public: size_t num_bits ); + void set_clock_rate(unit_t, double); + std::vector get_clock_rates(unit_t); double get_clock_rate(unit_t); void set_clock_enabled(unit_t, bool); @@ -79,6 +85,7 @@ private: usrp_e_iface::sptr _iface; usrp_e_clock_ctrl::sptr _clock; usrp_e_codec_ctrl::sptr _codec; + uhd::dict _clock_rates; }; /*********************************************************************** @@ -95,12 +102,24 @@ dboard_iface::sptr make_usrp_e_dboard_iface( /*********************************************************************** * Clock Rates **********************************************************************/ -double usrp_e_dboard_iface::get_clock_rate(unit_t unit){ +void usrp_e_dboard_iface::set_clock_rate(unit_t unit, double rate){ + _clock_rates[unit] = rate; switch(unit){ - case UNIT_RX: return _clock->get_rx_dboard_clock_rate(); - case UNIT_TX: return _clock->get_tx_dboard_clock_rate(); + case UNIT_RX: return _clock->set_rx_dboard_clock_rate(rate); + case UNIT_TX: return _clock->set_tx_dboard_clock_rate(rate); } - UHD_ASSERT_THROW(false); +} + +std::vector usrp_e_dboard_iface::get_clock_rates(unit_t unit){ + switch(unit){ + case UNIT_RX: return _clock->get_rx_dboard_clock_rates(); + case UNIT_TX: return _clock->get_tx_dboard_clock_rates(); + default: UHD_THROW_INVALID_CODE_PATH(); + } +} + +double usrp_e_dboard_iface::get_clock_rate(unit_t unit){ + return _clock_rates[unit]; } void usrp_e_dboard_iface::set_clock_enabled(unit_t unit, bool enb){ @@ -212,26 +231,28 @@ byte_vector_t usrp_e_dboard_iface::read_i2c(boost::uint8_t addr, size_t num_byte /*********************************************************************** * Aux DAX/ADC **********************************************************************/ -void usrp_e_dboard_iface::write_aux_dac(dboard_iface::unit_t, int which, float value){ +void usrp_e_dboard_iface::write_aux_dac(dboard_iface::unit_t, aux_dac_t which, float value){ //same aux dacs for each unit - static const uhd::dict which_to_aux_dac = map_list_of - (0, usrp_e_codec_ctrl::AUX_DAC_A) (1, usrp_e_codec_ctrl::AUX_DAC_B) - (2, usrp_e_codec_ctrl::AUX_DAC_C) (3, usrp_e_codec_ctrl::AUX_DAC_D) + static const uhd::dict which_to_aux_dac = map_list_of + (AUX_DAC_A, usrp_e_codec_ctrl::AUX_DAC_A) + (AUX_DAC_B, usrp_e_codec_ctrl::AUX_DAC_B) + (AUX_DAC_C, usrp_e_codec_ctrl::AUX_DAC_C) + (AUX_DAC_D, usrp_e_codec_ctrl::AUX_DAC_D) ; _codec->write_aux_dac(which_to_aux_dac[which], value); } -float usrp_e_dboard_iface::read_aux_adc(dboard_iface::unit_t unit, int which){ +float usrp_e_dboard_iface::read_aux_adc(dboard_iface::unit_t unit, aux_adc_t which){ static const uhd::dict< - unit_t, uhd::dict + unit_t, uhd::dict > unit_to_which_to_aux_adc = map_list_of (UNIT_RX, map_list_of - (0, usrp_e_codec_ctrl::AUX_ADC_A1) - (1, usrp_e_codec_ctrl::AUX_ADC_B1) + (AUX_ADC_A, usrp_e_codec_ctrl::AUX_ADC_A1) + (AUX_ADC_B, usrp_e_codec_ctrl::AUX_ADC_B1) ) (UNIT_TX, map_list_of - (0, usrp_e_codec_ctrl::AUX_ADC_A2) - (1, usrp_e_codec_ctrl::AUX_ADC_B2) + (AUX_ADC_A, usrp_e_codec_ctrl::AUX_ADC_A2) + (AUX_ADC_B, usrp_e_codec_ctrl::AUX_ADC_B2) ) ; return _codec->read_aux_adc(unit_to_which_to_aux_adc[unit][which]); -- cgit v1.2.3 From e6aed138b08100fe81355771fc62d4ff2f7556d0 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 23 Jun 2010 00:16:59 +0000 Subject: usrp-e: clock divider calculation fix --- host/lib/usrp/usrp_e/clock_ctrl.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/host/lib/usrp/usrp_e/clock_ctrl.cpp b/host/lib/usrp/usrp_e/clock_ctrl.cpp index 36799ef63..bf38db8a6 100644 --- a/host/lib/usrp/usrp_e/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e/clock_ctrl.cpp @@ -30,8 +30,8 @@ using namespace uhd; template static void set_clock_divider( size_t divider, div_type &low, div_type &high ){ - high = divider/2; - low = divider-high; + high = divider/2 - 1; + low = divider - high - 2; } /*********************************************************************** -- cgit v1.2.3 From 2ff1a854669a0fe5c8029f0c013e38faade6b826 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 23 Jun 2010 01:43:25 +0000 Subject: usrp-e: clock control constants to easily change dividers and counters, tweaks to ic reg maps common --- host/lib/ic_reg_maps/common.py | 4 +-- host/lib/ic_reg_maps/gen_ad9522_regs.py | 2 ++ host/lib/usrp/usrp_e/clock_ctrl.cpp | 50 ++++++++++++++++++++------------- 3 files changed, 34 insertions(+), 22 deletions(-) diff --git a/host/lib/ic_reg_maps/common.py b/host/lib/ic_reg_maps/common.py index 173186eb1..47325a7e3 100644 --- a/host/lib/ic_reg_maps/common.py +++ b/host/lib/ic_reg_maps/common.py @@ -59,7 +59,7 @@ public: delete _state; } -$body + $body void save_state(void){ if (_state == NULL) _state = new $(name)_t(); @@ -181,7 +181,7 @@ def generate(name, regs_tmpl, body_tmpl='', file=__file__): else: regs.append(reg(entry)) #evaluate the body template with the list of registers - body = parse_tmpl(body_tmpl, regs=regs).replace('\n', '\n ').strip() + body = '\n '.join(parse_tmpl(body_tmpl, regs=regs).splitlines()) #evaluate the code template with the parsed registers and arguments code = parse_tmpl(COMMON_TMPL, diff --git a/host/lib/ic_reg_maps/gen_ad9522_regs.py b/host/lib/ic_reg_maps/gen_ad9522_regs.py index 9da51205b..ed6b5f48d 100755 --- a/host/lib/ic_reg_maps/gen_ad9522_regs.py +++ b/host/lib/ic_reg_maps/gen_ad9522_regs.py @@ -32,9 +32,11 @@ cp_mode 0x010[3:2] 3 high_imp, force pll_power_down 0x010[1:0] 1 normal=0, async=1, sync=3 r_counter_lsb 0x011[7:0] 1 r_counter_msb 0x012[5:0] 0 +~r_counter r_counter_lsb, r_counter_msb a_counter 0x013[5:0] 0 b_counter_lsb 0x014[7:0] 3 b_counter_msb 0x015[4:0] 0 +~b_counter b_counter_lsb, b_counter_msb set_cp_pin_to_vcp_2 0x016[7] 0 normal, vcp_2 reset_r_counter 0x016[6] 0 reset_a_and_b_counters 0x016[5] 0 diff --git a/host/lib/usrp/usrp_e/clock_ctrl.cpp b/host/lib/usrp/usrp_e/clock_ctrl.cpp index bf38db8a6..0b18763a4 100644 --- a/host/lib/usrp/usrp_e/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e/clock_ctrl.cpp @@ -27,19 +27,31 @@ using namespace uhd; -template static void set_clock_divider( - size_t divider, div_type &low, div_type &high +template static void set_clock_divider( + size_t divider, div_type &low, div_type &high, bypass_type &bypass ){ high = divider/2 - 1; low = divider - high - 2; + bypass = (divider == 1)? 1 : 0; } /*********************************************************************** * Constants **********************************************************************/ -static const double master_clock_rate = 320e6; -static const size_t fpga_clock_divider = 5; //64 MHz -static const size_t codec_clock_divider = 5; //64 MHz +static const double ref_clock_rate = 10e6; + +static const size_t r_counter = 1; +static const size_t a_counter = 0; +static const size_t b_counter = 20; +static const size_t prescaler = 8; //set below with enum +static const size_t vco_divider = 5; //set below with enum + +static const size_t n_counter = prescaler * b_counter + a_counter; +static const size_t vco_clock_rate = ref_clock_rate/r_counter * n_counter; +static const double master_clock_rate = vco_clock_rate/vco_divider; + +static const size_t fpga_clock_divider = size_t(master_clock_rate/64e6); +static const size_t codec_clock_divider = size_t(master_clock_rate/64e6); /*********************************************************************** * Clock Control Implementation @@ -59,11 +71,9 @@ public: _ad9522_regs.enable_ref2 = 1; _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF2; - _ad9522_regs.r_counter_lsb = 1; - _ad9522_regs.r_counter_msb = 0; - _ad9522_regs.a_counter = 0; - _ad9522_regs.b_counter_lsb = 20; - _ad9522_regs.b_counter_msb = 0; + _ad9522_regs.set_r_counter(r_counter); + _ad9522_regs.a_counter = a_counter; + _ad9522_regs.set_b_counter(b_counter); _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV8_9; _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL; @@ -77,14 +87,16 @@ public: _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; set_clock_divider(fpga_clock_divider, _ad9522_regs.divider0_low_cycles, - _ad9522_regs.divider0_high_cycles + _ad9522_regs.divider0_high_cycles, + _ad9522_regs.divider0_bypass ); //setup codec clock _ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS; set_clock_divider(codec_clock_divider, _ad9522_regs.divider1_low_cycles, - _ad9522_regs.divider1_high_cycles + _ad9522_regs.divider1_high_cycles, + _ad9522_regs.divider1_bypass ); //setup test clock (same divider as codec clock) @@ -150,15 +162,14 @@ public: void set_rx_dboard_clock_rate(double rate){ assert_has(get_rx_dboard_clock_rates(), rate, "rx dboard clock rate"); size_t divider = size_t(rate/master_clock_rate); - //bypass when the divider ratio is one - _ad9522_regs.divider3_bypass = (divider == 1)? 1 : 0; - this->send_reg(0x19a); //set the divider registers set_clock_divider(divider, _ad9522_regs.divider3_low_cycles, - _ad9522_regs.divider3_high_cycles + _ad9522_regs.divider3_high_cycles, + _ad9522_regs.divider3_bypass ); this->send_reg(0x199); + this->send_reg(0x19a); this->latch_regs(); } @@ -181,15 +192,14 @@ public: void set_tx_dboard_clock_rate(double rate){ assert_has(get_tx_dboard_clock_rates(), rate, "tx dboard clock rate"); size_t divider = size_t(rate/master_clock_rate); - //bypass when the divider ratio is one - _ad9522_regs.divider2_bypass = (divider == 1)? 1 : 0; - this->send_reg(0x197); //set the divider registers set_clock_divider(divider, _ad9522_regs.divider2_low_cycles, - _ad9522_regs.divider2_high_cycles + _ad9522_regs.divider2_high_cycles, + _ad9522_regs.divider2_bypass ); this->send_reg(0x196); + this->send_reg(0x197); this->latch_regs(); } -- cgit v1.2.3 From 89a22c7dd531b1754f2401037a4a5c971139bd97 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 7 Jul 2010 01:58:30 +0000 Subject: usrp-e: tweaks to clock control logic --- host/lib/usrp/usrp_e/clock_ctrl.cpp | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/host/lib/usrp/usrp_e/clock_ctrl.cpp b/host/lib/usrp/usrp_e/clock_ctrl.cpp index 0b18763a4..df649cee6 100644 --- a/host/lib/usrp/usrp_e/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e/clock_ctrl.cpp @@ -43,11 +43,11 @@ static const double ref_clock_rate = 10e6; static const size_t r_counter = 1; static const size_t a_counter = 0; static const size_t b_counter = 20; -static const size_t prescaler = 8; //set below with enum -static const size_t vco_divider = 5; //set below with enum +static const size_t prescaler = 8; //set below with enum, set to 8 when input is under 2400 MHz +static const size_t vco_divider = 1; //set below with enum static const size_t n_counter = prescaler * b_counter + a_counter; -static const size_t vco_clock_rate = ref_clock_rate/r_counter * n_counter; +static const size_t vco_clock_rate = ref_clock_rate/r_counter * n_counter; //between 1400 and 1800 MHz static const double master_clock_rate = vco_clock_rate/vco_divider; static const size_t fpga_clock_divider = size_t(master_clock_rate/64e6); @@ -60,15 +60,18 @@ class usrp_e_clock_ctrl_impl : public usrp_e_clock_ctrl{ public: usrp_e_clock_ctrl_impl(usrp_e_iface::sptr iface){ _iface = iface; + std::cout << "master_clock_rate: " << (master_clock_rate/1e6) << " MHz" << std::endl; //init the clock gen registers //Note: out0 should already be clocking the FPGA or this isnt going to work _ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO; + _ad9522_regs.enb_stat_eeprom_at_stat_pin = 0; //use status pin _ad9522_regs.status_pin_control = 0x1; //n divider - _ad9522_regs.ld_pin_control = 0x32; //show ref2 + _ad9522_regs.ld_pin_control = 0x00; //dld _ad9522_regs.refmon_pin_control = 0x12; //show ref2 _ad9522_regs.enable_ref2 = 1; + _ad9522_regs.enable_ref1 = 0; _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF2; _ad9522_regs.set_r_counter(r_counter); @@ -80,7 +83,7 @@ public: _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_3_0MA; _ad9522_regs.vco_calibration_now = 1; //calibrate it! - _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5; + _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV1; _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_VCO; //setup fpga master clock -- cgit v1.2.3 From 998fee6ef064f1d53a61dd0eec79276d1e85291e Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 7 Jul 2010 02:19:20 +0000 Subject: usrp-e: removed top level header for usrp-e and fpga burner app, were not going to do it that way... --- host/include/uhd/usrp/CMakeLists.txt | 4 --- host/include/uhd/usrp/usrp_e.hpp | 54 --------------------------------- host/lib/usrp/usrp_e/CMakeLists.txt | 3 -- host/lib/usrp/usrp_e/fpga-downloader.cc | 3 +- host/lib/usrp/usrp_e/usrp_e_impl.cpp | 16 +++++----- host/lib/usrp/usrp_e/usrp_e_impl.hpp | 7 +++-- host/lib/usrp/usrp_e/usrp_e_none.cpp | 38 ----------------------- host/utils/CMakeLists.txt | 4 --- host/utils/usrp_e_load_fpga.cpp | 47 ---------------------------- 9 files changed, 14 insertions(+), 162 deletions(-) delete mode 100644 host/include/uhd/usrp/usrp_e.hpp delete mode 100644 host/lib/usrp/usrp_e/usrp_e_none.cpp delete mode 100644 host/utils/usrp_e_load_fpga.cpp diff --git a/host/include/uhd/usrp/CMakeLists.txt b/host/include/uhd/usrp/CMakeLists.txt index ff2636d8c..58aa8588a 100644 --- a/host/include/uhd/usrp/CMakeLists.txt +++ b/host/include/uhd/usrp/CMakeLists.txt @@ -31,10 +31,6 @@ INSTALL(FILES dboard_iface.hpp dboard_manager.hpp - ### usrp headers ### - usrp_e.hpp - usrp2.hpp - ### utilities ### tune_helper.hpp simple_usrp.hpp diff --git a/host/include/uhd/usrp/usrp_e.hpp b/host/include/uhd/usrp/usrp_e.hpp deleted file mode 100644 index 557058261..000000000 --- a/host/include/uhd/usrp/usrp_e.hpp +++ /dev/null @@ -1,54 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#ifndef INCLUDED_UHD_USRP_USRP_E_HPP -#define INCLUDED_UHD_USRP_USRP_E_HPP - -#include -#include - -namespace uhd{ namespace usrp{ - -/*! - * The USRP-Embedded device class. - */ -class UHD_API usrp_e : public device{ -public: - /*! - * Find usrp_e devices on the system via the device node. - * \param hint a device addr with the usrp_e address filled in - * \return a vector of device addresses for all usrp-e's found - */ - static device_addrs_t find(const device_addr_t &hint); - - /*! - * Make a usrp_e from a device address. - * \param addr the device address - * \return a device sptr to a new usrp_e - */ - static device::sptr make(const device_addr_t &addr); - - /*! - * Load the FPGA with an image file. - * \param bin_file the name of the fpga image file - */ - static void load_fpga(const std::string &bin_file); -}; - -}} //namespace - -#endif /* INCLUDED_UHD_USRP_USRP_E_HPP */ diff --git a/host/lib/usrp/usrp_e/CMakeLists.txt b/host/lib/usrp/usrp_e/CMakeLists.txt index 568fbd132..db6d162d4 100644 --- a/host/lib/usrp/usrp_e/CMakeLists.txt +++ b/host/lib/usrp/usrp_e/CMakeLists.txt @@ -59,7 +59,4 @@ IF(HAVE_USRP_E_REQUIRED_HEADERS) ) ELSE(HAVE_USRP_E_REQUIRED_HEADERS) MESSAGE(STATUS " Skipping usrp-e support.") - LIBUHD_APPEND_SOURCES( - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_none.cpp - ) ENDIF(HAVE_USRP_E_REQUIRED_HEADERS) diff --git a/host/lib/usrp/usrp_e/fpga-downloader.cc b/host/lib/usrp/usrp_e/fpga-downloader.cc index 4429786a9..ff8671e98 100644 --- a/host/lib/usrp/usrp_e/fpga-downloader.cc +++ b/host/lib/usrp/usrp_e/fpga-downloader.cc @@ -246,8 +246,7 @@ int main(int argc, char *argv[]) } */ -#include -void uhd::usrp::usrp_e::load_fpga(const std::string &bin_file){ +void usrp_e_load_fpga(const std::string &bin_file){ gpio gpio_prog_b(PROG_B, OUT); gpio gpio_init_b(INIT_B, IN); gpio gpio_done (DONE, IN); diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.cpp b/host/lib/usrp/usrp_e/usrp_e_impl.cpp index a534c74b2..76c77af15 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.cpp @@ -27,10 +27,6 @@ using namespace uhd; using namespace uhd::usrp; namespace fs = boost::filesystem; -UHD_STATIC_BLOCK(register_usrp_e_device){ - device::register_device(&usrp_e::find, &usrp_e::make); -} - /*********************************************************************** * Helper Functions **********************************************************************/ @@ -41,7 +37,7 @@ static std::string abs_path(const std::string &file_path){ /*********************************************************************** * Discovery **********************************************************************/ -device_addrs_t usrp_e::find(const device_addr_t &hint){ +static device_addrs_t usrp_e_find(const device_addr_t &hint){ device_addrs_t usrp_e_addrs; //return an empty list of addresses when type is set to non-usrp-e @@ -51,7 +47,7 @@ device_addrs_t usrp_e::find(const device_addr_t &hint){ if (not hint.has_key("node")){ device_addr_t new_addr = hint; new_addr["node"] = "/dev/usrp_e0"; - return usrp_e::find(new_addr); + return usrp_e_find(new_addr); } //use the given device node name @@ -68,8 +64,12 @@ device_addrs_t usrp_e::find(const device_addr_t &hint){ /*********************************************************************** * Make **********************************************************************/ -device::sptr usrp_e::make(const device_addr_t &device_addr){ - return sptr(new usrp_e_impl(device_addr["node"])); +static device::sptr usrp_e_make(const device_addr_t &device_addr){ + return device::sptr(new usrp_e_impl(device_addr["node"])); +} + +UHD_STATIC_BLOCK(register_usrp_e_device){ + device::register_device(&usrp_e_find, &usrp_e_make); } /*********************************************************************** diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index 487e295cb..e6bea1358 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -18,8 +18,8 @@ #include "usrp_e_iface.hpp" #include "clock_ctrl.hpp" #include "codec_ctrl.hpp" +#include #include -#include #include #include #include @@ -28,7 +28,10 @@ #ifndef INCLUDED_USRP_E_IMPL_HPP #define INCLUDED_USRP_E_IMPL_HPP -static const double MASTER_CLOCK_RATE = 64e6; +static const double MASTER_CLOCK_RATE = 64e6; //TODO get from clock control + +//! load an fpga image from a bin file into the usrp-e fpga +extern void usrp_e_load_fpga(const std::string &bin_file); /*! * Make a usrp-e dboard interface. diff --git a/host/lib/usrp/usrp_e/usrp_e_none.cpp b/host/lib/usrp/usrp_e/usrp_e_none.cpp deleted file mode 100644 index 09a3c6946..000000000 --- a/host/lib/usrp/usrp_e/usrp_e_none.cpp +++ /dev/null @@ -1,38 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include - -using namespace uhd; -using namespace uhd::usrp; - -/*! - * This file defines the usrp1e discover and make functions - * when the required kernel module headers are not present. - */ - -device_addrs_t usrp_e::find(const device_addr_t &){ - return device_addrs_t(); //return empty list -} - -device::sptr usrp_e::make(const device_addr_t &){ - throw std::runtime_error("this build has no usrp1e support"); -} - -void usrp_e::load_fpga(const std::string &){ - throw std::runtime_error("this build has no usrp1e support"); -} diff --git a/host/utils/CMakeLists.txt b/host/utils/CMakeLists.txt index cf056e135..8d260c06c 100644 --- a/host/utils/CMakeLists.txt +++ b/host/utils/CMakeLists.txt @@ -19,10 +19,6 @@ ADD_EXECUTABLE(uhd_find_devices uhd_find_devices.cpp) TARGET_LINK_LIBRARIES(uhd_find_devices uhd) INSTALL(TARGETS uhd_find_devices RUNTIME DESTINATION ${RUNTIME_DIR}) -ADD_EXECUTABLE(usrp_e_load_fpga usrp_e_load_fpga.cpp) -TARGET_LINK_LIBRARIES(usrp_e_load_fpga uhd) -INSTALL(TARGETS usrp_e_load_fpga RUNTIME DESTINATION ${PKG_DATA_DIR}/utils) - ADD_EXECUTABLE(uhd_usrp_probe uhd_usrp_probe.cpp) TARGET_LINK_LIBRARIES(uhd_usrp_probe uhd) INSTALL(TARGETS uhd_usrp_probe RUNTIME DESTINATION ${RUNTIME_DIR}) diff --git a/host/utils/usrp_e_load_fpga.cpp b/host/utils/usrp_e_load_fpga.cpp deleted file mode 100644 index 403130b53..000000000 --- a/host/utils/usrp_e_load_fpga.cpp +++ /dev/null @@ -1,47 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include -#include -#include -#include - -namespace po = boost::program_options; - -int main(int argc, char *argv[]){ - po::options_description desc("Allowed options"); - desc.add_options() - ("help", "help message") - ("file", po::value(), "path to fpga bin file") - ; - - po::variables_map vm; - po::store(po::parse_command_line(argc, argv, desc), vm); - po::notify(vm); - - //print the help message - if (vm.count("help") or vm.count("file") == 0){ - std::cout << boost::format("USRP1E Load FPGA %s") % desc << std::endl; - return ~0; - } - - //load the fpga - std::string file = vm["file"].as(); - uhd::usrp::usrp_e::load_fpga(file); - - return 0; -} -- cgit v1.2.3 From 416f720e56ff4542d5ba4b8c9c145f0a09bf341b Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 7 Jul 2010 03:40:25 +0000 Subject: uhd: updated code to build with latest api, not tested --- host/lib/usrp/usrp_e/io_impl.cpp | 112 ++++++++++++++++++++++------------- host/lib/usrp/usrp_e/mboard_impl.cpp | 4 +- host/lib/usrp/usrp_e/usrp_e_impl.hpp | 4 +- 3 files changed, 74 insertions(+), 46 deletions(-) diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index c168d6304..a77a73b38 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -24,6 +24,7 @@ #include //offsetof #include #include +#include #include using namespace uhd; @@ -127,10 +128,11 @@ private: * IO Implementation Details **********************************************************************/ struct usrp_e_impl::io_impl{ - vrt_packet_handler::recv_state recv_state; - vrt_packet_handler::send_state send_state; + //state management for the vrt packet handler code + vrt_packet_handler::recv_state packet_handler_recv_state; + vrt_packet_handler::send_state packet_handler_send_state; data_transport transport; - io_impl(int fd): transport(fd){} + io_impl(int fd): packet_handler_recv_state(1), transport(fd){} }; void usrp_e_impl::io_init(void){ @@ -150,35 +152,56 @@ void usrp_e_impl::io_init(void){ _io_impl = UHD_PIMPL_MAKE(io_impl, (_iface->get_file_descriptor())); } -static boost::uint32_t make_stream_cmd(bool now, bool chain, boost::uint32_t nsamps){ - return (((now)? 1 : 0) << 31) | (((chain)? 1 : 0) << 30) | nsamps; +static boost::uint32_t make_stream_cmd(bool now, bool chain, bool reload, boost::uint32_t nsamps){ + return (((now)? 1 : 0) << 31) | (((chain)? 1 : 0) << 30) | (((reload)? 1 : 0) << 29) | nsamps; } void usrp_e_impl::issue_stream_cmd(const stream_cmd_t &stream_cmd){ - boost::uint32_t cmd = 0; - switch(stream_cmd.stream_mode){ - case stream_cmd_t::STREAM_MODE_NUM_SAMPS_AND_DONE: - cmd = make_stream_cmd(stream_cmd.stream_now, false, stream_cmd.num_samps); - break; + UHD_ASSERT_THROW(stream_cmd.num_samps <= 0x3fffffff); - case stream_cmd_t::STREAM_MODE_NUM_SAMPS_AND_MORE: - cmd = make_stream_cmd(stream_cmd.stream_now, true, stream_cmd.num_samps); - break; + //setup the mode to instruction flags + typedef boost::tuple inst_t; + static const uhd::dict mode_to_inst = boost::assign::map_list_of + //reload, chain, samps + (stream_cmd_t::STREAM_MODE_START_CONTINUOUS, inst_t(true, true, false)) + (stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS, inst_t(false, false, false)) + (stream_cmd_t::STREAM_MODE_NUM_SAMPS_AND_DONE, inst_t(false, false, true)) + (stream_cmd_t::STREAM_MODE_NUM_SAMPS_AND_MORE, inst_t(false, true, true)) + ; + + //setup the instruction flag values + bool inst_reload, inst_chain, inst_samps; + boost::tie(inst_reload, inst_chain, inst_samps) = mode_to_inst[stream_cmd.stream_mode]; + + //issue the stream command + _iface->poke32(UE_REG_CTRL_RX_STREAM_CMD, make_stream_cmd( + (inst_samps)? stream_cmd.num_samps : ((inst_chain)? get_max_recv_samps_per_packet() : 1), + (stream_cmd.stream_now)? 1 : 0, + (inst_chain)? 1 : 0, + (inst_reload)? 1 : 0 + )); + _iface->poke32(UE_REG_CTRL_RX_TIME_SECS, boost::uint32_t(stream_cmd.time_spec.get_full_secs())); + _iface->poke32(UE_REG_CTRL_RX_TIME_TICKS, stream_cmd.time_spec.get_tick_count(MASTER_CLOCK_RATE)); - default: throw std::runtime_error("stream mode not implemented"); - } - _iface->poke32(UE_REG_CTRL_RX_STREAM_CMD, cmd); - _iface->poke32(UE_REG_CTRL_RX_TIME_SECS, stream_cmd.time_spec.secs); - _iface->poke32(UE_REG_CTRL_RX_TIME_TICKS, stream_cmd.time_spec.get_ticks(MASTER_CLOCK_RATE)); } /*********************************************************************** * Data Send **********************************************************************/ +bool get_send_buffs( + data_transport *trans, + vrt_packet_handler::managed_send_buffs_t &buffs +){ + UHD_ASSERT_THROW(buffs.size() == 1); + buffs[0] = trans->get_send_buff(); + return buffs[0].get() != NULL; +} + size_t usrp_e_impl::send( - const boost::asio::const_buffer &buff, - const uhd::tx_metadata_t &metadata, - const io_type_t & io_type, + const std::vector &buffs, + size_t num_samps, + const tx_metadata_t &metadata, + const io_type_t &io_type, send_mode_t send_mode ){ otw_type_t send_otw_type; @@ -187,15 +210,13 @@ size_t usrp_e_impl::send( send_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN; return vrt_packet_handler::send( - _io_impl->send_state, - buff, - metadata, - send_mode, - io_type, - send_otw_type, //TODO - MASTER_CLOCK_RATE, - uhd::transport::vrt::pack_le, - boost::bind(&data_transport::get_send_buff, &_io_impl->transport), + _io_impl->packet_handler_send_state, //last state of the send handler + buffs, num_samps, //buffer to fill + metadata, send_mode, //samples metadata + io_type, send_otw_type, //input and output types to convert + MASTER_CLOCK_RATE, //master clock tick rate + uhd::transport::vrt::if_hdr_pack_le, + boost::bind(&get_send_buffs, &_io_impl->transport, _1), get_max_send_samps_per_packet(), vrt_header_offset_words32 ); @@ -204,9 +225,19 @@ size_t usrp_e_impl::send( /*********************************************************************** * Data Recv **********************************************************************/ +bool get_recv_buffs( + data_transport *trans, + vrt_packet_handler::managed_recv_buffs_t &buffs +){ + UHD_ASSERT_THROW(buffs.size() == 1); + buffs[0] = trans->get_recv_buff(); + return buffs[0].get() != NULL; +} + size_t usrp_e_impl::recv( - const boost::asio::mutable_buffer &buff, - uhd::rx_metadata_t &metadata, + const std::vector &buffs, + size_t num_samps, + rx_metadata_t &metadata, const io_type_t &io_type, recv_mode_t recv_mode ){ @@ -216,15 +247,12 @@ size_t usrp_e_impl::recv( recv_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN; return vrt_packet_handler::recv( - _io_impl->recv_state, - buff, - metadata, - recv_mode, - io_type, - recv_otw_type, //TODO - MASTER_CLOCK_RATE, - uhd::transport::vrt::unpack_le, - boost::bind(&data_transport::get_recv_buff, &_io_impl->transport), - vrt_header_offset_words32 + _io_impl->packet_handler_recv_state, //last state of the recv handler + buffs, num_samps, //buffer to fill + metadata, recv_mode, //samples metadata + io_type, recv_otw_type, //input and output types to convert + MASTER_CLOCK_RATE, //master clock tick rate + uhd::transport::vrt::if_hdr_unpack_le, + boost::bind(get_recv_buffs, &_io_impl->transport, _1) ); } diff --git a/host/lib/usrp/usrp_e/mboard_impl.cpp b/host/lib/usrp/usrp_e/mboard_impl.cpp index e4a0e81af..e27c1964a 100644 --- a/host/lib/usrp/usrp_e/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e/mboard_impl.cpp @@ -116,10 +116,10 @@ void usrp_e_impl::mboard_set(const wax::obj &key, const wax::obj &val){ case MBOARD_PROP_TIME_NOW: case MBOARD_PROP_TIME_NEXT_PPS:{ time_spec_t time_spec = val.as(); - _iface->poke32(UE_REG_TIME64_TICKS, time_spec.get_ticks(MASTER_CLOCK_RATE)); + _iface->poke32(UE_REG_TIME64_TICKS, time_spec.get_tick_count(MASTER_CLOCK_RATE)); boost::uint32_t imm_flags = (key.as() == MBOARD_PROP_TIME_NOW)? 1 : 0; _iface->poke32(UE_REG_TIME64_IMM, imm_flags); - _iface->poke32(UE_REG_TIME64_SECS, time_spec.secs); + _iface->poke32(UE_REG_TIME64_SECS, time_spec.get_full_secs()); } return; diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index e6bea1358..c0e302bd8 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -81,8 +81,8 @@ public: ~usrp_e_impl(void); //the io interface - size_t send(const boost::asio::const_buffer &, const uhd::tx_metadata_t &, const uhd::io_type_t &, send_mode_t); - size_t recv(const boost::asio::mutable_buffer &, uhd::rx_metadata_t &, const uhd::io_type_t &, recv_mode_t); + size_t send(const std::vector &, size_t, const uhd::tx_metadata_t &, const uhd::io_type_t &, send_mode_t); + size_t recv(const std::vector &, size_t, uhd::rx_metadata_t &, const uhd::io_type_t &, recv_mode_t); size_t get_max_send_samps_per_packet(void) const{return 300;} size_t get_max_recv_samps_per_packet(void) const{return 300;} -- cgit v1.2.3 From 7c2e17b549fefb5a667cf77dd7d86ed55f7ebe13 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 7 Jul 2010 18:44:16 +0000 Subject: usrp-e: replaced stream cmd logic with common dsp type1 logic --- host/lib/usrp/usrp_e/io_impl.cpp | 31 ++++--------------------------- 1 file changed, 4 insertions(+), 27 deletions(-) diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index a77a73b38..9ebd55eac 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -17,6 +17,7 @@ #include "usrp_e_impl.hpp" #include "usrp_e_regs.hpp" +#include "../dsp_utils.hpp" #include "../../transport/vrt_packet_handler.hpp" #include #include //read, write @@ -24,10 +25,10 @@ #include //offsetof #include #include -#include #include using namespace uhd; +using namespace uhd::usrp; /*********************************************************************** * Constants @@ -152,33 +153,9 @@ void usrp_e_impl::io_init(void){ _io_impl = UHD_PIMPL_MAKE(io_impl, (_iface->get_file_descriptor())); } -static boost::uint32_t make_stream_cmd(bool now, bool chain, bool reload, boost::uint32_t nsamps){ - return (((now)? 1 : 0) << 31) | (((chain)? 1 : 0) << 30) | (((reload)? 1 : 0) << 29) | nsamps; -} - void usrp_e_impl::issue_stream_cmd(const stream_cmd_t &stream_cmd){ - UHD_ASSERT_THROW(stream_cmd.num_samps <= 0x3fffffff); - - //setup the mode to instruction flags - typedef boost::tuple inst_t; - static const uhd::dict mode_to_inst = boost::assign::map_list_of - //reload, chain, samps - (stream_cmd_t::STREAM_MODE_START_CONTINUOUS, inst_t(true, true, false)) - (stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS, inst_t(false, false, false)) - (stream_cmd_t::STREAM_MODE_NUM_SAMPS_AND_DONE, inst_t(false, false, true)) - (stream_cmd_t::STREAM_MODE_NUM_SAMPS_AND_MORE, inst_t(false, true, true)) - ; - - //setup the instruction flag values - bool inst_reload, inst_chain, inst_samps; - boost::tie(inst_reload, inst_chain, inst_samps) = mode_to_inst[stream_cmd.stream_mode]; - - //issue the stream command - _iface->poke32(UE_REG_CTRL_RX_STREAM_CMD, make_stream_cmd( - (inst_samps)? stream_cmd.num_samps : ((inst_chain)? get_max_recv_samps_per_packet() : 1), - (stream_cmd.stream_now)? 1 : 0, - (inst_chain)? 1 : 0, - (inst_reload)? 1 : 0 + _iface->poke32(UE_REG_CTRL_RX_STREAM_CMD, dsp_type1::calc_stream_cmd_word( + stream_cmd, get_max_recv_samps_per_packet() )); _iface->poke32(UE_REG_CTRL_RX_TIME_SECS, boost::uint32_t(stream_cmd.time_spec.get_full_secs())); _iface->poke32(UE_REG_CTRL_RX_TIME_TICKS, stream_cmd.time_spec.get_tick_count(MASTER_CLOCK_RATE)); -- cgit v1.2.3 From b285d23f5eba9b65f9baf799fee3f1389c132632 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 7 Jul 2010 22:55:14 +0000 Subject: usrp-e: fixed send and recv logic in io impl to deal with frame length correctly --- host/lib/usrp/usrp_e/io_impl.cpp | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index 9ebd55eac..8bcff1352 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -22,7 +22,6 @@ #include #include //read, write #include //transfer frame struct -#include //offsetof #include #include #include @@ -34,7 +33,7 @@ using namespace uhd::usrp; * Constants **********************************************************************/ static const size_t MAX_BUFF_SIZE = 2048; -static const size_t vrt_header_offset_words32 = offsetof(usrp_transfer_frame, buf)/sizeof(boost::uint32_t); +static const size_t vrt_header_offset_words32 = sizeof(usrp_transfer_frame)/sizeof(boost::uint32_t); static const bool usrp_e_io_impl_verbose = true; static const size_t recv_timeout_ms = 100; @@ -71,7 +70,7 @@ private: //and the send buffer commit method will set the length. const_cast( boost::asio::buffer_cast(buff) - )->len = boost::asio::buffer_size(buff); + )->len = boost::asio::buffer_size(buff) - sizeof(usrp_transfer_frame); return write( _fd, boost::asio::buffer_cast(buff), @@ -112,16 +111,16 @@ private: } //overwrite the vrt header length with the transfer frame length - size_t frame_size = boost::asio::buffer_cast(buff)->len; - boost::uint32_t *vrt_header = boost::asio::buffer_cast(buff) + vrt_header_offset_words32; - vrt_header[0] = (vrt_header[0] & ~0xffff) | ((frame_size/sizeof(boost::uint32_t)) & 0xffff); + usrp_transfer_frame *frame = boost::asio::buffer_cast(buff); + boost::uint32_t *vrt_header = reinterpret_cast(frame->buf); + vrt_header[0] = (vrt_header[0] & ~0xffff) | ((frame->len/sizeof(boost::uint32_t)) & 0xffff); - //std::cout << "len " << int(boost::asio::buffer_cast(buff)->len) << std::endl; + //std::cout << "len " << int(frame->len) << std::endl; //for (size_t i = 0; i < 7; i++){ // std::cout << boost::format(" 0x%08x") % boost::asio::buffer_cast(buff)[i] << std::endl; //} - return frame_size; + return read_ret; } }; @@ -230,6 +229,7 @@ size_t usrp_e_impl::recv( io_type, recv_otw_type, //input and output types to convert MASTER_CLOCK_RATE, //master clock tick rate uhd::transport::vrt::if_hdr_unpack_le, - boost::bind(get_recv_buffs, &_io_impl->transport, _1) + boost::bind(get_recv_buffs, &_io_impl->transport, _1), + vrt_header_offset_words32 ); } -- cgit v1.2.3 From c3ef4c04fd8d887a733fa9a8ed5b6702cf453a01 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 9 Jul 2010 14:20:30 -0700 Subject: point to new location for fifos --- usrp2/vrt/vita_rx.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/vrt/vita_rx.build b/usrp2/vrt/vita_rx.build index f6d2d75a3..010d1be6e 100755 --- a/usrp2/vrt/vita_rx.build +++ b/usrp2/vrt/vita_rx.build @@ -1 +1 @@ -iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v +iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../fifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v -- cgit v1.2.3 From ead865c28690deb1566ce6a20f54cfb43484ad01 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sat, 10 Jul 2010 06:13:47 +0000 Subject: usrp-e: added io_impl handle overrun --- host/lib/usrp/usrp_e/io_impl.cpp | 26 ++++++++++++++++++-------- host/lib/usrp/usrp_e/usrp_e_impl.hpp | 1 + 2 files changed, 19 insertions(+), 8 deletions(-) diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index 8bcff1352..d1a00bf25 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -63,7 +63,7 @@ public: private: int _fd; - size_t send(const boost::asio::const_buffer &buff){ + ssize_t send(const boost::asio::const_buffer &buff){ //Set the frame length in the frame header. //This is technically bad to write to a const buffer, //but this will go away when the ring gets implemented, @@ -77,7 +77,7 @@ private: boost::asio::buffer_size(buff) ); } - size_t recv(const boost::asio::mutable_buffer &buff){ + ssize_t recv(const boost::asio::mutable_buffer &buff){ //std::cout << boost::format( // "calling read on fd %d, buff size is %d" //) % _fd % boost::asio::buffer_size(buff) << std::endl; @@ -105,9 +105,9 @@ private: if (read_ret < ssize_t(sizeof(usrp_transfer_frame))){ if (usrp_e_io_impl_verbose) std::cerr << boost::format( "usrp-e io impl recv(): read() returned small value: %d\n" - " -> return 0 for error" + " -> return -1 for error" ) % read_ret << std::endl; - return 0; + return -1; } //overwrite the vrt header length with the transfer frame length @@ -116,7 +116,7 @@ private: vrt_header[0] = (vrt_header[0] & ~0xffff) | ((frame->len/sizeof(boost::uint32_t)) & 0xffff); //std::cout << "len " << int(frame->len) << std::endl; - //for (size_t i = 0; i < 7; i++){ + //for (size_t i = 0; i < 9; i++){ // std::cout << boost::format(" 0x%08x") % boost::asio::buffer_cast(buff)[i] << std::endl; //} @@ -132,6 +132,7 @@ struct usrp_e_impl::io_impl{ vrt_packet_handler::recv_state packet_handler_recv_state; vrt_packet_handler::send_state packet_handler_send_state; data_transport transport; + bool continuous_streaming; io_impl(int fd): packet_handler_recv_state(1), transport(fd){} }; @@ -153,12 +154,20 @@ void usrp_e_impl::io_init(void){ } void usrp_e_impl::issue_stream_cmd(const stream_cmd_t &stream_cmd){ + _io_impl->continuous_streaming = (stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_START_CONTINUOUS); _iface->poke32(UE_REG_CTRL_RX_STREAM_CMD, dsp_type1::calc_stream_cmd_word( stream_cmd, get_max_recv_samps_per_packet() )); _iface->poke32(UE_REG_CTRL_RX_TIME_SECS, boost::uint32_t(stream_cmd.time_spec.get_full_secs())); _iface->poke32(UE_REG_CTRL_RX_TIME_TICKS, stream_cmd.time_spec.get_tick_count(MASTER_CLOCK_RATE)); +} +void usrp_e_impl::handle_overrun(size_t){ + std::cerr << "O"; //the famous OOOOOOOOOOO + _iface->poke32(UE_REG_CTRL_RX_CLEAR_OVERRUN, 0); + if (_io_impl->continuous_streaming){ + this->issue_stream_cmd(stream_cmd_t::STREAM_MODE_START_CONTINUOUS); + } } /*********************************************************************** @@ -170,7 +179,7 @@ bool get_send_buffs( ){ UHD_ASSERT_THROW(buffs.size() == 1); buffs[0] = trans->get_send_buff(); - return buffs[0].get() != NULL; + return buffs[0].get(); } size_t usrp_e_impl::send( @@ -207,7 +216,7 @@ bool get_recv_buffs( ){ UHD_ASSERT_THROW(buffs.size() == 1); buffs[0] = trans->get_recv_buff(); - return buffs[0].get() != NULL; + return buffs[0].get(); } size_t usrp_e_impl::recv( @@ -229,7 +238,8 @@ size_t usrp_e_impl::recv( io_type, recv_otw_type, //input and output types to convert MASTER_CLOCK_RATE, //master clock tick rate uhd::transport::vrt::if_hdr_unpack_le, - boost::bind(get_recv_buffs, &_io_impl->transport, _1), + boost::bind(&get_recv_buffs, &_io_impl->transport, _1), + boost::bind(&usrp_e_impl::handle_overrun, this, _1), vrt_header_offset_words32 ); } diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index c0e302bd8..4a63a6d21 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -97,6 +97,7 @@ private: UHD_PIMPL_DECL(io_impl) _io_impl; void io_init(void); void issue_stream_cmd(const uhd::stream_cmd_t &stream_cmd); + void handle_overrun(size_t); //configuration shadows uhd::clock_config_t _clock_config; -- cgit v1.2.3 From d9b7d9f2f9c6ebe27b6cfd4085f4a5c524363a1f Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 14 Jul 2010 22:16:52 +0000 Subject: Convert basic test programs to use shorts in the GPP to avoid using short to float code in uhd. --- host/examples/rx_timed_samples.cpp | 6 +++--- host/examples/tx_timed_samples.cpp | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/host/examples/rx_timed_samples.cpp b/host/examples/rx_timed_samples.cpp index 3b9acbb2c..a72e1ec81 100644 --- a/host/examples/rx_timed_samples.cpp +++ b/host/examples/rx_timed_samples.cpp @@ -84,12 +84,12 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ //loop until total number of samples reached size_t num_acc_samps = 0; //number of accumulated samples + uhd::rx_metadata_t md; + std::vector > buff(dev->get_max_recv_samps_per_packet()); while(num_acc_samps < total_num_samps){ - uhd::rx_metadata_t md; - std::vector > buff(dev->get_max_recv_samps_per_packet()); size_t num_rx_samps = dev->recv( &buff.front(), buff.size(), md, - uhd::io_type_t::COMPLEX_FLOAT32, + uhd::io_type_t::COMPLEX_INT16, uhd::device::RECV_MODE_ONE_PACKET ); diff --git a/host/examples/tx_timed_samples.cpp b/host/examples/tx_timed_samples.cpp index 5b72bd72f..ceae58a22 100644 --- a/host/examples/tx_timed_samples.cpp +++ b/host/examples/tx_timed_samples.cpp @@ -77,13 +77,13 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ sdev->set_time_now(uhd::time_spec_t(0.0)); //allocate data to send - std::vector > buff(samps_per_packet, std::complex(ampl, ampl)); + std::vector > buff(samps_per_packet, std::complex(ampl, ampl)); + uhd::tx_metadata_t md; //send the data in multiple packets size_t num_packets = (total_num_samps+samps_per_packet-1)/samps_per_packet; for (size_t i = 0; i < num_packets; i++){ //setup the metadata flags and time spec - uhd::tx_metadata_t md; md.start_of_burst = true; //always SOB (good for continuous streaming) md.end_of_burst = (i == num_packets-1); //only last packet has EOB md.has_time_spec = (i == 0); //only first packet has time @@ -94,7 +94,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ //send the entire packet (driver fragments internally) size_t num_tx_samps = dev->send( &buff.front(), samps_to_send, md, - uhd::io_type_t::COMPLEX_FLOAT32, + uhd::io_type_t::COMPLEX_INT16, uhd::device::SEND_MODE_FULL_BUFF ); if(verbose) std::cout << std::endl << boost::format("Sent %d samples") % num_tx_samps << std::endl; -- cgit v1.2.3 From 624eb248cd5ee2343cb0f4f24f60916ea51b60fd Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 14 Jul 2010 22:17:35 +0000 Subject: Use largest possible packets for transfers. --- host/lib/usrp/usrp_e/usrp_e_impl.hpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index 4a63a6d21..efbf9f68f 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -83,8 +83,8 @@ public: //the io interface size_t send(const std::vector &, size_t, const uhd::tx_metadata_t &, const uhd::io_type_t &, send_mode_t); size_t recv(const std::vector &, size_t, uhd::rx_metadata_t &, const uhd::io_type_t &, recv_mode_t); - size_t get_max_send_samps_per_packet(void) const{return 300;} - size_t get_max_recv_samps_per_packet(void) const{return 300;} + size_t get_max_send_samps_per_packet(void) const{return 503;} + size_t get_max_recv_samps_per_packet(void) const{return 503;} private: //interface to ioctls and file descriptor -- cgit v1.2.3 From 5922f348e19fd477c311c0cadef4eb5d3a17d4c6 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 14 Jul 2010 19:37:45 -0700 Subject: make loopback compile --- usrp2/top/u1e/u1e_core.v | 3 +++ 1 file changed, 3 insertions(+) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 787bf016c..5b60578ce 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -108,6 +108,9 @@ module u1e_core assign tx_underrun = 0; assign rx_overrun = 0; + + wire run_tx, run_rx, strobe_tx, strobe_rx, tx1_src_rdy, tx1_dst_rdy; + wire [31:0] debug_vtd, debug_vtc; `endif // LOOPBACK `ifdef TIMED -- cgit v1.2.3 From a47e75c84099081a7f7b2a13e11c3615bed22a5c Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 16 Jul 2010 07:22:11 +0000 Subject: usrp-e: removed vrt header rewrite in io impl, its not in vrt packet parser stuff --- host/lib/usrp/usrp_e/io_impl.cpp | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index d1a00bf25..ecde9ca27 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -110,11 +110,7 @@ private: return -1; } - //overwrite the vrt header length with the transfer frame length - usrp_transfer_frame *frame = boost::asio::buffer_cast(buff); - boost::uint32_t *vrt_header = reinterpret_cast(frame->buf); - vrt_header[0] = (vrt_header[0] & ~0xffff) | ((frame->len/sizeof(boost::uint32_t)) & 0xffff); - + //usrp_transfer_frame *frame = boost::asio::buffer_cast(buff); //std::cout << "len " << int(frame->len) << std::endl; //for (size_t i = 0; i < 9; i++){ // std::cout << boost::format(" 0x%08x") % boost::asio::buffer_cast(buff)[i] << std::endl; -- cgit v1.2.3 From 1301d665d621358ec6eccb41a020a4689cb0b566 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 3 Aug 2010 17:57:39 -0700 Subject: usrp-e: fixed clock div calculation bug --- host/lib/usrp/usrp_e/clock_ctrl.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/host/lib/usrp/usrp_e/clock_ctrl.cpp b/host/lib/usrp/usrp_e/clock_ctrl.cpp index df649cee6..8a5bd1c6b 100644 --- a/host/lib/usrp/usrp_e/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e/clock_ctrl.cpp @@ -164,7 +164,7 @@ public: void set_rx_dboard_clock_rate(double rate){ assert_has(get_rx_dboard_clock_rates(), rate, "rx dboard clock rate"); - size_t divider = size_t(rate/master_clock_rate); + size_t divider = size_t(master_clock_rate/rate); //set the divider registers set_clock_divider(divider, _ad9522_regs.divider3_low_cycles, @@ -194,7 +194,7 @@ public: void set_tx_dboard_clock_rate(double rate){ assert_has(get_tx_dboard_clock_rates(), rate, "tx dboard clock rate"); - size_t divider = size_t(rate/master_clock_rate); + size_t divider = size_t(master_clock_rate/rate); //set the divider registers set_clock_divider(divider, _ad9522_regs.divider2_low_cycles, -- cgit v1.2.3 From 19974fa00b04280e52d3d644e8e12953c570c06d Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 10 Aug 2010 09:59:33 -0700 Subject: enlarge loopback fifo --- usrp2/top/u1e/u1e_core.v | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 5b60578ce..516a5cf96 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -101,7 +101,7 @@ module u1e_core wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int; `ifdef LOOPBACK - fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo + fifo_cascade #(.WIDTH(36), .SIZE(12)) loopback_fifo (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx | clear_rx), .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); @@ -437,9 +437,6 @@ module u1e_core { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int }, { EM_D } }; - //assign debug = { phase[23:8], txsync, txblank, tx }; - - assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]}, {tx1_src_rdy, tx1_dst_rdy, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; -- cgit v1.2.3 From cb92934527964b8fda924925dbc12b18d5ae7fad Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 11 Aug 2010 01:05:47 +0000 Subject: Loopback test now supports variable size and works with mmapable ring buffer. --- host/apps/omap_debug/Makefile | 6 +- host/apps/omap_debug/usrp-e-loopback.c | 39 ++++-- host/apps/omap_debug/usrp-e-mm-loopback.c | 194 ++++++++++++++++++++++++++++++ 3 files changed, 227 insertions(+), 12 deletions(-) create mode 100644 host/apps/omap_debug/usrp-e-mm-loopback.c diff --git a/host/apps/omap_debug/Makefile b/host/apps/omap_debug/Makefile index c11609bdd..46d4714a8 100644 --- a/host/apps/omap_debug/Makefile +++ b/host/apps/omap_debug/Makefile @@ -1,7 +1,7 @@ CFLAGS=-Wall -I../../lib/usrp/usrp_e/ -march=armv7-a -mtune=cortex-a8 -mfpu=neon -O3 CXXFLAGS=-Wall -I../../lib/usrp/usrp_e/ -march=armv7-a -mtune=cortex-a8 -mfpu=neon -O3 -all : usrp-e-spi usrp-e-i2c usrp-e-loopback usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio usrp-e-debug-pins usrp-e-random-loopback usrp-e-timed usrp-e-lb-test usrp-e-crc-rw clkgen-config +all : usrp-e-spi usrp-e-i2c usrp-e-loopback usrp-e-mm-loopback usrp-e-uart usrp-e-led usrp-e-ctl usrp-e-button usrp-e-uart-rx fpga-downloader usrp-e-gpio usrp-e-debug-pins usrp-e-random-loopback usrp-e-timed usrp-e-lb-test usrp-e-crc-rw clkgen-config usrp-e-spi : usrp-e-spi.c @@ -10,6 +10,9 @@ usrp-e-i2c : usrp-e-i2c.c usrp-e-loopback : usrp-e-loopback.c gcc -o $@ $< -lpthread ${CFLAGS} +usrp-e-mm-loopback : usrp-e-mm-loopback.c + gcc -o $@ $< -lpthread ${CFLAGS} + usrp-e-timed : usrp-e-timed.c gcc -o $@ $< -lpthread ${CFLAGS} @@ -42,6 +45,7 @@ clean : rm -f usrp-e-spi rm -f usrp-e-i2c rm -f usrp-e-loopback + rm -f usrp-e-mm-loopback rm -f usrp-e-timed rm -f usrp-e-rw-random rm -f usrp-e-uart diff --git a/host/apps/omap_debug/usrp-e-loopback.c b/host/apps/omap_debug/usrp-e-loopback.c index 929d65604..c463e774d 100644 --- a/host/apps/omap_debug/usrp-e-loopback.c +++ b/host/apps/omap_debug/usrp-e-loopback.c @@ -14,6 +14,7 @@ static int error; struct pkt { int checksum; int seq_num; + int len; short data[]; }; @@ -26,10 +27,11 @@ static int calc_checksum(struct pkt *p) i = 0; sum = 0; - for (i=0; i < packet_data_length; i++) + for (i=0; i < p->len; i++) sum += p->data[i]; sum += p->seq_num; + sum += p->len; return sum; } @@ -48,7 +50,7 @@ static void *read_thread(void *threadid) gettimeofday(&start_time, NULL); // IMPORTANT: must assume max length packet from fpga - rx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (1016 * 2)); + rx_data = malloc(2048); p = (struct pkt *) ((void *)rx_data + offsetof(struct usrp_transfer_frame, buf)); //p = &(rx_data->buf[0]); printf("Address of rx_data = %p, p = %p\n", rx_data, p); @@ -60,14 +62,16 @@ static void *read_thread(void *threadid) seq_num_failure = 0; while (1) { - cnt = read(fp, rx_data, 2048); if (cnt < 0) printf("Error returned from read: %d, sequence number = %d\n", cnt, p->seq_num); // printf("Packet received, status = %X, len = %d\n", rx_data->status, rx_data->len); -// printf("p->seq_num = %d\n", p->seq_num); +// printf("p->seq_num = %d, p->len = %d\n", p->seq_num, p->len); + + if (rx_data->len != (p->len*2 + 12)) + printf("rx_data->len = %d, p->len*2 + 12 = %d\n", rx_data->len, p->len*2 + 12); pkt_count++; @@ -83,8 +87,8 @@ static void *read_thread(void *threadid) prev_seq_num = p->seq_num; if (calc_checksum(p) != p->checksum) { - printf("Checksum fail packet = %X, expected = %X, pkt_count = %d\n", - calc_checksum(p), p->checksum, pkt_count); + printf("Cksum fail rx = %X, tx = %X, dif = %d, count = %d, len = %d, rx->len = %d\n", + calc_checksum(p), p->checksum, p->checksum - calc_checksum(p), pkt_count, p->len, rx_data->len); error = 1; } @@ -112,24 +116,23 @@ static void *read_thread(void *threadid) static void *write_thread(void *threadid) { - int seq_number, i, cnt; + int seq_number, i, cnt, data_length; struct usrp_transfer_frame *tx_data; struct pkt *p; printf("Greetings from the write thread!\n"); - tx_data = malloc(sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + (packet_data_length * 2)); + tx_data = malloc(2048); p = (struct pkt *) ((void *)tx_data + offsetof(struct usrp_transfer_frame, buf)); printf("Address of tx_data = %p, p = %p\n", tx_data, p); printf("sizeof rp_transfer_frame = %d, sizeof pkt = %d\n", sizeof(struct usrp_transfer_frame), sizeof(struct pkt)); - for (i=0; i < packet_data_length; i++) + for (i=0; i < 2048; i++) // p->data[i] = random() >> 16; p->data[i] = i; tx_data->status = 0xdeadbeef; - tx_data->len = 8 + packet_data_length * 2; printf("tx_data->len = %d\n", tx_data->len); @@ -137,9 +140,23 @@ static void *write_thread(void *threadid) while (1) { // printf("tx status = %X, len = %d\n", tx_data->status, tx_data->len); + if (packet_data_length > 0) + data_length = packet_data_length; + else + data_length = (random() & 0x1ff) + (1004 - 512); + +// printf("data_length = %d\n", data_length); + p->seq_num = seq_number++; + p->len = data_length; p->checksum = calc_checksum(p); - cnt = write(fp, tx_data, 2048); + tx_data->len = 12 + p->len * 2; + +// printf("tx status = %X, len = %d, p->len = %d\n", tx_data->status, tx_data->len, p->len); + + cnt = write(fp, tx_data, sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + 2 * p->len); +// cnt = write(fp, tx_data, 2048); + if (cnt < 0) printf("Error returned from write: %d\n", cnt); // sleep(1); diff --git a/host/apps/omap_debug/usrp-e-mm-loopback.c b/host/apps/omap_debug/usrp-e-mm-loopback.c new file mode 100644 index 000000000..d11cf7d09 --- /dev/null +++ b/host/apps/omap_debug/usrp-e-mm-loopback.c @@ -0,0 +1,194 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include "usrp_e.h" + +// max length #define PKT_DATA_LENGTH 1016 +static int packet_data_length; +static int error; + +struct pkt { + int len; + int checksum; + int seq_num; + short data[]; +}; + +static int fp; + +static int calc_checksum(struct pkt *p) +{ + int i, sum; + + i = 0; + sum = 0; + + for (i=0; i < p->len; i++) + sum += p->data[i]; + + sum += p->seq_num; + sum += p->len; + + return sum; +} + +static void *read_thread(void *threadid) +{ + char *rx_data; + int cnt, prev_seq_num, pkt_count, seq_num_failure; + struct pkt *p; + unsigned long bytes_transfered, elapsed_seconds; + struct timeval start_time, finish_time; + + printf("Greetings from the reading thread!\n"); + + bytes_transfered = 0; + gettimeofday(&start_time, NULL); + + // IMPORTANT: must assume max length packet from fpga + rx_data = malloc(2048); + p = (struct pkt *) ((void *)rx_data); + + prev_seq_num = 0; + pkt_count = 0; + seq_num_failure = 0; + + while (1) { + + cnt = read(fp, rx_data, 2048); + if (cnt < 0) + printf("Error returned from read: %d, sequence number = %d\n", cnt, p->seq_num); + +// printf("p->seq_num = %d\n", p->seq_num); + + + pkt_count++; + + if (p->seq_num != prev_seq_num + 1) { + printf("Sequence number fail, current = %d, previous = %d, pkt_count = %d\n", + p->seq_num, prev_seq_num, pkt_count); + + seq_num_failure ++; + if (seq_num_failure > 2) + error = 1; + } + + prev_seq_num = p->seq_num; + + if (calc_checksum(p) != p->checksum) { + printf("Checksum fail packet = %X, expected = %X, pkt_count = %d\n", + calc_checksum(p), p->checksum, pkt_count); + error = 1; + } + + bytes_transfered += cnt; + + if (bytes_transfered > (100 * 1000000)) { + gettimeofday(&finish_time, NULL); + elapsed_seconds = finish_time.tv_sec - start_time.tv_sec; + + printf("RX data transfer rate = %f K Samples/second\n", + (float) bytes_transfered / (float) elapsed_seconds / 4000); + + + start_time = finish_time; + bytes_transfered = 0; + } + + +// printf("."); +// fflush(stdout); +// printf("\n"); + } + +} + +static void *write_thread(void *threadid) +{ + int seq_number, i, cnt; + void *tx_data; + struct pkt *p; + + printf("Greetings from the write thread!\n"); + + tx_data = malloc(2048); + p = (struct pkt *) ((void *)tx_data); + + for (i=0; i < packet_data_length; i++) +// p->data[i] = random() >> 16; + p->data[i] = i; + + seq_number = 1; + + while (1) { + p->seq_num = seq_number++; + + if (packet_data_length > 0) + p->len = packet_data_length; + else + p->len = (random() & 0x1ff) + (1004 - 512); + + p->checksum = calc_checksum(p); + + cnt = write(fp, tx_data, p->len * 2 + 12); + if (cnt < 0) + printf("Error returned from write: %d\n", cnt); +// sleep(1); + } +} + + +int main(int argc, char *argv[]) +{ + pthread_t tx, rx; + long int t; + struct sched_param s = { + .sched_priority = 1 + }; + void *rb; + struct usrp_transfer_frame *tx_rb, *rx_rb; + + if (argc < 2) { + printf("%s data_size\n", argv[0]); + return -1; + } + + packet_data_length = atoi(argv[1]); + + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); + + rb = mmap(0, 202 * 4096, PROT_READ|PROT_WRITE, MAP_SHARED, fp, 0); + if (!rb) { + printf("mmap failed\n"); + exit; + } + + + sched_setscheduler(0, SCHED_RR, &s); + error = 0; + +#if 1 + if (pthread_create(&rx, NULL, read_thread, (void *) t)) { + printf("Failed to create rx thread\n"); + exit(-1); + } + + sleep(1); +#endif + + if (pthread_create(&tx, NULL, write_thread, (void *) t)) { + printf("Failed to create tx thread\n"); + exit(-1); + } + +// while (!error) + sleep(1000000000); + + printf("Done sleeping\n"); +} -- cgit v1.2.3 From 9e87ebda07dda14e5b0ab4c64b6adc9800358baa Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 11 Aug 2010 00:16:34 -0700 Subject: usrp-e: fixed warnings and errors, missing subdev spec stuff --- host/include/uhd/utils/pimpl.hpp | 3 +-- host/lib/usrp/usrp_e/dboard_iface.cpp | 2 ++ host/lib/usrp/usrp_e/dboard_impl.cpp | 37 +---------------------------------- host/lib/usrp/usrp_e/io_impl.cpp | 18 +++++++++++++++-- host/lib/usrp/usrp_e/usrp_e_iface.cpp | 22 ++++++++++----------- host/lib/usrp/usrp_e/usrp_e_impl.hpp | 5 ++--- 6 files changed, 33 insertions(+), 54 deletions(-) diff --git a/host/include/uhd/utils/pimpl.hpp b/host/include/uhd/utils/pimpl.hpp index 18454f0c4..09bf0c0a2 100644 --- a/host/include/uhd/utils/pimpl.hpp +++ b/host/include/uhd/utils/pimpl.hpp @@ -20,7 +20,6 @@ #include #include -#include /*! \file pimpl.hpp * "Pimpl idiom" (pointer to implementation idiom). @@ -51,6 +50,6 @@ * \param _args the constructor args for the pimpl */ #define UHD_PIMPL_MAKE(_name, _args) \ - boost::make_shared<_name> _args + boost::shared_ptr<_name>(new _name _args) #endif /* INCLUDED_UHD_UTILS_PIMPL_HPP */ diff --git a/host/lib/usrp/usrp_e/dboard_iface.cpp b/host/lib/usrp/usrp_e/dboard_iface.cpp index ce00cd40d..d5ec10d84 100644 --- a/host/lib/usrp/usrp_e/dboard_iface.cpp +++ b/host/lib/usrp/usrp_e/dboard_iface.cpp @@ -50,6 +50,8 @@ public: /* NOP */ } + std::string get_mboard_name(void){return "usrp-e";} + void write_aux_dac(unit_t, aux_dac_t, float); float read_aux_adc(unit_t, aux_adc_t); diff --git a/host/lib/usrp/usrp_e/dboard_impl.cpp b/host/lib/usrp/usrp_e/dboard_impl.cpp index a384c71a0..4d3f70dfe 100644 --- a/host/lib/usrp/usrp_e/dboard_impl.cpp +++ b/host/lib/usrp/usrp_e/dboard_impl.cpp @@ -51,10 +51,6 @@ void usrp_e_impl::dboard_init(void){ boost::bind(&usrp_e_impl::tx_dboard_get, this, _1, _2), boost::bind(&usrp_e_impl::tx_dboard_set, this, _1, _2) ); - - //init the subdevs in use (use the first subdevice) - rx_dboard_set(DBOARD_PROP_USED_SUBDEVS, prop_names_t(1, _dboard_manager->get_rx_subdev_names().at(0))); - tx_dboard_set(DBOARD_PROP_USED_SUBDEVS, prop_names_t(1, _dboard_manager->get_tx_subdev_names().at(0))); } /*********************************************************************** @@ -78,10 +74,6 @@ void usrp_e_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){ val = _dboard_manager->get_rx_subdev_names(); return; - case DBOARD_PROP_USED_SUBDEVS: - val = _rx_subdevs_in_use; - return; - case DBOARD_PROP_DBOARD_ID: val = _rx_db_eeprom.id; return; @@ -99,18 +91,6 @@ void usrp_e_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){ **********************************************************************/ void usrp_e_impl::rx_dboard_set(const wax::obj &key, const wax::obj &val){ switch(key.as()){ - case DBOARD_PROP_USED_SUBDEVS:{ - _rx_subdevs_in_use = val.as(); - UHD_ASSERT_THROW(_rx_subdevs_in_use.size() == 1); - wax::obj rx_subdev = _dboard_manager->get_rx_subdev(_rx_subdevs_in_use.at(0)); - std::cout << "Using: " << rx_subdev[SUBDEV_PROP_NAME].as() << std::endl; - _iface->poke32(UE_REG_DSP_RX_MUX, dsp_type1::calc_rx_mux_word( - rx_subdev[SUBDEV_PROP_QUADRATURE].as(), - rx_subdev[SUBDEV_PROP_IQ_SWAPPED].as() - )); - } - return; - case DBOARD_PROP_DBOARD_ID: _rx_db_eeprom.id = val.as(); _iface->write_eeprom(I2C_ADDR_RX_DB, 0, _rx_db_eeprom.get_eeprom_bytes()); @@ -141,10 +121,6 @@ void usrp_e_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){ val = _dboard_manager->get_tx_subdev_names(); return; - case DBOARD_PROP_USED_SUBDEVS: - val = _tx_subdevs_in_use; - return; - case DBOARD_PROP_DBOARD_ID: val = _tx_db_eeprom.id; return; @@ -161,18 +137,7 @@ void usrp_e_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){ * TX Dboard Set **********************************************************************/ void usrp_e_impl::tx_dboard_set(const wax::obj &key, const wax::obj &val){ - switch(key.as()){ - case DBOARD_PROP_USED_SUBDEVS:{ - _tx_subdevs_in_use = val.as(); - UHD_ASSERT_THROW(_tx_subdevs_in_use.size() == 1); - wax::obj tx_subdev = _dboard_manager->get_tx_subdev(_tx_subdevs_in_use.at(0)); - std::cout << "Using: " << tx_subdev[SUBDEV_PROP_NAME].as() << std::endl; - _iface->poke32(UE_REG_DSP_TX_MUX, dsp_type1::calc_tx_mux_word( - tx_subdev[SUBDEV_PROP_IQ_SWAPPED].as() - )); - } - return; - + switch(key.as()){ case DBOARD_PROP_DBOARD_ID: _tx_db_eeprom.id = val.as(); _iface->write_eeprom(I2C_ADDR_TX_DB, 0, _tx_db_eeprom.get_eeprom_bytes()); diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index ecde9ca27..0742c4514 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -24,6 +24,7 @@ #include //transfer frame struct #include #include +#include #include using namespace uhd; @@ -35,7 +36,6 @@ using namespace uhd::usrp; static const size_t MAX_BUFF_SIZE = 2048; static const size_t vrt_header_offset_words32 = sizeof(usrp_transfer_frame)/sizeof(boost::uint32_t); static const bool usrp_e_io_impl_verbose = true; -static const size_t recv_timeout_ms = 100; /*********************************************************************** * Data Transport (phony zero-copy with read/write) @@ -61,6 +61,8 @@ public: return 10; //FIXME no idea! } + size_t recv_timeout_ms; + private: int _fd; ssize_t send(const boost::asio::const_buffer &buff){ @@ -220,13 +222,17 @@ size_t usrp_e_impl::recv( size_t num_samps, rx_metadata_t &metadata, const io_type_t &io_type, - recv_mode_t recv_mode + recv_mode_t recv_mode, + size_t timeout_ms ){ otw_type_t recv_otw_type; recv_otw_type.width = 16; recv_otw_type.shift = 0; recv_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN; + //hand-off the timeout to the transport + _io_impl->transport.recv_timeout_ms = timeout_ms; + return vrt_packet_handler::recv( _io_impl->packet_handler_recv_state, //last state of the recv handler buffs, num_samps, //buffer to fill @@ -239,3 +245,11 @@ size_t usrp_e_impl::recv( vrt_header_offset_words32 ); } + +/*********************************************************************** + * Dummy Async Recv + **********************************************************************/ +bool usrp_e_impl::recv_async_msg(async_metadata_t &, size_t timeout_ms){ + boost::this_thread::sleep(boost::posix_time::milliseconds(timeout_ms)); + return false; +} diff --git a/host/lib/usrp/usrp_e/usrp_e_iface.cpp b/host/lib/usrp/usrp_e/usrp_e_iface.cpp index 21e91452f..f00e92946 100644 --- a/host/lib/usrp/usrp_e/usrp_e_iface.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_iface.cpp @@ -123,13 +123,13 @@ public: boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; //load the data struct - usrp_e_i2c &data = reinterpret_cast(mem); - data.addr = addr; - data.len = bytes.size(); - std::copy(bytes.begin(), bytes.end(), data.data); + usrp_e_i2c *data = reinterpret_cast(mem); + data->addr = addr; + data->len = bytes.size(); + std::copy(bytes.begin(), bytes.end(), data->data); //call the spi ioctl - this->ioctl(USRP_E_I2C_WRITE, &data); + this->ioctl(USRP_E_I2C_WRITE, data); } byte_vector_t read_i2c(boost::uint8_t addr, size_t num_bytes){ @@ -138,17 +138,17 @@ public: boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; //load the data struct - usrp_e_i2c &data = reinterpret_cast(mem); - data.addr = addr; - data.len = num_bytes; + usrp_e_i2c *data = reinterpret_cast(mem); + data->addr = addr; + data->len = num_bytes; //call the spi ioctl - this->ioctl(USRP_E_I2C_READ, &data); + this->ioctl(USRP_E_I2C_READ, data); //unload the data - byte_vector_t bytes(data.len); + byte_vector_t bytes(data->len); UHD_ASSERT_THROW(bytes.size() == num_bytes); - std::copy(data.data, data.data+bytes.size(), bytes.begin()); + std::copy(data->data, data->data+bytes.size(), bytes.begin()); return bytes; } diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index efbf9f68f..4bbe100c1 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -82,7 +82,8 @@ public: //the io interface size_t send(const std::vector &, size_t, const uhd::tx_metadata_t &, const uhd::io_type_t &, send_mode_t); - size_t recv(const std::vector &, size_t, uhd::rx_metadata_t &, const uhd::io_type_t &, recv_mode_t); + size_t recv(const std::vector &, size_t, uhd::rx_metadata_t &, const uhd::io_type_t &, recv_mode_t, size_t); + bool recv_async_msg(uhd::async_metadata_t &, size_t); size_t get_max_send_samps_per_packet(void) const{return 503;} size_t get_max_recv_samps_per_packet(void) const{return 503;} @@ -128,14 +129,12 @@ private: uhd::usrp::dboard_eeprom_t _rx_db_eeprom; void rx_dboard_get(const wax::obj &, wax::obj &); void rx_dboard_set(const wax::obj &, const wax::obj &); - uhd::prop_names_t _rx_subdevs_in_use; wax_obj_proxy::sptr _rx_dboard_proxy; //tx dboard functions and settings uhd::usrp::dboard_eeprom_t _tx_db_eeprom; void tx_dboard_get(const wax::obj &, wax::obj &); void tx_dboard_set(const wax::obj &, const wax::obj &); - uhd::prop_names_t _tx_subdevs_in_use; wax_obj_proxy::sptr _tx_dboard_proxy; //rx ddc functions and settings -- cgit v1.2.3 From 6ce879c36aedc7d69ceadbecd8878fa3856547f0 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 11 Aug 2010 17:23:42 +0000 Subject: Add usrp-e-mm-loopback to .gitignore. --- host/apps/omap_debug/.gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/host/apps/omap_debug/.gitignore b/host/apps/omap_debug/.gitignore index 5d6b1c6f5..008a23138 100644 --- a/host/apps/omap_debug/.gitignore +++ b/host/apps/omap_debug/.gitignore @@ -17,3 +17,4 @@ usrp-e-spi usrp-e-timed usrp-e-uart usrp-e-uart-rx +usrp-e-mm-loopback -- cgit v1.2.3 From 74e5238d08c780e96f617c86bea848a05f76988c Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 11 Aug 2010 17:53:53 +0000 Subject: Convert non-mmaped loopback test program to use new simple read/write api. Done by copying from the -mm version, which will be used to test mmaped ring buffer. --- host/apps/omap_debug/usrp-e-loopback.c | 76 +++++++++++++++------------------- 1 file changed, 33 insertions(+), 43 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-loopback.c b/host/apps/omap_debug/usrp-e-loopback.c index c463e774d..d11cf7d09 100644 --- a/host/apps/omap_debug/usrp-e-loopback.c +++ b/host/apps/omap_debug/usrp-e-loopback.c @@ -5,6 +5,7 @@ #include #include #include +#include #include "usrp_e.h" // max length #define PKT_DATA_LENGTH 1016 @@ -12,9 +13,9 @@ static int packet_data_length; static int error; struct pkt { + int len; int checksum; int seq_num; - int len; short data[]; }; @@ -38,8 +39,8 @@ static int calc_checksum(struct pkt *p) static void *read_thread(void *threadid) { + char *rx_data; int cnt, prev_seq_num, pkt_count, seq_num_failure; - struct usrp_transfer_frame *rx_data; struct pkt *p; unsigned long bytes_transfered, elapsed_seconds; struct timeval start_time, finish_time; @@ -51,32 +52,25 @@ static void *read_thread(void *threadid) // IMPORTANT: must assume max length packet from fpga rx_data = malloc(2048); - p = (struct pkt *) ((void *)rx_data + offsetof(struct usrp_transfer_frame, buf)); - //p = &(rx_data->buf[0]); - printf("Address of rx_data = %p, p = %p\n", rx_data, p); - printf("offsetof = %d\n", offsetof(struct usrp_transfer_frame, buf)); - printf("sizeof rx data = %d\n", sizeof(struct usrp_transfer_frame) + sizeof(struct pkt)); + p = (struct pkt *) ((void *)rx_data); prev_seq_num = 0; pkt_count = 0; seq_num_failure = 0; while (1) { + cnt = read(fp, rx_data, 2048); if (cnt < 0) printf("Error returned from read: %d, sequence number = %d\n", cnt, p->seq_num); -// printf("Packet received, status = %X, len = %d\n", rx_data->status, rx_data->len); -// printf("p->seq_num = %d, p->len = %d\n", p->seq_num, p->len); - +// printf("p->seq_num = %d\n", p->seq_num); - if (rx_data->len != (p->len*2 + 12)) - printf("rx_data->len = %d, p->len*2 + 12 = %d\n", rx_data->len, p->len*2 + 12); pkt_count++; if (p->seq_num != prev_seq_num + 1) { - printf("Sequence number fail, current = %X, previous = %X, pkt_count = %d\n", + printf("Sequence number fail, current = %d, previous = %d, pkt_count = %d\n", p->seq_num, prev_seq_num, pkt_count); seq_num_failure ++; @@ -87,12 +81,12 @@ static void *read_thread(void *threadid) prev_seq_num = p->seq_num; if (calc_checksum(p) != p->checksum) { - printf("Cksum fail rx = %X, tx = %X, dif = %d, count = %d, len = %d, rx->len = %d\n", - calc_checksum(p), p->checksum, p->checksum - calc_checksum(p), pkt_count, p->len, rx_data->len); + printf("Checksum fail packet = %X, expected = %X, pkt_count = %d\n", + calc_checksum(p), p->checksum, pkt_count); error = 1; } - bytes_transfered += rx_data->len; + bytes_transfered += cnt; if (bytes_transfered > (100 * 1000000)) { gettimeofday(&finish_time, NULL); @@ -116,47 +110,32 @@ static void *read_thread(void *threadid) static void *write_thread(void *threadid) { - int seq_number, i, cnt, data_length; - struct usrp_transfer_frame *tx_data; + int seq_number, i, cnt; + void *tx_data; struct pkt *p; printf("Greetings from the write thread!\n"); tx_data = malloc(2048); - p = (struct pkt *) ((void *)tx_data + offsetof(struct usrp_transfer_frame, buf)); - printf("Address of tx_data = %p, p = %p\n", tx_data, p); + p = (struct pkt *) ((void *)tx_data); - printf("sizeof rp_transfer_frame = %d, sizeof pkt = %d\n", sizeof(struct usrp_transfer_frame), sizeof(struct pkt)); - - for (i=0; i < 2048; i++) + for (i=0; i < packet_data_length; i++) // p->data[i] = random() >> 16; p->data[i] = i; - tx_data->status = 0xdeadbeef; - - printf("tx_data->len = %d\n", tx_data->len); - seq_number = 1; while (1) { -// printf("tx status = %X, len = %d\n", tx_data->status, tx_data->len); - if (packet_data_length > 0) - data_length = packet_data_length; - else - data_length = (random() & 0x1ff) + (1004 - 512); - -// printf("data_length = %d\n", data_length); - p->seq_num = seq_number++; - p->len = data_length; - p->checksum = calc_checksum(p); - tx_data->len = 12 + p->len * 2; -// printf("tx status = %X, len = %d, p->len = %d\n", tx_data->status, tx_data->len, p->len); + if (packet_data_length > 0) + p->len = packet_data_length; + else + p->len = (random() & 0x1ff) + (1004 - 512); - cnt = write(fp, tx_data, sizeof(struct usrp_transfer_frame) + sizeof(struct pkt) + 2 * p->len); -// cnt = write(fp, tx_data, 2048); + p->checksum = calc_checksum(p); + cnt = write(fp, tx_data, p->len * 2 + 12); if (cnt < 0) printf("Error returned from write: %d\n", cnt); // sleep(1); @@ -171,6 +150,8 @@ int main(int argc, char *argv[]) struct sched_param s = { .sched_priority = 1 }; + void *rb; + struct usrp_transfer_frame *tx_rb, *rx_rb; if (argc < 2) { printf("%s data_size\n", argv[0]); @@ -182,23 +163,32 @@ int main(int argc, char *argv[]) fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); + rb = mmap(0, 202 * 4096, PROT_READ|PROT_WRITE, MAP_SHARED, fp, 0); + if (!rb) { + printf("mmap failed\n"); + exit; + } + + sched_setscheduler(0, SCHED_RR, &s); error = 0; +#if 1 if (pthread_create(&rx, NULL, read_thread, (void *) t)) { printf("Failed to create rx thread\n"); exit(-1); } sleep(1); +#endif if (pthread_create(&tx, NULL, write_thread, (void *) t)) { printf("Failed to create tx thread\n"); exit(-1); } - while (!error) - sleep(1); +// while (!error) + sleep(1000000000); printf("Done sleeping\n"); } -- cgit v1.2.3 From 3f25b6fee4a7788ffea0224cb79bb6334b621992 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 11 Aug 2010 12:32:57 -0700 Subject: usrp-e: filled in properties and logic for subdev spec --- host/lib/usrp/usrp_e/dboard_impl.cpp | 1 - host/lib/usrp/usrp_e/mboard_impl.cpp | 36 ++++++++++++++++++++++++++++++++++++ host/lib/usrp/usrp_e/usrp_e_impl.hpp | 2 ++ 3 files changed, 38 insertions(+), 1 deletion(-) diff --git a/host/lib/usrp/usrp_e/dboard_impl.cpp b/host/lib/usrp/usrp_e/dboard_impl.cpp index 4d3f70dfe..809b6f06b 100644 --- a/host/lib/usrp/usrp_e/dboard_impl.cpp +++ b/host/lib/usrp/usrp_e/dboard_impl.cpp @@ -17,7 +17,6 @@ #include "usrp_e_impl.hpp" #include "usrp_e_regs.hpp" -#include "../dsp_utils.hpp" #include #include #include diff --git a/host/lib/usrp/usrp_e/mboard_impl.cpp b/host/lib/usrp/usrp_e/mboard_impl.cpp index e27c1964a..822f1571d 100644 --- a/host/lib/usrp/usrp_e/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e/mboard_impl.cpp @@ -17,6 +17,8 @@ #include "usrp_e_impl.hpp" #include "usrp_e_regs.hpp" +#include "../dsp_utils.hpp" +#include "../misc_utils.hpp" #include #include #include @@ -38,6 +40,10 @@ void usrp_e_impl::mboard_init(void){ _clock_config.pps_source = clock_config_t::PPS_SMA; //TODO poke the clock config regs + + //set default subdev specs + this->mboard_set(MBOARD_PROP_RX_SUBDEV_SPEC, subdev_spec_t()); + this->mboard_set(MBOARD_PROP_TX_SUBDEV_SPEC, subdev_spec_t()); } /*********************************************************************** @@ -98,6 +104,14 @@ void usrp_e_impl::mboard_get(const wax::obj &key_, wax::obj &val){ val = _clock_config; return; + case MBOARD_PROP_RX_SUBDEV_SPEC: + val = _rx_subdev_spec; + return; + + case MBOARD_PROP_TX_SUBDEV_SPEC: + val = _tx_subdev_spec; + return; + default: UHD_THROW_PROP_GET_ERROR(); } } @@ -123,6 +137,28 @@ void usrp_e_impl::mboard_set(const wax::obj &key, const wax::obj &val){ } return; + case MBOARD_PROP_RX_SUBDEV_SPEC: + _rx_subdev_spec = val.as(); + verify_rx_subdev_spec(_rx_subdev_spec, this->get_link()); + //sanity check + UHD_ASSERT_THROW(_rx_subdev_spec.size() == 1); + //set the mux + _iface->poke32(UE_REG_DSP_RX_MUX, dsp_type1::calc_rx_mux_word( + _dboard_manager->get_rx_subdev(_rx_subdev_spec.front().sd_name)[SUBDEV_PROP_CONNECTION].as() + )); + return; + + case MBOARD_PROP_TX_SUBDEV_SPEC: + _tx_subdev_spec = val.as(); + verify_tx_subdev_spec(_tx_subdev_spec, this->get_link()); + //sanity check + UHD_ASSERT_THROW(_tx_subdev_spec.size() == 1); + //set the mux + _iface->poke32(UE_REG_DSP_TX_MUX, dsp_type1::calc_tx_mux_word( + _dboard_manager->get_tx_subdev(_tx_subdev_spec.front().sd_name)[SUBDEV_PROP_CONNECTION].as() + )); + return; + default: UHD_THROW_PROP_SET_ERROR(); } } diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index 4bbe100c1..e3249e9de 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -20,6 +20,7 @@ #include "codec_ctrl.hpp" #include #include +#include #include #include #include @@ -119,6 +120,7 @@ private: void mboard_get(const wax::obj &, wax::obj &); void mboard_set(const wax::obj &, const wax::obj &); wax_obj_proxy::sptr _mboard_proxy; + uhd::usrp::subdev_spec_t _rx_subdev_spec, _tx_subdev_spec; //xx dboard functions and settings void dboard_init(void); -- cgit v1.2.3 From a58b90ef219746e927a777efba919db15d139e84 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 11 Aug 2010 22:23:40 +0000 Subject: Convert to use mmaped rx ring buffer. --- host/apps/omap_debug/usrp-e-mm-loopback.c | 63 ++++++++++++++++++++++++------- 1 file changed, 50 insertions(+), 13 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-mm-loopback.c b/host/apps/omap_debug/usrp-e-mm-loopback.c index d11cf7d09..722d09825 100644 --- a/host/apps/omap_debug/usrp-e-mm-loopback.c +++ b/host/apps/omap_debug/usrp-e-mm-loopback.c @@ -6,6 +6,7 @@ #include #include #include +#include #include "usrp_e.h" // max length #define PKT_DATA_LENGTH 1016 @@ -16,9 +17,20 @@ struct pkt { int len; int checksum; int seq_num; - short data[]; + short data[1024-6]; }; +/* delete after usrp_e.h updated */ +struct ring_buffer_info { + int flags; + int len; +}; + +struct ring_buffer_info (*rxi)[]; +struct ring_buffer_info (*txi)[]; +struct pkt (*rx_buf)[200]; +struct pkt (*tx_buf)[200]; + static int fp; static int calc_checksum(struct pkt *p) @@ -39,32 +51,44 @@ static int calc_checksum(struct pkt *p) static void *read_thread(void *threadid) { - char *rx_data; int cnt, prev_seq_num, pkt_count, seq_num_failure; struct pkt *p; unsigned long bytes_transfered, elapsed_seconds; struct timeval start_time, finish_time; + int rb_read; printf("Greetings from the reading thread!\n"); + printf("sizeof pkt = %d\n", sizeof(struct pkt)); + + rb_read = 0; bytes_transfered = 0; gettimeofday(&start_time, NULL); - // IMPORTANT: must assume max length packet from fpga - rx_data = malloc(2048); - p = (struct pkt *) ((void *)rx_data); - prev_seq_num = 0; pkt_count = 0; seq_num_failure = 0; while (1) { - cnt = read(fp, rx_data, 2048); - if (cnt < 0) - printf("Error returned from read: %d, sequence number = %d\n", cnt, p->seq_num); + if (!((*rxi)[rb_read].flags & RB_USER)) { + printf("Waiting for data\n"); + struct pollfd pfd; + pfd.fd = fp; + pfd.events = POLLIN; + ssize_t ret = poll(&pfd, 1, -1); + } -// printf("p->seq_num = %d\n", p->seq_num); + printf("pkt received, rb_read = %d\n", rb_read); + + cnt = (*rxi)[rb_read].len; + p = &(*rx_buf)[rb_read]; + +// cnt = read(fp, rx_data, 2048); +// if (cnt < 0) +// printf("Error returned from read: %d, sequence number = %d\n", cnt, p->seq_num); + + printf("p = %X, p->seq_num = %d p->len = %d\n", p, p->seq_num, p->len); pkt_count++; @@ -86,6 +110,12 @@ static void *read_thread(void *threadid) error = 1; } + (*rxi)[rb_read].flags = RB_KERNEL; + + rb_read++; + if (rb_read == 200) + rb_read = 0; + bytes_transfered += cnt; if (bytes_transfered > (100 * 1000000)) { @@ -151,7 +181,6 @@ int main(int argc, char *argv[]) .sched_priority = 1 }; void *rb; - struct usrp_transfer_frame *tx_rb, *rx_rb; if (argc < 2) { printf("%s data_size\n", argv[0]); @@ -164,11 +193,19 @@ int main(int argc, char *argv[]) printf("fp = %d\n", fp); rb = mmap(0, 202 * 4096, PROT_READ|PROT_WRITE, MAP_SHARED, fp, 0); - if (!rb) { - printf("mmap failed\n"); + if (rb == MAP_FAILED) { + perror("mmap failed"); exit; } + printf("rb = %X\n", rb); + + rxi = rb; + rx_buf = rb + 4096; + txi = rb + 4096 + 4096 * 200; + tx_buf = rb + 4096 * 2 + 4096 * 200; + + printf("rxi = %X, rx_buf = %X, txi = %X, tx_buf = %X\n", rxi, rx_buf, txi, tx_buf); sched_setscheduler(0, SCHED_RR, &s); error = 0; -- cgit v1.2.3 From 8e5040a9ec0639bc7b110ba96e256c48e5a62df7 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 11 Aug 2010 15:33:12 -0700 Subject: usrp-e: removed transfer frameness --- host/lib/usrp/usrp_e/io_impl.cpp | 26 ++++++-------------------- 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index 0742c4514..bbc3f5215 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -21,7 +21,6 @@ #include "../../transport/vrt_packet_handler.hpp" #include #include //read, write -#include //transfer frame struct #include #include #include @@ -34,7 +33,6 @@ using namespace uhd::usrp; * Constants **********************************************************************/ static const size_t MAX_BUFF_SIZE = 2048; -static const size_t vrt_header_offset_words32 = sizeof(usrp_transfer_frame)/sizeof(boost::uint32_t); static const bool usrp_e_io_impl_verbose = true; /*********************************************************************** @@ -66,15 +64,7 @@ public: private: int _fd; ssize_t send(const boost::asio::const_buffer &buff){ - //Set the frame length in the frame header. - //This is technically bad to write to a const buffer, - //but this will go away when the ring gets implemented, - //and the send buffer commit method will set the length. - const_cast( - boost::asio::buffer_cast(buff) - )->len = boost::asio::buffer_size(buff) - sizeof(usrp_transfer_frame); - return write( - _fd, + return write(_fd, boost::asio::buffer_cast(buff), boost::asio::buffer_size(buff) ); @@ -99,12 +89,11 @@ private: } //perform the blocking read(...) - ssize_t read_ret = read( - _fd, + ssize_t read_ret = read(_fd, boost::asio::buffer_cast(buff), boost::asio::buffer_size(buff) ); - if (read_ret < ssize_t(sizeof(usrp_transfer_frame))){ + if (read_ret < 0){ if (usrp_e_io_impl_verbose) std::cerr << boost::format( "usrp-e io impl recv(): read() returned small value: %d\n" " -> return -1 for error" @@ -112,8 +101,7 @@ private: return -1; } - //usrp_transfer_frame *frame = boost::asio::buffer_cast(buff); - //std::cout << "len " << int(frame->len) << std::endl; + //std::cout << "len " << int(read_ret) << std::endl; //for (size_t i = 0; i < 9; i++){ // std::cout << boost::format(" 0x%08x") % boost::asio::buffer_cast(buff)[i] << std::endl; //} @@ -200,8 +188,7 @@ size_t usrp_e_impl::send( MASTER_CLOCK_RATE, //master clock tick rate uhd::transport::vrt::if_hdr_pack_le, boost::bind(&get_send_buffs, &_io_impl->transport, _1), - get_max_send_samps_per_packet(), - vrt_header_offset_words32 + get_max_send_samps_per_packet() ); } @@ -241,8 +228,7 @@ size_t usrp_e_impl::recv( MASTER_CLOCK_RATE, //master clock tick rate uhd::transport::vrt::if_hdr_unpack_le, boost::bind(&get_recv_buffs, &_io_impl->transport, _1), - boost::bind(&usrp_e_impl::handle_overrun, this, _1), - vrt_header_offset_words32 + boost::bind(&usrp_e_impl::handle_overrun, this, _1) ); } -- cgit v1.2.3 From 9e97e773b9952ec3212e6c818bb40d785016afa4 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 11 Aug 2010 16:26:58 -0700 Subject: connect the setting reg to the real clock and reset --- usrp2/top/u1e/u1e_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 516a5cf96..4561df173 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -70,7 +70,7 @@ module u1e_core wire clear_rx_int, clear_tx_int, clear_tx, clear_rx, do_clear; setting_reg #(.my_addr(SR_CLEAR_FIFO), .width(2)) sr_clear - (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({clear_tx_int,clear_rx_int}),.changed(do_clear)); assign clear_tx = clear_tx_int & do_clear; assign clear_rx = clear_rx_int & do_clear; -- cgit v1.2.3 From 2ce128a2cf9ea8bea23e2cea28d0729719b42968 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 12 Aug 2010 03:49:37 +0000 Subject: uhd: avoid segfaults - use CPP macros for paths and dont split empty string --- host/lib/constants.hpp.in | 7 ++++--- host/lib/utils/paths.cpp | 12 ++++++------ 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/host/lib/constants.hpp.in b/host/lib/constants.hpp.in index 295c8f16c..aa51e558c 100644 --- a/host/lib/constants.hpp.in +++ b/host/lib/constants.hpp.in @@ -21,8 +21,9 @@ #include #include -static const std::string UHD_VERSION_STRING = "@CPACK_PACKAGE_VERSION@"; -static const std::string UHD_INSTALL_PREFIX = "@CMAKE_INSTALL_PREFIX@"; -static const std::string UHD_PKG_DATA_DIR = "@PKG_DATA_DIR@"; +//these should be pre-processor macros to avoid static initialization issues +#define UHD_VERSION_STRING "@CPACK_PACKAGE_VERSION@" +#define UHD_INSTALL_PREFIX "@CMAKE_INSTALL_PREFIX@" +#define UHD_PKG_DATA_DIR "@PKG_DATA_DIR@" #endif /* INCLUDED_LIBUHD_CONSTANTS_HPP */ diff --git a/host/lib/utils/paths.cpp b/host/lib/utils/paths.cpp index 0805a44fe..4029bd989 100644 --- a/host/lib/utils/paths.cpp +++ b/host/lib/utils/paths.cpp @@ -60,12 +60,14 @@ static std::vector get_env_paths(const std::string &var_name){ //split the path at the path separators std::vector path_strings; - boost::split(path_strings, var_value, boost::is_any_of(env_path_sep)); + if (not var_value.empty()) boost::split(//dont split empty strings + path_strings, var_value, boost::is_any_of(env_path_sep) + ); //convert to filesystem path, filter blank paths std::vector paths; BOOST_FOREACH(std::string &path_string, path_strings){ - if (path_string.size() == 0) continue; + if (path_string.empty()) continue; paths.push_back(fs::system_complete(path_string)); } return paths; @@ -74,17 +76,15 @@ static std::vector get_env_paths(const std::string &var_name){ /*********************************************************************** * Get a list of special purpose paths **********************************************************************/ -static const fs::path pkg_data_path = fs::path(UHD_INSTALL_PREFIX) / UHD_PKG_DATA_DIR; - std::vector get_image_paths(void){ std::vector paths = get_env_paths("UHD_IMAGE_PATH"); - paths.push_back(pkg_data_path / "images"); + paths.push_back(fs::path(UHD_INSTALL_PREFIX) / UHD_PKG_DATA_DIR / "images"); return paths; } std::vector get_module_paths(void){ std::vector paths = get_env_paths("UHD_MODULE_PATH"); - paths.push_back(pkg_data_path / "modules"); + paths.push_back(fs::path(UHD_INSTALL_PREFIX) / UHD_PKG_DATA_DIR / "modules"); return paths; } -- cgit v1.2.3 From 68a65581db6455bfd4652576eeb6795e3c1ca68b Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 12 Aug 2010 18:17:37 +0000 Subject: usrp-e: fix typo in verify subdev spec --- host/lib/usrp/usrp_e/mboard_impl.cpp | 4 ++-- host/utils/uhd_find_devices.cpp | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/host/lib/usrp/usrp_e/mboard_impl.cpp b/host/lib/usrp/usrp_e/mboard_impl.cpp index 822f1571d..4914bd3b7 100644 --- a/host/lib/usrp/usrp_e/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e/mboard_impl.cpp @@ -139,7 +139,7 @@ void usrp_e_impl::mboard_set(const wax::obj &key, const wax::obj &val){ case MBOARD_PROP_RX_SUBDEV_SPEC: _rx_subdev_spec = val.as(); - verify_rx_subdev_spec(_rx_subdev_spec, this->get_link()); + verify_rx_subdev_spec(_rx_subdev_spec, _mboard_proxy->get_link()); //sanity check UHD_ASSERT_THROW(_rx_subdev_spec.size() == 1); //set the mux @@ -150,7 +150,7 @@ void usrp_e_impl::mboard_set(const wax::obj &key, const wax::obj &val){ case MBOARD_PROP_TX_SUBDEV_SPEC: _tx_subdev_spec = val.as(); - verify_tx_subdev_spec(_tx_subdev_spec, this->get_link()); + verify_tx_subdev_spec(_tx_subdev_spec, _mboard_proxy->get_link()); //sanity check UHD_ASSERT_THROW(_tx_subdev_spec.size() == 1); //set the mux diff --git a/host/utils/uhd_find_devices.cpp b/host/utils/uhd_find_devices.cpp index 8281c92bc..b778eeb68 100644 --- a/host/utils/uhd_find_devices.cpp +++ b/host/utils/uhd_find_devices.cpp @@ -53,7 +53,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ std::cout << "-- UHD Device " << i << std::endl; std::cout << "--------------------------------------------------" << std::endl; std::cout << device_addrs[i].to_pp_string() << std::endl << std::endl; - uhd::device::make(device_addrs[i]); //test make + //uhd::device::make(device_addrs[i]); //test make } return 0; -- cgit v1.2.3 From 8c676eeb973593caecb7270a6106e8592f73a352 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 12 Aug 2010 21:28:26 +0000 Subject: usrp-e: added codec impl, probe works --- host/lib/usrp/usrp_e/CMakeLists.txt | 1 + host/lib/usrp/usrp_e/codec_impl.cpp | 96 ++++++++++++++++++++++++++++++++++++ host/lib/usrp/usrp_e/dboard_impl.cpp | 8 +++ host/lib/usrp/usrp_e/mboard_impl.cpp | 5 +- host/lib/usrp/usrp_e/usrp_e_impl.cpp | 8 +++ host/lib/usrp/usrp_e/usrp_e_impl.hpp | 8 +++ 6 files changed, 122 insertions(+), 4 deletions(-) create mode 100644 host/lib/usrp/usrp_e/codec_impl.cpp diff --git a/host/lib/usrp/usrp_e/CMakeLists.txt b/host/lib/usrp/usrp_e/CMakeLists.txt index 1d64d29d2..f0c125f26 100644 --- a/host/lib/usrp/usrp_e/CMakeLists.txt +++ b/host/lib/usrp/usrp_e/CMakeLists.txt @@ -32,6 +32,7 @@ IF(HAVE_LINUX_USRP_E_H) ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/clock_ctrl.hpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/codec_ctrl.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/codec_ctrl.hpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/codec_impl.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/dboard_impl.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/dboard_iface.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/dsp_impl.cpp diff --git a/host/lib/usrp/usrp_e/codec_impl.cpp b/host/lib/usrp/usrp_e/codec_impl.cpp new file mode 100644 index 000000000..51f7b02b8 --- /dev/null +++ b/host/lib/usrp/usrp_e/codec_impl.cpp @@ -0,0 +1,96 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "usrp_e_impl.hpp" +#include +#include + +using namespace uhd; +using namespace uhd::usrp; + +/*********************************************************************** + * Helper Methods + **********************************************************************/ +void usrp_e_impl::codec_init(void){ + //make proxies + _rx_codec_proxy = wax_obj_proxy::make( + boost::bind(&usrp_e_impl::rx_codec_get, this, _1, _2), + boost::bind(&usrp_e_impl::rx_codec_set, this, _1, _2) + ); + _tx_codec_proxy = wax_obj_proxy::make( + boost::bind(&usrp_e_impl::tx_codec_get, this, _1, _2), + boost::bind(&usrp_e_impl::tx_codec_set, this, _1, _2) + ); +} + +/*********************************************************************** + * RX Codec Properties + **********************************************************************/ +void usrp_e_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){ + wax::obj key; std::string name; + boost::tie(key, name) = extract_named_prop(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case CODEC_PROP_NAME: + val = std::string("usrp-e adc - ad9522"); + return; + + case CODEC_PROP_OTHERS: + val = prop_names_t(); + return; + + case CODEC_PROP_GAIN_NAMES: + val = prop_names_t(); //no gain elements to be controlled + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +void usrp_e_impl::rx_codec_set(const wax::obj &, const wax::obj &){ + UHD_THROW_PROP_SET_ERROR(); +} + +/*********************************************************************** + * TX Codec Properties + **********************************************************************/ +void usrp_e_impl::tx_codec_get(const wax::obj &key_, wax::obj &val){ + wax::obj key; std::string name; + boost::tie(key, name) = extract_named_prop(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case CODEC_PROP_NAME: + val = std::string("usrp-e dac - ad9522"); + return; + + case CODEC_PROP_OTHERS: + val = prop_names_t(); + return; + + case CODEC_PROP_GAIN_NAMES: + val = prop_names_t(); //no gain elements to be controlled + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +void usrp_e_impl::tx_codec_set(const wax::obj &, const wax::obj &){ + UHD_THROW_PROP_SET_ERROR(); +} diff --git a/host/lib/usrp/usrp_e/dboard_impl.cpp b/host/lib/usrp/usrp_e/dboard_impl.cpp index 809b6f06b..8aaf16c51 100644 --- a/host/lib/usrp/usrp_e/dboard_impl.cpp +++ b/host/lib/usrp/usrp_e/dboard_impl.cpp @@ -81,6 +81,10 @@ void usrp_e_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){ val = _dboard_iface; return; + case DBOARD_PROP_CODEC: + val = _rx_codec_proxy->get_link(); + return; + default: UHD_THROW_PROP_GET_ERROR(); } } @@ -128,6 +132,10 @@ void usrp_e_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){ val = _dboard_iface; return; + case DBOARD_PROP_CODEC: + val = _tx_codec_proxy->get_link(); + return; + default: UHD_THROW_PROP_GET_ERROR(); } } diff --git a/host/lib/usrp/usrp_e/mboard_impl.cpp b/host/lib/usrp/usrp_e/mboard_impl.cpp index 4914bd3b7..88e16a6f5 100644 --- a/host/lib/usrp/usrp_e/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e/mboard_impl.cpp @@ -22,6 +22,7 @@ #include #include #include +#include using namespace uhd; using namespace uhd::usrp; @@ -40,10 +41,6 @@ void usrp_e_impl::mboard_init(void){ _clock_config.pps_source = clock_config_t::PPS_SMA; //TODO poke the clock config regs - - //set default subdev specs - this->mboard_set(MBOARD_PROP_RX_SUBDEV_SPEC, subdev_spec_t()); - this->mboard_set(MBOARD_PROP_TX_SUBDEV_SPEC, subdev_spec_t()); } /*********************************************************************** diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.cpp b/host/lib/usrp/usrp_e/usrp_e_impl.cpp index 76c77af15..0566cfd59 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.cpp @@ -17,6 +17,7 @@ #include "usrp_e_impl.hpp" #include +#include #include #include #include @@ -93,8 +94,15 @@ usrp_e_impl::usrp_e_impl(const std::string &node){ rx_ddc_init(); tx_duc_init(); + //init the codec properties + codec_init(); + //init the io send/recv io_init(); + + //set default subdev specs + this->mboard_set(MBOARD_PROP_RX_SUBDEV_SPEC, subdev_spec_t()); + this->mboard_set(MBOARD_PROP_TX_SUBDEV_SPEC, subdev_spec_t()); } usrp_e_impl::~usrp_e_impl(void){ diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index e3249e9de..2457e27cc 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -152,6 +152,14 @@ private: void tx_duc_set(const wax::obj &, const wax::obj &); double _duc_freq; size_t _duc_interp; wax_obj_proxy::sptr _tx_duc_proxy; + + //codec functions and settings + void codec_init(void); + void rx_codec_get(const wax::obj &, wax::obj &); + void rx_codec_set(const wax::obj &, const wax::obj &); + void tx_codec_get(const wax::obj &, wax::obj &); + void tx_codec_set(const wax::obj &, const wax::obj &); + wax_obj_proxy::sptr _rx_codec_proxy, _tx_codec_proxy; }; #endif /* INCLUDED_USRP_E_IMPL_HPP */ -- cgit v1.2.3 From ac85d2b38c26fd6d31ba0a997d033b159d51769d Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 13 Aug 2010 01:09:45 +0000 Subject: usrp-e: codec gain control from properties interface --- host/lib/usrp/usrp_e/clock_ctrl.cpp | 1 - host/lib/usrp/usrp_e/codec_ctrl.cpp | 48 ++++++++++++++++++++++++++ host/lib/usrp/usrp_e/codec_ctrl.hpp | 19 ++++++++-- host/lib/usrp/usrp_e/codec_impl.cpp | 69 +++++++++++++++++++++++++++++++++---- 4 files changed, 128 insertions(+), 9 deletions(-) diff --git a/host/lib/usrp/usrp_e/clock_ctrl.cpp b/host/lib/usrp/usrp_e/clock_ctrl.cpp index 8a5bd1c6b..b53e880a2 100644 --- a/host/lib/usrp/usrp_e/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e/clock_ctrl.cpp @@ -60,7 +60,6 @@ class usrp_e_clock_ctrl_impl : public usrp_e_clock_ctrl{ public: usrp_e_clock_ctrl_impl(usrp_e_iface::sptr iface){ _iface = iface; - std::cout << "master_clock_rate: " << (master_clock_rate/1e6) << " MHz" << std::endl; //init the clock gen registers //Note: out0 should already be clocking the FPGA or this isnt going to work diff --git a/host/lib/usrp/usrp_e/codec_ctrl.cpp b/host/lib/usrp/usrp_e/codec_ctrl.cpp index ac61bc6b4..5322f94bd 100644 --- a/host/lib/usrp/usrp_e/codec_ctrl.cpp +++ b/host/lib/usrp/usrp_e/codec_ctrl.cpp @@ -31,6 +31,9 @@ using namespace uhd; static const bool codec_debug = false; +const gain_range_t usrp_e_codec_ctrl::tx_pga_gain_range(-20, 0, float(0.1)); +const gain_range_t usrp_e_codec_ctrl::rx_pga_gain_range(0, 20, 1); + /*********************************************************************** * Codec Control Implementation **********************************************************************/ @@ -44,6 +47,12 @@ public: float read_aux_adc(aux_adc_t which); void write_aux_dac(aux_dac_t which, float volts); + //pga gain control + void set_tx_pga_gain(float); + float get_tx_pga_gain(void); + void set_rx_pga_gain(float, char); + float get_rx_pga_gain(char); + private: usrp_e_iface::sptr _iface; ad9862_regs_t _ad9862_regs; @@ -119,6 +128,45 @@ usrp_e_codec_ctrl_impl::~usrp_e_codec_ctrl_impl(void){ this->send_reg(8); } +/*********************************************************************** + * Codec Control Gain Control Methods + **********************************************************************/ +void usrp_e_codec_ctrl_impl::set_tx_pga_gain(float gain){ + int gain_word = int(63*(gain - tx_pga_gain_range.min)/(tx_pga_gain_range.max - tx_pga_gain_range.min)); + _ad9862_regs.tx_pga_gain = std::clip(gain_word, 0, 63); + this->send_reg(16); +} + +float usrp_e_codec_ctrl_impl::get_tx_pga_gain(void){ + return (_ad9862_regs.tx_pga_gain*(tx_pga_gain_range.max - tx_pga_gain_range.min)/63) + tx_pga_gain_range.min; +} + +void usrp_e_codec_ctrl_impl::set_rx_pga_gain(float gain, char which){ + int gain_word = int(0x14*(gain - rx_pga_gain_range.min)/(rx_pga_gain_range.max - rx_pga_gain_range.min)); + gain_word = std::clip(gain_word, 0, 0x14); + switch(which){ + case 'A': + _ad9862_regs.rx_pga_a = gain_word; + this->send_reg(2); + return; + case 'B': + _ad9862_regs.rx_pga_b = gain_word; + this->send_reg(3); + return; + default: UHD_THROW_INVALID_CODE_PATH(); + } +} + +float usrp_e_codec_ctrl_impl::get_rx_pga_gain(char which){ + int gain_word; + switch(which){ + case 'A': gain_word = _ad9862_regs.rx_pga_a; break; + case 'B': gain_word = _ad9862_regs.rx_pga_b; break; + default: UHD_THROW_INVALID_CODE_PATH(); + } + return (gain_word*(rx_pga_gain_range.max - rx_pga_gain_range.min)/0x14) + rx_pga_gain_range.min; +} + /*********************************************************************** * Codec Control AUX ADC Methods **********************************************************************/ diff --git a/host/lib/usrp/usrp_e/codec_ctrl.hpp b/host/lib/usrp/usrp_e/codec_ctrl.hpp index b9005a82d..87b6ff951 100644 --- a/host/lib/usrp/usrp_e/codec_ctrl.hpp +++ b/host/lib/usrp/usrp_e/codec_ctrl.hpp @@ -19,6 +19,7 @@ #define INCLUDED_USRP_E_CODEC_CTRL_HPP #include "usrp_e_iface.hpp" +#include #include #include @@ -31,10 +32,13 @@ class usrp_e_codec_ctrl : boost::noncopyable{ public: typedef boost::shared_ptr sptr; + static const uhd::gain_range_t tx_pga_gain_range; + static const uhd::gain_range_t rx_pga_gain_range; + /*! - * Make a new clock control object. + * Make a new codec control object. * \param iface the usrp_e iface object - * \return the clock control object + * \return the codec control object */ static sptr make(usrp_e_iface::sptr iface); @@ -70,6 +74,17 @@ public: */ virtual void write_aux_dac(aux_dac_t which, float volts) = 0; + //! Set the TX PGA gain + virtual void set_tx_pga_gain(float gain) = 0; + + //! Get the TX PGA gain + virtual float get_tx_pga_gain(void) = 0; + + //! Set the RX PGA gain ('A' or 'B') + virtual void set_rx_pga_gain(float gain, char which) = 0; + + //! Get the RX PGA gain ('A' or 'B') + virtual float get_rx_pga_gain(char which) = 0; }; #endif /* INCLUDED_USRP_E_CODEC_CTRL_HPP */ diff --git a/host/lib/usrp/usrp_e/codec_impl.cpp b/host/lib/usrp/usrp_e/codec_impl.cpp index 51f7b02b8..84f8bd37f 100644 --- a/host/lib/usrp/usrp_e/codec_impl.cpp +++ b/host/lib/usrp/usrp_e/codec_impl.cpp @@ -16,6 +16,7 @@ // #include "usrp_e_impl.hpp" +#include #include #include @@ -40,6 +41,8 @@ void usrp_e_impl::codec_init(void){ /*********************************************************************** * RX Codec Properties **********************************************************************/ +static const std::string ad9862_pga_gain_name = "ad9862 pga"; + void usrp_e_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){ wax::obj key; std::string name; boost::tie(key, name) = extract_named_prop(key_); @@ -55,15 +58,46 @@ void usrp_e_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){ return; case CODEC_PROP_GAIN_NAMES: - val = prop_names_t(); //no gain elements to be controlled + val = prop_names_t(1, ad9862_pga_gain_name); + return; + + case CODEC_PROP_GAIN_RANGE: + UHD_ASSERT_THROW(name == ad9862_pga_gain_name); + val = usrp_e_codec_ctrl::rx_pga_gain_range; + return; + + case CODEC_PROP_GAIN_I: + UHD_ASSERT_THROW(name == ad9862_pga_gain_name); + val = _codec_ctrl->get_rx_pga_gain('A'); + return; + + case CODEC_PROP_GAIN_Q: + UHD_ASSERT_THROW(name == ad9862_pga_gain_name); + val = _codec_ctrl->get_rx_pga_gain('B'); return; default: UHD_THROW_PROP_GET_ERROR(); } } -void usrp_e_impl::rx_codec_set(const wax::obj &, const wax::obj &){ - UHD_THROW_PROP_SET_ERROR(); +void usrp_e_impl::rx_codec_set(const wax::obj &key_, const wax::obj &val){ + wax::obj key; std::string name; + boost::tie(key, name) = extract_named_prop(key_); + + //handle the set request conditioned on the key + switch(key.as()){ + case CODEC_PROP_GAIN_I: + UHD_ASSERT_THROW(name == ad9862_pga_gain_name); + _codec_ctrl->set_rx_pga_gain(val.as(), 'A'); + return; + + case CODEC_PROP_GAIN_Q: + UHD_ASSERT_THROW(name == ad9862_pga_gain_name); + _codec_ctrl->set_rx_pga_gain(val.as(), 'B'); + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } } /*********************************************************************** @@ -84,13 +118,36 @@ void usrp_e_impl::tx_codec_get(const wax::obj &key_, wax::obj &val){ return; case CODEC_PROP_GAIN_NAMES: - val = prop_names_t(); //no gain elements to be controlled + val = prop_names_t(1, ad9862_pga_gain_name); + return; + + case CODEC_PROP_GAIN_RANGE: + UHD_ASSERT_THROW(name == ad9862_pga_gain_name); + val = usrp_e_codec_ctrl::tx_pga_gain_range; + return; + + case CODEC_PROP_GAIN_I: //only one gain for I and Q + case CODEC_PROP_GAIN_Q: + UHD_ASSERT_THROW(name == ad9862_pga_gain_name); + val = _codec_ctrl->get_tx_pga_gain(); return; default: UHD_THROW_PROP_GET_ERROR(); } } -void usrp_e_impl::tx_codec_set(const wax::obj &, const wax::obj &){ - UHD_THROW_PROP_SET_ERROR(); +void usrp_e_impl::tx_codec_set(const wax::obj &key_, const wax::obj &val){ + wax::obj key; std::string name; + boost::tie(key, name) = extract_named_prop(key_); + + //handle the set request conditioned on the key + switch(key.as()){ + case CODEC_PROP_GAIN_I: //only one gain for I and Q + case CODEC_PROP_GAIN_Q: + UHD_ASSERT_THROW(name == ad9862_pga_gain_name); + _codec_ctrl->set_tx_pga_gain(val.as()); + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } } -- cgit v1.2.3 From 3091759d3f6a69bc0c56f2101b7b775de443212a Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 13 Aug 2010 11:49:36 -0700 Subject: this is necessary for some reason --- usrp2/top/u1e/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index f4a643176..3cb9fd8f3 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -95,6 +95,7 @@ GEN_PROG_FILE_PROPERTIES = \ "Create Binary Configuration File" TRUE \ "Done (Output Events)" 5 \ "Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" SIM_MODEL_PROPERTIES = "" -- cgit v1.2.3 From a340b9fb5ffe0e43a746ce8ce051b08444a1a713 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 13 Aug 2010 19:30:32 +0000 Subject: usrp-e: clock settings, ref doubler, disable test clock, lower cp current --- host/lib/usrp/usrp_e/clock_ctrl.cpp | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/host/lib/usrp/usrp_e/clock_ctrl.cpp b/host/lib/usrp/usrp_e/clock_ctrl.cpp index b53e880a2..22578a933 100644 --- a/host/lib/usrp/usrp_e/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e/clock_ctrl.cpp @@ -38,11 +38,13 @@ template static void set_clock_divider /*********************************************************************** * Constants **********************************************************************/ -static const double ref_clock_rate = 10e6; +static const bool enable_test_clock = false; +static const double ref_clock_doubler = 2; //enabled below +static const double ref_clock_rate = 10e6 * ref_clock_doubler; static const size_t r_counter = 1; static const size_t a_counter = 0; -static const size_t b_counter = 20; +static const size_t b_counter = 20 / ref_clock_doubler; static const size_t prescaler = 8; //set below with enum, set to 8 when input is under 2400 MHz static const size_t vco_divider = 1; //set below with enum @@ -64,6 +66,7 @@ public: //init the clock gen registers //Note: out0 should already be clocking the FPGA or this isnt going to work _ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO; + _ad9522_regs.enable_clock_doubler = 1; //enable ref clock doubler _ad9522_regs.enb_stat_eeprom_at_stat_pin = 0; //use status pin _ad9522_regs.status_pin_control = 0x1; //n divider _ad9522_regs.ld_pin_control = 0x00; //dld @@ -79,7 +82,7 @@ public: _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV8_9; _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL; - _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_3_0MA; + _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA; _ad9522_regs.vco_calibration_now = 1; //calibrate it! _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV1; @@ -103,7 +106,7 @@ public: //setup test clock (same divider as codec clock) _ad9522_regs.out4_format = ad9522_regs_t::OUT4_FORMAT_CMOS; - _ad9522_regs.out4_cmos_configuration = (true)? + _ad9522_regs.out4_cmos_configuration = (enable_test_clock)? ad9522_regs_t::OUT4_CMOS_CONFIGURATION_A_ON : ad9522_regs_t::OUT4_CMOS_CONFIGURATION_OFF; -- cgit v1.2.3 From 1b47702245f0c1f4dda3e0eff487bbe664d48855 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 17 Aug 2010 17:16:31 +0000 Subject: usrp-e: misc code tweaks --- host/examples/tx_timed_samples.cpp | 2 +- host/lib/usrp/usrp_e/clock_ctrl.cpp | 2 +- host/lib/usrp/usrp_e/codec_ctrl.cpp | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/host/examples/tx_timed_samples.cpp b/host/examples/tx_timed_samples.cpp index ceae58a22..aa22d3465 100644 --- a/host/examples/tx_timed_samples.cpp +++ b/host/examples/tx_timed_samples.cpp @@ -77,7 +77,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ sdev->set_time_now(uhd::time_spec_t(0.0)); //allocate data to send - std::vector > buff(samps_per_packet, std::complex(ampl, ampl)); + std::vector > buff(samps_per_packet, std::complex(ampl, ampl)); uhd::tx_metadata_t md; //send the data in multiple packets diff --git a/host/lib/usrp/usrp_e/clock_ctrl.cpp b/host/lib/usrp/usrp_e/clock_ctrl.cpp index 22578a933..62807aec2 100644 --- a/host/lib/usrp/usrp_e/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e/clock_ctrl.cpp @@ -39,7 +39,7 @@ template static void set_clock_divider * Constants **********************************************************************/ static const bool enable_test_clock = false; -static const double ref_clock_doubler = 2; //enabled below +static const size_t ref_clock_doubler = 2; //enabled below static const double ref_clock_rate = 10e6 * ref_clock_doubler; static const size_t r_counter = 1; diff --git a/host/lib/usrp/usrp_e/codec_ctrl.cpp b/host/lib/usrp/usrp_e/codec_ctrl.cpp index 5322f94bd..2bdbc0f1c 100644 --- a/host/lib/usrp/usrp_e/codec_ctrl.cpp +++ b/host/lib/usrp/usrp_e/codec_ctrl.cpp @@ -97,6 +97,7 @@ usrp_e_codec_ctrl_impl::usrp_e_codec_ctrl_impl(usrp_e_iface::sptr iface){ _ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_BYPASS; _ad9862_regs.dac_a_coarse_gain = 0x3; _ad9862_regs.dac_b_coarse_gain = 0x3; + _ad9862_regs.edges = ad9862_regs_t::EDGES_BOTH; //setup the dll _ad9862_regs.input_clk_ctrl = ad9862_regs_t::INPUT_CLK_CTRL_EXTERNAL; -- cgit v1.2.3 From 1e28ae518de1268efa370eb8b4b206b7d5a49b03 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 17 Aug 2010 19:23:56 +0000 Subject: usrp-e: building off of next branch --- host/config/Version.cmake | 2 +- host/lib/usrp/usrp_e/clock_ctrl.cpp | 3 ++- host/lib/usrp/usrp_e/codec_impl.cpp | 28 ++++++++++++---------------- host/lib/usrp/usrp_e/dboard_iface.cpp | 7 ++++++- host/lib/usrp/usrp_e/dboard_impl.cpp | 10 ++++------ host/lib/usrp/usrp_e/dsp_impl.cpp | 3 ++- host/lib/usrp/usrp_e/io_impl.cpp | 2 +- host/lib/usrp/usrp_e/mboard_impl.cpp | 16 +++++++--------- host/lib/usrp/usrp_e/usrp_e_impl.cpp | 5 ++--- 9 files changed, 37 insertions(+), 39 deletions(-) diff --git a/host/config/Version.cmake b/host/config/Version.cmake index a592a4565..9e4b6b306 100644 --- a/host/config/Version.cmake +++ b/host/config/Version.cmake @@ -42,7 +42,7 @@ ELSE(${GIT} STREQUAL "GIT-NOTFOUND") #extract the timestamp from the git log entry EXECUTE_PROCESS( WORKING_DIRECTORY ${CMAKE_SOURCE_DIR} - COMMAND ${PYTHON_EXECUTABLE} -c "import re; print re.match('^.*Date:\\s*(\\d*).*$', '''${_git_log}''', re.MULTILINE | re.DOTALL).groups()[0]" + COMMAND ${PYTHON_EXECUTABLE} -c "import re; print re.match('^.*Date:\\s*(\\d*).*$', ''' ${_git_log} ''', re.MULTILINE | re.DOTALL).groups()[0]" OUTPUT_VARIABLE _git_timestamp OUTPUT_STRIP_TRAILING_WHITESPACE ) diff --git a/host/lib/usrp/usrp_e/clock_ctrl.cpp b/host/lib/usrp/usrp_e/clock_ctrl.cpp index 62807aec2..10f263e1d 100644 --- a/host/lib/usrp/usrp_e/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e/clock_ctrl.cpp @@ -160,7 +160,8 @@ public: std::vector get_rx_dboard_clock_rates(void){ std::vector rates; - for(size_t div = 1; div <= 16+16; div++) rates.push_back(master_clock_rate/div); + for(size_t div = 2/*vco div == 1*/; div <= 16+16; div++) + rates.push_back(master_clock_rate/div); return rates; } diff --git a/host/lib/usrp/usrp_e/codec_impl.cpp b/host/lib/usrp/usrp_e/codec_impl.cpp index 84f8bd37f..696fb37ec 100644 --- a/host/lib/usrp/usrp_e/codec_impl.cpp +++ b/host/lib/usrp/usrp_e/codec_impl.cpp @@ -44,8 +44,7 @@ void usrp_e_impl::codec_init(void){ static const std::string ad9862_pga_gain_name = "ad9862 pga"; void usrp_e_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){ - wax::obj key; std::string name; - boost::tie(key, name) = extract_named_prop(key_); + named_prop_t key = named_prop_t::extract(key_); //handle the get request conditioned on the key switch(key.as()){ @@ -62,17 +61,17 @@ void usrp_e_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){ return; case CODEC_PROP_GAIN_RANGE: - UHD_ASSERT_THROW(name == ad9862_pga_gain_name); + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); val = usrp_e_codec_ctrl::rx_pga_gain_range; return; case CODEC_PROP_GAIN_I: - UHD_ASSERT_THROW(name == ad9862_pga_gain_name); + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); val = _codec_ctrl->get_rx_pga_gain('A'); return; case CODEC_PROP_GAIN_Q: - UHD_ASSERT_THROW(name == ad9862_pga_gain_name); + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); val = _codec_ctrl->get_rx_pga_gain('B'); return; @@ -81,18 +80,17 @@ void usrp_e_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){ } void usrp_e_impl::rx_codec_set(const wax::obj &key_, const wax::obj &val){ - wax::obj key; std::string name; - boost::tie(key, name) = extract_named_prop(key_); + named_prop_t key = named_prop_t::extract(key_); //handle the set request conditioned on the key switch(key.as()){ case CODEC_PROP_GAIN_I: - UHD_ASSERT_THROW(name == ad9862_pga_gain_name); + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); _codec_ctrl->set_rx_pga_gain(val.as(), 'A'); return; case CODEC_PROP_GAIN_Q: - UHD_ASSERT_THROW(name == ad9862_pga_gain_name); + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); _codec_ctrl->set_rx_pga_gain(val.as(), 'B'); return; @@ -104,8 +102,7 @@ void usrp_e_impl::rx_codec_set(const wax::obj &key_, const wax::obj &val){ * TX Codec Properties **********************************************************************/ void usrp_e_impl::tx_codec_get(const wax::obj &key_, wax::obj &val){ - wax::obj key; std::string name; - boost::tie(key, name) = extract_named_prop(key_); + named_prop_t key = named_prop_t::extract(key_); //handle the get request conditioned on the key switch(key.as()){ @@ -122,13 +119,13 @@ void usrp_e_impl::tx_codec_get(const wax::obj &key_, wax::obj &val){ return; case CODEC_PROP_GAIN_RANGE: - UHD_ASSERT_THROW(name == ad9862_pga_gain_name); + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); val = usrp_e_codec_ctrl::tx_pga_gain_range; return; case CODEC_PROP_GAIN_I: //only one gain for I and Q case CODEC_PROP_GAIN_Q: - UHD_ASSERT_THROW(name == ad9862_pga_gain_name); + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); val = _codec_ctrl->get_tx_pga_gain(); return; @@ -137,14 +134,13 @@ void usrp_e_impl::tx_codec_get(const wax::obj &key_, wax::obj &val){ } void usrp_e_impl::tx_codec_set(const wax::obj &key_, const wax::obj &val){ - wax::obj key; std::string name; - boost::tie(key, name) = extract_named_prop(key_); + named_prop_t key = named_prop_t::extract(key_); //handle the set request conditioned on the key switch(key.as()){ case CODEC_PROP_GAIN_I: //only one gain for I and Q case CODEC_PROP_GAIN_Q: - UHD_ASSERT_THROW(name == ad9862_pga_gain_name); + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); _codec_ctrl->set_tx_pga_gain(val.as()); return; diff --git a/host/lib/usrp/usrp_e/dboard_iface.cpp b/host/lib/usrp/usrp_e/dboard_iface.cpp index d5ec10d84..a9831ebc4 100644 --- a/host/lib/usrp/usrp_e/dboard_iface.cpp +++ b/host/lib/usrp/usrp_e/dboard_iface.cpp @@ -50,7 +50,12 @@ public: /* NOP */ } - std::string get_mboard_name(void){return "usrp-e";} + special_props_t get_special_props(void){ + special_props_t props; + props.soft_clock_divider = false; + props.mangle_i2c_addrs = false; + return props; + } void write_aux_dac(unit_t, aux_dac_t, float); float read_aux_adc(unit_t, aux_adc_t); diff --git a/host/lib/usrp/usrp_e/dboard_impl.cpp b/host/lib/usrp/usrp_e/dboard_impl.cpp index 8aaf16c51..79ff54c9d 100644 --- a/host/lib/usrp/usrp_e/dboard_impl.cpp +++ b/host/lib/usrp/usrp_e/dboard_impl.cpp @@ -56,8 +56,7 @@ void usrp_e_impl::dboard_init(void){ * RX Dboard Get **********************************************************************/ void usrp_e_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){ - wax::obj key; std::string name; - boost::tie(key, name) = extract_named_prop(key_); + named_prop_t key = named_prop_t::extract(key_); //handle the get request conditioned on the key switch(key.as()){ @@ -66,7 +65,7 @@ void usrp_e_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){ return; case DBOARD_PROP_SUBDEV: - val = _dboard_manager->get_rx_subdev(name); + val = _dboard_manager->get_rx_subdev(key.name); return; case DBOARD_PROP_SUBDEV_NAMES: @@ -107,8 +106,7 @@ void usrp_e_impl::rx_dboard_set(const wax::obj &key, const wax::obj &val){ * TX Dboard Get **********************************************************************/ void usrp_e_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){ - wax::obj key; std::string name; - boost::tie(key, name) = extract_named_prop(key_); + named_prop_t key = named_prop_t::extract(key_); //handle the get request conditioned on the key switch(key.as()){ @@ -117,7 +115,7 @@ void usrp_e_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){ return; case DBOARD_PROP_SUBDEV: - val = _dboard_manager->get_tx_subdev(name); + val = _dboard_manager->get_tx_subdev(key.name); return; case DBOARD_PROP_SUBDEV_NAMES: diff --git a/host/lib/usrp/usrp_e/dsp_impl.cpp b/host/lib/usrp/usrp_e/dsp_impl.cpp index 58a58706d..c133eafae 100644 --- a/host/lib/usrp/usrp_e/dsp_impl.cpp +++ b/host/lib/usrp/usrp_e/dsp_impl.cpp @@ -17,8 +17,9 @@ #include "usrp_e_impl.hpp" #include "usrp_e_regs.hpp" -#include "../dsp_utils.hpp" +#include #include +#include #include #define rint boost::math::iround diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index bbc3f5215..eaa45d60c 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -17,7 +17,7 @@ #include "usrp_e_impl.hpp" #include "usrp_e_regs.hpp" -#include "../dsp_utils.hpp" +#include #include "../../transport/vrt_packet_handler.hpp" #include #include //read, write diff --git a/host/lib/usrp/usrp_e/mboard_impl.cpp b/host/lib/usrp/usrp_e/mboard_impl.cpp index 88e16a6f5..3d4cef069 100644 --- a/host/lib/usrp/usrp_e/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e/mboard_impl.cpp @@ -17,8 +17,8 @@ #include "usrp_e_impl.hpp" #include "usrp_e_regs.hpp" -#include "../dsp_utils.hpp" -#include "../misc_utils.hpp" +#include +#include #include #include #include @@ -47,9 +47,7 @@ void usrp_e_impl::mboard_init(void){ * Mboard Get **********************************************************************/ void usrp_e_impl::mboard_get(const wax::obj &key_, wax::obj &val){ - wax::obj key; std::string name; - boost::tie(key, name) = extract_named_prop(key_); - + named_prop_t key = named_prop_t::extract(key_); //handle the get request conditioned on the key switch(key.as()){ @@ -62,7 +60,7 @@ void usrp_e_impl::mboard_get(const wax::obj &key_, wax::obj &val){ return; case MBOARD_PROP_RX_DBOARD: - UHD_ASSERT_THROW(name == ""); + UHD_ASSERT_THROW(key.name == ""); val = _rx_dboard_proxy->get_link(); return; @@ -71,7 +69,7 @@ void usrp_e_impl::mboard_get(const wax::obj &key_, wax::obj &val){ return; case MBOARD_PROP_TX_DBOARD: - UHD_ASSERT_THROW(name == ""); + UHD_ASSERT_THROW(key.name == ""); val = _tx_dboard_proxy->get_link(); return; @@ -80,7 +78,7 @@ void usrp_e_impl::mboard_get(const wax::obj &key_, wax::obj &val){ return; case MBOARD_PROP_RX_DSP: - UHD_ASSERT_THROW(name == ""); + UHD_ASSERT_THROW(key.name == ""); val = _rx_ddc_proxy->get_link(); return; @@ -89,7 +87,7 @@ void usrp_e_impl::mboard_get(const wax::obj &key_, wax::obj &val){ return; case MBOARD_PROP_TX_DSP: - UHD_ASSERT_THROW(name == ""); + UHD_ASSERT_THROW(key.name == ""); val = _tx_duc_proxy->get_link(); return; diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.cpp b/host/lib/usrp/usrp_e/usrp_e_impl.cpp index 0566cfd59..5c0e1dbb0 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.cpp @@ -113,8 +113,7 @@ usrp_e_impl::~usrp_e_impl(void){ * Device Get **********************************************************************/ void usrp_e_impl::get(const wax::obj &key_, wax::obj &val){ - wax::obj key; std::string name; - boost::tie(key, name) = extract_named_prop(key_); + named_prop_t key = named_prop_t::extract(key_); //handle the get request conditioned on the key switch(key.as()){ @@ -123,7 +122,7 @@ void usrp_e_impl::get(const wax::obj &key_, wax::obj &val){ return; case DEVICE_PROP_MBOARD: - UHD_ASSERT_THROW(name == ""); + UHD_ASSERT_THROW(key.name == ""); val = _mboard_proxy->get_link(); return; -- cgit v1.2.3 From 1d9d3dcc7b460e25881d182e74429f91cef31a50 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 17 Aug 2010 15:50:27 -0700 Subject: delay the q channel to make the channels line up on the AD9862 --- usrp2/top/u1e/u1e.v | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 523aae1b9..9536b5ced 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -99,6 +99,11 @@ module u1e TXSYNC <= 1; end `else // !`ifdef DCM + + reg[13:0] delay_q; + always @(posedge clk_fpga) + delay_q <= tx_q; + genvar i; generate for(i=0;i<14;i=i+1) @@ -111,7 +116,7 @@ module u1e .C1(~clk_fpga), // 1-bit clock input .CE(1'b1), // 1-bit clock enable input .D0(tx_i[i]), // 1-bit data input (associated with C0) - .D1(tx_q[i]), // 1-bit data input (associated with C1) + .D1(delay_q[i]), // 1-bit data input (associated with C1) .R(1'b0), // 1-bit reset input .S(1'b0)); // 1-bit set input end // block: gen_dacout -- cgit v1.2.3 From 746f94409d12b6ab2a0e99260655b5a0460ba220 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 17 Aug 2010 16:37:55 -0700 Subject: connect atr --- usrp2/top/u1e/u1e_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 4561df173..13e6f4b68 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -419,7 +419,7 @@ module u1e_core (.clk_i(wb_clk), .rst_i(wb_rst), .adr_i(s6_adr), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), - .run_rx(0), .run_tx(0), .ctrl_lines(atr_lines)); + .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines)); // ///////////////////////////////////////////////////////////////////////// -- cgit v1.2.3 From 270fb931f11b23a0119a8fe836bbd712d9a50c60 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Tue, 17 Aug 2010 23:38:39 +0000 Subject: Merging my work back to usrp_e branch. --- host/examples/rx_to_file.cpp | 138 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 host/examples/rx_to_file.cpp diff --git a/host/examples/rx_to_file.cpp b/host/examples/rx_to_file.cpp new file mode 100644 index 000000000..cb8c42acc --- /dev/null +++ b/host/examples/rx_to_file.cpp @@ -0,0 +1,138 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include +#include +#include +#include +#include +#include +#include + +namespace po = boost::program_options; + + +int UHD_SAFE_MAIN(int argc, char *argv[]){ + uhd::set_thread_priority_safe(); + + //variables to be set by po + std::string args; + time_t seconds_in_future; + size_t total_num_samps; + double rx_rate, freq; + + //setup the program options + po::options_description desc("Allowed options"); + desc.add_options() + ("help", "help message") + ("args", po::value(&args)->default_value(""), "simple uhd device address args") + ("secs", po::value(&seconds_in_future)->default_value(3), "number of seconds in the future to receive") + ("nsamps", po::value(&total_num_samps)->default_value(1000), "total number of samples to receive") + ("rxrate", po::value(&rx_rate)->default_value(100e6/16), "rate of incoming samples") + ("freq", po::value(&freq)->default_value(0), "rf center frequency in Hz") + ("dilv", "specify to disable inner-loop verbose") + ; + po::variables_map vm; + po::store(po::parse_command_line(argc, argv, desc), vm); + po::notify(vm); + + //print the help message + if (vm.count("help")){ + std::cout << boost::format("UHD RX Timed Samples %s") % desc << std::endl; + return ~0; + } + + bool verbose = vm.count("dilv") == 0; + + //create a usrp device + std::cout << std::endl; + std::cout << boost::format("Creating the usrp device with: %s...") % args << std::endl; + uhd::usrp::simple_usrp::sptr sdev = uhd::usrp::simple_usrp::make(args); + uhd::device::sptr dev = sdev->get_device(); + std::cout << boost::format("Using Device: %s") % sdev->get_pp_string() << std::endl; + + //set properties on the device + std::cout << boost::format("Setting RX Rate: %f Msps...") % (rx_rate/1e6) << std::endl; + sdev->set_rx_rate(rx_rate); + std::cout << boost::format("Actual RX Rate: %f Msps...") % (sdev->get_rx_rate()/1e6) << std::endl; + std::cout << boost::format("Setting device timestamp to 0...") << std::endl; + sdev->set_rx_freq(freq); + sdev->set_time_now(uhd::time_spec_t(0.0)); + + sleep(1); + std::cout << "LO Locked = " << sdev->get_rx_lo_locked() << std::endl; + + //setup streaming + std::cout << std::endl; + std::cout << boost::format( + "Begin streaming %u samples, %d seconds in the future..." + ) % total_num_samps % seconds_in_future << std::endl; + uhd::stream_cmd_t stream_cmd(uhd::stream_cmd_t::STREAM_MODE_NUM_SAMPS_AND_DONE); + stream_cmd.num_samps = total_num_samps; + stream_cmd.stream_now = false; + stream_cmd.time_spec = uhd::time_spec_t(seconds_in_future); + sdev->issue_stream_cmd(stream_cmd); + + //loop until total number of samples reached + size_t num_acc_samps = 0; //number of accumulated samples + uhd::rx_metadata_t md; + std::vector > buff(dev->get_max_recv_samps_per_packet()); + std::ofstream outfile("out.dat", std::ofstream::binary); + + while(num_acc_samps < total_num_samps){ + size_t num_rx_samps = dev->recv( + &buff.front(), buff.size(), md, + uhd::io_type_t::COMPLEX_INT16, + uhd::device::RECV_MODE_ONE_PACKET + ); + + //handle the error codes + switch(md.error_code){ + case uhd::rx_metadata_t::ERROR_CODE_NONE: + break; + + case uhd::rx_metadata_t::ERROR_CODE_TIMEOUT: + if (num_acc_samps == 0) continue; + std::cout << boost::format( + "Got timeout before all samples received, possible packet loss, exiting loop..." + ) << std::endl; + goto done_loop; + + default: + std::cout << boost::format( + "Got error code 0x%x, exiting loop..." + ) % md.error_code << std::endl; + goto done_loop; + } + + outfile.write((const char*)&buff[0], num_rx_samps * sizeof(std::complex)); + + if(verbose) std::cout << boost::format( + "Got packet: %u samples, %u full secs, %f frac secs" + ) % num_rx_samps % md.time_spec.get_full_secs() % md.time_spec.get_frac_secs() << std::endl; + + num_acc_samps += num_rx_samps; + } done_loop: + + outfile.close(); + + //finished + std::cout << std::endl << "Done!" << std::endl << std::endl; + + return 0; +} -- cgit v1.2.3 From e48dfb211609e26230c2e7c165ad3aa5d5b0ecfc Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Tue, 17 Aug 2010 23:39:36 +0000 Subject: Fix to create 90 phase shift on TX. --- host/lib/usrp/usrp_e/codec_ctrl.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/host/lib/usrp/usrp_e/codec_ctrl.cpp b/host/lib/usrp/usrp_e/codec_ctrl.cpp index 2bdbc0f1c..45063894e 100644 --- a/host/lib/usrp/usrp_e/codec_ctrl.cpp +++ b/host/lib/usrp/usrp_e/codec_ctrl.cpp @@ -89,6 +89,7 @@ usrp_e_codec_ctrl_impl::usrp_e_codec_ctrl_impl(usrp_e_iface::sptr iface){ //setup tx side of codec _ad9862_regs.two_data_paths = ad9862_regs_t::TWO_DATA_PATHS_BOTH; _ad9862_regs.interleaved = ad9862_regs_t::INTERLEAVED_INTERLEAVED; + _ad9862_regs.tx_retime = ad9862_regs_t::TX_RETIME_CLKOUT2; _ad9862_regs.tx_pga_gain = 199; //TODO bring under api control _ad9862_regs.tx_hilbert = ad9862_regs_t::TX_HILBERT_DIS; _ad9862_regs.interp = ad9862_regs_t::INTERP_2; -- cgit v1.2.3 From 02c2a3fd08b1ae1a306fa45d89b55dafeaffb508 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 17 Aug 2010 17:11:43 -0700 Subject: attach run_tx and run_rx to leds --- usrp2/top/u1e/u1e_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 13e6f4b68..63488f549 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -339,7 +339,7 @@ module u1e_core assign rx_enable = xfer_rate[14]; assign rate = xfer_rate[7:0]; - assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board + assign { debug_led[2],debug_led[0],debug_led[1] } = {run_rx,run_tx,reg_leds[0]}; // LEDs are arranged funny on board assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : -- cgit v1.2.3 From f7fab232e5b6124b0bda821736ac309ccc0cab94 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 18 Aug 2010 00:41:41 +0000 Subject: Really fix TX IQ phase offset. --- host/lib/usrp/usrp_e/codec_ctrl.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/host/lib/usrp/usrp_e/codec_ctrl.cpp b/host/lib/usrp/usrp_e/codec_ctrl.cpp index 45063894e..837219759 100644 --- a/host/lib/usrp/usrp_e/codec_ctrl.cpp +++ b/host/lib/usrp/usrp_e/codec_ctrl.cpp @@ -29,7 +29,7 @@ using namespace uhd; -static const bool codec_debug = false; +static const bool codec_debug = true; const gain_range_t usrp_e_codec_ctrl::tx_pga_gain_range(-20, 0, float(0.1)); const gain_range_t usrp_e_codec_ctrl::rx_pga_gain_range(0, 20, 1); @@ -98,7 +98,7 @@ usrp_e_codec_ctrl_impl::usrp_e_codec_ctrl_impl(usrp_e_iface::sptr iface){ _ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_BYPASS; _ad9862_regs.dac_a_coarse_gain = 0x3; _ad9862_regs.dac_b_coarse_gain = 0x3; - _ad9862_regs.edges = ad9862_regs_t::EDGES_BOTH; + _ad9862_regs.edges = ad9862_regs_t::EDGES_NORMAL; //setup the dll _ad9862_regs.input_clk_ctrl = ad9862_regs_t::INPUT_CLK_CTRL_EXTERNAL; -- cgit v1.2.3 From c3fc2010bffbb74414c029910347c6aa28c2b8d4 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 18 Aug 2010 00:53:58 +0000 Subject: usrp-e: added gain group property --- host/lib/usrp/usrp_e/dboard_iface.cpp | 5 ++++- host/lib/usrp/usrp_e/dboard_impl.cpp | 17 +++++++++++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/host/lib/usrp/usrp_e/dboard_iface.cpp b/host/lib/usrp/usrp_e/dboard_iface.cpp index a9831ebc4..c9efd0c9e 100644 --- a/host/lib/usrp/usrp_e/dboard_iface.cpp +++ b/host/lib/usrp/usrp_e/dboard_iface.cpp @@ -44,6 +44,9 @@ public: //init the clock rate shadows this->set_clock_rate(UNIT_RX, _clock->get_fpga_clock_rate()); this->set_clock_rate(UNIT_TX, _clock->get_fpga_clock_rate()); + + _iface->poke16(UE_REG_GPIO_RX_DBG, 0); + _iface->poke16(UE_REG_GPIO_TX_DBG, 0); } ~usrp_e_dboard_iface(void){ @@ -165,8 +168,8 @@ boost::uint16_t usrp_e_dboard_iface::read_gpio(unit_t unit){ switch(unit){ case UNIT_RX: return _iface->peek16(UE_REG_GPIO_RX_IO); case UNIT_TX: return _iface->peek16(UE_REG_GPIO_TX_IO); + default: UHD_THROW_INVALID_CODE_PATH(); } - UHD_ASSERT_THROW(false); } void usrp_e_dboard_iface::set_atr_reg(unit_t unit, atr_reg_t atr, boost::uint16_t value){ diff --git a/host/lib/usrp/usrp_e/dboard_impl.cpp b/host/lib/usrp/usrp_e/dboard_impl.cpp index 79ff54c9d..d4a27cb72 100644 --- a/host/lib/usrp/usrp_e/dboard_impl.cpp +++ b/host/lib/usrp/usrp_e/dboard_impl.cpp @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -84,6 +85,14 @@ void usrp_e_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){ val = _rx_codec_proxy->get_link(); return; + case DBOARD_PROP_GAIN_GROUP: + val = make_gain_group( + _dboard_manager->get_rx_subdev(key.name), + _rx_codec_proxy->get_link(), + GAIN_GROUP_POLICY_RX + ); + return; + default: UHD_THROW_PROP_GET_ERROR(); } } @@ -134,6 +143,14 @@ void usrp_e_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){ val = _tx_codec_proxy->get_link(); return; + case DBOARD_PROP_GAIN_GROUP: + val = make_gain_group( + _dboard_manager->get_tx_subdev(key.name), + _tx_codec_proxy->get_link(), + GAIN_GROUP_POLICY_TX + ); + return; + default: UHD_THROW_PROP_GET_ERROR(); } } -- cgit v1.2.3 From 50b70be92442c05f8cebb63f51333dab2568ca71 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 18 Aug 2010 22:07:09 +0000 Subject: Build rx_to_file example. --- host/examples/CMakeLists.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/host/examples/CMakeLists.txt b/host/examples/CMakeLists.txt index 10a9a833a..70e74a9a8 100644 --- a/host/examples/CMakeLists.txt +++ b/host/examples/CMakeLists.txt @@ -25,6 +25,9 @@ TARGET_LINK_LIBRARIES(benchmark_rx_rate uhd) ADD_EXECUTABLE(rx_timed_samples rx_timed_samples.cpp) TARGET_LINK_LIBRARIES(rx_timed_samples uhd) +ADD_EXECUTABLE(rx_to_file rx_to_file.cpp) +TARGET_LINK_LIBRARIES(rx_to_file uhd) + ADD_EXECUTABLE(tx_timed_samples tx_timed_samples.cpp) TARGET_LINK_LIBRARIES(tx_timed_samples uhd) -- cgit v1.2.3 From b0a2f23bb66fce362b70117efe7b4e967e891c14 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 19 Aug 2010 16:25:03 +0000 Subject: Add program to transmit samples from a file. --- host/examples/CMakeLists.txt | 5 ++ host/examples/tx_from_file.cpp | 123 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 128 insertions(+) create mode 100644 host/examples/tx_from_file.cpp diff --git a/host/examples/CMakeLists.txt b/host/examples/CMakeLists.txt index 70e74a9a8..cad01a7cc 100644 --- a/host/examples/CMakeLists.txt +++ b/host/examples/CMakeLists.txt @@ -31,10 +31,15 @@ TARGET_LINK_LIBRARIES(rx_to_file uhd) ADD_EXECUTABLE(tx_timed_samples tx_timed_samples.cpp) TARGET_LINK_LIBRARIES(tx_timed_samples uhd) +ADD_EXECUTABLE(tx_from_file tx_from_file.cpp) +TARGET_LINK_LIBRARIES(tx_from_file uhd) + INSTALL(TARGETS tx_continuous_samples benchmark_rx_rate rx_timed_samples tx_timed_samples + tx_from_file + rx_to_file RUNTIME DESTINATION ${PKG_DATA_DIR}/examples ) diff --git a/host/examples/tx_from_file.cpp b/host/examples/tx_from_file.cpp new file mode 100644 index 000000000..df6446c0c --- /dev/null +++ b/host/examples/tx_from_file.cpp @@ -0,0 +1,123 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include +#include +#include +#include +#include +#include +#include + +namespace po = boost::program_options; + +int UHD_SAFE_MAIN(int argc, char *argv[]){ + uhd::set_thread_priority_safe(); + + //variables to be set by po + std::string args; + time_t seconds_in_future; + size_t total_num_samps; + size_t samps_per_packet; + double tx_rate, freq; + float ampl; + + //setup the program options + po::options_description desc("Allowed options"); + desc.add_options() + ("help", "help message") + ("args", po::value(&args)->default_value(""), "simple uhd device address args") + ("secs", po::value(&seconds_in_future)->default_value(3), "number of seconds in the future to transmit") + ("nsamps", po::value(&total_num_samps)->default_value(1000), "total number of samples to transmit") + ("txrate", po::value(&tx_rate)->default_value(100e6/16), "rate of outgoing samples") + ("freq", po::value(&freq)->default_value(0), "rf center frequency in Hz") + ("ampl", po::value(&l)->default_value(float(0.3)), "amplitude of each sample") + ("dilv", "specify to disable inner-loop verbose") + ; + po::variables_map vm; + po::store(po::parse_command_line(argc, argv, desc), vm); + po::notify(vm); + + //print the help message + if (vm.count("help")){ + std::cout << boost::format("UHD TX Timed Samples %s") % desc << std::endl; + return ~0; + } + + bool verbose = vm.count("dilv") == 0; + + //create a usrp device + std::cout << std::endl; + std::cout << boost::format("Creating the usrp device with: %s...") % args << std::endl; + uhd::usrp::simple_usrp::sptr sdev = uhd::usrp::simple_usrp::make(args); + uhd::device::sptr dev = sdev->get_device(); + std::cout << boost::format("Using Device: %s") % sdev->get_pp_string() << std::endl; + + //set properties on the device + std::cout << boost::format("Setting TX Rate: %f Msps...") % (tx_rate/1e6) << std::endl; + sdev->set_tx_rate(tx_rate); + std::cout << boost::format("Actual TX Rate: %f Msps...") % (sdev->get_tx_rate()/1e6) << std::endl; + std::cout << boost::format("Setting device timestamp to 0...") << std::endl; + sdev->set_tx_freq(freq); + sdev->set_time_now(uhd::time_spec_t(0.0)); + + sdev->set_tx_gain(0); + + //allocate data to send + std::vector > buff; + uhd::tx_metadata_t md; + + std::cout << "Read data to send from file: in.dat" << std::endl; + std::ifstream infile("in.dat", std::ifstream::binary); + while (!infile.eof()) { + std::complex c; + infile.read((char *)&c, sizeof(std::complex)); + if (!((c.real() == 0) && (c.imag() == 0))) { + buff.push_back(c); +//std::cout << "C = " << c << std::endl; + } + } + samps_per_packet = buff.size(); + infile.close(); + std::cout << "Number of samples in file: " << samps_per_packet << std::endl; + + //send the data in multiple packets + size_t num_packets = (total_num_samps+samps_per_packet-1)/samps_per_packet; + for (size_t i = 0; i < num_packets; i++){ + //setup the metadata flags and time spec + md.start_of_burst = true; //always SOB (good for continuous streaming) + md.end_of_burst = (i == num_packets-1); //only last packet has EOB + md.has_time_spec = (i == 0); //only first packet has time + md.time_spec = uhd::time_spec_t(seconds_in_future); + + size_t samps_to_send = std::min(total_num_samps - samps_per_packet*i, samps_per_packet); + + //send the entire packet (driver fragments internally) + size_t num_tx_samps = dev->send( + &buff.front(), samps_to_send, md, + uhd::io_type_t::COMPLEX_INT16, + uhd::device::SEND_MODE_FULL_BUFF + ); + if(verbose) std::cout << std::endl << boost::format("Sent %d samples") % num_tx_samps << std::endl; + } + + //finished + std::cout << std::endl << "Done!" << std::endl << std::endl; + + return 0; +} -- cgit v1.2.3 From 2ef82f57b815a9e53685617f1b779d4cbdf7fb31 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 19 Aug 2010 16:26:37 +0000 Subject: Add get setting to the rx_to_file program. --- host/examples/rx_to_file.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/host/examples/rx_to_file.cpp b/host/examples/rx_to_file.cpp index cb8c42acc..79d3e9d8b 100644 --- a/host/examples/rx_to_file.cpp +++ b/host/examples/rx_to_file.cpp @@ -74,6 +74,10 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ sdev->set_rx_freq(freq); sdev->set_time_now(uhd::time_spec_t(0.0)); + uhd::gain_range_t rx_gain = sdev->get_rx_gain_range(); + std::cout << "Setting RX Gain to: " << rx_gain.max << std::endl; + sdev->set_rx_gain(rx_gain.max); + sleep(1); std::cout << "LO Locked = " << sdev->get_rx_lo_locked() << std::endl; -- cgit v1.2.3 From f568f651c423fca8c9cf607655ea50ac4cfab524 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 19 Aug 2010 16:27:51 +0000 Subject: Add gain setting to tx_timed_samples program. --- host/examples/tx_timed_samples.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/host/examples/tx_timed_samples.cpp b/host/examples/tx_timed_samples.cpp index aa22d3465..fa5bf4b2b 100644 --- a/host/examples/tx_timed_samples.cpp +++ b/host/examples/tx_timed_samples.cpp @@ -75,6 +75,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ std::cout << boost::format("Setting device timestamp to 0...") << std::endl; sdev->set_tx_freq(freq); sdev->set_time_now(uhd::time_spec_t(0.0)); + sdev->set_tx_gain(0); //allocate data to send std::vector > buff(samps_per_packet, std::complex(ampl, ampl)); -- cgit v1.2.3 From 38722979512f0f6d57db9fd5e314b94cad1f188e Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 19 Aug 2010 20:34:56 +0000 Subject: Add gain command line parameter. --- host/examples/tx_timed_samples.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/host/examples/tx_timed_samples.cpp b/host/examples/tx_timed_samples.cpp index fa5bf4b2b..f7d7ea2ca 100644 --- a/host/examples/tx_timed_samples.cpp +++ b/host/examples/tx_timed_samples.cpp @@ -35,6 +35,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ size_t samps_per_packet; double tx_rate, freq; float ampl; + float tx_gain; //setup the program options po::options_description desc("Allowed options"); @@ -47,6 +48,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ ("txrate", po::value(&tx_rate)->default_value(100e6/16), "rate of outgoing samples") ("freq", po::value(&freq)->default_value(0), "rf center frequency in Hz") ("ampl", po::value(&l)->default_value(float(0.3)), "amplitude of each sample") + ("gain", po::value(&tx_gain)->default_value(float(0)), "TX Gain setting") ("dilv", "specify to disable inner-loop verbose") ; po::variables_map vm; @@ -75,7 +77,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ std::cout << boost::format("Setting device timestamp to 0...") << std::endl; sdev->set_tx_freq(freq); sdev->set_time_now(uhd::time_spec_t(0.0)); - sdev->set_tx_gain(0); + sdev->set_tx_gain(tx_gain); //allocate data to send std::vector > buff(samps_per_packet, std::complex(ampl, ampl)); -- cgit v1.2.3 From 6be4654073523d0666be552eee28445eb5f72297 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 19 Aug 2010 22:23:01 +0000 Subject: Change clock dividers so DBSRX board locks. --- host/lib/usrp/usrp_e/clock_ctrl.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/host/lib/usrp/usrp_e/clock_ctrl.cpp b/host/lib/usrp/usrp_e/clock_ctrl.cpp index 10f263e1d..9d4625305 100644 --- a/host/lib/usrp/usrp_e/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e/clock_ctrl.cpp @@ -46,7 +46,7 @@ static const size_t r_counter = 1; static const size_t a_counter = 0; static const size_t b_counter = 20 / ref_clock_doubler; static const size_t prescaler = 8; //set below with enum, set to 8 when input is under 2400 MHz -static const size_t vco_divider = 1; //set below with enum +static const size_t vco_divider = 5; //set below with enum static const size_t n_counter = prescaler * b_counter + a_counter; static const size_t vco_clock_rate = ref_clock_rate/r_counter * n_counter; //between 1400 and 1800 MHz @@ -85,7 +85,7 @@ public: _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA; _ad9522_regs.vco_calibration_now = 1; //calibrate it! - _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV1; + _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5; _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_VCO; //setup fpga master clock @@ -160,7 +160,7 @@ public: std::vector get_rx_dboard_clock_rates(void){ std::vector rates; - for(size_t div = 2/*vco div == 1*/; div <= 16+16; div++) + for(size_t div = 1; div <= 16+16; div++) rates.push_back(master_clock_rate/div); return rates; } -- cgit v1.2.3 From ee20f8eb4f64d3fd8c34ef9cde5d125bd5a14816 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 18 Aug 2010 23:59:58 +0000 Subject: Change TX PGA gain scaling to match gnuradio scaling --- host/lib/usrp/usrp_e/codec_ctrl.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/host/lib/usrp/usrp_e/codec_ctrl.cpp b/host/lib/usrp/usrp_e/codec_ctrl.cpp index 837219759..17262d358 100644 --- a/host/lib/usrp/usrp_e/codec_ctrl.cpp +++ b/host/lib/usrp/usrp_e/codec_ctrl.cpp @@ -134,8 +134,8 @@ usrp_e_codec_ctrl_impl::~usrp_e_codec_ctrl_impl(void){ * Codec Control Gain Control Methods **********************************************************************/ void usrp_e_codec_ctrl_impl::set_tx_pga_gain(float gain){ - int gain_word = int(63*(gain - tx_pga_gain_range.min)/(tx_pga_gain_range.max - tx_pga_gain_range.min)); - _ad9862_regs.tx_pga_gain = std::clip(gain_word, 0, 63); + int gain_word = int(255*(gain - tx_pga_gain_range.min)/(tx_pga_gain_range.max - tx_pga_gain_range.min)); + _ad9862_regs.tx_pga_gain = std::clip(gain_word, 0, 255); this->send_reg(16); } -- cgit v1.2.3 From 50a2ccee65677ed855c1798185d963fde1607324 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 19 Aug 2010 13:08:04 -0700 Subject: catch up with tx_policy --- usrp2/fifo/fifo36_mux.v | 2 +- usrp2/fifo/fifo_new_tb.vcd | 5506 --------------------------------------- usrp2/fifo/fifo_tb.v | 25 +- usrp2/top/Makefile.common | 2 +- usrp2/top/u2_rev3/u2_core_udp.v | 56 +- usrp2/vrt/Makefile.srcs | 2 + usrp2/vrt/gen_context_pkt.v | 72 + usrp2/vrt/vita_rx_framer.v | 2 +- usrp2/vrt/vita_tx_chain.v | 71 + usrp2/vrt/vita_tx_control.v | 115 +- usrp2/vrt/vita_tx_deframer.v | 30 +- 11 files changed, 311 insertions(+), 5572 deletions(-) delete mode 100644 usrp2/fifo/fifo_new_tb.vcd create mode 100644 usrp2/vrt/gen_context_pkt.v create mode 100644 usrp2/vrt/vita_tx_chain.v diff --git a/usrp2/fifo/fifo36_mux.v b/usrp2/fifo/fifo36_mux.v index 04ec5abe8..92bf13ff9 100644 --- a/usrp2/fifo/fifo36_mux.v +++ b/usrp2/fifo/fifo36_mux.v @@ -52,6 +52,6 @@ module fifo36_mux assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_i : 0; assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_i : 0; assign src_rdy_o = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0; - assign data_0 = (state==MUX_DATA0) ? data0_i : data1_i; + assign data_o = (state==MUX_DATA0) ? data0_i : data1_i; endmodule // fifo36_demux diff --git a/usrp2/fifo/fifo_new_tb.vcd b/usrp2/fifo/fifo_new_tb.vcd deleted file mode 100644 index 796889e7d..000000000 --- a/usrp2/fifo/fifo_new_tb.vcd +++ /dev/null @@ -1,5506 +0,0 @@ -$date - Thu Mar 19 17:21:11 2009 -$end -$version - Icarus Verilog -$end -$timescale - 1ps -$end -$scope module fifo_new_tb $end -$var wire 1 ! dst_rdy_f36i $end -$var wire 36 " f36_in [35:0] $end -$var wire 36 # i1 [35:0] $end -$var wire 1 $ i1_dr $end -$var wire 1 % i1_sr $end -$var wire 19 & i2 [18:0] $end -$var wire 1 ' i2_dr $end -$var wire 1 ( i2_sr $end -$var wire 19 ) i3 [18:0] $end -$var wire 1 * i3_dr $end -$var wire 1 + i3_sr $end -$var wire 36 , i4 [35:0] $end -$var wire 1 - i4_sr $end -$var wire 8 . ll_data [7:0] $end -$var wire 1 / ll_dst_rdy_n $end -$var wire 1 0 ll_eof_n $end -$var wire 1 1 ll_sof_n $end -$var wire 1 2 ll_src_rdy_n $end -$var reg 1 3 clear $end -$var reg 1 4 clk $end -$var reg 16 5 count [15:0] $end -$var reg 1 6 dst_rdy_f36o $end -$var reg 32 7 f36_data [31:0] $end -$var reg 1 8 f36_eof $end -$var reg 2 9 f36_occ [1:0] $end -$var reg 1 : f36_sof $end -$var reg 1 ; i4_dr $end -$var reg 1 < rst $end -$var reg 1 = src_rdy_f36i $end -$scope module fifo_short1 $end -$var wire 1 > clear $end -$var wire 1 ? clk $end -$var wire 36 @ datain [35:0] $end -$var wire 36 A dataout [35:0] $end -$var wire 1 $ dst_rdy_i $end -$var wire 1 ! dst_rdy_o $end -$var wire 1 B read $end -$var wire 1 C reset $end -$var wire 1 D src_rdy_i $end -$var wire 1 % src_rdy_o $end -$var wire 1 E write $end -$var reg 4 F a [3:0] $end -$var reg 1 G empty $end -$var reg 1 H full $end -$var reg 5 I occupied [4:0] $end -$var reg 5 J space [4:0] $end -$scope begin gen_srl16[0] $end -$scope module srl16e $end -$var wire 1 K A0 $end -$var wire 1 L A1 $end -$var wire 1 M A2 $end -$var wire 1 N A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 O D $end -$var wire 1 P Q $end -$var reg 16 Q data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[1] $end -$scope module srl16e $end -$var wire 1 R A0 $end -$var wire 1 S A1 $end -$var wire 1 T A2 $end -$var wire 1 U A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 V D $end -$var wire 1 W Q $end -$var reg 16 X data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[2] $end -$scope module srl16e $end -$var wire 1 Y A0 $end -$var wire 1 Z A1 $end -$var wire 1 [ A2 $end -$var wire 1 \ A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 ] D $end -$var wire 1 ^ Q $end -$var reg 16 _ data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[3] $end -$scope module srl16e $end -$var wire 1 ` A0 $end -$var wire 1 a A1 $end -$var wire 1 b A2 $end -$var wire 1 c A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 d D $end -$var wire 1 e Q $end -$var reg 16 f data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[4] $end -$scope module srl16e $end -$var wire 1 g A0 $end -$var wire 1 h A1 $end -$var wire 1 i A2 $end -$var wire 1 j A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 k D $end -$var wire 1 l Q $end -$var reg 16 m data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[5] $end -$scope module srl16e $end -$var wire 1 n A0 $end -$var wire 1 o A1 $end -$var wire 1 p A2 $end -$var wire 1 q A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 r D $end -$var wire 1 s Q $end -$var reg 16 t data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[6] $end -$scope module srl16e $end -$var wire 1 u A0 $end -$var wire 1 v A1 $end -$var wire 1 w A2 $end -$var wire 1 x A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 y D $end -$var wire 1 z Q $end -$var reg 16 { data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[7] $end -$scope module srl16e $end -$var wire 1 | A0 $end -$var wire 1 } A1 $end -$var wire 1 ~ A2 $end -$var wire 1 !" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 "" D $end -$var wire 1 #" Q $end -$var reg 16 $" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[8] $end -$scope module srl16e $end -$var wire 1 %" A0 $end -$var wire 1 &" A1 $end -$var wire 1 '" A2 $end -$var wire 1 (" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 )" D $end -$var wire 1 *" Q $end -$var reg 16 +" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[9] $end -$scope module srl16e $end -$var wire 1 ," A0 $end -$var wire 1 -" A1 $end -$var wire 1 ." A2 $end -$var wire 1 /" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 0" D $end -$var wire 1 1" Q $end -$var reg 16 2" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[10] $end -$scope module srl16e $end -$var wire 1 3" A0 $end -$var wire 1 4" A1 $end -$var wire 1 5" A2 $end -$var wire 1 6" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 7" D $end -$var wire 1 8" Q $end -$var reg 16 9" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[11] $end -$scope module srl16e $end -$var wire 1 :" A0 $end -$var wire 1 ;" A1 $end -$var wire 1 <" A2 $end -$var wire 1 =" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 >" D $end -$var wire 1 ?" Q $end -$var reg 16 @" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[12] $end -$scope module srl16e $end -$var wire 1 A" A0 $end -$var wire 1 B" A1 $end -$var wire 1 C" A2 $end -$var wire 1 D" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 E" D $end -$var wire 1 F" Q $end -$var reg 16 G" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[13] $end -$scope module srl16e $end -$var wire 1 H" A0 $end -$var wire 1 I" A1 $end -$var wire 1 J" A2 $end -$var wire 1 K" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 L" D $end -$var wire 1 M" Q $end -$var reg 16 N" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[14] $end -$scope module srl16e $end -$var wire 1 O" A0 $end -$var wire 1 P" A1 $end -$var wire 1 Q" A2 $end -$var wire 1 R" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 S" D $end -$var wire 1 T" Q $end -$var reg 16 U" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[15] $end -$scope module srl16e $end -$var wire 1 V" A0 $end -$var wire 1 W" A1 $end -$var wire 1 X" A2 $end -$var wire 1 Y" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 Z" D $end -$var wire 1 [" Q $end -$var reg 16 \" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[16] $end -$scope module srl16e $end -$var wire 1 ]" A0 $end -$var wire 1 ^" A1 $end -$var wire 1 _" A2 $end -$var wire 1 `" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 a" D $end -$var wire 1 b" Q $end -$var reg 16 c" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[17] $end -$scope module srl16e $end -$var wire 1 d" A0 $end -$var wire 1 e" A1 $end -$var wire 1 f" A2 $end -$var wire 1 g" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 h" D $end -$var wire 1 i" Q $end -$var reg 16 j" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[18] $end -$scope module srl16e $end -$var wire 1 k" A0 $end -$var wire 1 l" A1 $end -$var wire 1 m" A2 $end -$var wire 1 n" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 o" D $end -$var wire 1 p" Q $end -$var reg 16 q" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[19] $end -$scope module srl16e $end -$var wire 1 r" A0 $end -$var wire 1 s" A1 $end -$var wire 1 t" A2 $end -$var wire 1 u" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 v" D $end -$var wire 1 w" Q $end -$var reg 16 x" data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[20] $end -$scope module srl16e $end -$var wire 1 y" A0 $end -$var wire 1 z" A1 $end -$var wire 1 {" A2 $end -$var wire 1 |" A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 }" D $end -$var wire 1 ~" Q $end -$var reg 16 !# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[21] $end -$scope module srl16e $end -$var wire 1 "# A0 $end -$var wire 1 ## A1 $end -$var wire 1 $# A2 $end -$var wire 1 %# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 &# D $end -$var wire 1 '# Q $end -$var reg 16 (# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[22] $end -$scope module srl16e $end -$var wire 1 )# A0 $end -$var wire 1 *# A1 $end -$var wire 1 +# A2 $end -$var wire 1 ,# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 -# D $end -$var wire 1 .# Q $end -$var reg 16 /# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[23] $end -$scope module srl16e $end -$var wire 1 0# A0 $end -$var wire 1 1# A1 $end -$var wire 1 2# A2 $end -$var wire 1 3# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 4# D $end -$var wire 1 5# Q $end -$var reg 16 6# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[24] $end -$scope module srl16e $end -$var wire 1 7# A0 $end -$var wire 1 8# A1 $end -$var wire 1 9# A2 $end -$var wire 1 :# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 ;# D $end -$var wire 1 <# Q $end -$var reg 16 =# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[25] $end -$scope module srl16e $end -$var wire 1 ># A0 $end -$var wire 1 ?# A1 $end -$var wire 1 @# A2 $end -$var wire 1 A# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 B# D $end -$var wire 1 C# Q $end -$var reg 16 D# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[26] $end -$scope module srl16e $end -$var wire 1 E# A0 $end -$var wire 1 F# A1 $end -$var wire 1 G# A2 $end -$var wire 1 H# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 I# D $end -$var wire 1 J# Q $end -$var reg 16 K# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[27] $end -$scope module srl16e $end -$var wire 1 L# A0 $end -$var wire 1 M# A1 $end -$var wire 1 N# A2 $end -$var wire 1 O# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 P# D $end -$var wire 1 Q# Q $end -$var reg 16 R# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[28] $end -$scope module srl16e $end -$var wire 1 S# A0 $end -$var wire 1 T# A1 $end -$var wire 1 U# A2 $end -$var wire 1 V# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 W# D $end -$var wire 1 X# Q $end -$var reg 16 Y# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[29] $end -$scope module srl16e $end -$var wire 1 Z# A0 $end -$var wire 1 [# A1 $end -$var wire 1 \# A2 $end -$var wire 1 ]# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 ^# D $end -$var wire 1 _# Q $end -$var reg 16 `# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[30] $end -$scope module srl16e $end -$var wire 1 a# A0 $end -$var wire 1 b# A1 $end -$var wire 1 c# A2 $end -$var wire 1 d# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 e# D $end -$var wire 1 f# Q $end -$var reg 16 g# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[31] $end -$scope module srl16e $end -$var wire 1 h# A0 $end -$var wire 1 i# A1 $end -$var wire 1 j# A2 $end -$var wire 1 k# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 l# D $end -$var wire 1 m# Q $end -$var reg 16 n# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[32] $end -$scope module srl16e $end -$var wire 1 o# A0 $end -$var wire 1 p# A1 $end -$var wire 1 q# A2 $end -$var wire 1 r# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 s# D $end -$var wire 1 t# Q $end -$var reg 16 u# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[33] $end -$scope module srl16e $end -$var wire 1 v# A0 $end -$var wire 1 w# A1 $end -$var wire 1 x# A2 $end -$var wire 1 y# A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 z# D $end -$var wire 1 {# Q $end -$var reg 16 |# data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[34] $end -$scope module srl16e $end -$var wire 1 }# A0 $end -$var wire 1 ~# A1 $end -$var wire 1 !$ A2 $end -$var wire 1 "$ A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 #$ D $end -$var wire 1 $$ Q $end -$var reg 16 %$ data [15:0] $end -$upscope $end -$upscope $end -$scope begin gen_srl16[35] $end -$scope module srl16e $end -$var wire 1 &$ A0 $end -$var wire 1 '$ A1 $end -$var wire 1 ($ A2 $end -$var wire 1 )$ A3 $end -$var wire 1 E CE $end -$var wire 1 ? CLK $end -$var wire 1 *$ D $end -$var wire 1 +$ Q $end -$var reg 16 ,$ data [15:0] $end -$upscope $end -$upscope $end -$upscope $end -$scope module fifo36_to_fifo19 $end -$var wire 1 > clear $end -$var wire 1 ? clk $end -$var wire 19 -$ f19_dataout [18:0] $end -$var wire 1 ' f19_dst_rdy_i $end -$var wire 1 ( f19_src_rdy_o $end -$var wire 1 .$ f19_xfer $end -$var wire 36 /$ f36_datain [35:0] $end -$var wire 1 $ f36_dst_rdy_o $end -$var wire 1 0$ f36_eof $end -$var wire 1 1$ f36_occ $end -$var wire 1 2$ f36_sof $end -$var wire 1 % f36_src_rdy_i $end -$var wire 1 3$ f36_xfer $end -$var wire 1 4$ half_line $end -$var wire 1 C reset $end -$var reg 1 5$ phase $end -$upscope $end -$scope module fifo19_to_ll8 $end -$var wire 1 6$ advance $end -$var wire 1 > clear $end -$var wire 1 ? clk $end -$var wire 19 7$ f19_data [18:0] $end -$var wire 1 ' f19_dst_rdy_o $end -$var wire 1 8$ f19_eof $end -$var wire 1 9$ f19_occ $end -$var wire 1 :$ f19_sof $end -$var wire 1 ( f19_src_rdy_i $end -$var wire 1 ;$ ll_dst_rdy $end -$var wire 1 / ll_dst_rdy_n $end -$var wire 1 <$ ll_eof $end -$var wire 1 0 ll_eof_n $end -$var wire 1 =$ ll_sof $end -$var wire 1 1 ll_sof_n $end -$var wire 1 >$ ll_src_rdy $end -$var wire 1 2 ll_src_rdy_n $end -$var wire 1 C reset $end -$var reg 8 ?$ ll_data [7:0] $end -$var reg 1 @$ state $end -$upscope $end -$scope module ll8_to_fifo19 $end -$var wire 1 > clear $end -$var wire 1 ? clk $end -$var wire 19 A$ f19_data [18:0] $end -$var wire 1 * f19_dst_rdy_i $end -$var wire 1 + f19_src_rdy_o $end -$var wire 8 B$ ll_data [7:0] $end -$var wire 1 C$ ll_dst_rdy $end -$var wire 1 / ll_dst_rdy_n $end -$var wire 1 D$ ll_eof $end -$var wire 1 0 ll_eof_n $end -$var wire 1 E$ ll_sof $end -$var wire 1 1 ll_sof_n $end -$var wire 1 F$ ll_src_rdy $end -$var wire 1 2 ll_src_rdy_n $end -$var wire 1 C reset $end -$var wire 1 G$ xfer_out $end -$var reg 8 H$ dat0 [7:0] $end -$var reg 8 I$ dat1 [7:0] $end -$var reg 1 J$ f19_eof $end -$var reg 1 K$ f19_occ $end -$var reg 1 L$ f19_sof $end -$var reg 2 M$ state [1:0] $end -$upscope $end -$scope module fifo19_to_fifo36 $end -$var wire 1 > clear $end -$var wire 1 ? clk $end -$var wire 19 N$ f19_datain [18:0] $end -$var wire 1 * f19_dst_rdy_o $end -$var wire 1 O$ f19_eof $end -$var wire 1 P$ f19_occ $end -$var wire 1 Q$ f19_sof $end -$var wire 1 + f19_src_rdy_i $end -$var wire 36 R$ f36_dataout [35:0] $end -$var wire 1 S$ f36_dst_rdy_i $end -$var wire 1 - f36_src_rdy_o $end -$var wire 1 C reset $end -$var wire 1 T$ xfer_out $end -$var reg 16 U$ dat0 [15:0] $end -$var reg 16 V$ dat1 [15:0] $end -$var reg 1 W$ f36_eof $end -$var reg 1 X$ f36_occ $end -$var reg 1 Y$ f36_sof $end -$var reg 2 Z$ state [1:0] $end -$upscope $end -$scope task PutPacketInFIFO36 $end -$var reg 32 [$ data_len [31:0] $end -$var reg 32 \$ data_start [31:0] $end -$upscope $end -$scope task ReadFromFIFO36 $end -$upscope $end -$upscope $end -$enddefinitions $end -#0 -$dumpvars -bx \$ -bx [$ -bx Z$ -xY$ -xX$ -xW$ -bx V$ -bx U$ -0T$ -0S$ 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a/usrp2/fifo/fifo_tb.v +++ b/usrp2/fifo/fifo_tb.v @@ -24,20 +24,39 @@ module fifo_new_tb(); wire i1_sr, i1_dr; wire i2_sr, i2_dr; wire i3_sr, i3_dr; + wire i7_sr, i7_dr; + reg i4_dr = 0; wire i4_sr; - wire [35:0] i1, i4; + wire [35:0] i1, i4, i7; wire [18:0] i2, i3; wire [7:0] ll_data; wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n; + wire [35:0] err_dat; + wire err_src_rdy, err_dst_rdy; + + reg trigger = 0; + initial #10000 trigger = 1; fifo_short #(.WIDTH(36)) fifo_short1 (.clk(clk),.reset(rst),.clear(clear), .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i), - .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) ); + .dataout(i7),.src_rdy_o(i7_sr),.dst_rdy_i(i7_dr) ); + gen_context_pkt #(.PROT_ENG_FLAGS(1)) gcp + (.clk(clk),.reset(rst),.clear(clear), + .trigger(trigger), .sent(), + .streamid(32'hDEAD_F00D), .vita_time(64'h01234567_89ABCDEF), .message(32'hBEEF_2940), + .data_o(err_dat), .src_rdy_o(err_src_rdy), .dst_rdy_i(err_dst_rdy)); + + fifo36_mux #(.prio(0)) fifo36_mux + (.clk(clk), .reset(rst), .clear(clear), + .data0_i(i7), .src0_rdy_i(i7_sr), .dst0_rdy_o(i7_dr), + .data1_i(err_dat), .src1_rdy_i(err_src_rdy), .dst1_rdy_o(err_dst_rdy), + .data_o(i1), .src_rdy_o(i1_sr), .dst_rdy_i(i1_dr)); + fifo36_to_fifo19 fifo36_to_fifo19 (.clk(clk),.reset(rst),.clear(clear), .f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr), @@ -59,7 +78,7 @@ module fifo_new_tb(); (.clk(clk),.reset(rst),.clear(clear), .f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr), .f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) ); - + task ReadFromFIFO36; begin $display("Read from FIFO36"); diff --git a/usrp2/top/Makefile.common b/usrp2/top/Makefile.common index d0435fa1e..4da64ac28 100644 --- a/usrp2/top/Makefile.common +++ b/usrp2/top/Makefile.common @@ -47,7 +47,7 @@ $(ISE_FILE): $$(SOURCES) $$(MAKEFILE_LIST) @echo $@ $(ISE_HELPER) "" -$(BIN_FILE): $(ISE_FILE) +$(BIN_FILE): $(ISE_FILE) $$(SOURCES) $$(MAKEFILE_LIST) @echo $@ $(ISE_HELPER) "Generate Programming File" touch $@ diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index b034791a7..124930c23 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -423,7 +423,10 @@ module u2_core cycle_count <= 0; else cycle_count <= cycle_count + 1; - + + //compatibility number -> increment when the fpga has been sufficiently altered + localparam compat_num = 32'd1; + wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), @@ -431,7 +434,7 @@ module u2_core .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count) + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(status_enc),.word15(cycle_count) ); // ///////////////////////////////////////////////////////////////////////// @@ -466,11 +469,20 @@ module u2_core .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy), .debug(debug_udp) ); + wire [35:0] tx_err_data, udp1_tx_data; + wire tx_err_src_rdy, tx_err_dst_rdy, udp1_tx_src_rdy, udp1_tx_dst_rdy; + fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), - .dataout(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); + .dataout(udp1_tx_data), .src_rdy_o(udp1_tx_src_rdy), .dst_rdy_i(udp1_tx_dst_rdy)); + fifo36_mux #(.prio(0)) mux_err_stream + (.clk(dsp_clk), .reset(dsp_reset), .clear(0), + .data0_i(udp1_tx_data), .src0_rdy_i(udp1_tx_src_rdy), .dst0_rdy_o(udp1_tx_dst_rdy), + .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), + .data_o(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); + fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy), @@ -639,40 +651,26 @@ module u2_core // DSP TX wire [35:0] tx_data; - wire [99:0] tx1_data; - wire tx_src_rdy, tx_dst_rdy, tx1_src_rdy, tx1_dst_rdy; - - wire [31:0] debug_vtc, debug_vtd, debug_vt; + wire tx_src_rdy, tx_dst_rdy; + wire [31:0] debug_vt; fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i), .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) ); - vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), - .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), - .debug(debug_vtd) ); - - vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .vita_time(vita_time),.underrun(underrun), - .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .debug(debug_vtc) ); - - assign debug_vt = debug_vtc | debug_vtd; - - dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx - (.clk(dsp_clk),.rst(dsp_rst), + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(1), .PROT_ENG_FLAGS(1)) + vita_tx_chain + (.clk(dsp_clk), .reset(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), .dac_a(dac_a),.dac_b(dac_b), - .debug(debug_tx_dsp) ); - + .underrun(underrun), .run(run_tx), + .debug(debug_vt)); + assign dsp_rst = wb_rst; // /////////////////////////////////////////////////////////////////////////////////// diff --git a/usrp2/vrt/Makefile.srcs b/usrp2/vrt/Makefile.srcs index 07c62224b..dc4bd8c96 100644 --- a/usrp2/vrt/Makefile.srcs +++ b/usrp2/vrt/Makefile.srcs @@ -10,4 +10,6 @@ vita_rx_control.v \ vita_rx_framer.v \ vita_tx_control.v \ vita_tx_deframer.v \ +vita_tx_chain.v \ +gen_context_pkt.v \ )) diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v new file mode 100644 index 000000000..780a027ba --- /dev/null +++ b/usrp2/vrt/gen_context_pkt.v @@ -0,0 +1,72 @@ + + +module gen_context_pkt + #(parameter PROT_ENG_FLAGS=1) + (input clk, input reset, input clear, + input trigger, output sent, + input [31:0] streamid, + input [63:0] vita_time, + input [31:0] message, + output [35:0] data_o, output src_rdy_o, input dst_rdy_i); + + localparam CTXT_IDLE = 0; + localparam CTXT_PROT_ENG = 1; + localparam CTXT_HEADER = 2; + localparam CTXT_STREAMID = 3; + localparam CTXT_SECS = 4; + localparam CTXT_TICS = 5; + localparam CTXT_TICS2 = 6; + localparam CTXT_MESSAGE = 7; + localparam CTXT_DONE = 8; + + reg [33:0] data_int; + wire src_rdy_int, dst_rdy_int; + wire [3:0] seqno = 0; + reg [3:0] ctxt_state; + reg [63:0] err_time; + + always @(posedge clk) + if(reset | clear) + ctxt_state <= CTXT_IDLE; + else + case(ctxt_state) + CTXT_IDLE : + if(trigger) + begin + err_time <= vita_time; + if(PROT_ENG_FLAGS) + ctxt_state <= CTXT_PROT_ENG; + else + ctxt_state <= CTXT_HEADER; + end + + CTXT_DONE : + if(~trigger) + ctxt_state <= CTXT_IDLE; + + default : + if(dst_rdy_int) + ctxt_state <= ctxt_state + 1; + endcase // case (ctxt_state) + + assign src_rdy_int = ~( (ctxt_state == CTXT_IDLE) | (ctxt_state == CTXT_DONE) ); + + always @* + case(ctxt_state) + CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd24 }; + CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd6 }; + CTXT_STREAMID : data_int <= { 2'b00, streamid }; + CTXT_SECS : data_int <= { 2'b00, err_time[63:32] }; + CTXT_TICS : data_int <= { 2'b00, 32'd0 }; + CTXT_TICS2 : data_int <= { 2'b00, err_time[31:0] }; + CTXT_MESSAGE : data_int <= { 2'b10, message }; + default : data_int <= {2'b00, 32'b00}; + endcase // case (ctxt_state) + + fifo_short #(.WIDTH(34)) ctxt_fifo + (.clk(clk), .reset(reset), .clear(clear), + .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), + .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); + assign data_o[35:34] = 2'b00; + +endmodule // gen_context_pkt diff --git a/usrp2/vrt/vita_rx_framer.v b/usrp2/vrt/vita_rx_framer.v index fd82263d0..235817941 100644 --- a/usrp2/vrt/vita_rx_framer.v +++ b/usrp2/vrt/vita_rx_framer.v @@ -128,7 +128,7 @@ module vita_rx_framer VITA_ERR_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]}; VITA_ERR_TICS : pkt_fifo_line <= {2'b00,32'd0}; VITA_ERR_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]}; - VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b11,28'd0,flags_fifo_o}; + VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b10,28'd0,flags_fifo_o}; //VITA_ERR_TRAILER : pkt_fifo_line <= {2'b11,vita_trailer}; default : pkt_fifo_line <= 34'h0_FFFF_FFFF; diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v new file mode 100644 index 000000000..662cdca62 --- /dev/null +++ b/usrp2/vrt/vita_tx_chain.v @@ -0,0 +1,71 @@ + +module vita_tx_chain + #(parameter BASE_CTRL=0, + parameter BASE_DSP=0, + parameter REPORT_ERROR=0, + parameter PROT_ENG_FLAGS=0) + (input clk, input reset, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + input [63:0] vita_time, + input [35:0] tx_data_i, input tx_src_rdy_i, output tx_dst_rdy_o, + output [35:0] err_data_o, output err_src_rdy_o, input err_dst_rdy_i, + output [15:0] dac_a, output [15:0] dac_b, + output underrun, output run, + output [31:0] debug); + + localparam MAXCHAN = 1; + localparam FIFOWIDTH = 5+64+16+(32*MAXCHAN); + + wire [FIFOWIDTH-1:0] tx1_data; + wire tx1_src_rdy, tx1_dst_rdy; + wire clear_vita; + wire [31:0] sample_tx; + wire [31:0] streamid, message; + wire trigger, sent; + wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp; + + wire error; + wire [31:0] error_code; + wire clear_seqnum; + + assign underrun = error; + assign message = error_code; + + setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(streamid),.changed(clear_seqnum)); + + vita_tx_deframer #(.BASE(BASE_CTRL), .MAXCHAN(MAXCHAN)) vita_tx_deframer + (.clk(clk), .reset(reset), .clear(clear_vita), .clear_seqnum(clear_seqnum), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o), + .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), + .debug(debug_vtd) ); + + vita_tx_control #(.BASE(BASE_CTRL), .WIDTH(32*MAXCHAN)) vita_tx_control + (.clk(clk), .reset(reset), .clear(clear_vita), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time),.error(error),.error_code(error_code), + .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), + .sample(sample_tx), .run(run), .strobe(strobe_tx), + .debug(debug_vtc) ); + + dsp_core_tx #(.BASE(BASE_DSP)) dsp_core_tx + (.clk(clk),.rst(reset), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .sample(sample_tx), .run(run), .strobe(strobe_tx), + .dac_a(dac_a),.dac_b(dac_b), + .debug(debug_tx_dsp) ); + + generate + if(REPORT_ERROR==1) + gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt + (.clk(clk), .reset(reset), .clear(clear_vita), + .trigger(error), .sent(), + .streamid(streamid), .vita_time(vita_time), .message(message), + .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i)); + endgenerate + + assign debug = debug_vtc | debug_vtd; + +endmodule // vita_tx_chain diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index bffc64e52..d0516bec8 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -6,10 +6,11 @@ module vita_tx_control input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, - output underrun, + output error, + output reg [31:0] error_code, // From vita_tx_deframer - input [4+64+WIDTH-1:0] sample_fifo_i, + input [5+64+16+WIDTH-1:0] sample_fifo_i, input sample_fifo_src_rdy_i, output sample_fifo_dst_rdy_o, @@ -20,14 +21,17 @@ module vita_tx_control output [31:0] debug ); - - assign sample = sample_fifo_i[4+64+WIDTH-1:4+64]; + + assign sample = sample_fifo_i[5+64+16+WIDTH-1:5+64+16]; wire [63:0] send_time = sample_fifo_i[63:0]; - wire eop = sample_fifo_i[64]; - wire eob = sample_fifo_i[65]; - wire sob = sample_fifo_i[66]; - wire send_at = sample_fifo_i[67]; + wire [15:0] seqnum = sample_fifo_i[79:64]; + wire eop = sample_fifo_i[80]; + wire eob = sample_fifo_i[81]; + wire sob = sample_fifo_i[82]; + wire send_at = sample_fifo_i[83]; + wire seqnum_err = sample_fifo_i[84]; + wire now, early, late, too_early; // FIXME ignore too_early for now for timing reasons @@ -40,8 +44,15 @@ module vita_tx_control localparam IBS_IDLE = 0; localparam IBS_RUN = 1; // FIXME do we need this? localparam IBS_CONT_BURST = 2; - localparam IBS_UNDERRUN = 3; - localparam IBS_UNDERRUN_DONE = 4; + localparam IBS_ERROR = 3; + localparam IBS_ERROR_DONE = 4; + localparam IBS_ERROR_WAIT = 5; + + wire [31:0] CODE_UNDERRUN = {seqnum,16'd2}; + wire [31:0] CODE_SEQ_ERROR = {seqnum,16'd4}; + wire [31:0] CODE_TIME_ERROR = {seqnum,16'd8}; + wire [31:0] CODE_UNDERRUN_MIDPKT = {seqnum,16'd16}; + wire [31:0] CODE_SEQ_ERROR_MIDBURST = {seqnum,16'd32}; reg [2:0] ibs_state; @@ -50,22 +61,49 @@ module vita_tx_control (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(clear_state)); + wire [31:0] error_policy; + setting_reg #(.my_addr(BASE+3)) sr_error_policy + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(error_policy),.changed()); + + wire policy_wait = error_policy[0]; + wire policy_next_packet = error_policy[1]; + wire policy_next_burst = error_policy[2]; + reg send_error; + always @(posedge clk) if(reset | clear_state) - ibs_state <= 0; + begin + ibs_state <= IBS_IDLE; + send_error <= 0; + end else case(ibs_state) IBS_IDLE : if(sample_fifo_src_rdy_i) - if(~send_at | now) + if(seqnum_err) + begin + ibs_state <= IBS_ERROR; + error_code <= CODE_SEQ_ERROR; + send_error <= 1; + end + else if(~send_at | now) ibs_state <= IBS_RUN; else if(late | too_early) - ibs_state <= IBS_UNDERRUN; + begin + ibs_state <= IBS_ERROR; + error_code <= CODE_TIME_ERROR; + send_error <= 1; + end IBS_RUN : if(strobe) if(~sample_fifo_src_rdy_i) - ibs_state <= IBS_UNDERRUN; + begin + ibs_state <= IBS_ERROR; + error_code <= CODE_UNDERRUN_MIDPKT; + send_error <= 1; + end else if(eop) if(eob) ibs_state <= IBS_IDLE; @@ -74,24 +112,53 @@ module vita_tx_control IBS_CONT_BURST : if(strobe) - ibs_state <= IBS_UNDERRUN_DONE; + begin + if(policy_next_packet) + ibs_state <= IBS_ERROR_DONE; + else if(policy_wait) + ibs_state <= IBS_ERROR_WAIT; + else + ibs_state <= IBS_ERROR; + error_code <= CODE_UNDERRUN; + send_error <= 1; + end else if(sample_fifo_src_rdy_i) - ibs_state <= IBS_RUN; + if(seqnum_err) + begin + ibs_state <= IBS_ERROR; + error_code <= CODE_SEQ_ERROR_MIDBURST; + send_error <= 1; + end + else + ibs_state <= IBS_RUN; - IBS_UNDERRUN : - if(sample_fifo_src_rdy_i & eop) - ibs_state <= IBS_UNDERRUN_DONE; + IBS_ERROR : + begin + send_error <= 0; + if(sample_fifo_src_rdy_i & eop) + if(policy_next_packet | (policy_next_burst & eob)) + ibs_state <= IBS_IDLE; + else if(policy_wait) + ibs_state <= IBS_ERROR_WAIT; + end - IBS_UNDERRUN_DONE : - ; + IBS_ERROR_DONE : + begin + send_error <= 0; + ibs_state <= IBS_IDLE; + end + + IBS_ERROR_WAIT : + send_error <= 0; endcase // case (ibs_state) - assign sample_fifo_dst_rdy_o = (ibs_state == IBS_UNDERRUN) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout + assign sample_fifo_dst_rdy_o = (ibs_state == IBS_ERROR) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST); - assign underrun = (ibs_state == IBS_UNDERRUN_DONE); + //assign error = (ibs_state == IBS_ERROR_DONE); + assign error = send_error; assign debug = { { now,early,late,too_early,eop,eob,sob,send_at }, - { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, underrun, ibs_state[2:0] }, + { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, error, ibs_state[2:0] }, { 8'b0 }, { 8'b0 } }; diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v index 3b95f5902..f9cd7d00d 100644 --- a/usrp2/vrt/vita_tx_deframer.v +++ b/usrp2/vrt/vita_tx_deframer.v @@ -2,7 +2,7 @@ module vita_tx_deframer #(parameter BASE=0, parameter MAXCHAN=1) - (input clk, input reset, input clear, + (input clk, input reset, input clear, input clear_seqnum, input set_stb, input [7:0] set_addr, input [31:0] set_data, // To FIFO interface of Buffer Pool @@ -10,7 +10,7 @@ module vita_tx_deframer input src_rdy_i, output dst_rdy_o, - output [4+64+(32*MAXCHAN)-1:0] sample_fifo_o, + output [5+64+16+(32*MAXCHAN)-1:0] sample_fifo_o, output sample_fifo_src_rdy_o, input sample_fifo_dst_rdy_i, @@ -21,6 +21,8 @@ module vita_tx_deframer output [31:0] debug ); + localparam FIFOWIDTH = 5+64+16+(32*MAXCHAN); + wire [1:0] numchan; setting_reg #(.my_addr(BASE), .at_reset(0), .width(2)) sr_numchan (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), @@ -36,14 +38,18 @@ module vita_tx_deframer assign is_sob = data_i[25]; assign is_eob = data_i[24]; wire eof = data_i[33]; - reg has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg; reg has_trailer_reg, is_sob_reg, is_eob_reg; - + reg [15:0] pkt_len; reg [1:0] vector_phase; wire line_done; + reg seqnum_err; + reg [3:0] seqnum_reg; + wire [3:0] seqnum = data_i[19:16]; + wire [3:0] next_seqnum = seqnum_reg + 4'd1; + // Output FIFO for packetized data localparam VITA_HEADER = 0; localparam VITA_STREAMID = 1; @@ -61,6 +67,13 @@ module vita_tx_deframer wire eop = eof | (pkt_len==hdr_len); // FIXME would ignoring eof allow larger VITA packets? wire fifo_space; + + always @(posedge clk) + if(reset | clear_seqnum) + seqnum_reg <= 4'hF; + else + if((vita_state==VITA_HEADER) & src_rdy_i) + seqnum_reg <= seqnum; always @(posedge clk) if(reset | clear) @@ -68,6 +81,7 @@ module vita_tx_deframer vita_state <= VITA_HEADER; {has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg, has_trailer_reg, is_sob_reg, is_eob_reg} <= 0; + seqnum_err <= 0; end else if((vita_state == VITA_STORE) & fifo_space) @@ -99,6 +113,7 @@ module vita_tx_deframer vita_state <= VITA_TICS; else vita_state <= VITA_PAYLOAD; + seqnum_err <= ~(seqnum == next_seqnum); end // case: VITA_HEADER VITA_STREAMID : if(has_classid_reg) @@ -145,7 +160,7 @@ module vita_tx_deframer assign line_done = (vector_phase == numchan); - wire [4+64+32*MAXCHAN-1:0] fifo_i; + wire [FIFOWIDTH-1:0] fifo_i; reg [63:0] send_time; reg [31:0] sample_a, sample_b, sample_c, sample_d; @@ -169,13 +184,14 @@ module vita_tx_deframer endcase // case (vector_phase) wire store = (vita_state == VITA_STORE); - fifo_short #(.WIDTH(4+64+32*MAXCHAN)) short_tx_q + fifo_short #(.WIDTH(FIFOWIDTH)) short_tx_q (.clk(clk), .reset(reset), .clear(clear), .datain(fifo_i), .src_rdy_i(store), .dst_rdy_o(fifo_space), .dataout(sample_fifo_o), .src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i) ); // sob, eob, has_secs (send_at) ignored on all lines except first - assign fifo_i = {sample_d,sample_c,sample_b,sample_a,has_secs_reg,is_sob_reg,is_eob_reg,eop,send_time}; + assign fifo_i = {sample_d,sample_c,sample_b,sample_a,seqnum_err,has_secs_reg,is_sob_reg,is_eob_reg,eop, + 12'd0,seqnum_reg,send_time}; assign dst_rdy_o = ~(vita_state == VITA_PAYLOAD) & ~((vita_state==VITA_STORE)& ~fifo_space) ; -- cgit v1.2.3 From 7d602e283bc30669df6c155f1abe5196a272b9b4 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 19 Aug 2010 13:08:23 -0700 Subject: properly integrate the new tx chain --- usrp2/top/u1e/u1e_core.v | 58 ++++++++++++++++++++++-------------------------- 1 file changed, 27 insertions(+), 31 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 63488f549..33020ad5a 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -59,8 +59,9 @@ module u1e_core wire [31:0] debug_gpmc; - wire [35:0] tx_data, rx_data; - wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy; + wire [35:0] tx_data, rx_data, tx_err_data; + wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, + tx_err_src_rdy, tx_err_dst_rdy; reg [15:0] tx_frame_len; wire [15:0] rx_frame_len; wire [7:0] rate; @@ -109,7 +110,7 @@ module u1e_core assign tx_underrun = 0; assign rx_overrun = 0; - wire run_tx, run_rx, strobe_tx, strobe_rx, tx1_src_rdy, tx1_dst_rdy; + wire run_tx, run_rx, strobe_tx, strobe_rx; wire [31:0] debug_vtd, debug_vtc; `endif // LOOPBACK @@ -154,8 +155,9 @@ module u1e_core wire rx1_dst_rdy, rx1_src_rdy; wire [99:0] rx1_data; wire run_rx; - - + wire [35:0] vita_rx_data; + wire vita_rx_src_rdy, vita_rx_dst_rdy; + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx (.clk(wb_clk),.rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), @@ -175,41 +177,35 @@ module u1e_core (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy), - .data_o(rx_data), .dst_rdy_i(rx_dst_rdy), .src_rdy_o(rx_src_rdy), + .data_o(vita_rx_data), .dst_rdy_i(vita_rx_dst_rdy), .src_rdy_o(vita_rx_src_rdy), .fifo_occupied(), .fifo_full(), .fifo_empty(), .debug_rx(vrf_debug) ); - + + fifo36_mux #(.prio(0)) mux_err_stream + (.clk(dsp_clk), .reset(dsp_reset), .clear(0), + .data0_i(vita_rx_data), .src0_rdy_i(vita_rx_src_rdy), .dst0_rdy_o(vita_rx_dst_rdy), + .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), + .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + // /////////////////////////////////////////////////////////////////////////////////// // DSP TX - wire [99:0] tx1_data; - wire tx1_src_rdy, tx1_dst_rdy; wire [15:0] tx_i_int, tx_q_int; wire [31:0] debug_vtc, debug_vtd, debug_vt; wire run_tx; - vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer - (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), - .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), - .debug(debug_vtd) ); - - vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control - (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .vita_time(vita_time),.underrun(tx_underrun), - .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .debug(debug_vtc) ); - - dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx - (.clk(wb_clk),.rst(wb_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(1), .PROT_ENG_FLAGS(1)) + vita_tx_chain + (.clk(dsp_clk), .reset(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), .dac_a(tx_i_int),.dac_b(tx_q_int), - .debug(debug_tx_dsp) ); - + .underrun(underrun), .run(run_tx), + .debug(debug_vt)); + assign tx_i = tx_i_int[15:2]; assign tx_q = tx_q_int[15:2]; @@ -438,7 +434,7 @@ module u1e_core { EM_D } }; assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]}, - {tx1_src_rdy, tx1_dst_rdy, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; + {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; assign debug_gpio_1 = debug_vtd | debug_vtc; -- cgit v1.2.3 From 105efcdfc21f760e9615e9a3221ef6ae13b01f1c Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 23 Aug 2010 17:12:43 -0700 Subject: debug pins cleanup --- usrp2/top/u1e/u1e_core.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 33020ad5a..ff9a846b5 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -111,7 +111,6 @@ module u1e_core assign rx_overrun = 0; wire run_tx, run_rx, strobe_tx, strobe_rx; - wire [31:0] debug_vtd, debug_vtc; `endif // LOOPBACK `ifdef TIMED @@ -191,7 +190,7 @@ module u1e_core // DSP TX wire [15:0] tx_i_int, tx_q_int; - wire [31:0] debug_vtc, debug_vtd, debug_vt; + wire [31:0] debug_vt; wire run_tx; vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), @@ -429,6 +428,7 @@ module u1e_core // Debug circuitry assign debug_clk = { EM_CLK, clk_fpga }; + assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, rx_overrun, tx_underrun }, { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int }, { EM_D } }; @@ -436,7 +436,7 @@ module u1e_core assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]}, {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; - assign debug_gpio_1 = debug_vtd | debug_vtc; + assign debug_gpio_1 = debug_vt; /* assign debug_gpio_1 = { {rx_enable, rx_src_rdy, rx_dst_rdy, rx_src_rdy & ~rx_dst_rdy}, -- cgit v1.2.3 From 87a64f5979e712fd0fa30cf0676f3c395599ff69 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 23 Aug 2010 19:20:02 -0700 Subject: match the signal names in this design --- usrp2/top/u1e/u1e_core.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index ff9a846b5..eda4e463d 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -181,7 +181,7 @@ module u1e_core .debug_rx(vrf_debug) ); fifo36_mux #(.prio(0)) mux_err_stream - (.clk(dsp_clk), .reset(dsp_reset), .clear(0), + (.clk(wb_clk), .reset(wb_rst), .clear(0), .data0_i(vita_rx_data), .src0_rdy_i(vita_rx_src_rdy), .dst0_rdy_o(vita_rx_dst_rdy), .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); @@ -196,8 +196,8 @@ module u1e_core vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), .REPORT_ERROR(1), .PROT_ENG_FLAGS(1)) vita_tx_chain - (.clk(dsp_clk), .reset(dsp_rst), - .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + (.clk(wb_clk), .reset(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .vita_time(vita_time), .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), -- cgit v1.2.3 From d3501cda50407143db85f7ea5eb894c71ecd8aac Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 24 Aug 2010 18:11:46 +0000 Subject: usrp-e: added dboard iface set gpio debug call --- host/lib/usrp/usrp_e/dboard_iface.cpp | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/host/lib/usrp/usrp_e/dboard_iface.cpp b/host/lib/usrp/usrp_e/dboard_iface.cpp index c9efd0c9e..1bd177f60 100644 --- a/host/lib/usrp/usrp_e/dboard_iface.cpp +++ b/host/lib/usrp/usrp_e/dboard_iface.cpp @@ -67,6 +67,7 @@ public: void set_atr_reg(unit_t, atr_reg_t, boost::uint16_t); void set_gpio_ddr(unit_t, boost::uint16_t); void write_gpio(unit_t, boost::uint16_t); + void set_gpio_debug(unit_t, int); boost::uint16_t read_gpio(unit_t); void write_i2c(boost::uint8_t, const byte_vector_t &); @@ -193,6 +194,29 @@ void usrp_e_dboard_iface::set_atr_reg(unit_t unit, atr_reg_t atr, boost::uint16_ _iface->poke16(unit_to_atr_to_addr[unit][atr], value); } +void usrp_e_dboard_iface::set_gpio_debug(unit_t unit, int which){ + //set this unit to all outputs + this->set_gpio_ddr(unit, 0xffff); + + //calculate the debug selections + boost::uint32_t dbg_sels = 0x0; + int sel = (which == 0)? GPIO_SEL_DEBUG_0 : GPIO_SEL_DEBUG_1; + for(size_t i = 0; i < 16; i++) dbg_sels |= sel << i; + + //set the debug on and which debug selection + switch(unit){ + case UNIT_RX: + _iface->poke16(UE_REG_GPIO_RX_DBG, 0xffff); + _iface->poke16(UE_REG_GPIO_RX_SEL, dbg_sels); + return; + + case UNIT_TX: + _iface->poke16(UE_REG_GPIO_TX_DBG, 0xffff); + _iface->poke16(UE_REG_GPIO_TX_SEL, dbg_sels); + return; + } +} + /*********************************************************************** * SPI **********************************************************************/ -- cgit v1.2.3 From 743ea16da4eef07cf9956f4098fc4b959e689c00 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 24 Aug 2010 12:08:22 -0700 Subject: no need for protocol headers since we're not doing ethernet --- usrp2/top/u1e/u1e_core.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index eda4e463d..d7c4ff509 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -194,7 +194,7 @@ module u1e_core wire run_tx; vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), - .REPORT_ERROR(1), .PROT_ENG_FLAGS(1)) + .REPORT_ERROR(1), .PROT_ENG_FLAGS(0)) vita_tx_chain (.clk(wb_clk), .reset(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), -- cgit v1.2.3 From 65821027b8d41e9c736bc7e29a4fa1f84dc890ba Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 24 Aug 2010 19:26:15 +0000 Subject: usrp-e: fixed codec control gain calculation error, added tx policy registers, set to next packet --- host/lib/usrp/usrp_e/codec_ctrl.cpp | 18 +++++++++++------- host/lib/usrp/usrp_e/io_impl.cpp | 2 +- host/lib/usrp/usrp_e/mboard_impl.cpp | 4 ++++ host/lib/usrp/usrp_e/usrp_e_regs.hpp | 6 ++++++ 4 files changed, 22 insertions(+), 8 deletions(-) diff --git a/host/lib/usrp/usrp_e/codec_ctrl.cpp b/host/lib/usrp/usrp_e/codec_ctrl.cpp index 17262d358..a728d7e46 100644 --- a/host/lib/usrp/usrp_e/codec_ctrl.cpp +++ b/host/lib/usrp/usrp_e/codec_ctrl.cpp @@ -29,7 +29,7 @@ using namespace uhd; -static const bool codec_debug = true; +static const bool codec_debug = false; const gain_range_t usrp_e_codec_ctrl::tx_pga_gain_range(-20, 0, float(0.1)); const gain_range_t usrp_e_codec_ctrl::rx_pga_gain_range(0, 20, 1); @@ -133,19 +133,23 @@ usrp_e_codec_ctrl_impl::~usrp_e_codec_ctrl_impl(void){ /*********************************************************************** * Codec Control Gain Control Methods **********************************************************************/ +static const int mtpgw = 255; //maximum tx pga gain word + void usrp_e_codec_ctrl_impl::set_tx_pga_gain(float gain){ - int gain_word = int(255*(gain - tx_pga_gain_range.min)/(tx_pga_gain_range.max - tx_pga_gain_range.min)); - _ad9862_regs.tx_pga_gain = std::clip(gain_word, 0, 255); + int gain_word = int(mtpgw*(gain - tx_pga_gain_range.min)/(tx_pga_gain_range.max - tx_pga_gain_range.min)); + _ad9862_regs.tx_pga_gain = std::clip(gain_word, 0, mtpgw); this->send_reg(16); } float usrp_e_codec_ctrl_impl::get_tx_pga_gain(void){ - return (_ad9862_regs.tx_pga_gain*(tx_pga_gain_range.max - tx_pga_gain_range.min)/63) + tx_pga_gain_range.min; + return (_ad9862_regs.tx_pga_gain*(tx_pga_gain_range.max - tx_pga_gain_range.min)/mtpgw) + tx_pga_gain_range.min; } +static const int mrpgw = 0x14; //maximum rx pga gain word + void usrp_e_codec_ctrl_impl::set_rx_pga_gain(float gain, char which){ - int gain_word = int(0x14*(gain - rx_pga_gain_range.min)/(rx_pga_gain_range.max - rx_pga_gain_range.min)); - gain_word = std::clip(gain_word, 0, 0x14); + int gain_word = int(mrpgw*(gain - rx_pga_gain_range.min)/(rx_pga_gain_range.max - rx_pga_gain_range.min)); + gain_word = std::clip(gain_word, 0, mrpgw); switch(which){ case 'A': _ad9862_regs.rx_pga_a = gain_word; @@ -166,7 +170,7 @@ float usrp_e_codec_ctrl_impl::get_rx_pga_gain(char which){ case 'B': gain_word = _ad9862_regs.rx_pga_b; break; default: UHD_THROW_INVALID_CODE_PATH(); } - return (gain_word*(rx_pga_gain_range.max - rx_pga_gain_range.min)/0x14) + rx_pga_gain_range.min; + return (gain_word*(rx_pga_gain_range.max - rx_pga_gain_range.min)/mrpgw) + rx_pga_gain_range.min; } /*********************************************************************** diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index eaa45d60c..1bb67d9aa 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -33,7 +33,7 @@ using namespace uhd::usrp; * Constants **********************************************************************/ static const size_t MAX_BUFF_SIZE = 2048; -static const bool usrp_e_io_impl_verbose = true; +static const bool usrp_e_io_impl_verbose = false; /*********************************************************************** * Data Transport (phony zero-copy with read/write) diff --git a/host/lib/usrp/usrp_e/mboard_impl.cpp b/host/lib/usrp/usrp_e/mboard_impl.cpp index 3d4cef069..047db3f7c 100644 --- a/host/lib/usrp/usrp_e/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e/mboard_impl.cpp @@ -41,6 +41,10 @@ void usrp_e_impl::mboard_init(void){ _clock_config.pps_source = clock_config_t::PPS_SMA; //TODO poke the clock config regs + + //setup the tx policy + _iface->poke32(UE_REG_CTRL_TX_REPORT_SID, 1); + _iface->poke32(UE_REG_CTRL_TX_POLICY, UE_FLAG_CTRL_TX_POLICY_NEXT_PACKET); } /*********************************************************************** diff --git a/host/lib/usrp/usrp_e/usrp_e_regs.hpp b/host/lib/usrp/usrp_e/usrp_e_regs.hpp index 41cbfa1e2..a4f42093e 100644 --- a/host/lib/usrp/usrp_e/usrp_e_regs.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_regs.hpp @@ -151,6 +151,12 @@ //////////////////////////////////////////////// #define UE_REG_CTRL_TX_NCHANNELS UE_REG_SR_ADDR(24) #define UE_REG_CTRL_TX_CLEAR_UNDERRUN UE_REG_SR_ADDR(25) +#define UE_REG_CTRL_TX_REPORT_SID UE_REG_SR_ADDR(26) +#define UE_REG_CTRL_TX_POLICY UE_REG_SR_ADDR(27) + +#define UE_FLAG_CTRL_TX_POLICY_WAIT (0x1 << 0) +#define UE_FLAG_CTRL_TX_POLICY_NEXT_PACKET (0x1 << 1) +#define UE_FLAG_CTRL_TX_POLICY_NEXT_BURST (0x1 << 2) ///////////////////////////////////////////////// // VITA49 64 bit time (write only) -- cgit v1.2.3 From 924914beaac3dd3a2d9fe40c9067ad4f9147a4f6 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 25 Aug 2010 21:10:41 +0000 Subject: usrp-e: implemented tx policy and handling of async messages --- host/lib/usrp/usrp_e/io_impl.cpp | 129 +++++++++++++++++++++++++++++++---- host/lib/usrp/usrp_e/mboard_impl.cpp | 4 -- 2 files changed, 114 insertions(+), 19 deletions(-) diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index 1bb67d9aa..31ea4c6c0 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -18,6 +18,8 @@ #include "usrp_e_impl.hpp" #include "usrp_e_regs.hpp" #include +#include +#include #include "../../transport/vrt_packet_handler.hpp" #include #include //read, write @@ -28,12 +30,15 @@ using namespace uhd; using namespace uhd::usrp; +using namespace uhd::transport; /*********************************************************************** * Constants **********************************************************************/ static const size_t MAX_BUFF_SIZE = 2048; static const bool usrp_e_io_impl_verbose = false; +static const size_t tx_async_report_sid = 1; +static const int underflow_flags = async_metadata_t::EVENT_CODE_UNDERFLOW | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET; /*********************************************************************** * Data Transport (phony zero-copy with read/write) @@ -52,15 +57,15 @@ public: } size_t get_num_recv_frames(void) const{ - return 10; //FIXME no idea! + return 100; //FIXME no idea! + //this will be an important number when packet ring gets implemented } size_t get_num_send_frames(void) const{ - return 10; //FIXME no idea! + return 100; //FIXME no idea! + //this will be an important number when packet ring gets implemented } - size_t recv_timeout_ms; - private: int _fd; ssize_t send(const boost::asio::const_buffer &buff){ @@ -79,7 +84,7 @@ private: pollfd pfd; pfd.fd = _fd; pfd.events = POLLIN; - ssize_t poll_ret = poll(&pfd, 1, recv_timeout_ms); + ssize_t poll_ret = poll(&pfd, 1, 100/*ms*/); if (poll_ret <= 0){ if (usrp_e_io_impl_verbose) std::cerr << boost::format( "usrp-e io impl recv(): poll() returned non-positive value: %d\n" @@ -111,7 +116,11 @@ private: }; /*********************************************************************** - * IO Implementation Details + * io impl details (internal to this file) + * - pirate crew of 1 + * - bounded buffer + * - thread loop + * - vrt packet handler states **********************************************************************/ struct usrp_e_impl::io_impl{ //state management for the vrt packet handler code @@ -119,9 +128,88 @@ struct usrp_e_impl::io_impl{ vrt_packet_handler::send_state packet_handler_send_state; data_transport transport; bool continuous_streaming; - io_impl(int fd): packet_handler_recv_state(1), transport(fd){} + io_impl(int fd): + transport(fd), + recv_pirate_booty(recv_booty_type::make(transport.get_num_recv_frames())), + async_msg_fifo(bounded_buffer::make(100/*messages deep*/)) + { + /* NOP */ + } + + ~io_impl(void){ + recv_pirate_crew_raiding = false; + recv_pirate_crew.interrupt_all(); + recv_pirate_crew.join_all(); + } + + bool get_recv_buffs(vrt_packet_handler::managed_recv_buffs_t &buffs, size_t timeout_ms){ + UHD_ASSERT_THROW(buffs.size() == 1); + boost::this_thread::disable_interruption di; //disable because the wait can throw + return recv_pirate_booty->pop_with_timed_wait(buffs.front(), boost::posix_time::milliseconds(timeout_ms)); + } + + //a pirate's life is the life for me! + void recv_pirate_loop(); + typedef bounded_buffer recv_booty_type; + recv_booty_type::sptr recv_pirate_booty; + bounded_buffer::sptr async_msg_fifo; + boost::thread_group recv_pirate_crew; + bool recv_pirate_crew_raiding; }; +/*********************************************************************** + * Receive Pirate Loop + * - while raiding, loot for recv buffers + * - put booty into the alignment buffer + **********************************************************************/ +void usrp_e_impl::io_impl::recv_pirate_loop( + +){ + set_thread_priority_safe(); + recv_pirate_crew_raiding = true; + //size_t next_packet_seq = 0; + + while(recv_pirate_crew_raiding){ + managed_recv_buffer::sptr buff = this->transport.get_recv_buff(); + if (not buff.get()) continue; //ignore timeout/error buffers + + try{ + //extract the vrt header packet info + vrt::if_packet_info_t if_packet_info; + if_packet_info.num_packet_words32 = buff->size()/sizeof(boost::uint32_t); + const boost::uint32_t *vrt_hdr = buff->cast(); + vrt::if_hdr_unpack_le(vrt_hdr, if_packet_info); + + //handle a tx async report message + if (if_packet_info.sid == tx_async_report_sid and if_packet_info.packet_type != vrt::if_packet_info_t::PACKET_TYPE_DATA){ + + //fill in the async metadata + async_metadata_t metadata; + metadata.channel = 0; + metadata.has_time_spec = if_packet_info.has_tsi and if_packet_info.has_tsf; + metadata.time_spec = time_spec_t( + time_t(if_packet_info.tsi), size_t(if_packet_info.tsf), MASTER_CLOCK_RATE + ); + metadata.event_code = vrt_packet_handler::get_context_code(vrt_hdr, if_packet_info); + + //print the famous U, and push the metadata into the message queue + if (metadata.event_code & underflow_flags) std::cerr << "U" << std::flush; + async_msg_fifo->push_with_pop_on_full(metadata); + continue; + } + + }catch(const std::exception &e){ + std::cerr << "Error (usrp-e recv pirate loop): " << e.what() << std::endl; + } + + //usrp-e back-pressures on receive: push with wait + recv_pirate_booty->push_with_wait(buff); + } +} + +/*********************************************************************** + * Helper Functions + **********************************************************************/ void usrp_e_impl::io_init(void){ //setup rx data path _iface->poke32(UE_REG_CTRL_RX_NSAMPS_PER_PKT, get_max_recv_samps_per_packet()); @@ -136,7 +224,16 @@ void usrp_e_impl::io_init(void){ _iface->poke32(UE_REG_CTRL_RX_VRT_STREAM_ID, 0); _iface->poke32(UE_REG_CTRL_RX_VRT_TRAILER, 0); + //setup the tx policy + _iface->poke32(UE_REG_CTRL_TX_REPORT_SID, tx_async_report_sid); + _iface->poke32(UE_REG_CTRL_TX_POLICY, UE_FLAG_CTRL_TX_POLICY_NEXT_PACKET); + _io_impl = UHD_PIMPL_MAKE(io_impl, (_iface->get_file_descriptor())); + + //spawn a pirate, yarrr! + _io_impl->recv_pirate_crew.create_thread(boost::bind( + &usrp_e_impl::io_impl::recv_pirate_loop, _io_impl.get() + )); } void usrp_e_impl::issue_stream_cmd(const stream_cmd_t &stream_cmd){ @@ -217,9 +314,6 @@ size_t usrp_e_impl::recv( recv_otw_type.shift = 0; recv_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN; - //hand-off the timeout to the transport - _io_impl->transport.recv_timeout_ms = timeout_ms; - return vrt_packet_handler::recv( _io_impl->packet_handler_recv_state, //last state of the recv handler buffs, num_samps, //buffer to fill @@ -227,15 +321,20 @@ size_t usrp_e_impl::recv( io_type, recv_otw_type, //input and output types to convert MASTER_CLOCK_RATE, //master clock tick rate uhd::transport::vrt::if_hdr_unpack_le, - boost::bind(&get_recv_buffs, &_io_impl->transport, _1), + boost::bind(&usrp_e_impl::io_impl::get_recv_buffs, _io_impl.get(), _1, timeout_ms), boost::bind(&usrp_e_impl::handle_overrun, this, _1) ); } /*********************************************************************** - * Dummy Async Recv + * Async Recv **********************************************************************/ -bool usrp_e_impl::recv_async_msg(async_metadata_t &, size_t timeout_ms){ - boost::this_thread::sleep(boost::posix_time::milliseconds(timeout_ms)); - return false; +bool usrp_e_impl::recv_async_msg( + async_metadata_t &async_metadata, + size_t timeout_ms +){ + boost::this_thread::disable_interruption di; //disable because the wait can throw + return _io_impl->async_msg_fifo->pop_with_timed_wait( + async_metadata, boost::posix_time::milliseconds(timeout_ms) + ); } diff --git a/host/lib/usrp/usrp_e/mboard_impl.cpp b/host/lib/usrp/usrp_e/mboard_impl.cpp index 047db3f7c..3d4cef069 100644 --- a/host/lib/usrp/usrp_e/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e/mboard_impl.cpp @@ -41,10 +41,6 @@ void usrp_e_impl::mboard_init(void){ _clock_config.pps_source = clock_config_t::PPS_SMA; //TODO poke the clock config regs - - //setup the tx policy - _iface->poke32(UE_REG_CTRL_TX_REPORT_SID, 1); - _iface->poke32(UE_REG_CTRL_TX_POLICY, UE_FLAG_CTRL_TX_POLICY_NEXT_PACKET); } /*********************************************************************** -- cgit v1.2.3 From 94e9baee9598f304b0e6918894876b16ffc8b2d7 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 27 Aug 2010 14:59:33 -0700 Subject: move declaration to make loopback compile --- usrp2/top/u1e/u1e_core.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index d7c4ff509..4a80fe916 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -46,6 +46,8 @@ module u1e_core wire [31:0] set_data; wire set_stb; + wire [31:0] debug_vt; + // ///////////////////////////////////////////////////////////////////////////////////// // GPMC Slave to Wishbone Master localparam dw = 16; @@ -190,7 +192,6 @@ module u1e_core // DSP TX wire [15:0] tx_i_int, tx_q_int; - wire [31:0] debug_vt; wire run_tx; vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), -- cgit v1.2.3 From 63a07eb9c8ba49657a815e62e8937c65e2a8362a Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Sat, 28 Aug 2010 15:23:31 -0400 Subject: Add support for building c programs. Remove -pedantic and -ansi flags. --- host/CMakeLists.txt | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/host/CMakeLists.txt b/host/CMakeLists.txt index ceea5d024..78948d9bd 100644 --- a/host/CMakeLists.txt +++ b/host/CMakeLists.txt @@ -16,7 +16,7 @@ # CMAKE_MINIMUM_REQUIRED(VERSION 2.6) -PROJECT(UHD CXX) +PROJECT(UHD CXX C) ENABLE_TESTING() ######################################################################## @@ -61,8 +61,6 @@ ENDIF(NOT CMAKE_BUILD_TYPE) IF(CMAKE_COMPILER_IS_GNUCXX) ADD_DEFINITIONS(-Wall) ADD_DEFINITIONS(-Wextra) - ADD_DEFINITIONS(-pedantic) - ADD_DEFINITIONS(-ansi) #only export symbols that are declared to be part of the uhd api: UHD_ADD_OPTIONAL_CXX_COMPILER_FLAG(-fvisibility=hidden HAVE_VISIBILITY_HIDDEN) ENDIF(CMAKE_COMPILER_IS_GNUCXX) -- cgit v1.2.3 From a79d320d7691fea82c9194d59a5d4dc7bbb40317 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Sat, 28 Aug 2010 15:30:38 -0400 Subject: Move fpga-downloader and usrp-e-loopback into utils so they get packaged for installation on the USRP Embedded. --- host/utils/CMakeLists.txt | 8 ++ host/utils/fpga-downloader.cpp | 251 +++++++++++++++++++++++++++++++++++++++++ host/utils/usrp-e-loopback.c | 194 +++++++++++++++++++++++++++++++ 3 files changed, 453 insertions(+) create mode 100644 host/utils/fpga-downloader.cpp create mode 100644 host/utils/usrp-e-loopback.c diff --git a/host/utils/CMakeLists.txt b/host/utils/CMakeLists.txt index c349a9018..0e3f81d0a 100644 --- a/host/utils/CMakeLists.txt +++ b/host/utils/CMakeLists.txt @@ -24,9 +24,17 @@ TARGET_LINK_LIBRARIES(uhd_find_devices uhd) ADD_EXECUTABLE(uhd_usrp_probe uhd_usrp_probe.cpp) TARGET_LINK_LIBRARIES(uhd_usrp_probe uhd) +ADD_EXECUTABLE(fpga-downloader fpga-downloader.cpp) +TARGET_LINK_LIBRARIES(fpga-downloader) + +ADD_EXECUTABLE(usrp-e-loopback usrp-e-loopback.c) +TARGET_LINK_LIBRARIES(usrp-e-loopback pthread) + INSTALL(TARGETS uhd_find_devices uhd_usrp_probe + fpga-downloader + usrp-e-loopback RUNTIME DESTINATION ${RUNTIME_DIR} ) diff --git a/host/utils/fpga-downloader.cpp b/host/utils/fpga-downloader.cpp new file mode 100644 index 000000000..fb96b64a3 --- /dev/null +++ b/host/utils/fpga-downloader.cpp @@ -0,0 +1,251 @@ +/* -*- c++ -*- */ +/* + * Copyright 2003,2004,2008,2009 Free Software Foundation, Inc. + * + * This file is part of GNU Radio + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. +*/ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +/* + * Configuration connections + * + * CCK - MCSPI1_CLK + * DIN - MCSPI1_MOSI + * PROG_B - GPIO_175 - output (change mux) + * DONE - GPIO_173 - input (change mux) + * INIT_B - GPIO_114 - input (change mux) + * +*/ + +const unsigned int PROG_B = 175; +const unsigned int DONE = 173; +const unsigned int INIT_B = 114; + +static std::string bit_file = "safe_u1e.bin"; + +const int BUF_SIZE = 4096; + +enum gpio_direction {IN, OUT}; + +class gpio { + public: + + gpio(unsigned int gpio_num, gpio_direction pin_direction); + + bool get_value(); + void set_value(bool state); + + private: + + std::stringstream base_path; + std::fstream value_file; +}; + +class spidev { + public: + + spidev(std::string dev_name); + ~spidev(); + + void send(char *wbuf, char *rbuf, unsigned int nbytes); + + private: + + int fd; + +}; + +gpio::gpio(unsigned int gpio_num, gpio_direction pin_direction) +{ + std::fstream export_file; + + export_file.open("/sys/class/gpio/export", std::ios::out); + if (!export_file.is_open()) ///\todo Poor error handling + std::cout << "Failed to open gpio export file." << std::endl; + + export_file << gpio_num << std::endl; + + base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush; + + std::fstream direction_file; + std::string direction_file_name; + + direction_file_name = base_path.str() + "/direction"; + + direction_file.open(direction_file_name.c_str()); + if (!direction_file.is_open()) + std::cout << "Failed to open direction file." << std::endl; + if (pin_direction == OUT) + direction_file << "out" << std::endl; + else + direction_file << "in" << std::endl; + + std::string value_file_name; + + value_file_name = base_path.str() + "/value"; + + value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out); + if (!value_file.is_open()) + std::cout << "Failed to open value file." << std::endl; +} + +bool gpio::get_value() +{ + + std::string val; + + std::getline(value_file, val); + value_file.seekg(0); + + if (val == "0") + return false; + else if (val == "1") + return true; + else + std::cout << "Data read from value file|" << val << "|" << std::endl; + + return false; +} + +void gpio::set_value(bool state) +{ + + if (state) + value_file << "1" << std::endl; + else + value_file << "0" << std::endl; +} + +static void prepare_fpga_for_configuration(gpio &prog, gpio &init) +{ + + prog.set_value(true); + prog.set_value(false); + prog.set_value(true); + +#if 0 + bool ready_to_program(false); + unsigned int count(0); + do { + ready_to_program = init.get_value(); + count++; + + sleep(1); + } while (count < 10 && !ready_to_program); + + if (count == 10) { + std::cout << "FPGA not ready for programming." << std::endl; + exit(-1); + } +#endif +} + +spidev::spidev(std::string fname) +{ + int ret; + int mode = 0; + int speed = 12000000; + int bits = 8; + + fd = open(fname.c_str(), O_RDWR); + + ret = ioctl(fd, SPI_IOC_WR_MODE, &mode); + ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed); + ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits); +} + + +spidev::~spidev() +{ + close(fd); +} + +void spidev::send(char *buf, char *rbuf, unsigned int nbytes) +{ + int ret; + + struct spi_ioc_transfer tr; + tr.tx_buf = (unsigned long) buf; + tr.rx_buf = (unsigned long) rbuf; + tr.len = nbytes; + tr.delay_usecs = 0; + tr.speed_hz = 48000000; + tr.bits_per_word = 8; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + +} + +static void send_file_to_fpga(std::string &file_name, gpio &error, gpio &done) +{ + std::ifstream bitstream; + + std::cout << "File name - " << file_name.c_str() << std::endl; + + bitstream.open(file_name.c_str(), std::ios::binary); + if (!bitstream.is_open()) + std::cout << "File " << file_name << " not opened succesfully." << std::endl; + + spidev spi("/dev/spidev1.0"); + char buf[BUF_SIZE]; + char rbuf[BUF_SIZE]; + + do { + bitstream.read(buf, BUF_SIZE); + spi.send(buf, rbuf, bitstream.gcount()); + + if (error.get_value()) + std::cout << "INIT_B went high, error occured." << std::endl; + + if (!done.get_value()) + std::cout << "Configuration complete." << std::endl; + + } while (bitstream.gcount() == BUF_SIZE); +} + +int main(int argc, char *argv[]) +{ + + gpio gpio_prog_b(PROG_B, OUT); + gpio gpio_init_b(INIT_B, IN); + gpio gpio_done (DONE, IN); + + if (argc == 2) + bit_file = argv[1]; + + std::cout << "FPGA config file: " << bit_file << std::endl; + + prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b); + + std::cout << "Done = " << gpio_done.get_value() << std::endl; + + send_file_to_fpga(bit_file, gpio_init_b, gpio_done); +} + diff --git a/host/utils/usrp-e-loopback.c b/host/utils/usrp-e-loopback.c new file mode 100644 index 000000000..f400fe0be --- /dev/null +++ b/host/utils/usrp-e-loopback.c @@ -0,0 +1,194 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// max length #define PKT_DATA_LENGTH 1016 +static int packet_data_length; +static int error; + +struct pkt { + int len; + int checksum; + int seq_num; + short data[]; +}; + +static int fp; + +static int calc_checksum(struct pkt *p) +{ + int i, sum; + + i = 0; + sum = 0; + + for (i=0; i < p->len; i++) + sum += p->data[i]; + + sum += p->seq_num; + sum += p->len; + + return sum; +} + +static void *read_thread(void *threadid) +{ + char *rx_data; + int cnt, prev_seq_num, pkt_count, seq_num_failure; + struct pkt *p; + unsigned long bytes_transfered, elapsed_seconds; + struct timeval start_time, finish_time; + + printf("Greetings from the reading thread!\n"); + + bytes_transfered = 0; + gettimeofday(&start_time, NULL); + + // IMPORTANT: must assume max length packet from fpga + rx_data = malloc(2048); + p = (struct pkt *) ((void *)rx_data); + + prev_seq_num = 0; + pkt_count = 0; + seq_num_failure = 0; + + while (1) { + + cnt = read(fp, rx_data, 2048); + if (cnt < 0) + printf("Error returned from read: %d, sequence number = %d\n", cnt, p->seq_num); + +// printf("p->seq_num = %d\n", p->seq_num); + + + pkt_count++; + + if (p->seq_num != prev_seq_num + 1) { + printf("Sequence number fail, current = %d, previous = %d, pkt_count = %d\n", + p->seq_num, prev_seq_num, pkt_count); + + seq_num_failure ++; + if (seq_num_failure > 2) + error = 1; + } + + prev_seq_num = p->seq_num; + + if (calc_checksum(p) != p->checksum) { + printf("Checksum fail packet = %X, expected = %X, pkt_count = %d\n", + calc_checksum(p), p->checksum, pkt_count); + error = 1; + } + + bytes_transfered += cnt; + + if (bytes_transfered > (100 * 1000000)) { + gettimeofday(&finish_time, NULL); + elapsed_seconds = finish_time.tv_sec - start_time.tv_sec; + + printf("RX data transfer rate = %f K Samples/second\n", + (float) bytes_transfered / (float) elapsed_seconds / 4000); + + + start_time = finish_time; + bytes_transfered = 0; + } + + +// printf("."); +// fflush(stdout); +// printf("\n"); + } + +} + +static void *write_thread(void *threadid) +{ + int seq_number, i, cnt; + void *tx_data; + struct pkt *p; + + printf("Greetings from the write thread!\n"); + + tx_data = malloc(2048); + p = (struct pkt *) ((void *)tx_data); + + for (i=0; i < packet_data_length; i++) +// p->data[i] = random() >> 16; + p->data[i] = i; + + seq_number = 1; + + while (1) { + p->seq_num = seq_number++; + + if (packet_data_length > 0) + p->len = packet_data_length; + else + p->len = (random() & 0x1ff) + (1004 - 512); + + p->checksum = calc_checksum(p); + + cnt = write(fp, tx_data, p->len * 2 + 12); + if (cnt < 0) + printf("Error returned from write: %d\n", cnt); +// sleep(1); + } +} + + +int main(int argc, char *argv[]) +{ + pthread_t tx, rx; + long int t; + struct sched_param s = { + .sched_priority = 1 + }; + void *rb; + struct usrp_transfer_frame *tx_rb, *rx_rb; + + if (argc < 2) { + printf("%s data_size\n", argv[0]); + return -1; + } + + packet_data_length = atoi(argv[1]); + + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); + + rb = mmap(0, 202 * 4096, PROT_READ|PROT_WRITE, MAP_SHARED, fp, 0); + if (!rb) { + printf("mmap failed\n"); + exit; + } + + + sched_setscheduler(0, SCHED_RR, &s); + error = 0; + +#if 1 + if (pthread_create(&rx, NULL, read_thread, (void *) t)) { + printf("Failed to create rx thread\n"); + exit(-1); + } + + sleep(1); +#endif + + if (pthread_create(&tx, NULL, write_thread, (void *) t)) { + printf("Failed to create tx thread\n"); + exit(-1); + } + +// while (!error) + sleep(1000000000); + + printf("Done sleeping\n"); +} -- cgit v1.2.3 From ee44eecc3e2047b1514794add99203c4d2d3c7cc Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Sat, 28 Aug 2010 19:54:03 -0400 Subject: Test if usrp_e kernel module is loaded before trying to load the FPGA. Do not load the the fpga if the kernel module is loaded. --- host/utils/fpga-downloader.cpp | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/host/utils/fpga-downloader.cpp b/host/utils/fpga-downloader.cpp index fb96b64a3..80ee71600 100644 --- a/host/utils/fpga-downloader.cpp +++ b/host/utils/fpga-downloader.cpp @@ -27,6 +27,7 @@ #include #include +#include #include #include #include @@ -240,6 +241,21 @@ int main(int argc, char *argv[]) if (argc == 2) bit_file = argv[1]; + bool module_found(false); + std::ifstream mod_file("/proc/modules"); + while (!mod_file.eof()) { + std::string line; + getline(mod_file, line); + if (line.find("usrp_e") != std::string::npos) + module_found = true; + } + mod_file.close(); + + if (module_found) { + std::cout << "USRP Embedded kernel module loaded, not loading FPGA." << std::endl; + return -1; + } + std::cout << "FPGA config file: " << bit_file << std::endl; prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b); -- cgit v1.2.3 From cd84e9dbfcc12584eba890a6618d38832e5d8dba Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Sun, 29 Aug 2010 08:16:00 -0400 Subject: Add usrp-e-debug-pins to utils. This is the wrong place for the regs header file. --- host/utils/CMakeLists.txt | 4 + host/utils/usrp-e-debug-pins.c | 77 ++++++++++++++++ host/utils/usrp_e_regs.hpp | 196 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 277 insertions(+) create mode 100644 host/utils/usrp-e-debug-pins.c create mode 100644 host/utils/usrp_e_regs.hpp diff --git a/host/utils/CMakeLists.txt b/host/utils/CMakeLists.txt index 0e3f81d0a..6515048eb 100644 --- a/host/utils/CMakeLists.txt +++ b/host/utils/CMakeLists.txt @@ -30,11 +30,15 @@ TARGET_LINK_LIBRARIES(fpga-downloader) ADD_EXECUTABLE(usrp-e-loopback usrp-e-loopback.c) TARGET_LINK_LIBRARIES(usrp-e-loopback pthread) +ADD_EXECUTABLE(usrp-e-debug-pins usrp-e-debug-pins.c) +TARGET_LINK_LIBRARIES(usrp-e-debug-pins) + INSTALL(TARGETS uhd_find_devices uhd_usrp_probe fpga-downloader usrp-e-loopback + usrp-e-debug-pins RUNTIME DESTINATION ${RUNTIME_DIR} ) diff --git a/host/utils/usrp-e-debug-pins.c b/host/utils/usrp-e-debug-pins.c new file mode 100644 index 000000000..1ed2c8983 --- /dev/null +++ b/host/utils/usrp-e-debug-pins.c @@ -0,0 +1,77 @@ +#include +#include +#include +#include +#include +#include +#include + +#include +#include "usrp_e_regs.hpp" + +// Usage: usrp_e_gpio + +static int fp; + +static int read_reg(__u16 reg) +{ + int ret; + struct usrp_e_ctl16 d; + + d.offset = reg; + d.count = 1; + ret = ioctl(fp, USRP_E_READ_CTL16, &d); + return d.buf[0]; +} + +static void write_reg(__u16 reg, __u16 val) +{ + int ret; + struct usrp_e_ctl16 d; + + d.offset = reg; + d.count = 1; + d.buf[0] = val; + ret = ioctl(fp, USRP_E_WRITE_CTL16, &d); +} + +int main(int argc, char *argv[]) +{ + int test; + + test = 0; + if (argc < 2) { + printf("%s 0|1|off\n", argv[0]); + } + + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); + if (fp < 0) { + perror("Open failed"); + return -1; + } + + if (strcmp(argv[1], "0") == 0) { + printf("Selected 0 based on %s\n", argv[1]); + write_reg(UE_REG_GPIO_TX_DDR, 0xFFFF); + write_reg(UE_REG_GPIO_RX_DDR, 0xFFFF); + write_reg(UE_REG_GPIO_TX_SEL, 0x0); + write_reg(UE_REG_GPIO_RX_SEL, 0x0); + write_reg(UE_REG_GPIO_TX_DBG, 0xFFFF); + write_reg(UE_REG_GPIO_RX_DBG, 0xFFFF); + } else if (strcmp(argv[1], "1") == 0) { + printf("Selected 1 based on %s\n", argv[1]); + write_reg(UE_REG_GPIO_TX_DDR, 0xFFFF); + write_reg(UE_REG_GPIO_RX_DDR, 0xFFFF); + write_reg(UE_REG_GPIO_TX_SEL, 0xFFFF); + write_reg(UE_REG_GPIO_RX_SEL, 0xFFFF); + write_reg(UE_REG_GPIO_TX_DBG, 0xFFFF); + write_reg(UE_REG_GPIO_RX_DBG, 0xFFFF); + } else { + printf("Selected off based on %s\n", argv[1]); + write_reg(UE_REG_GPIO_TX_DDR, 0x0); + write_reg(UE_REG_GPIO_RX_DDR, 0x0); + } + + return 0; +} diff --git a/host/utils/usrp_e_regs.hpp b/host/utils/usrp_e_regs.hpp new file mode 100644 index 000000000..a4f42093e --- /dev/null +++ b/host/utils/usrp_e_regs.hpp @@ -0,0 +1,196 @@ + + +//////////////////////////////////////////////////////////////// +// +// Memory map for embedded wishbone bus +// +//////////////////////////////////////////////////////////////// + +// All addresses are byte addresses. All accesses are word (16-bit) accesses. +// This means that address bit 0 is usually 0. +// There are 11 bits of address for the control. + +#ifndef __USRP_E_REGS_H +#define __USRP_E_REGS_H + +///////////////////////////////////////////////////// +// Slave pointers + +#define UE_REG_SLAVE(n) ((n)<<7) +#define UE_REG_SR_ADDR(n) ((UE_REG_SLAVE(5)) + (4*(n))) + +///////////////////////////////////////////////////// +// Slave 0 -- Misc Regs + +#define UE_REG_MISC_BASE UE_REG_SLAVE(0) + +#define UE_REG_MISC_LED UE_REG_MISC_BASE + 0 +#define UE_REG_MISC_SW UE_REG_MISC_BASE + 2 +#define UE_REG_MISC_CGEN_CTRL UE_REG_MISC_BASE + 4 +#define UE_REG_MISC_CGEN_ST UE_REG_MISC_BASE + 6 +#define UE_REG_MISC_TEST UE_REG_MISC_BASE + 8 +#define UE_REG_MISC_RX_LEN UE_REG_MISC_BASE + 10 +#define UE_REG_MISC_TX_LEN UE_REG_MISC_BASE + 12 + +///////////////////////////////////////////////////// +// Slave 1 -- UART +// CLKDIV is 16 bits, others are only 8 + +#define UE_REG_UART_BASE UE_REG_SLAVE(1) + +#define UE_REG_UART_CLKDIV UE_REG_UART_BASE + 0 +#define UE_REG_UART_TXLEVEL UE_REG_UART_BASE + 2 +#define UE_REG_UART_RXLEVEL UE_REG_UART_BASE + 4 +#define UE_REG_UART_TXCHAR UE_REG_UART_BASE + 6 +#define UE_REG_UART_RXCHAR UE_REG_UART_BASE + 8 + +///////////////////////////////////////////////////// +// Slave 2 -- SPI Core +// This should be accessed through the IOCTL +// Users should not touch directly + +#define UE_REG_SPI_BASE UE_REG_SLAVE(2) + +//spi slave constants +#define UE_SPI_SS_AD9522 (1 << 3) +#define UE_SPI_SS_AD9862 (1 << 2) +#define UE_SPI_SS_TX_DB (1 << 1) +#define UE_SPI_SS_RX_DB (1 << 0) + +//////////////////////////////////////////////// +// Slave 3 -- I2C Core +// This should be accessed through the IOCTL +// Users should not touch directly + +#define UE_REG_I2C_BASE UE_REG_SLAVE(3) + + +//////////////////////////////////////////////// +// Slave 4 -- GPIO + +#define UE_REG_GPIO_BASE UE_REG_SLAVE(4) + +#define UE_REG_GPIO_RX_IO UE_REG_GPIO_BASE + 0 +#define UE_REG_GPIO_TX_IO UE_REG_GPIO_BASE + 2 +#define UE_REG_GPIO_RX_DDR UE_REG_GPIO_BASE + 4 +#define UE_REG_GPIO_TX_DDR UE_REG_GPIO_BASE + 6 +#define UE_REG_GPIO_RX_SEL UE_REG_GPIO_BASE + 8 +#define UE_REG_GPIO_TX_SEL UE_REG_GPIO_BASE + 10 +#define UE_REG_GPIO_RX_DBG UE_REG_GPIO_BASE + 12 +#define UE_REG_GPIO_TX_DBG UE_REG_GPIO_BASE + 14 + +//possible bit values for sel when dbg is 0: +#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg +#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic + +//possible bit values for sel when dbg is 1: +#define GPIO_SEL_DEBUG_0 0 // if pin is an output, debug lines from FPGA fabric +#define GPIO_SEL_DEBUG_1 1 // if pin is an output, debug lines from FPGA fabric + + +//////////////////////////////////////////////////// +// Slave 5 -- Settings Bus +// +// Output-only, no readback, 32 registers total +// Each register must be written 32 bits at a time +// First the address xxx_xx00 and then xxx_xx10 + +#define UE_REG_SETTINGS_BASE UE_REG_SLAVE(5) + +/////////////////////////////////////////////////// +// Slave 6 -- ATR Controller +// 16 regs + +#define UE_REG_ATR_BASE UE_REG_SLAVE(6) + +#define UE_REG_ATR_IDLE_RXSIDE UE_REG_ATR_BASE + 0 +#define UE_REG_ATR_IDLE_TXSIDE UE_REG_ATR_BASE + 2 +#define UE_REG_ATR_INTX_RXSIDE UE_REG_ATR_BASE + 4 +#define UE_REG_ATR_INTX_TXSIDE UE_REG_ATR_BASE + 6 +#define UE_REG_ATR_INRX_RXSIDE UE_REG_ATR_BASE + 8 +#define UE_REG_ATR_INRX_TXSIDE UE_REG_ATR_BASE + 10 +#define UE_REG_ATR_FULL_RXSIDE UE_REG_ATR_BASE + 12 +#define UE_REG_ATR_FULL_TXSIDE UE_REG_ATR_BASE + 14 + +///////////////////////////////////////////////// +// DSP RX Regs +//////////////////////////////////////////////// +#define UE_REG_DSP_RX_FREQ UE_REG_SR_ADDR(0) +#define UE_REG_DSP_RX_SCALE_IQ UE_REG_SR_ADDR(1) // {scale_i,scale_q} +#define UE_REG_DSP_RX_DECIM_RATE UE_REG_SR_ADDR(2) // hb and decim rate +#define UE_REG_DSP_RX_DCOFFSET_I UE_REG_SR_ADDR(3) // Bit 31 high sets fixed offset mode, using lower 14 bits, // otherwise it is automatic +#define UE_REG_DSP_RX_DCOFFSET_Q UE_REG_SR_ADDR(4) // Bit 31 high sets fixed offset mode, using lower 14 bits +#define UE_REG_DSP_RX_MUX UE_REG_SR_ADDR(5) + +/////////////////////////////////////////////////// +// VITA RX CTRL regs +/////////////////////////////////////////////////// +// The following 3 are logically a single command register. +// They are clocked into the underlying fifo when time_ticks is written. +#define UE_REG_CTRL_RX_STREAM_CMD UE_REG_SR_ADDR(8) // {now, chain, num_samples(30) +#define UE_REG_CTRL_RX_TIME_SECS UE_REG_SR_ADDR(9) +#define UE_REG_CTRL_RX_TIME_TICKS UE_REG_SR_ADDR(10) +#define UE_REG_CTRL_RX_CLEAR_OVERRUN UE_REG_SR_ADDR(11) // write anything to clear overrun +#define UE_REG_CTRL_RX_VRT_HEADER UE_REG_SR_ADDR(12) // word 0 of packet. FPGA fills in packet counter +#define UE_REG_CTRL_RX_VRT_STREAM_ID UE_REG_SR_ADDR(13) // word 1 of packet. +#define UE_REG_CTRL_RX_VRT_TRAILER UE_REG_SR_ADDR(14) +#define UE_REG_CTRL_RX_NSAMPS_PER_PKT UE_REG_SR_ADDR(15) +#define UE_REG_CTRL_RX_NCHANNELS UE_REG_SR_ADDR(16) // 1 in basic case, up to 4 for vector sources + +///////////////////////////////////////////////// +// DSP TX Regs +//////////////////////////////////////////////// +#define UE_REG_DSP_TX_FREQ UE_REG_SR_ADDR(17) +#define UE_REG_DSP_TX_SCALE_IQ UE_REG_SR_ADDR(18) // {scale_i,scale_q} +#define UE_REG_DSP_TX_INTERP_RATE UE_REG_SR_ADDR(19) +#define UE_REG_DSP_TX_UNUSED UE_REG_SR_ADDR(20) +#define UE_REG_DSP_TX_MUX UE_REG_SR_ADDR(21) + +///////////////////////////////////////////////// +// VITA TX CTRL regs +//////////////////////////////////////////////// +#define UE_REG_CTRL_TX_NCHANNELS UE_REG_SR_ADDR(24) +#define UE_REG_CTRL_TX_CLEAR_UNDERRUN UE_REG_SR_ADDR(25) +#define UE_REG_CTRL_TX_REPORT_SID UE_REG_SR_ADDR(26) +#define UE_REG_CTRL_TX_POLICY UE_REG_SR_ADDR(27) + +#define UE_FLAG_CTRL_TX_POLICY_WAIT (0x1 << 0) +#define UE_FLAG_CTRL_TX_POLICY_NEXT_PACKET (0x1 << 1) +#define UE_FLAG_CTRL_TX_POLICY_NEXT_BURST (0x1 << 2) + +///////////////////////////////////////////////// +// VITA49 64 bit time (write only) +//////////////////////////////////////////////// + /*! + * \brief Time 64 flags + * + * 
+   *
+   *    3                   2                   1
+   *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   * +-----------------------------------------------------------+-+-+
+   * |                                                           |S|P|
+   * +-----------------------------------------------------------+-+-+
+   *
+   * P - PPS edge selection (0=negedge, 1=posedge, default=0)
+   * S - Source (0=sma, 1=mimo, 0=default)
+   *
+   *
+ */ +#define UE_REG_TIME64_SECS UE_REG_SR_ADDR(28) // value to set absolute secs to on next PPS +#define UE_REG_TIME64_TICKS UE_REG_SR_ADDR(29) // value to set absolute ticks to on next PPS +#define UE_REG_TIME64_FLAGS UE_REG_SR_ADDR(30) // flags - see chart above +#define UE_REG_TIME64_IMM UE_REG_SR_ADDR(31) // set immediate (0=latch on next pps, 1=latch immediate, default=0) +#define UE_REG_TIME64_TPS UE_REG_SR_ADDR(31) // clock ticks per second (counter rollover) + +//pps flags (see above) +#define UE_FLAG_TIME64_PPS_NEGEDGE (0 << 0) +#define UE_FLAG_TIME64_PPS_POSEDGE (1 << 0) +#define UE_FLAG_TIME64_PPS_SMA (0 << 1) +#define UE_FLAG_TIME64_PPS_MIMO (1 << 1) + +#define UE_FLAG_TIME64_LATCH_NOW 1 +#define UE_FLAG_TIME64_LATCH_NEXT_PPS 0 + +#endif + -- cgit v1.2.3 From c3cd5ccbf38294a3dd4ae1e386ddefb2071f59b6 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Mon, 30 Aug 2010 15:11:05 -0700 Subject: add register to tell host about compatibility level and which image we are using --- usrp2/top/u1e/u1e_core.v | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 4a80fe916..5c4b6de6c 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -34,7 +34,9 @@ module u1e_core localparam SR_TX_DSP = 17; // 5 regs localparam SR_TX_CTRL = 24; // 2 regs localparam SR_TIME64 = 28; // 4 regs - + + wire COMPAT_NUM = 8'd2; + wire wb_clk = clk_fpga; wire wb_rst = rst_fpga; @@ -104,6 +106,8 @@ module u1e_core wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int; `ifdef LOOPBACK + wire [7:0] WHOAMI = 1; + fifo_cascade #(.WIDTH(36), .SIZE(12)) loopback_fifo (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx | clear_rx), .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy), @@ -116,7 +120,8 @@ module u1e_core `endif // LOOPBACK `ifdef TIMED - + wire [7:0] WHOAMI = 2; + // TX side wire tx_enable; @@ -147,6 +152,8 @@ module u1e_core `endif // `ifdef TIMED `ifdef DSP + wire [7:0] WHOAMI = 0; + wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug; // ///////////////////////////////////////////////////////////////////////// @@ -303,9 +310,10 @@ module u1e_core localparam REG_CGEN_CTRL = 7'd4; // out localparam REG_CGEN_ST = 7'd6; // in localparam REG_TEST = 7'd8; // out - localparam REG_RX_FRAMELEN = 7'd10; // out - localparam REG_TX_FRAMELEN = 7'd12; // in - localparam REG_XFER_RATE = 7'd14; // in + localparam REG_RX_FRAMELEN = 7'd10; // in + localparam REG_TX_FRAMELEN = 7'd12; // out + localparam REG_XFER_RATE = 7'd14; // out + localparam REG_COMPAT = 7'd16; // in always @(posedge wb_clk) if(wb_rst) @@ -344,6 +352,7 @@ module u1e_core (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : (s0_adr[6:0] == REG_TEST) ? reg_test : (s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len : + (s0_adr[6:0] == REG_COMPAT) ? { WHOAMI, COMPAT_NUM } : 16'hBEEF; assign s0_ack = s0_stb & s0_cyc; -- cgit v1.2.3 From 709d93fd675298c7d6fb3e97c60ae7258496efc4 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 7 Sep 2010 19:07:34 -0700 Subject: fixed makefile to compile with our new system --- usrp2/top/u1e_passthru/Makefile | 80 +++++++++++++++++++---------------------- 1 file changed, 36 insertions(+), 44 deletions(-) diff --git a/usrp2/top/u1e_passthru/Makefile b/usrp2/top/u1e_passthru/Makefile index 62923f87f..d1950629b 100644 --- a/usrp2/top/u1e_passthru/Makefile +++ b/usrp2/top/u1e_passthru/Makefile @@ -1,20 +1,30 @@ # # Copyright 2008 Ettus Research LLC -# +# ################################################## -# xtclsh Shell and tcl Script Path +# Project Setup ################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl +TOP_MODULE = passthru +BUILD_DIR = $(abspath build$(ISE)) ################################################## -# Project Setup +# Include other makefiles ################################################## -BUILD_DIR := build/ -export TOP_MODULE := passthru -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extram/Makefile.srcs +include ../../gpmc/Makefile.srcs ################################################## # Project Properties @@ -34,16 +44,21 @@ simulator "ISE Simulator (VHDL/Verilog)" \ ################################################## # Sources ################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -top/u1e_passthru/passthru.ucf \ -top/u1e_passthru/passthru.v +TOP_SRCS = \ +passthru.v \ +passthru.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ +$(GPMC_SRCS) ################################################## # Process Properties ################################################## -export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ "Pack I/O Registers into IOBs" Yes \ "Optimization Effort" High \ "Optimize Instantiated Primitives" TRUE \ @@ -52,10 +67,10 @@ export SYNTHESIZE_PROPERTIES := \ "Use Synchronous Reset" Auto \ "Use Synchronous Set" Auto -export TRANSLATE_PROPERTIES := \ +TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" -export MAP_PROPERTIES := \ +MAP_PROPERTIES = \ "Allow Logic Optimization Across Hierarchy" TRUE \ "Map to Input Functions" 4 \ "Optimization Strategy (Cover Mode)" Speed \ @@ -66,14 +81,14 @@ export MAP_PROPERTIES := \ "Combinatorial Logic Optimization" TRUE \ "Register Duplication" TRUE -export PLACE_ROUTE_PROPERTIES := \ +PLACE_ROUTE_PROPERTIES = \ "Place & Route Effort Level (Overall)" High -export STATIC_TIMING_PROPERTIES := \ +STATIC_TIMING_PROPERTIES = \ "Number of Paths in Error/Verbose Report" 10 \ "Report Type" "Error Report" -export GEN_PROG_FILE_PROPERTIES := \ +GEN_PROG_FILE_PROPERTIES = \ "Configuration Rate" 6 \ "Create Binary Configuration File" TRUE \ "Done (Output Events)" 5 \ @@ -81,27 +96,4 @@ export GEN_PROG_FILE_PROPERTIES := \ "Enable Outputs (Output Events)" 6 \ "Unused IOB Pins" "Pull Up" -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -clean: - rm -rf $(BUILD_DIR) - - +SIM_MODEL_PROPERTIES = "" -- cgit v1.2.3 From d2d5be27b09faee1481a763ce25e7b95460a46c9 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 9 Sep 2010 10:02:10 -0400 Subject: Add clkgen-config, usrp-e-i2c and usrp-e-spi to the installed utils. --- host/utils/CMakeLists.txt | 12 ++ host/utils/clkgen-config.cpp | 296 +++++++++++++++++++++++++++++++++++++++++++ host/utils/usrp-e-i2c.c | 87 +++++++++++++ host/utils/usrp-e-spi.c | 54 ++++++++ 4 files changed, 449 insertions(+) create mode 100644 host/utils/clkgen-config.cpp create mode 100644 host/utils/usrp-e-i2c.c create mode 100644 host/utils/usrp-e-spi.c diff --git a/host/utils/CMakeLists.txt b/host/utils/CMakeLists.txt index 6515048eb..ff0ca895a 100644 --- a/host/utils/CMakeLists.txt +++ b/host/utils/CMakeLists.txt @@ -27,18 +27,30 @@ TARGET_LINK_LIBRARIES(uhd_usrp_probe uhd) ADD_EXECUTABLE(fpga-downloader fpga-downloader.cpp) TARGET_LINK_LIBRARIES(fpga-downloader) +ADD_EXECUTABLE(clkgen-config clkgen-config.cpp) +TARGET_LINK_LIBRARIES(clkgen-config) + ADD_EXECUTABLE(usrp-e-loopback usrp-e-loopback.c) TARGET_LINK_LIBRARIES(usrp-e-loopback pthread) ADD_EXECUTABLE(usrp-e-debug-pins usrp-e-debug-pins.c) TARGET_LINK_LIBRARIES(usrp-e-debug-pins) +ADD_EXECUTABLE(usrp-e-i2c usrp-e-i2c.c) +TARGET_LINK_LIBRARIES(usrp-e-i2c) + +ADD_EXECUTABLE(usrp-e-spi usrp-e-spi.c) +TARGET_LINK_LIBRARIES(usrp-e-spi) + INSTALL(TARGETS uhd_find_devices uhd_usrp_probe fpga-downloader usrp-e-loopback usrp-e-debug-pins + usrp-e-spi + usrp-e-i2c + clkgen-config RUNTIME DESTINATION ${RUNTIME_DIR} ) diff --git a/host/utils/clkgen-config.cpp b/host/utils/clkgen-config.cpp new file mode 100644 index 000000000..e8279b4ae --- /dev/null +++ b/host/utils/clkgen-config.cpp @@ -0,0 +1,296 @@ +/* -*- c++ -*- */ +/* + * Copyright 2003,2004,2008,2009 Free Software Foundation, Inc. + * + * This file is part of UHD + * + * GNU Radio is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3, or (at your option) + * any later version. + * + * GNU Radio is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GNU Radio; see the file COPYING. If not, write to + * the Free Software Foundation, Inc., 51 Franklin Street, + * Boston, MA 02110-1301, USA. +*/ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + + +// Programming data for clock gen chip +static const unsigned int config_data[] = { + 0x000024, + 0x023201, + 0x000081, + 0x000400, + 0x00104c, + 0x001101, + 0x001200, + 0x001300, + 0x001414, + 0x001500, + 0x001604, + 0x001704, + 0x001807, + 0x001900, + //0x001a00,//for debug + 0x001a32, + 0x001b12, + 0x001c44, + 0x001d00, + 0x001e00, + 0x00f062, + 0x00f162, + 0x00f262, + 0x00f362, + 0x00f462, + 0x00f562, + 0x00f662, + 0x00f762, + 0x00f862, + 0x00f962, + 0x00fa62, + 0x00fb62, + 0x00fc00, + 0x00fd00, + 0x019021, + 0x019100, + 0x019200, + 0x019333, + 0x019400, + 0x019500, + 0x019611, + 0x019700, + 0x019800, + 0x019900, + 0x019a00, + 0x019b00, + 0x01e003, + 0x01e102, + 0x023000, + 0x023201, + 0x0b0201, + 0x0b0300, + 0x001fff, + 0x0a0000, + 0x0a0100, + 0x0a0200, + 0x0a0302, + 0x0a0400, + 0x0a0504, + 0x0a060e, + 0x0a0700, + 0x0a0810, + 0x0a090e, + 0x0a0a00, + 0x0a0bf0, + 0x0a0c0b, + 0x0a0d01, + 0x0a0e90, + 0x0a0f01, + 0x0a1001, + 0x0a11e0, + 0x0a1201, + 0x0a1302, + 0x0a1430, + 0x0a1580, + 0x0a16ff, + 0x023201, + 0x0b0301, + 0x023201, +}; + + +const unsigned int CLKGEN_SELECT = 145; + + +enum gpio_direction {IN, OUT}; + +class gpio { + public: + + gpio(unsigned int gpio_num, gpio_direction pin_direction, bool close_action); + ~gpio(); + + bool get_value(); + void set_value(bool state); + + private: + + unsigned int gpio_num; + + std::stringstream base_path; + std::fstream value_file; + std::fstream direction_file; + bool close_action; // True set to input and release, false do nothing +}; + +class spidev { + public: + + spidev(std::string dev_name); + ~spidev(); + + void send(char *wbuf, char *rbuf, unsigned int nbytes); + + private: + + int fd; + +}; + +gpio::gpio(unsigned int _gpio_num, gpio_direction pin_direction, bool close_action) +{ + std::fstream export_file; + + gpio_num = _gpio_num; + + export_file.open("/sys/class/gpio/export", std::ios::out); + if (!export_file.is_open()) ///\todo Poor error handling + std::cout << "Failed to open gpio export file." << std::endl; + + export_file << gpio_num << std::endl; + + base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush; + + std::string direction_file_name; + + direction_file_name = base_path.str() + "/direction"; + + direction_file.open(direction_file_name.c_str()); + if (!direction_file.is_open()) + std::cout << "Failed to open direction file." << std::endl; + if (pin_direction == OUT) + direction_file << "out" << std::endl; + else + direction_file << "in" << std::endl; + + std::string value_file_name; + + value_file_name = base_path.str() + "/value"; + + value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out); + if (!value_file.is_open()) + std::cout << "Failed to open value file." << std::endl; +} + +bool gpio::get_value() +{ + + std::string val; + + std::getline(value_file, val); + value_file.seekg(0); + + if (val == "0") + return false; + else if (val == "1") + return true; + else + std::cout << "Data read from value file|" << val << "|" << std::endl; + + return false; +} + +void gpio::set_value(bool state) +{ + + if (state) + value_file << "1" << std::endl; + else + value_file << "0" << std::endl; +} + +gpio::~gpio() +{ + if (close_action) { + std::fstream unexport_file; + + direction_file << "in" << std::endl; + + unexport_file.open("/sys/class/gpio/unexport", std::ios::out); + if (!unexport_file.is_open()) ///\todo Poor error handling + std::cout << "Failed to open gpio export file." << std::endl; + + unexport_file << gpio_num << std::endl; + + } + +} + +spidev::spidev(std::string fname) +{ + int ret; + int mode = 0; + int speed = 12000; + int bits = 24; + + fd = open(fname.c_str(), O_RDWR); + + ret = ioctl(fd, SPI_IOC_WR_MODE, &mode); + ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed); + ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits); +} + + +spidev::~spidev() +{ + close(fd); +} + +void spidev::send(char *buf, char *rbuf, unsigned int nbytes) +{ + int ret; + + struct spi_ioc_transfer tr; + tr.tx_buf = (unsigned long) buf; + tr.rx_buf = (unsigned long) rbuf; + tr.len = nbytes; + tr.delay_usecs = 0; + tr.speed_hz = 12000000; + tr.bits_per_word = 24; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + +} + +static void send_config_to_clkgen(gpio &chip_select, const unsigned int data[], unsigned int data_size) +{ + spidev spi("/dev/spidev1.0"); + unsigned int rbuf; + + for (unsigned int i = 0; i < data_size; i++) { + + std::cout << "sending " << std::hex << data[i] << std::endl; + chip_select.set_value(0); + spi.send((char *)&data[i], (char *)&rbuf, 4); + chip_select.set_value(1); + + }; +} + +int main(int argc, char *argv[]) +{ + + gpio clkgen_select(CLKGEN_SELECT, OUT, true); + + send_config_to_clkgen(clkgen_select, config_data, sizeof(config_data)/sizeof(unsigned int)); +} + diff --git a/host/utils/usrp-e-i2c.c b/host/utils/usrp-e-i2c.c new file mode 100644 index 000000000..c6fd4c632 --- /dev/null +++ b/host/utils/usrp-e-i2c.c @@ -0,0 +1,87 @@ +#include +#include +#include +#include +#include +#include +#include + +#include + +// Usage: usrp_e_i2c w address data0 data1 data 2 .... +// Usage: usrp_e_i2c r address count + +int main(int argc, char *argv[]) +{ + int fp, ret, i, tmp; + struct usrp_e_i2c *i2c_msg; + int direction, address, count; + + if (argc < 3) { + printf("Usage: usrp-e-i2c w address data0 data1 data2 ...\n"); + printf("Usage: usrp-e-i2c r address count\n"); + printf("All addresses and data in hex.\n"); + exit(-1); + } + + if (strcmp(argv[1], "r") == 0) { + direction = 0; + } else if (strcmp(argv[1], "w") == 0) { + direction = 1; + } else { + return -1; + } + + sscanf(argv[2], "%X", &address); + printf("Address = %X\n", address); + + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); + if (fp < 0) { + perror("Open failed"); + return -1; + } + +// sleep(1); + + if (direction) { + count = argc - 3; + } else { + sscanf(argv[3], "%X", &count); + } + printf("Count = %X\n", count); + + i2c_msg = malloc(sizeof(i2c_msg) + count * sizeof(char)); + + i2c_msg->addr = address; + i2c_msg->len = count; + + for (i = 0; i < count; i++) { + i2c_msg->data[i] = i; + } + + if (direction) { + // Write + + for (i=0; idata[i] = tmp; + } + + ret = ioctl(fp, USRP_E_I2C_WRITE, i2c_msg); + printf("Return value from i2c_write ioctl: %d\n", ret); + } else { + // Read + + ret = ioctl(fp, USRP_E_I2C_READ, i2c_msg); + printf("Return value from i2c_read ioctl: %d\n", ret); + + printf("Ioctl: %d Data read :", ret); + for (i=0; idata[i]); + } + printf("\n"); + + } + return 0; +} diff --git a/host/utils/usrp-e-spi.c b/host/utils/usrp-e-spi.c new file mode 100644 index 000000000..5203f56a8 --- /dev/null +++ b/host/utils/usrp-e-spi.c @@ -0,0 +1,54 @@ +#include +#include +#include +#include +#include +#include + +#include + +// Usage: usrp_e_spi w|rb slave data + +int main(int argc, char *argv[]) +{ + int fp, slave, length, ret; + unsigned int data; + struct usrp_e_spi spi_dat; + + if (argc < 5) { + printf("Usage: usrp_e_spi w|rb slave transfer_length data\n"); + exit(-1); + } + + slave = atoi(argv[2]); + length = atoi(argv[3]); + data = atoll(argv[4]); + + printf("Data = %X\n", data); + + fp = open("/dev/usrp_e0", O_RDWR); + printf("fp = %d\n", fp); + if (fp < 0) { + perror("Open failed"); + return -1; + } + +// sleep(1); + + + spi_dat.slave = slave; + spi_dat.data = data; + spi_dat.length = length; + spi_dat.flags = UE_SPI_PUSH_FALL | UE_SPI_LATCH_RISE; + + if (*argv[1] == 'r') { + spi_dat.readback = 1; + ret = ioctl(fp, USRP_E_SPI, &spi_dat); + printf("Ioctl returns: %d, Data returned = %d\n", ret, spi_dat.data); + } else { + spi_dat.readback = 0; + ioctl(fp, USRP_E_SPI, &spi_dat); + } + + return 0; +} -- cgit v1.2.3 From 8db1a3901972745dfab310be77c409a82b63e941 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 9 Sep 2010 11:24:58 -0700 Subject: pins are different on rev2 --- usrp2/top/u1e_passthru/passthru.ucf | 268 +----------------------------------- 1 file changed, 4 insertions(+), 264 deletions(-) diff --git a/usrp2/top/u1e_passthru/passthru.ucf b/usrp2/top/u1e_passthru/passthru.ucf index fcfce61b2..64e6f0440 100644 --- a/usrp2/top/u1e_passthru/passthru.ucf +++ b/usrp2/top/u1e_passthru/passthru.ucf @@ -1,266 +1,6 @@ - -#NET "CLK_FPGA_P" LOC = "Y11" ; -#NET "CLK_FPGA_N" LOC = "Y10" ; - -## GPMC -#NET "EM_D<15>" LOC = "D13" ; -#NET "EM_D<14>" LOC = "D15" ; -#NET "EM_D<13>" LOC = "C16" ; -#NET "EM_D<12>" LOC = "B20" ; -#NET "EM_D<11>" LOC = "A19" ; -#NET "EM_D<10>" LOC = "A17" ; -#NET "EM_D<9>" LOC = "E15" ; -#NET "EM_D<8>" LOC = "F15" ; -#NET "EM_D<7>" LOC = "E16" ; -#NET "EM_D<6>" LOC = "F16" ; -#NET "EM_D<5>" LOC = "B17" ; -#NET "EM_D<4>" LOC = "C17" ; -#NET "EM_D<3>" LOC = "B19" ; -#NET "EM_D<2>" LOC = "D19" ; -#NET "EM_D<1>" LOC = "C19" ; -#NET "EM_D<0>" LOC = "A20" ; - -#NET "EM_A<10>" LOC = "C14" ; -#NET "EM_A<9>" LOC = "C10" ; -#NET "EM_A<8>" LOC = "C5" ; -#NET "EM_A<7>" LOC = "A18" ; -#NET "EM_A<6>" LOC = "A15" ; -#NET "EM_A<5>" LOC = "A12" ; -#NET "EM_A<4>" LOC = "A10" ; -#NET "EM_A<3>" LOC = "E7" ; -#NET "EM_A<2>" LOC = "A7" ; -#NET "EM_A<1>" LOC = "C15" ; - -#NET "EM_NCS6" LOC = "E17" ; -##NET "EM_NCS5" LOC = "E10" ; -#NET "EM_NCS4" LOC = "E6" ; -##NET "EM_NCS1" LOC = "D18" ; -##NET "EM_NCS0" LOC = "D17" ; - -#NET "EM_CLK" LOC = "F11" ; -#NET "EM_WAIT0" LOC = "F14" ; -#NET "EM_NBE<1>" LOC = "D14" ; -#NET "EM_NBE<0>" LOC = "A13" ; -#NET "EM_NWE" LOC = "B13" ; -#NET "EM_NOE" LOC = "A14" ; -##NET "EM_NADV_ALE" LOC = "B15" ; -##NET "EM_NWP" LOC = "F13" ; - -## Overo GPIO -#NET "overo_gpio0" LOC = "F9" ; # MISC GPIO for debug -#NET "overo_gpio14" LOC = "C4" ; # MISC GPIO for debug -#NET "overo_gpio21" LOC = "D5" ; # MISC GPIO for debug -#NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug -#NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug -#NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug -#NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug -#NET "overo_gpio127" LOC = "C8" ; # passed through as cgen_sen_b -#NET "overo_gpio128" LOC = "G8" ; # MISC GPIO for debug -#NET "overo_gpio144" LOC = "A5" ; # tx_have_space -NET "overo_gpio145" LOC = "C7" ; # tx_underrun -#NET "overo_gpio146" LOC = "A6" ; # rx_have_data -#NET "overo_gpio147" LOC = "B6" ; # rx_overrun -#NET "overo_gpio163" LOC = "D7" ; # MISC GPIO for debug -#NET "overo_gpio170" LOC = "E8" ; # MISC GPIO for debug -#NET "overo_gpio176" LOC = "B4" ; # MISC GPIO for debug - -## Overo UART -##NET "overo_txd1" LOC = "C6" ; -##NET "overo_rxd1" LOC = "D6" ; - -## FTDI UART to USB converter -#NET "FPGA_TXD" LOC = "U1" ; -#NET "FPGA_RXD" LOC = "T6" ; - -##NET "SYSEN" LOC = "C11" ; - -## I2C -#NET "db_scl" LOC = "U4" ; -#NET "db_sda" LOC = "U5" ; - -## SPI -### DBoard SPI -#NET "db_sclk_rx" LOC = "W3" ; -#NET "db_miso_rx" LOC = "W2" ; -#NET "db_mosi_rx" LOC = "V4" ; -#NET "db_sen_rx" LOC = "V3" ; -#NET "db_sclk_tx" LOC = "Y1" ; -#NET "db_miso_tx" LOC = "W1" ; -#NET "db_mosi_tx" LOC = "R3" ; -#NET "db_sen_tx" LOC = "T4" ; - -### AD9862 SPI and aux SPI Interfaces -##NET "aux_sdi_codec" LOC = "F19" ; -##NET "aux_sdo_codec" LOC = "F18" ; -##NET "aux_sclk_codec" LOC = "D21" ; -#NET "sen_codec" LOC = "D20" ; -#NET "mosi_codec" LOC = "E19" ; -#NET "miso_codec" LOC = "F21" ; -#NET "sclk_codec" LOC = "E20" ; - -### Clock Gen SPI -#NET "cgen_miso" LOC = "U2" ; -NET "cgen_mosi" LOC = "V1" ; -NET "cgen_sclk" LOC = "R5" ; -NET "cgen_sen_b" LOC = "T1" ; - -## Clock gen control -#NET "cgen_st_status" LOC = "D4" ; -#NET "cgen_st_ld" LOC = "D1" ; -#NET "cgen_st_refmon" LOC = "E1" ; -#NET "cgen_sync_b" LOC = "M1" ; -#NET "cgen_ref_sel" LOC = "J1" ; - -## Debug pins -#NET "debug_led<2>" LOC = "T5" ; -#NET "debug_led<1>" LOC = "R2" ; -#NET "debug_led<0>" LOC = "R1" ; -#NET "debug<0>" LOC = "P6" ; -#NET "debug<1>" LOC = "R6" ; -#NET "debug<2>" LOC = "P1" ; -#NET "debug<3>" LOC = "P2" ; -#NET "debug<4>" LOC = "N6" ; -#NET "debug<5>" LOC = "N5" ; -#NET "debug<6>" LOC = "N1" ; -#NET "debug<7>" LOC = "K2" ; -#NET "debug<8>" LOC = "K3" ; -#NET "debug<9>" LOC = "K6" ; -#NET "debug<10>" LOC = "L5" ; -#NET "debug<11>" LOC = "H2" ; -#NET "debug<12>" LOC = "K4" ; -#NET "debug<13>" LOC = "K5" ; -#NET "debug<14>" LOC = "G1" ; -#NET "debug<15>" LOC = "H1" ; -#NET "debug<16>" LOC = "H5" ; -#NET "debug<17>" LOC = "H6" ; -#NET "debug<18>" LOC = "E3" ; -#NET "debug<19>" LOC = "E4" ; -#NET "debug<20>" LOC = "G5" ; -#NET "debug<21>" LOC = "G6" ; -#NET "debug<22>" LOC = "F2" ; -#NET "debug<23>" LOC = "F1" ; -#NET "debug<24>" LOC = "H3" ; -#NET "debug<25>" LOC = "H4" ; -#NET "debug<26>" LOC = "F4" ; -#NET "debug<27>" LOC = "F5" ; -#NET "debug<28>" LOC = "C2" ; -#NET "debug<29>" LOC = "C1" ; -#NET "debug<30>" LOC = "F3" ; -#NET "debug<31>" LOC = "G3" ; -#NET "debug_clk<0>" LOC = "L6" ; -#NET "debug_clk<1>" LOC = "M5" ; - -#NET "debug_pb<2>" LOC = "Y2" ; -#NET "debug_pb<1>" LOC = "AA1" ; -#NET "debug_pb<0>" LOC = "N3" ; - -#NET "dip_sw<7>" LOC = "T3" ; -#NET "dip_sw<6>" LOC = "U3" ; -#NET "dip_sw<5>" LOC = "M3" ; -#NET "dip_sw<4>" LOC = "N4" ; -#NET "dip_sw<3>" LOC = "J3" ; -#NET "dip_sw<2>" LOC = "J4" ; -#NET "dip_sw<1>" LOC = "J6" ; -#NET "dip_sw<0>" LOC = "J7" ; - -##NET "RXSYNC" LOC = "F22" ; -##NET "reset_codec" LOC = "D22" ; - -##NET "DB<11>" LOC = "E22" ; -##NET "DB<10>" LOC = "J19" ; -##NET "DB<9>" LOC = "H20" ; -##NET "DB<8>" LOC = "G19" ; -##NET "DB<7>" LOC = "F20" ; -##NET "DB<6>" LOC = "K16" ; -##NET "DB<5>" LOC = "J17" ; -##NET "DB<4>" LOC = "H22" ; -##NET "DB<3>" LOC = "G22" ; -##NET "DB<2>" LOC = "H17" ; -##NET "DB<1>" LOC = "H18" ; -##NET "DB<0>" LOC = "K20" ; -##NET "DA<11>" LOC = "J20" ; -##NET "DA<10>" LOC = "K19" ; -##NET "DA<9>" LOC = "K18" ; -##NET "DA<8>" LOC = "L22" ; -##NET "DA<7>" LOC = "K22" ; -##NET "DA<6>" LOC = "N22" ; -##NET "DA<5>" LOC = "M22" ; -##NET "DA<4>" LOC = "N20" ; -##NET "DA<3>" LOC = "N19" ; -##NET "DA<2>" LOC = "R22" ; -##NET "DA<1>" LOC = "P22" ; -##NET "DA<0>" LOC = "N17" ; - -#NET "TX<13>" LOC = "P19" ; -#NET "TX<12>" LOC = "R18" ; -#NET "TX<11>" LOC = "U20" ; -#NET "TX<10>" LOC = "T20" ; -#NET "TX<9>" LOC = "R19" ; -#NET "TX<8>" LOC = "R20" ; -#NET "TX<7>" LOC = "W22" ; -#NET "TX<6>" LOC = "Y22" ; -#NET "TX<5>" LOC = "T18" ; -#NET "TX<4>" LOC = "T17" ; -#NET "TX<3>" LOC = "W19" ; -#NET "TX<2>" LOC = "V20" ; -#NET "TX<1>" LOC = "Y21" ; -#NET "TX<0>" LOC = "AA22" ; -#NET "TXSYNC" LOC = "U18" ; -#NET "TXBLANK" LOC = "U19" ; - -#NET "PPS_IN" LOC = "M17" ; - -#NET "io_tx<0>" LOC = "AB20" ; -#NET "io_tx<1>" LOC = "Y17" ; -#NET "io_tx<2>" LOC = "Y16" ; -#NET "io_tx<3>" LOC = "U16" ; -#NET "io_tx<4>" LOC = "V16" ; -#NET "io_tx<5>" LOC = "AB19" ; -#NET "io_tx<6>" LOC = "AA19" ; -#NET "io_tx<7>" LOC = "U14" ; -#NET "io_tx<8>" LOC = "U15" ; -#NET "io_tx<9>" LOC = "AB17" ; -#NET "io_tx<10>" LOC = "AB18" ; -#NET "io_tx<11>" LOC = "Y13" ; -#NET "io_tx<12>" LOC = "W14" ; -#NET "io_tx<13>" LOC = "U13" ; -#NET "io_tx<14>" LOC = "AA15" ; -#NET "io_tx<15>" LOC = "AB14" ; - -#NET "io_rx<0>" LOC = "Y8" ; -#NET "io_rx<1>" LOC = "Y9" ; -#NET "io_rx<2>" LOC = "V7" ; -#NET "io_rx<3>" LOC = "U8" ; -#NET "io_rx<4>" LOC = "V10" ; -#NET "io_rx<5>" LOC = "U9" ; -#NET "io_rx<6>" LOC = "AB7" ; -#NET "io_rx<7>" LOC = "AA8" ; -#NET "io_rx<8>" LOC = "W8" ; -#NET "io_rx<9>" LOC = "V8" ; -#NET "io_rx<10>" LOC = "AB5" ; -#NET "io_rx<11>" LOC = "AB6" ; -#NET "io_rx<12>" LOC = "AB4" ; -#NET "io_rx<13>" LOC = "AA4" ; -#NET "io_rx<14>" LOC = "W5" ; -#NET "io_rx<15>" LOC = "Y4" ; - -##NET "CLKOUT2_CODEC" LOC = "U12" ; -##NET "CLKOUT1_CODEC" LOC = "V12" ; - -## FPGA Config Pins -##NET "fpga_cfg_prog_b" LOC = "A2" ; -##NET "fpga_cfg_done" LOC = "AB21" ; +NET "overo_gpio145" LOC = "C7" ; +NET "cgen_mosi" LOC = "E22" ; +NET "cgen_sclk" LOC = "J19" ; +NET "cgen_sen_b" LOC = "H20" ; NET "fpga_cfg_din" LOC = "W17" ; NET "fpga_cfg_cclk" LOC = "V17" ; -##NET "fpga_cfg_init_b" LOC = "W15" ; - -## Unused -##NET "unnamed_net37" LOC = "B1" ; # TMS -##NET "unnamed_net36" LOC = "B22" ; # TDO -##NET "unnamed_net35" LOC = "D2" ; # TDI -##NET "unnamed_net34" LOC = "A21" ; # TCK -##NET "unnamed_net45" LOC = "F7" ; # PUDC_B -##NET "unnamed_net44" LOC = "V6" ; # M2 -##NET "unnamed_net43" LOC = "AA3" ; # M1 -##NET "unnamed_net42" LOC = "AB3" ; # M0 -##NET "GND" LOC = "V19" ; # Suspend, unused -- cgit v1.2.3 From 4a757e64cbb513e6461e547f4d095b0539ae0b09 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 9 Sep 2010 15:55:35 -0400 Subject: Convert fc32_to_item32_nswap to use ARM NEON if available. --- host/lib/transport/CMakeLists.txt | 6 ++++++ host/lib/transport/convert_types_impl.hpp | 24 ++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/host/lib/transport/CMakeLists.txt b/host/lib/transport/CMakeLists.txt index 753fd5e85..43449d732 100644 --- a/host/lib/transport/CMakeLists.txt +++ b/host/lib/transport/CMakeLists.txt @@ -45,6 +45,12 @@ IF(HAVE_EMMINTRIN_H) ADD_DEFINITIONS(-DHAVE_EMMINTRIN_H) ENDIF(HAVE_EMMINTRIN_H) +INCLUDE(CheckIncludeFileCXX) +CHECK_INCLUDE_FILE_CXX(arm_neon.h HAVE_ARM_NEON_H) + +IF(HAVE_ARM_NEON_H) + ADD_DEFINITIONS(-DHAVE_ARM_NEON_H) +ENDIF(HAVE_ARM_NEON_H) ######################################################################## # Setup defines for interface address discovery ######################################################################## diff --git a/host/lib/transport/convert_types_impl.hpp b/host/lib/transport/convert_types_impl.hpp index 90618dec6..6cfc8fed6 100644 --- a/host/lib/transport/convert_types_impl.hpp +++ b/host/lib/transport/convert_types_impl.hpp @@ -32,6 +32,14 @@ #include #endif +#ifdef HAVE_ARM_NEON_H + #define USE_ARM_NEON_H +#endif + +#if defined(USE_ARM_NEON_H) + #include +#endif + /*********************************************************************** * Typedefs **********************************************************************/ @@ -135,6 +143,22 @@ static UHD_INLINE void fc32_to_item32_nswap( } } +#elif defined(USE_ARM_NEON_H) +static UHD_INLINE void fc32_to_item32_nswap( + const fc32_t *input, item32_t *output, size_t nsamps) +{ + size_t i; + + float32x4_t Q0 = vdupq_n_f32(shorts_per_float); + for (i=0; i < (nsamps & ~0x03); i+=4) { + float32x4_t Q1 = vld1q_f32(reinterpret_cast(&input[i])); + float32x4_t Q2 = vmulq_f32(Q1, Q0); + int32x4_t Q3 = vcvtq_s32_f32(Q2); + int16x4_t D8 = vmovn_s32(Q3); + vst1_s16((reinterpret_cast(&output[i])), D8); + } +} + #else static UHD_INLINE void fc32_to_item32_nswap( const fc32_t *input, item32_t *output, size_t nsamps -- cgit v1.2.3 From 08eb9d2937c28edfb6d1fe7fb168ef77727406d5 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 9 Sep 2010 14:19:14 -0700 Subject: updated pins to match rev2, removed dip switch, etc. seems to compile ok. --- usrp2/top/u1e/u1e.ucf | 251 +++++++++++++++++++++++------------------------ usrp2/top/u1e/u1e.v | 8 +- usrp2/top/u1e/u1e_core.v | 8 +- 3 files changed, 130 insertions(+), 137 deletions(-) diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 659a9dce5..51968d24a 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -54,8 +54,10 @@ NET "overo_gpio22" LOC = "A3" ; # MISC GPIO for debug NET "overo_gpio23" LOC = "B3" ; # MISC GPIO for debug NET "overo_gpio64" LOC = "A4" ; # MISC GPIO for debug NET "overo_gpio65" LOC = "F8" ; # MISC GPIO for debug -NET "overo_gpio127" LOC = "C8" ; # MISC GPIO for debug, also used on the passthru image as the cgen_sen_b pin -NET "overo_gpio128" LOC = "G8" ; # MISC GPIO for debug + +NET "overo_gpio127" LOC = "C8" ; # Changed name to gpio10 +NET "overo_gpio128" LOC = "G8" ; # Changed name to gpio186 + NET "overo_gpio144" LOC = "A5" ; # tx_have_space NET "overo_gpio145" LOC = "C7" ; # tx_underrun NET "overo_gpio146" LOC = "A6" ; # rx_have_data @@ -69,146 +71,137 @@ NET "overo_gpio176" LOC = "B4" ; # MISC GPIO for debug #NET "overo_rxd1" LOC = "D6" ; ## FTDI UART to USB converter -NET "FPGA_TXD" LOC = "U1" ; -NET "FPGA_RXD" LOC = "T6" ; +NET "FPGA_TXD" LOC = "G19" ; +NET "FPGA_RXD" LOC = "F20" ; #NET "SYSEN" LOC = "C11" ; ## I2C -NET "db_scl" LOC = "U4" ; -NET "db_sda" LOC = "U5" ; +NET "db_scl" LOC = "F19" ; +NET "db_sda" LOC = "F18" ; ## SPI ### DBoard SPI -NET "db_sclk_rx" LOC = "W3" ; -NET "db_miso_rx" LOC = "W2" ; -NET "db_mosi_rx" LOC = "V4" ; -NET "db_sen_rx" LOC = "V3" ; -NET "db_sclk_tx" LOC = "Y1" ; -NET "db_miso_tx" LOC = "W1" ; -NET "db_mosi_tx" LOC = "R3" ; -NET "db_sen_tx" LOC = "T4" ; +NET "db_sclk_rx" LOC = "D21" ; +NET "db_miso_rx" LOC = "D22" ; +NET "db_mosi_rx" LOC = "D20" ; +NET "db_sen_rx" LOC = "E19" ; +NET "db_sclk_tx" LOC = "F21" ; +NET "db_miso_tx" LOC = "E20" ; +NET "db_mosi_tx" LOC = "G17" ; +NET "db_sen_tx" LOC = "G18" ; ### AD9862 SPI and aux SPI Interfaces -#NET "aux_sdi_codec" LOC = "F19" ; -#NET "aux_sdo_codec" LOC = "F18" ; -#NET "aux_sclk_codec" LOC = "D21" ; -NET "sen_codec" LOC = "D20" ; -NET "mosi_codec" LOC = "E19" ; -NET "miso_codec" LOC = "F21" ; -NET "sclk_codec" LOC = "E20" ; +#NET "aux_sdi_codec" LOC = "G3" ; +#NET "aux_sdo_codec" LOC = "F3" ; +#NET "aux_sclk_codec" LOC = "C1" ; +NET "sen_codec" LOC = "F5" ; +NET "mosi_codec" LOC = "F4" ; +NET "miso_codec" LOC = "H4" ; +NET "sclk_codec" LOC = "H3" ; ### Clock Gen SPI -NET "cgen_miso" LOC = "U2" ; -NET "cgen_mosi" LOC = "V1" ; -NET "cgen_sclk" LOC = "R5" ; -NET "cgen_sen_b" LOC = "T1" ; +NET "cgen_miso" LOC = "F22" ; +NET "cgen_mosi" LOC = "E22" ; +NET "cgen_sclk" LOC = "J19" ; +NET "cgen_sen_b" LOC = "H20" ; ## Clock gen control -NET "cgen_st_status" LOC = "D4" ; -NET "cgen_st_ld" LOC = "D1" ; -NET "cgen_st_refmon" LOC = "E1" ; -NET "cgen_sync_b" LOC = "M1" ; -NET "cgen_ref_sel" LOC = "J1" ; +NET "cgen_st_status" LOC = "P20" ; +NET "cgen_st_ld" LOC = "R17" ; +NET "cgen_st_refmon" LOC = "P17" ; +NET "cgen_sync_b" LOC = "U18" ; +NET "cgen_ref_sel" LOC = "U19" ; ## Debug pins -NET "debug_led<2>" LOC = "T5" ; -NET "debug_led<1>" LOC = "R2" ; -NET "debug_led<0>" LOC = "R1" ; -NET "debug<0>" LOC = "P6" ; -NET "debug<1>" LOC = "R6" ; -NET "debug<2>" LOC = "P1" ; -NET "debug<3>" LOC = "P2" ; -NET "debug<4>" LOC = "N6" ; -NET "debug<5>" LOC = "N5" ; -NET "debug<6>" LOC = "N1" ; -NET "debug<7>" LOC = "K2" ; -NET "debug<8>" LOC = "K3" ; -NET "debug<9>" LOC = "K6" ; -NET "debug<10>" LOC = "L5" ; -NET "debug<11>" LOC = "H2" ; -NET "debug<12>" LOC = "K4" ; -NET "debug<13>" LOC = "K5" ; -NET "debug<14>" LOC = "G1" ; -NET "debug<15>" LOC = "H1" ; -NET "debug<16>" LOC = "H5" ; -NET "debug<17>" LOC = "H6" ; -NET "debug<18>" LOC = "E3" ; -NET "debug<19>" LOC = "E4" ; -NET "debug<20>" LOC = "G5" ; -NET "debug<21>" LOC = "G6" ; -NET "debug<22>" LOC = "F2" ; -NET "debug<23>" LOC = "F1" ; -NET "debug<24>" LOC = "H3" ; -NET "debug<25>" LOC = "H4" ; -NET "debug<26>" LOC = "F4" ; -NET "debug<27>" LOC = "F5" ; -NET "debug<28>" LOC = "C2" ; -NET "debug<29>" LOC = "C1" ; -NET "debug<30>" LOC = "F3" ; -NET "debug<31>" LOC = "G3" ; -NET "debug_clk<0>" LOC = "L6" ; -NET "debug_clk<1>" LOC = "M5" ; +NET "debug_led<3>" LOC = "Y15" ; +NET "debug_led<2>" LOC = "K16" ; +NET "debug_led<1>" LOC = "J17" ; +NET "debug_led<0>" LOC = "H22" ; +NET "debug<0>" LOC = "G22" ; +NET "debug<1>" LOC = "H17" ; +NET "debug<2>" LOC = "H18" ; +NET "debug<3>" LOC = "K20" ; +NET "debug<4>" LOC = "J20" ; +NET "debug<5>" LOC = "K19" ; +NET "debug<6>" LOC = "K18" ; +NET "debug<7>" LOC = "L22" ; +NET "debug<8>" LOC = "K22" ; +NET "debug<9>" LOC = "N22" ; +NET "debug<10>" LOC = "M22" ; +NET "debug<11>" LOC = "N20" ; +NET "debug<12>" LOC = "N19" ; +NET "debug<13>" LOC = "R22" ; +NET "debug<14>" LOC = "P22" ; +NET "debug<15>" LOC = "N17" ; +NET "debug<16>" LOC = "P16" ; +NET "debug<17>" LOC = "U22" ; +NET "debug<18>" LOC = "P19" ; +NET "debug<19>" LOC = "R18" ; +NET "debug<20>" LOC = "U20" ; +NET "debug<21>" LOC = "T20" ; +NET "debug<22>" LOC = "R19" ; +NET "debug<23>" LOC = "R20" ; +NET "debug<24>" LOC = "W22" ; +NET "debug<25>" LOC = "Y22" ; +NET "debug<26>" LOC = "T18" ; +NET "debug<27>" LOC = "T17" ; +NET "debug<28>" LOC = "W19" ; +NET "debug<29>" LOC = "V20" ; +NET "debug<30>" LOC = "Y21" ; +NET "debug<31>" LOC = "AA22" ; +NET "debug_clk<0>" LOC = "N18" ; +NET "debug_clk<1>" LOC = "M17" ; -NET "debug_pb<2>" LOC = "Y2" ; -NET "debug_pb<1>" LOC = "AA1" ; -NET "debug_pb<0>" LOC = "N3" ; +NET "debug_pb" LOC = "C22" ; -NET "dip_sw<7>" LOC = "T3" ; -NET "dip_sw<6>" LOC = "U3" ; -NET "dip_sw<5>" LOC = "M3" ; -NET "dip_sw<4>" LOC = "N4" ; -NET "dip_sw<3>" LOC = "J3" ; -NET "dip_sw<2>" LOC = "J4" ; -NET "dip_sw<1>" LOC = "J6" ; -NET "dip_sw<0>" LOC = "J7" ; +#NET "reset_codec" LOC = "C2" ; -#NET "reset_codec" LOC = "D22" ; +NET "RXSYNC" LOC = "F2" ; +NET "DB<11>" LOC = "G6" ; +NET "DB<10>" LOC = "G5" ; +NET "DB<9>" LOC = "E4" ; +NET "DB<8>" LOC = "E3" ; +NET "DB<7>" LOC = "H6" ; +NET "DB<6>" LOC = "H5" ; +NET "DB<5>" LOC = "H1" ; +NET "DB<4>" LOC = "G1" ; +NET "DB<3>" LOC = "K5" ; +NET "DB<2>" LOC = "K4" ; +NET "DB<1>" LOC = "H2" ; +NET "DB<0>" LOC = "L5" ; -NET "RXSYNC" LOC = "F22" ; -NET "DB<11>" LOC = "E22" ; -NET "DB<10>" LOC = "J19" ; -NET "DB<9>" LOC = "H20" ; -NET "DB<8>" LOC = "G19" ; -NET "DB<7>" LOC = "F20" ; -NET "DB<6>" LOC = "K16" ; -NET "DB<5>" LOC = "J17" ; -NET "DB<4>" LOC = "H22" ; -NET "DB<3>" LOC = "G22" ; -NET "DB<2>" LOC = "H17" ; -NET "DB<1>" LOC = "H18" ; -NET "DB<0>" LOC = "K20" ; -NET "DA<11>" LOC = "J20" ; -NET "DA<10>" LOC = "K19" ; -NET "DA<9>" LOC = "K18" ; -NET "DA<8>" LOC = "L22" ; -NET "DA<7>" LOC = "K22" ; -NET "DA<6>" LOC = "N22" ; -NET "DA<5>" LOC = "M22" ; -NET "DA<4>" LOC = "N20" ; -NET "DA<3>" LOC = "N19" ; -NET "DA<2>" LOC = "R22" ; -NET "DA<1>" LOC = "P22" ; -NET "DA<0>" LOC = "N17" ; +NET "DA<11>" LOC = "K6" ; +NET "DA<10>" LOC = "K3" ; +NET "DA<9>" LOC = "K2" ; +NET "DA<8>" LOC = "N1" ; +NET "DA<7>" LOC = "N5" ; +NET "DA<6>" LOC = "N6" ; +NET "DA<5>" LOC = "P2" ; +NET "DA<4>" LOC = "P1" ; +NET "DA<3>" LOC = "R6" ; +NET "DA<2>" LOC = "P6" ; +NET "DA<1>" LOC = "R1" ; +NET "DA<0>" LOC = "R2" ; -NET "TX<13>" LOC = "P19" ; -NET "TX<12>" LOC = "R18" ; -NET "TX<11>" LOC = "U20" ; -NET "TX<10>" LOC = "T20" ; -NET "TX<9>" LOC = "R19" ; -NET "TX<8>" LOC = "R20" ; -NET "TX<7>" LOC = "W22" ; -NET "TX<6>" LOC = "Y22" ; -NET "TX<5>" LOC = "T18" ; -NET "TX<4>" LOC = "T17" ; -NET "TX<3>" LOC = "W19" ; -NET "TX<2>" LOC = "V20" ; -NET "TX<1>" LOC = "Y21" ; -NET "TX<0>" LOC = "AA22" ; -NET "TXSYNC" LOC = "U18" ; -NET "TXBLANK" LOC = "U19" ; +NET "TX<13>" LOC = "T6" ; +NET "TX<12>" LOC = "U1" ; +NET "TX<11>" LOC = "T1" ; +NET "TX<10>" LOC = "R5" ; +NET "TX<9>" LOC = "V1" ; +NET "TX<8>" LOC = "U2" ; +NET "TX<7>" LOC = "T4" ; +NET "TX<6>" LOC = "R3" ; +NET "TX<5>" LOC = "W1" ; +NET "TX<4>" LOC = "Y1" ; +NET "TX<3>" LOC = "V3" ; +NET "TX<2>" LOC = "V4" ; +NET "TX<1>" LOC = "W2" ; +NET "TX<0>" LOC = "W3" ; +NET "TXSYNC" LOC = "U5" ; +NET "TXBLANK" LOC = "U4" ; -NET "PPS_IN" LOC = "M17" ; +NET "PPS_IN" LOC = "M5" ; NET "io_tx<0>" LOC = "AB20" ; NET "io_tx<1>" LOC = "Y17" ; @@ -255,12 +248,12 @@ NET "io_rx<15>" LOC = "Y4" ; #NET "fpga_cfg_init_b" LOC = "W15" ; ## Unused -#NET "unnamed_net37" LOC = "B1" ; # TMS -#NET "unnamed_net36" LOC = "B22" ; # TDO -#NET "unnamed_net35" LOC = "D2" ; # TDI -#NET "unnamed_net34" LOC = "A21" ; # TCK -#NET "unnamed_net45" LOC = "F7" ; # PUDC_B -#NET "unnamed_net44" LOC = "V6" ; # M2 -#NET "unnamed_net43" LOC = "AA3" ; # M1 -#NET "unnamed_net42" LOC = "AB3" ; # M0 +#NET "unnamed_net53" LOC = "B1" ; # TMS +#NET "unnamed_net52" LOC = "B22" ; # TDO +#NET "unnamed_net51" LOC = "D2" ; # TDI +#NET "unnamed_net50" LOC = "A21" ; # TCK +#NET "unnamed_net59" LOC = "F7" ; # PUDC_B +#NET "unnamed_net58" LOC = "V6" ; # M2 +#NET "unnamed_net57" LOC = "AA3" ; # M1 +#NET "unnamed_net56" LOC = "AB3" ; # M0 #NET "GND" LOC = "V19" ; # Suspend, unused diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 9536b5ced..7ddbfd537 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -5,8 +5,8 @@ module u1e (input CLK_FPGA_P, input CLK_FPGA_N, // Diff - output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - input [2:0] debug_pb, input [7:0] dip_sw, output FPGA_TXD, input FPGA_RXD, + output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + input debug_pb, output FPGA_TXD, input FPGA_RXD, // GPMC input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, @@ -137,9 +137,9 @@ module u1e // ///////////////////////////////////////////////////////////////////////// // Main U1E Core - u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb[2]), + u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), - .debug_pb(~debug_pb), .dip_sw(dip_sw), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), + .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 5c4b6de6c..42333a722 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -6,8 +6,8 @@ module u1e_core (input clk_fpga, input rst_fpga, - output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - input [2:0] debug_pb, input [7:0] dip_sw, output debug_txd, input debug_rxd, + output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + output debug_txd, input debug_rxd, // GPMC input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, @@ -343,11 +343,11 @@ module u1e_core assign rx_enable = xfer_rate[14]; assign rate = xfer_rate[7:0]; - assign { debug_led[2],debug_led[0],debug_led[1] } = {run_rx,run_tx,reg_leds[0]}; // LEDs are arranged funny on board + assign { debug_led[3:0] } = {run_rx,run_tx,reg_leds[1:0]}; assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : - (s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} : + (s0_adr[6:0] == REG_SWITCHES) ? { 16'd0 } : (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : (s0_adr[6:0] == REG_TEST) ? reg_test : -- cgit v1.2.3 From f0db419b8c6366503542c3e97f8556bbb6ca94cd Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 9 Sep 2010 16:27:53 -0700 Subject: usrp-e: typo fix for ad9522 regs size --- host/lib/ic_reg_maps/gen_ad9522_regs.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/host/lib/ic_reg_maps/gen_ad9522_regs.py b/host/lib/ic_reg_maps/gen_ad9522_regs.py index ed6b5f48d..a5debe568 100755 --- a/host/lib/ic_reg_maps/gen_ad9522_regs.py +++ b/host/lib/ic_reg_maps/gen_ad9522_regs.py @@ -134,8 +134,8 @@ reg2eeprom 0xB03[0] 0 # Template for methods in the body of the struct ######################################################################## BODY_TMPL="""\ -boost::uint8_t get_reg(boost::uint16_t addr){ - boost::uint8_t reg = 0; +boost::uint32_t get_reg(boost::uint16_t addr){ + boost::uint32_t reg = 0; switch(addr){ #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) case $addr: @@ -154,7 +154,7 @@ boost::uint8_t get_reg(boost::uint16_t addr){ return reg; } -void set_reg(boost::uint8_t addr, boost::uint32_t reg){ +void set_reg(boost::uint16_t addr, boost::uint32_t reg){ switch(addr){ #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs))) case $addr: -- cgit v1.2.3 From bc824badaa981c1785d8c76d7cf56274d7c582b8 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 9 Sep 2010 16:28:37 -0700 Subject: usrp-e: configure flag option for usrp-e support --- host/lib/usrp/usrp_e/CMakeLists.txt | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/host/lib/usrp/usrp_e/CMakeLists.txt b/host/lib/usrp/usrp_e/CMakeLists.txt index f0c125f26..da759d931 100644 --- a/host/lib/usrp/usrp_e/CMakeLists.txt +++ b/host/lib/usrp/usrp_e/CMakeLists.txt @@ -25,7 +25,18 @@ MESSAGE(STATUS "Configuring usrp-e support...") INCLUDE(CheckIncludeFileCXX) CHECK_INCLUDE_FILE_CXX(linux/usrp_e.h HAVE_LINUX_USRP_E_H) -IF(HAVE_LINUX_USRP_E_H) +IF(DEFINED ENABLE_USRP_E) + IF(ENABLE_USRP_E) + MESSAGE(STATUS "USRP-E support enabled by configure flag") + ELSE(ENABLE_USRP_E) + MESSAGE(STATUS "USRP-E support disabled by configure flag") + ENDIF(ENABLE_USRP_E) +ELSE(DEFINED ENABLE_USRP_E) #not defined: automatic enabling of component + SET(ENABLE_USRP_E ${HAVE_LINUX_USRP_E_H}) +ENDIF(DEFINED ENABLE_USRP_E) +SET(ENABLE_USRP_E ${ENABLE_USRP_E} CACHE BOOL "enable USRP-E support") + +IF(ENABLE_USRP_E) MESSAGE(STATUS " Building usrp-e support.") LIBUHD_APPEND_SOURCES( ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/clock_ctrl.cpp @@ -45,6 +56,6 @@ IF(HAVE_LINUX_USRP_E_H) ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_iface.hpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_regs.hpp ) -ELSE(HAVE_LINUX_USRP_E_H) +ELSE(ENABLE_USRP_E) MESSAGE(STATUS " Skipping usrp-e support.") -ENDIF(HAVE_LINUX_USRP_E_H) +ENDIF(ENABLE_USRP_E) -- cgit v1.2.3 From d1a327862292d52d659b117aef28e37d9f60fb4b Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 9 Sep 2010 19:30:02 -0400 Subject: Restore tx and rx timed smaple programs to the versions in master. They use floating point. --- host/examples/rx_timed_samples.cpp | 6 +++--- host/examples/tx_timed_samples.cpp | 9 +++------ 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/host/examples/rx_timed_samples.cpp b/host/examples/rx_timed_samples.cpp index 5fbf8b6c5..4856f6779 100644 --- a/host/examples/rx_timed_samples.cpp +++ b/host/examples/rx_timed_samples.cpp @@ -85,12 +85,12 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ //loop until total number of samples reached size_t num_acc_samps = 0; //number of accumulated samples - uhd::rx_metadata_t md; - std::vector > buff(dev->get_max_recv_samps_per_packet()); while(num_acc_samps < total_num_samps){ + uhd::rx_metadata_t md; + std::vector > buff(dev->get_max_recv_samps_per_packet()); size_t num_rx_samps = dev->recv( &buff.front(), buff.size(), md, - uhd::io_type_t::COMPLEX_INT16, + uhd::io_type_t::COMPLEX_FLOAT32, uhd::device::RECV_MODE_ONE_PACKET ); diff --git a/host/examples/tx_timed_samples.cpp b/host/examples/tx_timed_samples.cpp index f7d7ea2ca..5b72bd72f 100644 --- a/host/examples/tx_timed_samples.cpp +++ b/host/examples/tx_timed_samples.cpp @@ -35,7 +35,6 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ size_t samps_per_packet; double tx_rate, freq; float ampl; - float tx_gain; //setup the program options po::options_description desc("Allowed options"); @@ -48,7 +47,6 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ ("txrate", po::value(&tx_rate)->default_value(100e6/16), "rate of outgoing samples") ("freq", po::value(&freq)->default_value(0), "rf center frequency in Hz") ("ampl", po::value(&l)->default_value(float(0.3)), "amplitude of each sample") - ("gain", po::value(&tx_gain)->default_value(float(0)), "TX Gain setting") ("dilv", "specify to disable inner-loop verbose") ; po::variables_map vm; @@ -77,16 +75,15 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ std::cout << boost::format("Setting device timestamp to 0...") << std::endl; sdev->set_tx_freq(freq); sdev->set_time_now(uhd::time_spec_t(0.0)); - sdev->set_tx_gain(tx_gain); //allocate data to send - std::vector > buff(samps_per_packet, std::complex(ampl, ampl)); - uhd::tx_metadata_t md; + std::vector > buff(samps_per_packet, std::complex(ampl, ampl)); //send the data in multiple packets size_t num_packets = (total_num_samps+samps_per_packet-1)/samps_per_packet; for (size_t i = 0; i < num_packets; i++){ //setup the metadata flags and time spec + uhd::tx_metadata_t md; md.start_of_burst = true; //always SOB (good for continuous streaming) md.end_of_burst = (i == num_packets-1); //only last packet has EOB md.has_time_spec = (i == 0); //only first packet has time @@ -97,7 +94,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ //send the entire packet (driver fragments internally) size_t num_tx_samps = dev->send( &buff.front(), samps_to_send, md, - uhd::io_type_t::COMPLEX_INT16, + uhd::io_type_t::COMPLEX_FLOAT32, uhd::device::SEND_MODE_FULL_BUFF ); if(verbose) std::cout << std::endl << boost::format("Sent %d samples") % num_tx_samps << std::endl; -- cgit v1.2.3 From 93b77c39985f63dffcca3ef569aee8ee45708a1f Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 9 Sep 2010 19:30:50 -0400 Subject: Allow programs to find usrp_e.h header, even if it is not installed in /usr/include/linux. --- host/include/linux/usrp_e.h | 88 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 host/include/linux/usrp_e.h diff --git a/host/include/linux/usrp_e.h b/host/include/linux/usrp_e.h new file mode 100644 index 000000000..b098ad114 --- /dev/null +++ b/host/include/linux/usrp_e.h @@ -0,0 +1,88 @@ + +/* + * Copyright (C) 2010 Ettus Research, LLC + * + * Written by Philip Balister + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __USRP_E_H +#define __USRP_E_H + +#include +#include + +struct usrp_e_ctl16 { + __u32 offset; + __u32 count; + __u16 buf[20]; +}; + +struct usrp_e_ctl32 { + __u32 offset; + __u32 count; + __u32 buf[10]; +}; + +/* SPI interface */ + +#define UE_SPI_TXONLY 0 +#define UE_SPI_TXRX 1 + +/* Defines for spi ctrl register */ +#define UE_SPI_CTRL_TXNEG (1 << 10) +#define UE_SPI_CTRL_RXNEG (1 << 9) + +#define UE_SPI_PUSH_RISE 0 +#define UE_SPI_PUSH_FALL UE_SPI_CTRL_TXNEG +#define UE_SPI_LATCH_RISE 0 +#define UE_SPI_LATCH_FALL UE_SPI_CTRL_RXNEG + +struct usrp_e_spi { + __u8 readback; + __u32 slave; + __u32 data; + __u32 length; + __u32 flags; +}; + +struct usrp_e_i2c { + __u8 addr; + __u32 len; + __u8 data[]; +}; + +#define USRP_E_IOC_MAGIC 'u' +#define USRP_E_WRITE_CTL16 _IOW(USRP_E_IOC_MAGIC, 0x20, struct usrp_e_ctl16) +#define USRP_E_READ_CTL16 _IOWR(USRP_E_IOC_MAGIC, 0x21, struct usrp_e_ctl16) +#define USRP_E_WRITE_CTL32 _IOW(USRP_E_IOC_MAGIC, 0x22, struct usrp_e_ctl32) +#define USRP_E_READ_CTL32 _IOWR(USRP_E_IOC_MAGIC, 0x23, struct usrp_e_ctl32) +#define USRP_E_SPI _IOWR(USRP_E_IOC_MAGIC, 0x24, struct usrp_e_spi) +#define USRP_E_I2C_READ _IOWR(USRP_E_IOC_MAGIC, 0x25, struct usrp_e_i2c) +#define USRP_E_I2C_WRITE _IOW(USRP_E_IOC_MAGIC, 0x26, struct usrp_e_i2c) + +/* Data transfer frame definition */ + +struct usrp_transfer_frame { + __u32 status; + __u32 len; + __u8 buf[]; +}; + +/* Flag defines */ +#define RB_USER (1 << 0) +#define RB_KERNEL (1 << 1) +#define RB_OVERRUN (1 << 2) +#define RB_DMA_ACTIVE (1 << 3) + +struct ring_buffer_entry { + unsigned int flags; + unsigned long dma_addr; + struct usrp_transfer_frame *frame_addr; +}; + +#endif -- cgit v1.2.3 From 09a1b77a65202e6c569be7e1b31d9d453ef388a2 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 9 Sep 2010 20:40:55 -0400 Subject: Fix errors. --- host/lib/transport/convert_types_impl.hpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/host/lib/transport/convert_types_impl.hpp b/host/lib/transport/convert_types_impl.hpp index 6cfc8fed6..04e6fc81a 100644 --- a/host/lib/transport/convert_types_impl.hpp +++ b/host/lib/transport/convert_types_impl.hpp @@ -150,13 +150,16 @@ static UHD_INLINE void fc32_to_item32_nswap( size_t i; float32x4_t Q0 = vdupq_n_f32(shorts_per_float); - for (i=0; i < (nsamps & ~0x03); i+=4) { + for (i=0; i < (nsamps & ~0x03); i+=2) { float32x4_t Q1 = vld1q_f32(reinterpret_cast(&input[i])); float32x4_t Q2 = vmulq_f32(Q1, Q0); int32x4_t Q3 = vcvtq_s32_f32(Q2); int16x4_t D8 = vmovn_s32(Q3); vst1_s16((reinterpret_cast(&output[i])), D8); } + + for (; i < nsamps; i++) + output[i] = fc32_to_item32(input[i]); } #else -- cgit v1.2.3 From 136e507182085fc5e666c08a0099103caba19c24 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Fri, 10 Sep 2010 10:07:37 -0400 Subject: Install main_test so we can test cross compiled uhd. --- host/test/CMakeLists.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/host/test/CMakeLists.txt b/host/test/CMakeLists.txt index c620fd641..0d4607f68 100644 --- a/host/test/CMakeLists.txt +++ b/host/test/CMakeLists.txt @@ -40,3 +40,8 @@ ADD_TEST(test main_test) # demo of a loadable module ######################################################################## ADD_LIBRARY(module_test MODULE module_test.cpp) + +INSTALL(TARGETS + main_test + RUNTIME DESTINATION ${PKG_DATA_DIR}/tests +) -- cgit v1.2.3 From a845814e3e648e5625649c2f34f462bc29641fa7 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Fri, 10 Sep 2010 15:47:20 -0400 Subject: Reverse I and Q on the wire. --- host/lib/transport/convert_types_impl.hpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/host/lib/transport/convert_types_impl.hpp b/host/lib/transport/convert_types_impl.hpp index 04e6fc81a..b9a47eb0e 100644 --- a/host/lib/transport/convert_types_impl.hpp +++ b/host/lib/transport/convert_types_impl.hpp @@ -155,7 +155,8 @@ static UHD_INLINE void fc32_to_item32_nswap( float32x4_t Q2 = vmulq_f32(Q1, Q0); int32x4_t Q3 = vcvtq_s32_f32(Q2); int16x4_t D8 = vmovn_s32(Q3); - vst1_s16((reinterpret_cast(&output[i])), D8); + int16x4_t D9 = vrev32_s16(D8); + vst1_s16((reinterpret_cast(&output[i])), D9); } for (; i < nsamps; i++) -- cgit v1.2.3 From f177ce94fb4d4d2bdb19339c24bf5dc6035f1411 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 16 Sep 2010 14:01:43 -0700 Subject: send all gpmc signals to mictor --- usrp2/top/u1e_ethdebug/.gitignore | 6 +++ usrp2/top/u1e_ethdebug/Makefile | 83 +++++++++++++++++++++++++++++++++++++ usrp2/top/u1e_ethdebug/u1e.ucf | 86 +++++++++++++++++++++++++++++++++++++++ usrp2/top/u1e_ethdebug/u1e.v | 26 ++++++++++++ 4 files changed, 201 insertions(+) create mode 100644 usrp2/top/u1e_ethdebug/.gitignore create mode 100644 usrp2/top/u1e_ethdebug/Makefile create mode 100644 usrp2/top/u1e_ethdebug/u1e.ucf create mode 100644 usrp2/top/u1e_ethdebug/u1e.v diff --git a/usrp2/top/u1e_ethdebug/.gitignore b/usrp2/top/u1e_ethdebug/.gitignore new file mode 100644 index 000000000..8d872713e --- /dev/null +++ b/usrp2/top/u1e_ethdebug/.gitignore @@ -0,0 +1,6 @@ +*~ +build +*.log +*.cmd +tb_u1e +*.lxt diff --git a/usrp2/top/u1e_ethdebug/Makefile b/usrp2/top/u1e_ethdebug/Makefile new file mode 100644 index 000000000..751b52970 --- /dev/null +++ b/usrp2/top/u1e_ethdebug/Makefile @@ -0,0 +1,83 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u1e +BUILD_DIR = $(abspath build$(ISE)) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u1e.v \ +u1e.ucf + +SOURCES = $(abspath $(TOP_SRCS)) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +SIM_MODEL_PROPERTIES = "" diff --git a/usrp2/top/u1e_ethdebug/u1e.ucf b/usrp2/top/u1e_ethdebug/u1e.ucf new file mode 100644 index 000000000..0d4384a2a --- /dev/null +++ b/usrp2/top/u1e_ethdebug/u1e.ucf @@ -0,0 +1,86 @@ + +## GPMC +NET "EM_D<15>" LOC = "D13" ; +NET "EM_D<14>" LOC = "D15" ; +NET "EM_D<13>" LOC = "C16" ; +NET "EM_D<12>" LOC = "B20" ; +NET "EM_D<11>" LOC = "A19" ; +NET "EM_D<10>" LOC = "A17" ; +NET "EM_D<9>" LOC = "E15" ; +NET "EM_D<8>" LOC = "F15" ; +NET "EM_D<7>" LOC = "E16" ; +NET "EM_D<6>" LOC = "F16" ; +NET "EM_D<5>" LOC = "B17" ; +NET "EM_D<4>" LOC = "C17" ; +NET "EM_D<3>" LOC = "B19" ; +NET "EM_D<2>" LOC = "D19" ; +NET "EM_D<1>" LOC = "C19" ; +NET "EM_D<0>" LOC = "A20" ; + +NET "EM_A<10>" LOC = "C14" ; +NET "EM_A<9>" LOC = "C10" ; +NET "EM_A<8>" LOC = "C5" ; +NET "EM_A<7>" LOC = "A18" ; +NET "EM_A<6>" LOC = "A15" ; +NET "EM_A<5>" LOC = "A12" ; +NET "EM_A<4>" LOC = "A10" ; +NET "EM_A<3>" LOC = "E7" ; +NET "EM_A<2>" LOC = "A7" ; +NET "EM_A<1>" LOC = "C15" ; + +NET "EM_NCS6" LOC = "E17" ; +NET "EM_NCS5" LOC = "E10" ; +NET "EM_NCS4" LOC = "E6" ; +#NET "EM_NCS1" LOC = "D18" ; +#NET "EM_NCS0" LOC = "D17" ; + +NET "EM_CLK" LOC = "F11" ; +NET "EM_WAIT0" LOC = "F14" ; +NET "EM_NBE<1>" LOC = "D14" ; +NET "EM_NBE<0>" LOC = "A13" ; +NET "EM_NWE" LOC = "B13" ; +NET "EM_NOE" LOC = "A14" ; +NET "EM_NADV_ALE" LOC = "B15" ; +NET "EM_NWP" LOC = "F13" ; + +## Debug pins +NET "debug_led<3>" LOC = "Y15" ; +NET "debug_led<2>" LOC = "K16" ; +NET "debug_led<1>" LOC = "J17" ; +NET "debug_led<0>" LOC = "H22" ; +NET "debug<0>" LOC = "G22" ; +NET "debug<1>" LOC = "H17" ; +NET "debug<2>" LOC = "H18" ; +NET "debug<3>" LOC = "K20" ; +NET "debug<4>" LOC = "J20" ; +NET "debug<5>" LOC = "K19" ; +NET "debug<6>" LOC = "K18" ; +NET "debug<7>" LOC = "L22" ; +NET "debug<8>" LOC = "K22" ; +NET "debug<9>" LOC = "N22" ; +NET "debug<10>" LOC = "M22" ; +NET "debug<11>" LOC = "N20" ; +NET "debug<12>" LOC = "N19" ; +NET "debug<13>" LOC = "R22" ; +NET "debug<14>" LOC = "P22" ; +NET "debug<15>" LOC = "N17" ; +NET "debug<16>" LOC = "P16" ; +NET "debug<17>" LOC = "U22" ; +NET "debug<18>" LOC = "P19" ; +NET "debug<19>" LOC = "R18" ; +NET "debug<20>" LOC = "U20" ; +NET "debug<21>" LOC = "T20" ; +NET "debug<22>" LOC = "R19" ; +NET "debug<23>" LOC = "R20" ; +NET "debug<24>" LOC = "W22" ; +NET "debug<25>" LOC = "Y22" ; +NET "debug<26>" LOC = "T18" ; +NET "debug<27>" LOC = "T17" ; +NET "debug<28>" LOC = "W19" ; +NET "debug<29>" LOC = "V20" ; +NET "debug<30>" LOC = "Y21" ; +NET "debug<31>" LOC = "AA22" ; +NET "debug_clk<0>" LOC = "N18" ; +NET "debug_clk<1>" LOC = "M17" ; + +NET "debug_pb" LOC = "C22" ; diff --git a/usrp2/top/u1e_ethdebug/u1e.v b/usrp2/top/u1e_ethdebug/u1e.v new file mode 100644 index 000000000..c4740b941 --- /dev/null +++ b/usrp2/top/u1e_ethdebug/u1e.v @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +//`define DCM 1 + +module u1e + (output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + input debug_pb, + + // GPMC + input EM_CLK, input [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, input EM_NWE, input EM_NOE, + input EM_NADV_ALE, input EM_NWP + ); + + assign debug_clk = {EM_CLK, EM_NADV_ALE}; + + assign debug_led = {EM_NWP, EM_A[9], EM_A[8], debug_pb}; + + assign debug = { { EM_NBE[1:0], EM_WAIT0, EM_NCS4, EM_NCS5, EM_NCS6, EM_NWE, EM_NOE }, + { EM_A[10], EM_A[7:1] }, + { EM_D[15:8] }, + { EM_D[7:0] } }; + + +endmodule // u1e -- cgit v1.2.3 From 7888b861d51fc612abe4c28a2f05c83df7ec1cb1 Mon Sep 17 00:00:00 2001 From: root Date: Mon, 20 Sep 2010 20:31:52 +0000 Subject: Fix really dumb mistake in rad ring buffer code. Add/comment debug lines. --- host/apps/omap_debug/usrp-e-mm-loopback.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-mm-loopback.c b/host/apps/omap_debug/usrp-e-mm-loopback.c index 722d09825..7a1747f9b 100644 --- a/host/apps/omap_debug/usrp-e-mm-loopback.c +++ b/host/apps/omap_debug/usrp-e-mm-loopback.c @@ -72,14 +72,14 @@ static void *read_thread(void *threadid) while (1) { if (!((*rxi)[rb_read].flags & RB_USER)) { - printf("Waiting for data\n"); +// printf("Waiting for data\n"); struct pollfd pfd; pfd.fd = fp; pfd.events = POLLIN; ssize_t ret = poll(&pfd, 1, -1); } - printf("pkt received, rb_read = %d\n", rb_read); +// printf("pkt received, rb_read = %d\n", rb_read); cnt = (*rxi)[rb_read].len; p = &(*rx_buf)[rb_read]; @@ -88,7 +88,7 @@ static void *read_thread(void *threadid) // if (cnt < 0) // printf("Error returned from read: %d, sequence number = %d\n", cnt, p->seq_num); - printf("p = %X, p->seq_num = %d p->len = %d\n", p, p->seq_num, p->len); +// printf("p = %X, p->seq_num = %d p->len = %d\n", p, p->seq_num, p->len); pkt_count++; @@ -96,6 +96,8 @@ static void *read_thread(void *threadid) if (p->seq_num != prev_seq_num + 1) { printf("Sequence number fail, current = %d, previous = %d, pkt_count = %d\n", p->seq_num, prev_seq_num, pkt_count); + printf("pkt received, rb_read = %d\n", rb_read); + printf("p = %X, p->seq_num = %d p->len = %d\n", p, p->seq_num, p->len); seq_num_failure ++; if (seq_num_failure > 2) @@ -113,7 +115,7 @@ static void *read_thread(void *threadid) (*rxi)[rb_read].flags = RB_KERNEL; rb_read++; - if (rb_read == 200) + if (rb_read == 100) rb_read = 0; bytes_transfered += cnt; -- cgit v1.2.3 From d4a80a2b93a13dc371ef100df962ba99c53a9bb9 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Tue, 21 Sep 2010 13:33:51 +0000 Subject: Fix ring buffer size calculation. --- host/apps/omap_debug/usrp-e-mm-loopback.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-mm-loopback.c b/host/apps/omap_debug/usrp-e-mm-loopback.c index 7a1747f9b..71519d535 100644 --- a/host/apps/omap_debug/usrp-e-mm-loopback.c +++ b/host/apps/omap_debug/usrp-e-mm-loopback.c @@ -194,18 +194,18 @@ int main(int argc, char *argv[]) fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); - rb = mmap(0, 202 * 4096, PROT_READ|PROT_WRITE, MAP_SHARED, fp, 0); + rb = mmap(0, 102 * 4096, PROT_READ|PROT_WRITE, MAP_SHARED, fp, 0); if (rb == MAP_FAILED) { perror("mmap failed"); - exit; + return -1; } printf("rb = %X\n", rb); rxi = rb; rx_buf = rb + 4096; - txi = rb + 4096 + 4096 * 200; - tx_buf = rb + 4096 * 2 + 4096 * 200; + txi = rb + 4096 + 4096 * 100; + tx_buf = rb + 4096 * 2 + 4096 * 100; printf("rxi = %X, rx_buf = %X, txi = %X, tx_buf = %X\n", rxi, rx_buf, txi, tx_buf); -- cgit v1.2.3 From d6c4fbb29e818aec79864d25a0d308decb0db92d Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Tue, 21 Sep 2010 18:07:25 +0000 Subject: Read the ring buffer size from the kernel and use that to set up the structures that read and write the ring buffer. --- host/apps/omap_debug/usrp-e-mm-loopback.c | 27 +++++++++++++++--------- host/apps/omap_debug/usrp_e.h | 35 +++++++++++++++---------------- host/include/linux/usrp_e.h | 35 +++++++++++++++---------------- 3 files changed, 51 insertions(+), 46 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-mm-loopback.c b/host/apps/omap_debug/usrp-e-mm-loopback.c index 71519d535..a1da926a2 100644 --- a/host/apps/omap_debug/usrp-e-mm-loopback.c +++ b/host/apps/omap_debug/usrp-e-mm-loopback.c @@ -1,5 +1,6 @@ #include #include +#include #include #include #include @@ -20,12 +21,6 @@ struct pkt { short data[1024-6]; }; -/* delete after usrp_e.h updated */ -struct ring_buffer_info { - int flags; - int len; -}; - struct ring_buffer_info (*rxi)[]; struct ring_buffer_info (*txi)[]; struct pkt (*rx_buf)[200]; @@ -182,6 +177,8 @@ int main(int argc, char *argv[]) struct sched_param s = { .sched_priority = 1 }; + struct usrp_e_ring_buffer_size_t rb_size; + int ret, map_size, page_size; void *rb; if (argc < 2) { @@ -194,7 +191,14 @@ int main(int argc, char *argv[]) fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); - rb = mmap(0, 102 * 4096, PROT_READ|PROT_WRITE, MAP_SHARED, fp, 0); + page_size = getpagesize(); + + ret = ioctl(fp, USRP_E_GET_RB_INFO, &rb_size); + + map_size = (rb_size.num_pages_rx_flags + rb_size.num_pages_tx_flags) * page_size + + (rb_size.num_rx_frames + rb_size.num_tx_frames) * (page_size >> 1); + + rb = mmap(0, map_size, PROT_READ|PROT_WRITE, MAP_SHARED, fp, 0); if (rb == MAP_FAILED) { perror("mmap failed"); return -1; @@ -203,9 +207,12 @@ int main(int argc, char *argv[]) printf("rb = %X\n", rb); rxi = rb; - rx_buf = rb + 4096; - txi = rb + 4096 + 4096 * 100; - tx_buf = rb + 4096 * 2 + 4096 * 100; + rx_buf = rb + (rb_size.num_pages_rx_flags * page_size); + txi = rb + (rb_size.num_pages_rx_flags * page_size) + + (rb_size.num_rx_frames * page_size >> 1); + tx_buf = rb + (rb_size.num_pages_rx_flags * page_size) + + (rb_size.num_rx_frames * page_size >> 1) + + (rb_size.num_pages_tx_flags * page_size); printf("rxi = %X, rx_buf = %X, txi = %X, tx_buf = %X\n", rxi, rx_buf, txi, tx_buf); diff --git a/host/apps/omap_debug/usrp_e.h b/host/apps/omap_debug/usrp_e.h index b098ad114..fd38027d4 100644 --- a/host/apps/omap_debug/usrp_e.h +++ b/host/apps/omap_debug/usrp_e.h @@ -34,8 +34,8 @@ struct usrp_e_ctl32 { #define UE_SPI_TXRX 1 /* Defines for spi ctrl register */ -#define UE_SPI_CTRL_TXNEG (1 << 10) -#define UE_SPI_CTRL_RXNEG (1 << 9) +#define UE_SPI_CTRL_TXNEG (BIT(10)) +#define UE_SPI_CTRL_RXNEG (BIT(9)) #define UE_SPI_PUSH_RISE 0 #define UE_SPI_PUSH_FALL UE_SPI_CTRL_TXNEG @@ -64,25 +64,24 @@ struct usrp_e_i2c { #define USRP_E_SPI _IOWR(USRP_E_IOC_MAGIC, 0x24, struct usrp_e_spi) #define USRP_E_I2C_READ _IOWR(USRP_E_IOC_MAGIC, 0x25, struct usrp_e_i2c) #define USRP_E_I2C_WRITE _IOW(USRP_E_IOC_MAGIC, 0x26, struct usrp_e_i2c) +#define USRP_E_GET_RB_INFO _IOR(USRP_E_IOC_MAGIC, 0x27, struct usrp_e_ring_buffer_size_t) -/* Data transfer frame definition */ - -struct usrp_transfer_frame { - __u32 status; - __u32 len; - __u8 buf[]; +/* Flag defines */ +#define RB_USER (1<<0) +#define RB_KERNEL (1<<1) +#define RB_OVERRUN (1<<2) +#define RB_DMA_ACTIVE (1<<3) + +struct ring_buffer_info { + int flags; + int len; }; -/* Flag defines */ -#define RB_USER (1 << 0) -#define RB_KERNEL (1 << 1) -#define RB_OVERRUN (1 << 2) -#define RB_DMA_ACTIVE (1 << 3) - -struct ring_buffer_entry { - unsigned int flags; - unsigned long dma_addr; - struct usrp_transfer_frame *frame_addr; +struct usrp_e_ring_buffer_size_t { + int num_pages_rx_flags; + int num_rx_frames; + int num_pages_tx_flags; + int num_tx_frames; }; #endif diff --git a/host/include/linux/usrp_e.h b/host/include/linux/usrp_e.h index b098ad114..fd38027d4 100644 --- a/host/include/linux/usrp_e.h +++ b/host/include/linux/usrp_e.h @@ -34,8 +34,8 @@ struct usrp_e_ctl32 { #define UE_SPI_TXRX 1 /* Defines for spi ctrl register */ -#define UE_SPI_CTRL_TXNEG (1 << 10) -#define UE_SPI_CTRL_RXNEG (1 << 9) +#define UE_SPI_CTRL_TXNEG (BIT(10)) +#define UE_SPI_CTRL_RXNEG (BIT(9)) #define UE_SPI_PUSH_RISE 0 #define UE_SPI_PUSH_FALL UE_SPI_CTRL_TXNEG @@ -64,25 +64,24 @@ struct usrp_e_i2c { #define USRP_E_SPI _IOWR(USRP_E_IOC_MAGIC, 0x24, struct usrp_e_spi) #define USRP_E_I2C_READ _IOWR(USRP_E_IOC_MAGIC, 0x25, struct usrp_e_i2c) #define USRP_E_I2C_WRITE _IOW(USRP_E_IOC_MAGIC, 0x26, struct usrp_e_i2c) +#define USRP_E_GET_RB_INFO _IOR(USRP_E_IOC_MAGIC, 0x27, struct usrp_e_ring_buffer_size_t) -/* Data transfer frame definition */ - -struct usrp_transfer_frame { - __u32 status; - __u32 len; - __u8 buf[]; +/* Flag defines */ +#define RB_USER (1<<0) +#define RB_KERNEL (1<<1) +#define RB_OVERRUN (1<<2) +#define RB_DMA_ACTIVE (1<<3) + +struct ring_buffer_info { + int flags; + int len; }; -/* Flag defines */ -#define RB_USER (1 << 0) -#define RB_KERNEL (1 << 1) -#define RB_OVERRUN (1 << 2) -#define RB_DMA_ACTIVE (1 << 3) - -struct ring_buffer_entry { - unsigned int flags; - unsigned long dma_addr; - struct usrp_transfer_frame *frame_addr; +struct usrp_e_ring_buffer_size_t { + int num_pages_rx_flags; + int num_rx_frames; + int num_pages_tx_flags; + int num_tx_frames; }; #endif -- cgit v1.2.3 From 380889798a9a9b5319e708743c5bb216405f77f4 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Tue, 21 Sep 2010 19:47:32 +0000 Subject: Convert write to use the mmap interface. --- host/apps/omap_debug/usrp-e-mm-loopback.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-mm-loopback.c b/host/apps/omap_debug/usrp-e-mm-loopback.c index a1da926a2..81bdb410a 100644 --- a/host/apps/omap_debug/usrp-e-mm-loopback.c +++ b/host/apps/omap_debug/usrp-e-mm-loopback.c @@ -137,7 +137,7 @@ static void *read_thread(void *threadid) static void *write_thread(void *threadid) { - int seq_number, i, cnt; + int seq_number, i, cnt, rb_write; void *tx_data; struct pkt *p; @@ -151,6 +151,7 @@ static void *write_thread(void *threadid) p->data[i] = i; seq_number = 1; + rb_write = 0; while (1) { p->seq_num = seq_number++; @@ -162,9 +163,26 @@ static void *write_thread(void *threadid) p->checksum = calc_checksum(p); - cnt = write(fp, tx_data, p->len * 2 + 12); - if (cnt < 0) - printf("Error returned from write: %d\n", cnt); + if (!((*txi)[rb_write].flags & RB_KERNEL)) { +// printf("Waiting for space\n"); + struct pollfd pfd; + pfd.fd = fp; + pfd.events = POLLOUT; + ssize_t ret = poll(&pfd, 1, -1); + } + + memcpy(&(*tx_buf)[rb_write], tx_data, p->len * 2 + 12); + + (*txi)[rb_write].len = p->len * 2 + 12; + (*txi)[rb_write].flags = RB_USER; + + rb_write++; + if (rb_write == 100) + rb_write = 0; + +// cnt = write(fp, tx_data, p->len * 2 + 12); +// if (cnt < 0) +// printf("Error returned from write: %d\n", cnt); // sleep(1); } } -- cgit v1.2.3 From 943bfa271c97b36dcba74f1d65220e6f66f50c7f Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Tue, 21 Sep 2010 19:59:02 +0000 Subject: Use the ring buffer sizes read from the kernel. --- host/apps/omap_debug/usrp-e-mm-loopback.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/host/apps/omap_debug/usrp-e-mm-loopback.c b/host/apps/omap_debug/usrp-e-mm-loopback.c index 81bdb410a..053f60b60 100644 --- a/host/apps/omap_debug/usrp-e-mm-loopback.c +++ b/host/apps/omap_debug/usrp-e-mm-loopback.c @@ -27,6 +27,7 @@ struct pkt (*rx_buf)[200]; struct pkt (*tx_buf)[200]; static int fp; +static struct usrp_e_ring_buffer_size_t rb_size; static int calc_checksum(struct pkt *p) { @@ -110,7 +111,7 @@ static void *read_thread(void *threadid) (*rxi)[rb_read].flags = RB_KERNEL; rb_read++; - if (rb_read == 100) + if (rb_read == rb_size.num_rx_frames) rb_read = 0; bytes_transfered += cnt; @@ -177,7 +178,7 @@ static void *write_thread(void *threadid) (*txi)[rb_write].flags = RB_USER; rb_write++; - if (rb_write == 100) + if (rb_write == rb_size.num_tx_frames) rb_write = 0; // cnt = write(fp, tx_data, p->len * 2 + 12); @@ -195,7 +196,6 @@ int main(int argc, char *argv[]) struct sched_param s = { .sched_priority = 1 }; - struct usrp_e_ring_buffer_size_t rb_size; int ret, map_size, page_size; void *rb; -- cgit v1.2.3 From 77cdb4a9695e71e64e1d87cfad2cb4d8717f971e Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Tue, 21 Sep 2010 20:06:43 +0000 Subject: Use a dummy write to start DMA transfers when sending data to the FPGA. Poll will also start data transfers. --- host/apps/omap_debug/usrp-e-mm-loopback.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/host/apps/omap_debug/usrp-e-mm-loopback.c b/host/apps/omap_debug/usrp-e-mm-loopback.c index 053f60b60..f5fc83c87 100644 --- a/host/apps/omap_debug/usrp-e-mm-loopback.c +++ b/host/apps/omap_debug/usrp-e-mm-loopback.c @@ -181,7 +181,7 @@ static void *write_thread(void *threadid) if (rb_write == rb_size.num_tx_frames) rb_write = 0; -// cnt = write(fp, tx_data, p->len * 2 + 12); + cnt = write(fp, NULL, 0); // if (cnt < 0) // printf("Error returned from write: %d\n", cnt); // sleep(1); -- cgit v1.2.3 From d78fd935865e3ebece9163a85b4b8043beef4eee Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 21 Sep 2010 17:00:44 -0700 Subject: fix timing issue on DAC outputs with rev 2. This puts the whole system on a 90 degree phase shift --- usrp2/top/u1e/u1e.ucf | 38 +++++++++++++++++++------------------- usrp2/top/u1e/u1e.v | 37 ++++++------------------------------- 2 files changed, 25 insertions(+), 50 deletions(-) diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 51968d24a..5581b1dbd 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -95,10 +95,10 @@ NET "db_sen_tx" LOC = "G18" ; #NET "aux_sdi_codec" LOC = "G3" ; #NET "aux_sdo_codec" LOC = "F3" ; #NET "aux_sclk_codec" LOC = "C1" ; -NET "sen_codec" LOC = "F5" ; -NET "mosi_codec" LOC = "F4" ; +NET "sen_codec" LOC = "F5" |IOSTANDARD = LVCMOS33; +NET "mosi_codec" LOC = "F4" |IOSTANDARD = LVCMOS33; NET "miso_codec" LOC = "H4" ; -NET "sclk_codec" LOC = "H3" ; +NET "sclk_codec" LOC = "H3" |IOSTANDARD = LVCMOS33; ### Clock Gen SPI NET "cgen_miso" LOC = "F22" ; @@ -184,22 +184,22 @@ NET "DA<2>" LOC = "P6" ; NET "DA<1>" LOC = "R1" ; NET "DA<0>" LOC = "R2" ; -NET "TX<13>" LOC = "T6" ; -NET "TX<12>" LOC = "U1" ; -NET "TX<11>" LOC = "T1" ; -NET "TX<10>" LOC = "R5" ; -NET "TX<9>" LOC = "V1" ; -NET "TX<8>" LOC = "U2" ; -NET "TX<7>" LOC = "T4" ; -NET "TX<6>" LOC = "R3" ; -NET "TX<5>" LOC = "W1" ; -NET "TX<4>" LOC = "Y1" ; -NET "TX<3>" LOC = "V3" ; -NET "TX<2>" LOC = "V4" ; -NET "TX<1>" LOC = "W2" ; -NET "TX<0>" LOC = "W3" ; -NET "TXSYNC" LOC = "U5" ; -NET "TXBLANK" LOC = "U4" ; +NET "TX<13>" LOC = "T6" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<12>" LOC = "U1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<11>" LOC = "T1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<10>" LOC = "R5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<9>" LOC = "V1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<8>" LOC = "U2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<7>" LOC = "T4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<6>" LOC = "R3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<5>" LOC = "W1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<4>" LOC = "Y1" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<3>" LOC = "V3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<2>" LOC = "V4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<1>" LOC = "W2" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TX<0>" LOC = "W3" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TXSYNC" LOC = "U5" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; +NET "TXBLANK" LOC = "U4" |IOSTANDARD = LVCMOS33 |DRIVE = 12 |SLEW = FAST ; NET "PPS_IN" LOC = "M5" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index 7ddbfd537..ee087e59d 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -1,8 +1,6 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -//`define DCM 1 - module u1e (input CLK_FPGA_P, input CLK_FPGA_N, // Diff output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, @@ -41,11 +39,10 @@ module u1e IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); -`ifdef DCM - wire clk_2x, dcm_rst, dcm_locked; + wire clk_2x, dcm_rst, dcm_locked, clk_fb; DCM #(.CLK_FEEDBACK ( "1X" ), - .CLKDV_DIVIDE ( 2.0 ), - .CLKFX_DIVIDE ( 1 ), + .CLKDV_DIVIDE ( 2 ), + .CLKFX_DIVIDE ( 2 ), .CLKFX_MULTIPLY ( 2 ), .CLKIN_DIVIDE_BY_2 ( "FALSE" ), .CLKIN_PERIOD ( 15.625 ), @@ -57,15 +54,12 @@ module u1e .FACTORY_JF ( 16'h8080 ), .PHASE_SHIFT ( 0 ), .STARTUP_WAIT ( "FALSE" )) - clk_doubler (.CLKFB(clk_fpga), .CLKIN(clk_fpga_in), .RST(dcm_rst), + clk_doubler (.CLKFB(clk_fb), .CLKIN(clk_fpga_in), .RST(dcm_rst), .DSSEN(0), .PSCLK(0), .PSEN(0), .PSINCDEC(0), .PSDONE(), .CLKDV(), .CLKFX(), .CLKFX180(), - .CLK2X(clk_2x), .CLK2X180(), - .CLK0(clk_fpga), .CLK90(), .CLK180(), .CLK270(), + .CLK2X(), .CLK2X180(), + .CLK0(clk_fb), .CLK90(clk_fpga), .CLK180(), .CLK270(), .LOCKED(dcm_locked), .STATUS()); -`else // !`ifdef DCM - BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga)); -`endif // !`ifdef DCM // ///////////////////////////////////////////////////////////////////////// // SPI @@ -83,23 +77,6 @@ module u1e assign TXBLANK = 0; wire [13:0] tx_i, tx_q; -`ifdef DCM - reg [13:0] TX; - reg TXSYNC; - - always @(posedge clk_2x) - if(clk_fpga) - begin - TX <= tx_i; - TXSYNC <= 0; // Low indicates first data item - end - else - begin - TX <= tx_q; - TXSYNC <= 1; - end -`else // !`ifdef DCM - reg[13:0] delay_q; always @(posedge clk_fpga) delay_q <= tx_q; @@ -133,8 +110,6 @@ module u1e .R(1'b0), // 1-bit reset input .S(1'b0)); // 1-bit set input -`endif // !`ifdef DCM - // ///////////////////////////////////////////////////////////////////////// // Main U1E Core u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb), -- cgit v1.2.3 From 27eb894c397f758528f59bc24f2ac645f0fccc4b Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 23 Sep 2010 11:40:19 -0700 Subject: watch the ethernet chip select on our debug bus --- usrp2/top/u1e/u1e.ucf | 2 +- usrp2/top/u1e/u1e.v | 7 ++++--- usrp2/top/u1e/u1e_core.v | 5 +++-- 3 files changed, 8 insertions(+), 6 deletions(-) diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf index 5581b1dbd..0c487a601 100644 --- a/usrp2/top/u1e/u1e.ucf +++ b/usrp2/top/u1e/u1e.ucf @@ -32,7 +32,7 @@ NET "EM_A<2>" LOC = "A7" ; NET "EM_A<1>" LOC = "C15" ; NET "EM_NCS6" LOC = "E17" ; -#NET "EM_NCS5" LOC = "E10" ; +NET "EM_NCS5" LOC = "E10" ; NET "EM_NCS4" LOC = "E6" ; #NET "EM_NCS1" LOC = "D18" ; #NET "EM_NCS0" LOC = "D17" ; diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v index ee087e59d..445b14a03 100644 --- a/usrp2/top/u1e/u1e.v +++ b/usrp2/top/u1e/u1e.v @@ -8,7 +8,8 @@ module u1e // GPMC input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, - input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, + input EM_NWE, input EM_NOE, inout db_sda, inout db_scl, // I2C @@ -116,8 +117,8 @@ module u1e .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), - .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), - .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), + .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS5(EM_NCS5), + .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), .db_sda(db_sda), .db_scl(db_scl), .sclk(sclk), .sen({cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso), .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 42333a722..619e44b8a 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -11,7 +11,8 @@ module u1e_core // GPMC input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, - input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, + input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, + input EM_NWE, input EM_NOE, inout db_sda, inout db_scl, output sclk, output [7:0] sen, output mosi, input miso, @@ -439,7 +440,7 @@ module u1e_core assign debug_clk = { EM_CLK, clk_fpga }; - assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, rx_overrun, tx_underrun }, + assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun }, { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int }, { EM_D } }; -- cgit v1.2.3 From 69992b4133145cd92629a0d15354b5d33f0c4973 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 23 Sep 2010 17:15:14 -0700 Subject: better debug pins --- usrp2/top/u1e_ethdebug/u1e.ucf | 8 +++++--- usrp2/top/u1e_ethdebug/u1e.v | 10 ++++++---- 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/usrp2/top/u1e_ethdebug/u1e.ucf b/usrp2/top/u1e_ethdebug/u1e.ucf index 0d4384a2a..d6a2ea4ed 100644 --- a/usrp2/top/u1e_ethdebug/u1e.ucf +++ b/usrp2/top/u1e_ethdebug/u1e.ucf @@ -36,12 +36,14 @@ NET "EM_NCS4" LOC = "E6" ; NET "EM_CLK" LOC = "F11" ; NET "EM_WAIT0" LOC = "F14" ; -NET "EM_NBE<1>" LOC = "D14" ; -NET "EM_NBE<0>" LOC = "A13" ; +#NET "EM_NBE<1>" LOC = "D14" ; +#NET "EM_NBE<0>" LOC = "A13" ; NET "EM_NWE" LOC = "B13" ; NET "EM_NOE" LOC = "A14" ; NET "EM_NADV_ALE" LOC = "B15" ; -NET "EM_NWP" LOC = "F13" ; +#NET "EM_NWP" LOC = "F13" ; +NET "overo_gpio64" LOC = "A4" ; # nRESET +NET "overo_gpio176" LOC = "B4" ; # IRQ ## Debug pins NET "debug_led<3>" LOC = "Y15" ; diff --git a/usrp2/top/u1e_ethdebug/u1e.v b/usrp2/top/u1e_ethdebug/u1e.v index c4740b941..2a543a313 100644 --- a/usrp2/top/u1e_ethdebug/u1e.v +++ b/usrp2/top/u1e_ethdebug/u1e.v @@ -8,16 +8,18 @@ module u1e input debug_pb, // GPMC - input EM_CLK, input [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, + input EM_CLK, input [15:0] EM_D, input [10:1] EM_A, input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, input EM_NWE, input EM_NOE, - input EM_NADV_ALE, input EM_NWP + input EM_NADV_ALE, + + input overo_gpio64, input overo_gpio176 ); assign debug_clk = {EM_CLK, EM_NADV_ALE}; - assign debug_led = {EM_NWP, EM_A[9], EM_A[8], debug_pb}; + assign debug_led = {1'b0, EM_A[9], EM_A[8], debug_pb}; - assign debug = { { EM_NBE[1:0], EM_WAIT0, EM_NCS4, EM_NCS5, EM_NCS6, EM_NWE, EM_NOE }, + assign debug = { {overo_gpio64, overo_gpio176, EM_WAIT0, EM_NCS4, EM_NCS5, EM_NCS6, EM_NWE, EM_NOE }, { EM_A[10], EM_A[7:1] }, { EM_D[15:8] }, { EM_D[7:0] } }; -- cgit v1.2.3 From 1f77494788fa4fa8450aaf170055553bd0e5fe8e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 24 Sep 2010 14:37:15 -0700 Subject: allow for CS to rise before, at the same time, or after OE --- usrp2/gpmc/fifo_to_gpmc_async.v | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/usrp2/gpmc/fifo_to_gpmc_async.v b/usrp2/gpmc/fifo_to_gpmc_async.v index 5ac8b19bd..cf8b6e861 100644 --- a/usrp2/gpmc/fifo_to_gpmc_async.v +++ b/usrp2/gpmc/fifo_to_gpmc_async.v @@ -11,23 +11,22 @@ module fifo_to_gpmc_async input [15:0] frame_len); // Synchronize the async control signals - reg [1:0] cs_del, oe_del; + reg [2:0] cs_del, oe_del; reg [15:0] counter; always @(posedge clk) if(reset) begin - cs_del <= 2'b11; - oe_del <= 2'b11; + cs_del <= 3'b11; + oe_del <= 3'b11; end else begin - cs_del <= { cs_del[0], EM_NCS }; - oe_del <= { oe_del[0], EM_NOE }; + cs_del <= { cs_del[1:0], EM_NCS }; + oe_del <= { oe_del[1:0], EM_NOE }; end - //wire do_read = (~cs_del[0] & (oe_del == 2'b10)); - wire do_read = (~cs_del[1] & (oe_del == 2'b01)); // change output on trailing edge + wire do_read = ( (~cs_del[1] | ~cs_del[2]) & (oe_del[1:0] == 2'b01)); // change output on trailing edge wire first_read = (counter == 0); wire last_read = ((counter+1) == frame_len); -- cgit v1.2.3 From 082715d0c90b615874fe6bbe93069fa696b3d47a Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 24 Sep 2010 15:56:52 -0700 Subject: usrp-e: updated dsp for multiple shift properties --- host/lib/usrp/usrp_e/dsp_impl.cpp | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/host/lib/usrp/usrp_e/dsp_impl.cpp b/host/lib/usrp/usrp_e/dsp_impl.cpp index c133eafae..9312bb603 100644 --- a/host/lib/usrp/usrp_e/dsp_impl.cpp +++ b/host/lib/usrp/usrp_e/dsp_impl.cpp @@ -44,7 +44,9 @@ void usrp_e_impl::rx_ddc_init(void){ /*********************************************************************** * RX DDC Get **********************************************************************/ -void usrp_e_impl::rx_ddc_get(const wax::obj &key, wax::obj &val){ +void usrp_e_impl::rx_ddc_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + switch(key.as()){ case DSP_PROP_NAME: val = std::string("usrp-e ddc0"); @@ -58,6 +60,10 @@ void usrp_e_impl::rx_ddc_get(const wax::obj &key, wax::obj &val){ val = _ddc_freq; return; + case DSP_PROP_FREQ_SHIFT_NAMES: + val = prop_names_t(1, ""); + return; + case DSP_PROP_CODEC_RATE: val = MASTER_CLOCK_RATE; return; @@ -73,7 +79,9 @@ void usrp_e_impl::rx_ddc_get(const wax::obj &key, wax::obj &val){ /*********************************************************************** * RX DDC Set **********************************************************************/ -void usrp_e_impl::rx_ddc_set(const wax::obj &key, const wax::obj &val){ +void usrp_e_impl::rx_ddc_set(const wax::obj &key_, const wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + switch(key.as()){ case DSP_PROP_FREQ_SHIFT:{ @@ -119,7 +127,9 @@ void usrp_e_impl::tx_duc_init(void){ /*********************************************************************** * TX DUC Get **********************************************************************/ -void usrp_e_impl::tx_duc_get(const wax::obj &key, wax::obj &val){ +void usrp_e_impl::tx_duc_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + switch(key.as()){ case DSP_PROP_NAME: val = std::string("usrp-e duc0"); @@ -133,6 +143,10 @@ void usrp_e_impl::tx_duc_get(const wax::obj &key, wax::obj &val){ val = _duc_freq; return; + case DSP_PROP_FREQ_SHIFT_NAMES: + val = prop_names_t(1, ""); + return; + case DSP_PROP_CODEC_RATE: val = MASTER_CLOCK_RATE; return; @@ -148,7 +162,9 @@ void usrp_e_impl::tx_duc_get(const wax::obj &key, wax::obj &val){ /*********************************************************************** * TX DUC Set **********************************************************************/ -void usrp_e_impl::tx_duc_set(const wax::obj &key, const wax::obj &val){ +void usrp_e_impl::tx_duc_set(const wax::obj &key_, const wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + switch(key.as()){ case DSP_PROP_FREQ_SHIFT:{ -- cgit v1.2.3 From c75286df4689369aa9a3f4148b964d66109e085e Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Sat, 25 Sep 2010 11:51:04 -0400 Subject: Add more NEON for type conversion. --- host/lib/transport/convert_types_impl.hpp | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/host/lib/transport/convert_types_impl.hpp b/host/lib/transport/convert_types_impl.hpp index b9a47eb0e..48ff99725 100644 --- a/host/lib/transport/convert_types_impl.hpp +++ b/host/lib/transport/convert_types_impl.hpp @@ -266,6 +266,26 @@ static UHD_INLINE void item32_to_fc32_nswap( } } +#elif defined(USE_ARM_NEON_H) +static UHD_INLINE void item32_to_fc32_nswap( + const item32_t *input, fc32_t *output, size_t nsamps) +{ + size_t i; + + float32x4_t Q1 = vdupq_n_f32(floats_per_short); + for (i=0; i < (nsamps & ~0x03); i+=2) { + int16x4_t D0 = vld1_s16(reinterpret_cast(&input[i])); + int16x4_t D1 = vrev32_s16(D0); + int32x4_t Q2 = vmovl_s16(D1); + float32x4_t Q3 = vcvtq_f32_s32(Q2); + float32x4_t Q4 = vmulq_f32(Q3, Q1); + vst1q_f32((reinterpret_cast(&output[i])), Q4); + } + + for (; i < nsamps; i++) + output[i] = item32_to_fc32(input[i]); +} + #else static UHD_INLINE void item32_to_fc32_nswap( const item32_t *input, fc32_t *output, size_t nsamps -- cgit v1.2.3 From 018813d46def4d25ec5a937da2235d7f2adce5b3 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Sun, 26 Sep 2010 21:21:37 -0400 Subject: Add define so uusrp_e support is enabled. --- host/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/host/CMakeLists.txt b/host/CMakeLists.txt index 89487c86b..6c96706a5 100644 --- a/host/CMakeLists.txt +++ b/host/CMakeLists.txt @@ -64,7 +64,7 @@ IF(CMAKE_COMPILER_IS_GNUCXX) #causes trouble when compiling libusb1.0 on macintosh #comment out until mac ports libusb gets its act together #ADD_DEFINITIONS(-pedantic) - ADD_DEFINITIONS(-ansi) + #ADD_DEFINITIONS(-ansi) #only export symbols that are declared to be part of the uhd api: UHD_ADD_OPTIONAL_CXX_COMPILER_FLAG(-fvisibility=hidden HAVE_VISIBILITY_HIDDEN) ENDIF(CMAKE_COMPILER_IS_GNUCXX) -- cgit v1.2.3 From 507283b3d43d653bf7ff1b2aa04f3d642297c9b1 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Sun, 26 Sep 2010 21:22:07 -0400 Subject: Remove BIT macro --- host/include/linux/usrp_e.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/host/include/linux/usrp_e.h b/host/include/linux/usrp_e.h index fd38027d4..80f3a287b 100644 --- a/host/include/linux/usrp_e.h +++ b/host/include/linux/usrp_e.h @@ -34,8 +34,8 @@ struct usrp_e_ctl32 { #define UE_SPI_TXRX 1 /* Defines for spi ctrl register */ -#define UE_SPI_CTRL_TXNEG (BIT(10)) -#define UE_SPI_CTRL_RXNEG (BIT(9)) +#define UE_SPI_CTRL_TXNEG (1<<10) +#define UE_SPI_CTRL_RXNEG (1<<9) #define UE_SPI_PUSH_RISE 0 #define UE_SPI_PUSH_FALL UE_SPI_CTRL_TXNEG -- cgit v1.2.3 From 20c364cb6e2d175525c1885c8ac122187853dc95 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Sun, 26 Sep 2010 21:22:51 -0400 Subject: Really enable usrp_e support. Previous commit commented out the ansi flag so C++ comments in C compile. --- host/lib/usrp/usrp_e/CMakeLists.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/host/lib/usrp/usrp_e/CMakeLists.txt b/host/lib/usrp/usrp_e/CMakeLists.txt index da759d931..fbcd19276 100644 --- a/host/lib/usrp/usrp_e/CMakeLists.txt +++ b/host/lib/usrp/usrp_e/CMakeLists.txt @@ -25,6 +25,8 @@ MESSAGE(STATUS "Configuring usrp-e support...") INCLUDE(CheckIncludeFileCXX) CHECK_INCLUDE_FILE_CXX(linux/usrp_e.h HAVE_LINUX_USRP_E_H) +SET(ENABLE_USRP_E TRUE) + IF(DEFINED ENABLE_USRP_E) IF(ENABLE_USRP_E) MESSAGE(STATUS "USRP-E support enabled by configure flag") -- cgit v1.2.3 From dd9f9c340a8def560235d737df446454ea75dadc Mon Sep 17 00:00:00 2001 From: root Date: Thu, 30 Sep 2010 18:25:24 +0000 Subject: Ignore direction for GPIO 114 since it is always an input. --- host/apps/omap_debug/fpga-downloader.cc | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/host/apps/omap_debug/fpga-downloader.cc b/host/apps/omap_debug/fpga-downloader.cc index fb96b64a3..4e475b5c1 100644 --- a/host/apps/omap_debug/fpga-downloader.cc +++ b/host/apps/omap_debug/fpga-downloader.cc @@ -97,15 +97,17 @@ gpio::gpio(unsigned int gpio_num, gpio_direction pin_direction) std::fstream direction_file; std::string direction_file_name; - direction_file_name = base_path.str() + "/direction"; - - direction_file.open(direction_file_name.c_str()); - if (!direction_file.is_open()) - std::cout << "Failed to open direction file." << std::endl; - if (pin_direction == OUT) - direction_file << "out" << std::endl; - else - direction_file << "in" << std::endl; + if (gpio_num != 114) { + direction_file_name = base_path.str() + "/direction"; + + direction_file.open(direction_file_name.c_str()); + if (!direction_file.is_open()) + std::cout << "Failed to open direction file." << std::endl; + if (pin_direction == OUT) + direction_file << "out" << std::endl; + else + direction_file << "in" << std::endl; + } std::string value_file_name; -- cgit v1.2.3 From 7f8d7b0e2fef1b2d5bb9c8047380dcf958c0c49c Mon Sep 17 00:00:00 2001 From: root Date: Thu, 30 Sep 2010 18:25:24 +0000 Subject: Ignore direction for GPIO 114 since it is always an input. --- host/apps/omap_debug/fpga-downloader.cc | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/host/apps/omap_debug/fpga-downloader.cc b/host/apps/omap_debug/fpga-downloader.cc index fb96b64a3..4e475b5c1 100644 --- a/host/apps/omap_debug/fpga-downloader.cc +++ b/host/apps/omap_debug/fpga-downloader.cc @@ -97,15 +97,17 @@ gpio::gpio(unsigned int gpio_num, gpio_direction pin_direction) std::fstream direction_file; std::string direction_file_name; - direction_file_name = base_path.str() + "/direction"; - - direction_file.open(direction_file_name.c_str()); - if (!direction_file.is_open()) - std::cout << "Failed to open direction file." << std::endl; - if (pin_direction == OUT) - direction_file << "out" << std::endl; - else - direction_file << "in" << std::endl; + if (gpio_num != 114) { + direction_file_name = base_path.str() + "/direction"; + + direction_file.open(direction_file_name.c_str()); + if (!direction_file.is_open()) + std::cout << "Failed to open direction file." << std::endl; + if (pin_direction == OUT) + direction_file << "out" << std::endl; + else + direction_file << "in" << std::endl; + } std::string value_file_name; -- cgit v1.2.3 From cc97c6ee0b3dbc8e0ed6bfae01505fcb209d13cb Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 30 Sep 2010 15:12:30 -0700 Subject: usrp-e: update to build with the master --- host/lib/usrp/usrp_e/dboard_iface.cpp | 5 +++++ host/lib/usrp/usrp_e/io_impl.cpp | 18 +++++------------- 2 files changed, 10 insertions(+), 13 deletions(-) diff --git a/host/lib/usrp/usrp_e/dboard_iface.cpp b/host/lib/usrp/usrp_e/dboard_iface.cpp index 1bd177f60..6898df8df 100644 --- a/host/lib/usrp/usrp_e/dboard_iface.cpp +++ b/host/lib/usrp/usrp_e/dboard_iface.cpp @@ -91,6 +91,7 @@ public: std::vector get_clock_rates(unit_t); double get_clock_rate(unit_t); void set_clock_enabled(unit_t, bool); + double get_codec_rate(unit_t); private: usrp_e_iface::sptr _iface; @@ -140,6 +141,10 @@ void usrp_e_dboard_iface::set_clock_enabled(unit_t unit, bool enb){ } } +double usrp_e_dboard_iface::get_codec_rate(unit_t){ + return _clock->get_fpga_clock_rate(); +} + /*********************************************************************** * GPIO **********************************************************************/ diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index 31ea4c6c0..e57d6ce35 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -39,6 +39,7 @@ static const size_t MAX_BUFF_SIZE = 2048; static const bool usrp_e_io_impl_verbose = false; static const size_t tx_async_report_sid = 1; static const int underflow_flags = async_metadata_t::EVENT_CODE_UNDERFLOW | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET; +static const double recv_timeout_ms = 100; /*********************************************************************** * Data Transport (phony zero-copy with read/write) @@ -74,7 +75,7 @@ private: boost::asio::buffer_size(buff) ); } - ssize_t recv(const boost::asio::mutable_buffer &buff){ + ssize_t recv(const boost::asio::mutable_buffer &buff, size_t to_ms){ //std::cout << boost::format( // "calling read on fd %d, buff size is %d" //) % _fd % boost::asio::buffer_size(buff) << std::endl; @@ -84,7 +85,7 @@ private: pollfd pfd; pfd.fd = _fd; pfd.events = POLLIN; - ssize_t poll_ret = poll(&pfd, 1, 100/*ms*/); + ssize_t poll_ret = poll(&pfd, 1, to_ms); if (poll_ret <= 0){ if (usrp_e_io_impl_verbose) std::cerr << boost::format( "usrp-e io impl recv(): poll() returned non-positive value: %d\n" @@ -170,7 +171,7 @@ void usrp_e_impl::io_impl::recv_pirate_loop( //size_t next_packet_seq = 0; while(recv_pirate_crew_raiding){ - managed_recv_buffer::sptr buff = this->transport.get_recv_buff(); + managed_recv_buffer::sptr buff = this->transport.get_recv_buff(recv_timeout_ms); if (not buff.get()) continue; //ignore timeout/error buffers try{ @@ -262,7 +263,7 @@ bool get_send_buffs( ){ UHD_ASSERT_THROW(buffs.size() == 1); buffs[0] = trans->get_send_buff(); - return buffs[0].get(); + return buffs[0].get() != NULL; } size_t usrp_e_impl::send( @@ -292,15 +293,6 @@ size_t usrp_e_impl::send( /*********************************************************************** * Data Recv **********************************************************************/ -bool get_recv_buffs( - data_transport *trans, - vrt_packet_handler::managed_recv_buffs_t &buffs -){ - UHD_ASSERT_THROW(buffs.size() == 1); - buffs[0] = trans->get_recv_buff(); - return buffs[0].get(); -} - size_t usrp_e_impl::recv( const std::vector &buffs, size_t num_samps, -- cgit v1.2.3 From 46d2fc423d2fdcf32454621c6f41e555d2496702 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 30 Sep 2010 17:56:36 -0700 Subject: usrp-e: untested attempt at zero copy iface for mmap --- host/lib/usrp/usrp_e/CMakeLists.txt | 1 + host/lib/usrp/usrp_e/io_impl.cpp | 97 ++---------- host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp | 201 +++++++++++++++++++++++++ 3 files changed, 212 insertions(+), 87 deletions(-) create mode 100644 host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp diff --git a/host/lib/usrp/usrp_e/CMakeLists.txt b/host/lib/usrp/usrp_e/CMakeLists.txt index da759d931..bab868f90 100644 --- a/host/lib/usrp/usrp_e/CMakeLists.txt +++ b/host/lib/usrp/usrp_e/CMakeLists.txt @@ -54,6 +54,7 @@ IF(ENABLE_USRP_E) ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_impl.hpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_iface.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_iface.hpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_regs.hpp ) ELSE(ENABLE_USRP_E) diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index e57d6ce35..0b5fa054b 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -22,8 +22,6 @@ #include #include "../../transport/vrt_packet_handler.hpp" #include -#include //read, write -#include #include #include #include @@ -32,90 +30,15 @@ using namespace uhd; using namespace uhd::usrp; using namespace uhd::transport; +zero_copy_if::sptr usrp_e_make_mmap_zero_copy(usrp_e_iface::sptr iface); + /*********************************************************************** * Constants **********************************************************************/ -static const size_t MAX_BUFF_SIZE = 2048; -static const bool usrp_e_io_impl_verbose = false; static const size_t tx_async_report_sid = 1; static const int underflow_flags = async_metadata_t::EVENT_CODE_UNDERFLOW | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET; static const double recv_timeout_ms = 100; -/*********************************************************************** - * Data Transport (phony zero-copy with read/write) - **********************************************************************/ -class data_transport: - public transport::phony_zero_copy_recv_if, - public transport::phony_zero_copy_send_if -{ -public: - data_transport(int fd): - transport::phony_zero_copy_recv_if(MAX_BUFF_SIZE), - transport::phony_zero_copy_send_if(MAX_BUFF_SIZE), - _fd(fd) - { - /* NOP */ - } - - size_t get_num_recv_frames(void) const{ - return 100; //FIXME no idea! - //this will be an important number when packet ring gets implemented - } - - size_t get_num_send_frames(void) const{ - return 100; //FIXME no idea! - //this will be an important number when packet ring gets implemented - } - -private: - int _fd; - ssize_t send(const boost::asio::const_buffer &buff){ - return write(_fd, - boost::asio::buffer_cast(buff), - boost::asio::buffer_size(buff) - ); - } - ssize_t recv(const boost::asio::mutable_buffer &buff, size_t to_ms){ - //std::cout << boost::format( - // "calling read on fd %d, buff size is %d" - //) % _fd % boost::asio::buffer_size(buff) << std::endl; - - //setup and call poll on the file descriptor - //return 0 and do not read when poll times out - pollfd pfd; - pfd.fd = _fd; - pfd.events = POLLIN; - ssize_t poll_ret = poll(&pfd, 1, to_ms); - if (poll_ret <= 0){ - if (usrp_e_io_impl_verbose) std::cerr << boost::format( - "usrp-e io impl recv(): poll() returned non-positive value: %d\n" - " -> return 0 for timeout" - ) % poll_ret << std::endl; - return 0; //timeout - } - - //perform the blocking read(...) - ssize_t read_ret = read(_fd, - boost::asio::buffer_cast(buff), - boost::asio::buffer_size(buff) - ); - if (read_ret < 0){ - if (usrp_e_io_impl_verbose) std::cerr << boost::format( - "usrp-e io impl recv(): read() returned small value: %d\n" - " -> return -1 for error" - ) % read_ret << std::endl; - return -1; - } - - //std::cout << "len " << int(read_ret) << std::endl; - //for (size_t i = 0; i < 9; i++){ - // std::cout << boost::format(" 0x%08x") % boost::asio::buffer_cast(buff)[i] << std::endl; - //} - - return read_ret; - } -}; - /*********************************************************************** * io impl details (internal to this file) * - pirate crew of 1 @@ -127,11 +50,11 @@ struct usrp_e_impl::io_impl{ //state management for the vrt packet handler code vrt_packet_handler::recv_state packet_handler_recv_state; vrt_packet_handler::send_state packet_handler_send_state; - data_transport transport; + zero_copy_if::sptr data_xport; bool continuous_streaming; - io_impl(int fd): - transport(fd), - recv_pirate_booty(recv_booty_type::make(transport.get_num_recv_frames())), + io_impl(usrp_e_iface::sptr iface): + data_xport(usrp_e_make_mmap_zero_copy(iface)), + recv_pirate_booty(recv_booty_type::make(data_xport->get_num_recv_frames())), async_msg_fifo(bounded_buffer::make(100/*messages deep*/)) { /* NOP */ @@ -171,7 +94,7 @@ void usrp_e_impl::io_impl::recv_pirate_loop( //size_t next_packet_seq = 0; while(recv_pirate_crew_raiding){ - managed_recv_buffer::sptr buff = this->transport.get_recv_buff(recv_timeout_ms); + managed_recv_buffer::sptr buff = this->data_xport->get_recv_buff(recv_timeout_ms); if (not buff.get()) continue; //ignore timeout/error buffers try{ @@ -229,7 +152,7 @@ void usrp_e_impl::io_init(void){ _iface->poke32(UE_REG_CTRL_TX_REPORT_SID, tx_async_report_sid); _iface->poke32(UE_REG_CTRL_TX_POLICY, UE_FLAG_CTRL_TX_POLICY_NEXT_PACKET); - _io_impl = UHD_PIMPL_MAKE(io_impl, (_iface->get_file_descriptor())); + _io_impl = UHD_PIMPL_MAKE(io_impl, (_iface)); //spawn a pirate, yarrr! _io_impl->recv_pirate_crew.create_thread(boost::bind( @@ -258,7 +181,7 @@ void usrp_e_impl::handle_overrun(size_t){ * Data Send **********************************************************************/ bool get_send_buffs( - data_transport *trans, + zero_copy_if::sptr trans, vrt_packet_handler::managed_send_buffs_t &buffs ){ UHD_ASSERT_THROW(buffs.size() == 1); @@ -285,7 +208,7 @@ size_t usrp_e_impl::send( io_type, send_otw_type, //input and output types to convert MASTER_CLOCK_RATE, //master clock tick rate uhd::transport::vrt::if_hdr_pack_le, - boost::bind(&get_send_buffs, &_io_impl->transport, _1), + boost::bind(&get_send_buffs, _io_impl->data_xport, _1), get_max_send_samps_per_packet() ); } diff --git a/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp b/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp new file mode 100644 index 000000000..0910caa6f --- /dev/null +++ b/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp @@ -0,0 +1,201 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include +#include +#include //mmap +#include //getpagesize +#include //poll +#include +#include "usrp_e_iface.hpp" + +using namespace uhd; +using namespace uhd::transport; + +static const bool debug_verbose = false; + +/*********************************************************************** + * The managed receive buffer implementation + **********************************************************************/ +class usrp_e_mmap_managed_recv_buffer : public managed_recv_buffer{ +public: + usrp_e_mmap_managed_recv_buffer( + const void *mem, size_t len, ring_buffer_info *info + ): + _buff(mem, len), _info(info) + { + /* NOP */ + } + + ~usrp_e_mmap_managed_recv_buffer(void){ + _info->flags = RB_KERNEL; + } + +private: + const boost::asio::const_buffer &get(void) const{ + return _buff; + } + + const boost::asio::const_buffer _buff; + ring_buffer_info *_info; +}; + +/*********************************************************************** + * The managed send buffer implementation + **********************************************************************/ +class usrp_e_mmap_managed_send_buffer : public managed_send_buffer{ +public: + usrp_e_mmap_managed_send_buffer( + void *mem, size_t len, ring_buffer_info *info, int fd + ): + _buff(mem, len), _info(info), _fd(fd), _commited(false) + { + /* NOP */ + } + + ~usrp_e_mmap_managed_send_buffer(void){ + if (not _commited) this->commit(0); + } + + ssize_t commit(size_t num_bytes){ + _commited = true; + _info->len = num_bytes; + _info->flags = RB_USER; + ssize_t ret = ::write(_fd, NULL, 0); + return (ret < 0)? ret : num_bytes; + } + +private: + const boost::asio::mutable_buffer &get(void) const{ + return _buff; + } + + const boost::asio::mutable_buffer _buff; + ring_buffer_info *_info; + int _fd; + bool _commited; +}; + +/*********************************************************************** + * The zero copy interface implementation + **********************************************************************/ +class usrp_e_mmap_zero_copy_impl : public zero_copy_if{ +public: + usrp_e_mmap_zero_copy_impl(usrp_e_iface::sptr iface): + _fd(iface->get_file_descriptor()), _recv_index(0), _send_index(0) + { + //get system sizes + iface->ioctl(USRP_E_GET_RB_INFO, &_rb_size); + size_t page_size = getpagesize(); + _frame_size = page_size/2; + + //calculate the memory size + size_t map_size = + (_rb_size.num_pages_rx_flags + _rb_size.num_pages_tx_flags) * page_size + + (_rb_size.num_rx_frames + _rb_size.num_tx_frames) * _frame_size; + + //call mmap to get the memory + void *ring_buffer = mmap( + NULL, map_size, PROT_READ | PROT_WRITE, MAP_SHARED, _fd, 0 + ); + UHD_ASSERT_THROW(ring_buffer != MAP_FAILED); + + //calculate the memory offsets for info and buffers + size_t recv_info_off = 0; + size_t recv_buff_off = recv_info_off + (_rb_size.num_pages_rx_flags * page_size); + size_t send_info_off = recv_buff_off + (_rb_size.num_rx_frames * _frame_size); + size_t send_buff_off = send_info_off + (_rb_size.num_pages_tx_flags * page_size); + + //set the internal pointers for info and buffers + typedef ring_buffer_info (*rbi_pta)[]; + boost::uint8_t *rb_ptr = reinterpret_cast(ring_buffer); + _recv_info = reinterpret_cast(rb_ptr + recv_info_off); + _recv_buff = rb_ptr + recv_buff_off; + _send_info = reinterpret_cast(rb_ptr + send_info_off); + _send_buff = rb_ptr + send_buff_off; + } + + managed_recv_buffer::sptr get_recv_buff(size_t timeout_ms){ + //grab pointers to the info and buffer + ring_buffer_info *info = (*_recv_info) + _recv_index; + void *mem = _recv_buff + _frame_size*_recv_index; + + //poll/wait for a ready frame + if (not (info->flags & RB_USER)){ + pollfd pfd; + pfd.fd = _fd; + pfd.events = POLLIN; + ssize_t poll_ret = poll(&pfd, 1, timeout_ms); + if (poll_ret <= 0) return managed_recv_buffer::sptr(); + } + + //increment the index for the next call + if (++_recv_index == size_t(_rb_size.num_rx_frames)) _recv_index = 0; + + //return the managed buffer for this frame + return managed_recv_buffer::sptr( + new usrp_e_mmap_managed_recv_buffer(mem, info->len, info) + ); + } + + size_t get_num_recv_frames(void) const{ + return _rb_size.num_rx_frames; + } + + managed_send_buffer::sptr get_send_buff(void){ + //grab pointers to the info and buffer + ring_buffer_info *info = (*_send_info) + _send_index; + void *mem = _send_buff + _frame_size*_send_index; + + //poll/wait for a ready frame + if (not (info->flags & RB_KERNEL)){ + pollfd pfd; + pfd.fd = _fd; + pfd.events = POLLOUT; + ssize_t poll_ret = poll(&pfd, 1, -1 /*forever*/); + if (poll_ret <= 0) return managed_send_buffer::sptr(); + } + + //increment the index for the next call + if (++_send_index == size_t(_rb_size.num_tx_frames)) _send_index = 0; + + //return the managed buffer for this frame + return managed_send_buffer::sptr( + new usrp_e_mmap_managed_send_buffer(mem, _frame_size, info, _fd) + ); + } + + size_t get_num_send_frames(void) const{ + return _rb_size.num_tx_frames; + } + +private: + int _fd; + usrp_e_ring_buffer_size_t _rb_size; + size_t _frame_size; + ring_buffer_info (*_recv_info)[], (*_send_info)[]; + boost::uint8_t *_recv_buff, *_send_buff; + size_t _recv_index, _send_index; +}; + +/*********************************************************************** + * The zero copy interface make function + **********************************************************************/ +zero_copy_if::sptr usrp_e_make_mmap_zero_copy(usrp_e_iface::sptr iface){ + return zero_copy_if::sptr(new usrp_e_mmap_zero_copy_impl(iface)); +} -- cgit v1.2.3 From c0e03bb2edea4645f46f25afcc9be8b7b03f68df Mon Sep 17 00:00:00 2001 From: root Date: Thu, 30 Sep 2010 18:25:24 +0000 Subject: Ignore direction for GPIO 114 since it is always an input. --- host/apps/omap_debug/fpga-downloader.cc | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/host/apps/omap_debug/fpga-downloader.cc b/host/apps/omap_debug/fpga-downloader.cc index fb96b64a3..4e475b5c1 100644 --- a/host/apps/omap_debug/fpga-downloader.cc +++ b/host/apps/omap_debug/fpga-downloader.cc @@ -97,15 +97,17 @@ gpio::gpio(unsigned int gpio_num, gpio_direction pin_direction) std::fstream direction_file; std::string direction_file_name; - direction_file_name = base_path.str() + "/direction"; - - direction_file.open(direction_file_name.c_str()); - if (!direction_file.is_open()) - std::cout << "Failed to open direction file." << std::endl; - if (pin_direction == OUT) - direction_file << "out" << std::endl; - else - direction_file << "in" << std::endl; + if (gpio_num != 114) { + direction_file_name = base_path.str() + "/direction"; + + direction_file.open(direction_file_name.c_str()); + if (!direction_file.is_open()) + std::cout << "Failed to open direction file." << std::endl; + if (pin_direction == OUT) + direction_file << "out" << std::endl; + else + direction_file << "in" << std::endl; + } std::string value_file_name; -- cgit v1.2.3 From b34af3c910a54d8afd4b1f00f1254c3ab762c82a Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 4 Oct 2010 11:17:01 -0700 Subject: usrp-e: implemented mmap with new zero_copy timeout work, added much debug verbosity --- host/lib/usrp/usrp_e/io_impl.cpp | 48 ++++---- host/lib/usrp/usrp_e/usrp_e_impl.hpp | 6 +- host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp | 161 ++++++++++++------------- 3 files changed, 107 insertions(+), 108 deletions(-) diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index 0b5fa054b..1e577a4df 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -37,7 +37,7 @@ zero_copy_if::sptr usrp_e_make_mmap_zero_copy(usrp_e_iface::sptr iface); **********************************************************************/ static const size_t tx_async_report_sid = 1; static const int underflow_flags = async_metadata_t::EVENT_CODE_UNDERFLOW | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET; -static const double recv_timeout_ms = 100; +static const bool recv_debug = true; /*********************************************************************** * io impl details (internal to this file) @@ -66,10 +66,10 @@ struct usrp_e_impl::io_impl{ recv_pirate_crew.join_all(); } - bool get_recv_buffs(vrt_packet_handler::managed_recv_buffs_t &buffs, size_t timeout_ms){ + bool get_recv_buffs(vrt_packet_handler::managed_recv_buffs_t &buffs, double timeout){ UHD_ASSERT_THROW(buffs.size() == 1); boost::this_thread::disable_interruption di; //disable because the wait can throw - return recv_pirate_booty->pop_with_timed_wait(buffs.front(), boost::posix_time::milliseconds(timeout_ms)); + return recv_pirate_booty->pop_with_timed_wait(buffs.front(), timeout); } //a pirate's life is the life for me! @@ -94,9 +94,17 @@ void usrp_e_impl::io_impl::recv_pirate_loop( //size_t next_packet_seq = 0; while(recv_pirate_crew_raiding){ - managed_recv_buffer::sptr buff = this->data_xport->get_recv_buff(recv_timeout_ms); + managed_recv_buffer::sptr buff = this->data_xport->get_recv_buff(); if (not buff.get()) continue; //ignore timeout/error buffers + if (recv_debug){ + std::cout << "len " << buff->size() << std::endl; + for (size_t i = 0; i < 9; i++){ + std::cout << boost::format(" 0x%08x") % buff->cast()[i] << std::endl; + } + std::cout << std::endl << std::endl; + } + try{ //extract the vrt header packet info vrt::if_packet_info_t if_packet_info; @@ -181,20 +189,18 @@ void usrp_e_impl::handle_overrun(size_t){ * Data Send **********************************************************************/ bool get_send_buffs( - zero_copy_if::sptr trans, + zero_copy_if::sptr trans, double timeout, vrt_packet_handler::managed_send_buffs_t &buffs ){ UHD_ASSERT_THROW(buffs.size() == 1); - buffs[0] = trans->get_send_buff(); + buffs[0] = trans->get_send_buff(timeout); return buffs[0].get() != NULL; } size_t usrp_e_impl::send( - const std::vector &buffs, - size_t num_samps, - const tx_metadata_t &metadata, - const io_type_t &io_type, - send_mode_t send_mode + const std::vector &buffs, size_t num_samps, + const tx_metadata_t &metadata, const io_type_t &io_type, + send_mode_t send_mode, double timeout ){ otw_type_t send_otw_type; send_otw_type.width = 16; @@ -208,7 +214,7 @@ size_t usrp_e_impl::send( io_type, send_otw_type, //input and output types to convert MASTER_CLOCK_RATE, //master clock tick rate uhd::transport::vrt::if_hdr_pack_le, - boost::bind(&get_send_buffs, _io_impl->data_xport, _1), + boost::bind(&get_send_buffs, _io_impl->data_xport, timeout, _1), get_max_send_samps_per_packet() ); } @@ -217,12 +223,9 @@ size_t usrp_e_impl::send( * Data Recv **********************************************************************/ size_t usrp_e_impl::recv( - const std::vector &buffs, - size_t num_samps, - rx_metadata_t &metadata, - const io_type_t &io_type, - recv_mode_t recv_mode, - size_t timeout_ms + const std::vector &buffs, size_t num_samps, + rx_metadata_t &metadata, const io_type_t &io_type, + recv_mode_t recv_mode, double timeout ){ otw_type_t recv_otw_type; recv_otw_type.width = 16; @@ -236,7 +239,7 @@ size_t usrp_e_impl::recv( io_type, recv_otw_type, //input and output types to convert MASTER_CLOCK_RATE, //master clock tick rate uhd::transport::vrt::if_hdr_unpack_le, - boost::bind(&usrp_e_impl::io_impl::get_recv_buffs, _io_impl.get(), _1, timeout_ms), + boost::bind(&usrp_e_impl::io_impl::get_recv_buffs, _io_impl.get(), _1, timeout), boost::bind(&usrp_e_impl::handle_overrun, this, _1) ); } @@ -245,11 +248,8 @@ size_t usrp_e_impl::recv( * Async Recv **********************************************************************/ bool usrp_e_impl::recv_async_msg( - async_metadata_t &async_metadata, - size_t timeout_ms + async_metadata_t &async_metadata, double timeout ){ boost::this_thread::disable_interruption di; //disable because the wait can throw - return _io_impl->async_msg_fifo->pop_with_timed_wait( - async_metadata, boost::posix_time::milliseconds(timeout_ms) - ); + return _io_impl->async_msg_fifo->pop_with_timed_wait(async_metadata, timeout); } diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index 2457e27cc..49912050e 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -82,9 +82,9 @@ public: ~usrp_e_impl(void); //the io interface - size_t send(const std::vector &, size_t, const uhd::tx_metadata_t &, const uhd::io_type_t &, send_mode_t); - size_t recv(const std::vector &, size_t, uhd::rx_metadata_t &, const uhd::io_type_t &, recv_mode_t, size_t); - bool recv_async_msg(uhd::async_metadata_t &, size_t); + size_t send(const std::vector &, size_t, const uhd::tx_metadata_t &, const uhd::io_type_t &, send_mode_t, double); + size_t recv(const std::vector &, size_t, uhd::rx_metadata_t &, const uhd::io_type_t &, recv_mode_t, double); + bool recv_async_msg(uhd::async_metadata_t &, double); size_t get_max_send_samps_per_packet(void) const{return 503;} size_t get_max_recv_samps_per_packet(void) const{return 503;} diff --git a/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp b/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp index 0910caa6f..e62205a3f 100644 --- a/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp @@ -15,86 +15,27 @@ // along with this program. If not, see . // +#include "usrp_e_iface.hpp" #include #include #include #include //mmap #include //getpagesize #include //poll -#include -#include "usrp_e_iface.hpp" +#include +#include +#include using namespace uhd; using namespace uhd::transport; -static const bool debug_verbose = false; - -/*********************************************************************** - * The managed receive buffer implementation - **********************************************************************/ -class usrp_e_mmap_managed_recv_buffer : public managed_recv_buffer{ -public: - usrp_e_mmap_managed_recv_buffer( - const void *mem, size_t len, ring_buffer_info *info - ): - _buff(mem, len), _info(info) - { - /* NOP */ - } - - ~usrp_e_mmap_managed_recv_buffer(void){ - _info->flags = RB_KERNEL; - } - -private: - const boost::asio::const_buffer &get(void) const{ - return _buff; - } - - const boost::asio::const_buffer _buff; - ring_buffer_info *_info; -}; - -/*********************************************************************** - * The managed send buffer implementation - **********************************************************************/ -class usrp_e_mmap_managed_send_buffer : public managed_send_buffer{ -public: - usrp_e_mmap_managed_send_buffer( - void *mem, size_t len, ring_buffer_info *info, int fd - ): - _buff(mem, len), _info(info), _fd(fd), _commited(false) - { - /* NOP */ - } - - ~usrp_e_mmap_managed_send_buffer(void){ - if (not _commited) this->commit(0); - } - - ssize_t commit(size_t num_bytes){ - _commited = true; - _info->len = num_bytes; - _info->flags = RB_USER; - ssize_t ret = ::write(_fd, NULL, 0); - return (ret < 0)? ret : num_bytes; - } - -private: - const boost::asio::mutable_buffer &get(void) const{ - return _buff; - } - - const boost::asio::mutable_buffer _buff; - ring_buffer_info *_info; - int _fd; - bool _commited; -}; +static const bool fp_verbose = true; //fast-path verbose +static const bool sp_verbose = true; //slow-path verbose /*********************************************************************** * The zero copy interface implementation **********************************************************************/ -class usrp_e_mmap_zero_copy_impl : public zero_copy_if{ +class usrp_e_mmap_zero_copy_impl : public zero_copy_if, public boost::enable_shared_from_this { public: usrp_e_mmap_zero_copy_impl(usrp_e_iface::sptr iface): _fd(iface->get_file_descriptor()), _recv_index(0), _send_index(0) @@ -105,15 +46,26 @@ public: _frame_size = page_size/2; //calculate the memory size - size_t map_size = + _map_size = (_rb_size.num_pages_rx_flags + _rb_size.num_pages_tx_flags) * page_size + (_rb_size.num_rx_frames + _rb_size.num_tx_frames) * _frame_size; + //print sizes summary + if (sp_verbose){ + std::cout << "page_size: " << page_size << std::endl; + std::cout << "frame_size: " << _frame_size << std::endl; + std::cout << "num_pages_rx_flags: " << _rb_size.num_pages_rx_flags << std::endl; + std::cout << "num_rx_frames: " << _rb_size.num_rx_frames << std::endl; + std::cout << "num_pages_tx_flags: " << _rb_size.num_pages_tx_flags << std::endl; + std::cout << "num_tx_frames: " << _rb_size.num_tx_frames << std::endl; + std::cout << "map_size: " << _map_size << std::endl; + } + //call mmap to get the memory - void *ring_buffer = mmap( - NULL, map_size, PROT_READ | PROT_WRITE, MAP_SHARED, _fd, 0 + _mapped_mem = ::mmap( + NULL, _map_size, PROT_READ | PROT_WRITE, MAP_SHARED, _fd, 0 ); - UHD_ASSERT_THROW(ring_buffer != MAP_FAILED); + UHD_ASSERT_THROW(_mapped_mem != MAP_FAILED); //calculate the memory offsets for info and buffers size_t recv_info_off = 0; @@ -121,16 +73,31 @@ public: size_t send_info_off = recv_buff_off + (_rb_size.num_rx_frames * _frame_size); size_t send_buff_off = send_info_off + (_rb_size.num_pages_tx_flags * page_size); + //print offset summary + if (sp_verbose){ + std::cout << "recv_info_off: " << recv_info_off << std::endl; + std::cout << "recv_buff_off: " << recv_buff_off << std::endl; + std::cout << "send_info_off: " << send_info_off << std::endl; + std::cout << "send_buff_off: " << send_buff_off << std::endl; + } + //set the internal pointers for info and buffers typedef ring_buffer_info (*rbi_pta)[]; - boost::uint8_t *rb_ptr = reinterpret_cast(ring_buffer); + char *rb_ptr = reinterpret_cast(_mapped_mem); _recv_info = reinterpret_cast(rb_ptr + recv_info_off); _recv_buff = rb_ptr + recv_buff_off; _send_info = reinterpret_cast(rb_ptr + send_info_off); _send_buff = rb_ptr + send_buff_off; } - managed_recv_buffer::sptr get_recv_buff(size_t timeout_ms){ + ~usrp_e_mmap_zero_copy_impl(void){ + if (sp_verbose) std::cout << "cleanup: munmap" << std::endl; + ::munmap(_mapped_mem, _map_size); + } + + managed_recv_buffer::sptr get_recv_buff(double timeout){ + if (fp_verbose) std::cout << "get_recv_buff: " << _recv_index << std::endl; + //grab pointers to the info and buffer ring_buffer_info *info = (*_recv_info) + _recv_index; void *mem = _recv_buff + _frame_size*_recv_index; @@ -140,7 +107,8 @@ public: pollfd pfd; pfd.fd = _fd; pfd.events = POLLIN; - ssize_t poll_ret = poll(&pfd, 1, timeout_ms); + ssize_t poll_ret = ::poll(&pfd, 1, size_t(timeout*1e3)); + if (fp_verbose) std::cout << " POLLIN: " << poll_ret << std::endl; if (poll_ret <= 0) return managed_recv_buffer::sptr(); } @@ -148,8 +116,10 @@ public: if (++_recv_index == size_t(_rb_size.num_rx_frames)) _recv_index = 0; //return the managed buffer for this frame - return managed_recv_buffer::sptr( - new usrp_e_mmap_managed_recv_buffer(mem, info->len, info) + if (fp_verbose) std::cout << " make_recv_buff: " << info->len << std::endl; + return managed_recv_buffer::make_safe( + boost::asio::const_buffer(mem, info->len), + boost::bind(&usrp_e_mmap_zero_copy_impl::release, shared_from_this(), info) ); } @@ -157,7 +127,9 @@ public: return _rb_size.num_rx_frames; } - managed_send_buffer::sptr get_send_buff(void){ + managed_send_buffer::sptr get_send_buff(double timeout){ + if (fp_verbose) std::cout << "get_send_buff: " << _send_index << std::endl; + //grab pointers to the info and buffer ring_buffer_info *info = (*_send_info) + _send_index; void *mem = _send_buff + _frame_size*_send_index; @@ -167,7 +139,8 @@ public: pollfd pfd; pfd.fd = _fd; pfd.events = POLLOUT; - ssize_t poll_ret = poll(&pfd, 1, -1 /*forever*/); + ssize_t poll_ret = ::poll(&pfd, 1, size_t(timeout*1e3)); + if (fp_verbose) std::cout << " POLLOUT: " << poll_ret << std::endl; if (poll_ret <= 0) return managed_send_buffer::sptr(); } @@ -175,8 +148,10 @@ public: if (++_send_index == size_t(_rb_size.num_tx_frames)) _send_index = 0; //return the managed buffer for this frame - return managed_send_buffer::sptr( - new usrp_e_mmap_managed_send_buffer(mem, _frame_size, info, _fd) + if (fp_verbose) std::cout << " make_send_buff: " << _frame_size << std::endl; + return managed_send_buffer::make_safe( + boost::asio::mutable_buffer(mem, _frame_size), + boost::bind(&usrp_e_mmap_zero_copy_impl::commit, shared_from_this(), info, _1) ); } @@ -185,11 +160,35 @@ public: } private: + + void release(ring_buffer_info *info){ + if (fp_verbose) std::cout << "recv buff: release" << std::endl; + info->flags = RB_KERNEL; + } + + void commit(ring_buffer_info *info, size_t len){ + if (fp_verbose) std::cout << "send buff: commit " << len << std::endl; + info->len = len; + info->flags = RB_USER; + if (::write(_fd, NULL, 0) < 0){ + std::cerr << UHD_THROW_SITE_INFO("write error") << std::endl; + } + } + int _fd; + + //the mapped memory itself + void *_mapped_mem; + + //mapped memory sizes usrp_e_ring_buffer_size_t _rb_size; - size_t _frame_size; + size_t _frame_size, _map_size; + + //pointers to sections in the mapped memory ring_buffer_info (*_recv_info)[], (*_send_info)[]; - boost::uint8_t *_recv_buff, *_send_buff; + char *_recv_buff, *_send_buff; + + //indexes into sub-sections of mapped memory size_t _recv_index, _send_index; }; -- cgit v1.2.3 From f642942dc364c1d26a9128c1ba631d3604d0671a Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 4 Oct 2010 15:17:57 -0700 Subject: usrp-e: check if flags are ready after poll --- host/lib/usrp/usrp_e/io_impl.cpp | 6 +++--- host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp | 12 ++++++++++++ 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index 1e577a4df..2802a6b87 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -130,12 +130,12 @@ void usrp_e_impl::io_impl::recv_pirate_loop( continue; } + //same number of frames as the data transport -> always immediate + recv_pirate_booty->push_with_wait(buff); + }catch(const std::exception &e){ std::cerr << "Error (usrp-e recv pirate loop): " << e.what() << std::endl; } - - //usrp-e back-pressures on receive: push with wait - recv_pirate_booty->push_with_wait(buff); } } diff --git a/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp b/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp index e62205a3f..9e25ed088 100644 --- a/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp @@ -112,6 +112,12 @@ public: if (poll_ret <= 0) return managed_recv_buffer::sptr(); } + //check that the frame is really ready + if (not (info->flags & RB_USER)){ + if (fp_verbose) std::cout << " flags: not ready" << std::endl; + return managed_recv_buffer::sptr(); + } + //increment the index for the next call if (++_recv_index == size_t(_rb_size.num_rx_frames)) _recv_index = 0; @@ -144,6 +150,12 @@ public: if (poll_ret <= 0) return managed_send_buffer::sptr(); } + //check that the frame is really ready + if (not (info->flags & RB_KERNEL)){ + if (fp_verbose) std::cout << " flags: not ready" << std::endl; + return managed_send_buffer::sptr(); + } + //increment the index for the next call if (++_send_index == size_t(_rb_size.num_tx_frames)) _send_index = 0; -- cgit v1.2.3 From 12901b055f021acf1b02f4bc7e9c3c8d1aa426e5 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 6 Oct 2010 18:48:03 -0400 Subject: Add flag that indicates userspace has started processing a frame. --- host/include/linux/usrp_e.h | 1 + 1 file changed, 1 insertion(+) diff --git a/host/include/linux/usrp_e.h b/host/include/linux/usrp_e.h index 80f3a287b..cb62d940d 100644 --- a/host/include/linux/usrp_e.h +++ b/host/include/linux/usrp_e.h @@ -71,6 +71,7 @@ struct usrp_e_i2c { #define RB_KERNEL (1<<1) #define RB_OVERRUN (1<<2) #define RB_DMA_ACTIVE (1<<3) +#define RB_USER_PROCESS (1<<4) struct ring_buffer_info { int flags; -- cgit v1.2.3 From d5a0960455560e9f6077aa45d52aa01c469769dd Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 6 Oct 2010 16:26:35 -0700 Subject: usrp-e: implemented the USER_PROCESS flag and CTM poll technique --- host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp | 33 +++++++++++--------------- 1 file changed, 14 insertions(+), 19 deletions(-) diff --git a/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp b/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp index 9e25ed088..4e10bcc48 100644 --- a/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp @@ -31,6 +31,7 @@ using namespace uhd::transport; static const bool fp_verbose = true; //fast-path verbose static const bool sp_verbose = true; //slow-path verbose +static const size_t poll_breakout = 10; //how many poll timeouts constitute a full timeout /*********************************************************************** * The zero copy interface implementation @@ -104,19 +105,19 @@ public: //poll/wait for a ready frame if (not (info->flags & RB_USER)){ - pollfd pfd; - pfd.fd = _fd; - pfd.events = POLLIN; - ssize_t poll_ret = ::poll(&pfd, 1, size_t(timeout*1e3)); - if (fp_verbose) std::cout << " POLLIN: " << poll_ret << std::endl; - if (poll_ret <= 0) return managed_recv_buffer::sptr(); - } - - //check that the frame is really ready - if (not (info->flags & RB_USER)){ - if (fp_verbose) std::cout << " flags: not ready" << std::endl; - return managed_recv_buffer::sptr(); - } + for (size_t i = 0; i < poll_breakout; i++){ + pollfd pfd; + pfd.fd = _fd; + pfd.events = POLLIN; + ssize_t poll_ret = ::poll(&pfd, 1, size_t(timeout*1e3/poll_breakout)); + if (fp_verbose) std::cout << " POLLIN: " << poll_ret << std::endl; + if (poll_ret > 0) goto found_user_frame; //good poll, continue on + } + return managed_recv_buffer::sptr(); //timed-out for real + } found_user_frame: + + //the process has claimed the frame + info->flags = RB_USER_PROCESS; //increment the index for the next call if (++_recv_index == size_t(_rb_size.num_rx_frames)) _recv_index = 0; @@ -150,12 +151,6 @@ public: if (poll_ret <= 0) return managed_send_buffer::sptr(); } - //check that the frame is really ready - if (not (info->flags & RB_KERNEL)){ - if (fp_verbose) std::cout << " flags: not ready" << std::endl; - return managed_send_buffer::sptr(); - } - //increment the index for the next call if (++_send_index == size_t(_rb_size.num_tx_frames)) _send_index = 0; -- cgit v1.2.3 From be6a6b291400dde7b2b3b935e2eedd8d892e54f8 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 7 Oct 2010 10:27:30 -0700 Subject: usrp-e: use frame size to calculate the max samples per packet --- host/lib/usrp/usrp_e/io_impl.cpp | 43 ++++++++++++++++++-------- host/lib/usrp/usrp_e/usrp_e_impl.hpp | 6 ++-- host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp | 8 +++++ 3 files changed, 42 insertions(+), 15 deletions(-) diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index 2802a6b87..406b7269f 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -91,7 +91,6 @@ void usrp_e_impl::io_impl::recv_pirate_loop( ){ set_thread_priority_safe(); recv_pirate_crew_raiding = true; - //size_t next_packet_seq = 0; while(recv_pirate_crew_raiding){ managed_recv_buffer::sptr buff = this->data_xport->get_recv_buff(); @@ -143,6 +142,15 @@ void usrp_e_impl::io_impl::recv_pirate_loop( * Helper Functions **********************************************************************/ void usrp_e_impl::io_init(void){ + //setup otw types + _send_otw_type.width = 16; + _send_otw_type.shift = 0; + _send_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN; + + _recv_otw_type.width = 16; + _recv_otw_type.shift = 0; + _recv_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN; + //setup rx data path _iface->poke32(UE_REG_CTRL_RX_NSAMPS_PER_PKT, get_max_recv_samps_per_packet()); _iface->poke32(UE_REG_CTRL_RX_NCHANNELS, 1); @@ -197,21 +205,25 @@ bool get_send_buffs( return buffs[0].get() != NULL; } +size_t usrp_e_impl::get_max_send_samps_per_packet(void) const{ + static const size_t hdr_size = 0 + + vrt::max_if_hdr_words32*sizeof(boost::uint32_t) + - sizeof(vrt::if_packet_info_t().cid) //no class id ever used + ; + size_t bpp = _io_impl->data_xport->get_send_frame_size() - hdr_size; + return bpp/_send_otw_type.get_sample_size(); +} + size_t usrp_e_impl::send( const std::vector &buffs, size_t num_samps, const tx_metadata_t &metadata, const io_type_t &io_type, send_mode_t send_mode, double timeout ){ - otw_type_t send_otw_type; - send_otw_type.width = 16; - send_otw_type.shift = 0; - send_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN; - return vrt_packet_handler::send( _io_impl->packet_handler_send_state, //last state of the send handler buffs, num_samps, //buffer to fill metadata, send_mode, //samples metadata - io_type, send_otw_type, //input and output types to convert + io_type, _send_otw_type, //input and output types to convert MASTER_CLOCK_RATE, //master clock tick rate uhd::transport::vrt::if_hdr_pack_le, boost::bind(&get_send_buffs, _io_impl->data_xport, timeout, _1), @@ -222,21 +234,26 @@ size_t usrp_e_impl::send( /*********************************************************************** * Data Recv **********************************************************************/ +size_t usrp_e_impl::get_max_recv_samps_per_packet(void) const{ + static const size_t hdr_size = 0 + + vrt::max_if_hdr_words32*sizeof(boost::uint32_t) + + sizeof(vrt::if_packet_info_t().tlr) //forced to have trailer + - sizeof(vrt::if_packet_info_t().cid) //no class id ever used + ; + size_t bpp = _io_impl->data_xport->get_recv_frame_size() - hdr_size; + return bpp/_recv_otw_type.get_sample_size(); +} + size_t usrp_e_impl::recv( const std::vector &buffs, size_t num_samps, rx_metadata_t &metadata, const io_type_t &io_type, recv_mode_t recv_mode, double timeout ){ - otw_type_t recv_otw_type; - recv_otw_type.width = 16; - recv_otw_type.shift = 0; - recv_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN; - return vrt_packet_handler::recv( _io_impl->packet_handler_recv_state, //last state of the recv handler buffs, num_samps, //buffer to fill metadata, recv_mode, //samples metadata - io_type, recv_otw_type, //input and output types to convert + io_type, _recv_otw_type, //input and output types to convert MASTER_CLOCK_RATE, //master clock tick rate uhd::transport::vrt::if_hdr_unpack_le, boost::bind(&usrp_e_impl::io_impl::get_recv_buffs, _io_impl.get(), _1, timeout), diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index 49912050e..95d80fed5 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -85,8 +86,8 @@ public: size_t send(const std::vector &, size_t, const uhd::tx_metadata_t &, const uhd::io_type_t &, send_mode_t, double); size_t recv(const std::vector &, size_t, uhd::rx_metadata_t &, const uhd::io_type_t &, recv_mode_t, double); bool recv_async_msg(uhd::async_metadata_t &, double); - size_t get_max_send_samps_per_packet(void) const{return 503;} - size_t get_max_recv_samps_per_packet(void) const{return 503;} + size_t get_max_send_samps_per_packet(void) const; + size_t get_max_recv_samps_per_packet(void) const; private: //interface to ioctls and file descriptor @@ -97,6 +98,7 @@ private: //handle io stuff UHD_PIMPL_DECL(io_impl) _io_impl; + uhd::otw_type_t _send_otw_type, _recv_otw_type; void io_init(void); void issue_stream_cmd(const uhd::stream_cmd_t &stream_cmd); void handle_overrun(size_t); diff --git a/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp b/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp index 4e10bcc48..bc18c490b 100644 --- a/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp @@ -134,6 +134,10 @@ public: return _rb_size.num_rx_frames; } + size_t get_recv_frame_size(void) const{ + return _frame_size; + } + managed_send_buffer::sptr get_send_buff(double timeout){ if (fp_verbose) std::cout << "get_send_buff: " << _send_index << std::endl; @@ -166,6 +170,10 @@ public: return _rb_size.num_tx_frames; } + size_t get_send_frame_size(void) const{ + return _frame_size; + } + private: void release(ring_buffer_info *info){ -- cgit v1.2.3 From c830a0d2c491fb61c2b401db94ed0a147bca4a24 Mon Sep 17 00:00:00 2001 From: root Date: Wed, 13 Oct 2010 23:00:20 +0000 Subject: USRP-E: updated the loopback tester for length checking. Checks lengths by pushing them into a circular buffer and popping them out. Protected by mutex so it doesn't go chewing on itself. --- host/utils/usrp-e-loopback.c | 47 +++++++++++++++++++++++++++++++++++++++----- 1 file changed, 42 insertions(+), 5 deletions(-) diff --git a/host/utils/usrp-e-loopback.c b/host/utils/usrp-e-loopback.c index f400fe0be..454d81ba7 100644 --- a/host/utils/usrp-e-loopback.c +++ b/host/utils/usrp-e-loopback.c @@ -8,7 +8,7 @@ #include #include -// max length #define PKT_DATA_LENGTH 1016 +#define MAX_PACKET_SIZE 1016 static int packet_data_length; static int error; @@ -19,6 +19,30 @@ struct pkt { short data[]; }; +static int length_array[2048]; +static int length_array_tail = 0; +static int length_array_head = 0; + +pthread_mutex_t length_array_mutex; //gotta lock the index to keep it from getting hosed + +//yes this is a circular buffer that does not check empty +//no i don't want to hear about it +void push_length_array(int length) { + pthread_mutex_lock(&length_array_mutex); + if(length_array_tail > 2047) length_array_tail = 0; + length_array[length_array_tail++] = length; + pthread_mutex_unlock(&length_array_mutex); +} + +int pop_length_array(void) { + int retval; + pthread_mutex_lock(&length_array_mutex); + if(length_array_head > 2047) length_array_head = 0; + retval = length_array[length_array_head++]; + pthread_mutex_unlock(&length_array_mutex); + return retval; +} + static int fp; static int calc_checksum(struct pkt *p) @@ -29,10 +53,10 @@ static int calc_checksum(struct pkt *p) sum = 0; for (i=0; i < p->len; i++) - sum += p->data[i]; + sum ^= p->data[i]; - sum += p->seq_num; - sum += p->len; + sum ^= p->seq_num; + sum ^= p->len; return sum; } @@ -44,6 +68,7 @@ static void *read_thread(void *threadid) struct pkt *p; unsigned long bytes_transfered, elapsed_seconds; struct timeval start_time, finish_time; + int expected_count; printf("Greetings from the reading thread!\n"); @@ -78,6 +103,11 @@ static void *read_thread(void *threadid) error = 1; } + expected_count = pop_length_array()*2+12; + if(cnt != expected_count) { + printf("Received %d bytes, expected %d\n", cnt, expected_count); + } + prev_seq_num = p->seq_num; if (calc_checksum(p) != p->checksum) { @@ -131,7 +161,9 @@ static void *write_thread(void *threadid) if (packet_data_length > 0) p->len = packet_data_length; else - p->len = (random() & 0x1ff) + (1004 - 512); + p->len = (random()<<1 & 0x1ff) + (1004 - 512); + + push_length_array(p->len); p->checksum = calc_checksum(p); @@ -146,6 +178,7 @@ static void *write_thread(void *threadid) int main(int argc, char *argv[]) { pthread_t tx, rx; + pthread_mutex_init(&length_array_mutex, 0); long int t; struct sched_param s = { .sched_priority = 1 @@ -159,6 +192,10 @@ int main(int argc, char *argv[]) } packet_data_length = atoi(argv[1]); + if(packet_data_length > MAX_PACKET_SIZE) { + printf("Packet size must be smaller than %i\n", MAX_PACKET_SIZE); + exit(-1); + } fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); -- cgit v1.2.3 From 0582d9f5bc4793aa0ce609933e8cc108255903e8 Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Thu, 14 Oct 2010 16:52:48 +0000 Subject: USRP-E: brought loopback test updates in from usrp_e branch. --- host/utils/usrp-e-loopback.c | 47 +++++++++++++++++++++++++++++++++++++++----- 1 file changed, 42 insertions(+), 5 deletions(-) diff --git a/host/utils/usrp-e-loopback.c b/host/utils/usrp-e-loopback.c index f400fe0be..454d81ba7 100644 --- a/host/utils/usrp-e-loopback.c +++ b/host/utils/usrp-e-loopback.c @@ -8,7 +8,7 @@ #include #include -// max length #define PKT_DATA_LENGTH 1016 +#define MAX_PACKET_SIZE 1016 static int packet_data_length; static int error; @@ -19,6 +19,30 @@ struct pkt { short data[]; }; +static int length_array[2048]; +static int length_array_tail = 0; +static int length_array_head = 0; + +pthread_mutex_t length_array_mutex; //gotta lock the index to keep it from getting hosed + +//yes this is a circular buffer that does not check empty +//no i don't want to hear about it +void push_length_array(int length) { + pthread_mutex_lock(&length_array_mutex); + if(length_array_tail > 2047) length_array_tail = 0; + length_array[length_array_tail++] = length; + pthread_mutex_unlock(&length_array_mutex); +} + +int pop_length_array(void) { + int retval; + pthread_mutex_lock(&length_array_mutex); + if(length_array_head > 2047) length_array_head = 0; + retval = length_array[length_array_head++]; + pthread_mutex_unlock(&length_array_mutex); + return retval; +} + static int fp; static int calc_checksum(struct pkt *p) @@ -29,10 +53,10 @@ static int calc_checksum(struct pkt *p) sum = 0; for (i=0; i < p->len; i++) - sum += p->data[i]; + sum ^= p->data[i]; - sum += p->seq_num; - sum += p->len; + sum ^= p->seq_num; + sum ^= p->len; return sum; } @@ -44,6 +68,7 @@ static void *read_thread(void *threadid) struct pkt *p; unsigned long bytes_transfered, elapsed_seconds; struct timeval start_time, finish_time; + int expected_count; printf("Greetings from the reading thread!\n"); @@ -78,6 +103,11 @@ static void *read_thread(void *threadid) error = 1; } + expected_count = pop_length_array()*2+12; + if(cnt != expected_count) { + printf("Received %d bytes, expected %d\n", cnt, expected_count); + } + prev_seq_num = p->seq_num; if (calc_checksum(p) != p->checksum) { @@ -131,7 +161,9 @@ static void *write_thread(void *threadid) if (packet_data_length > 0) p->len = packet_data_length; else - p->len = (random() & 0x1ff) + (1004 - 512); + p->len = (random()<<1 & 0x1ff) + (1004 - 512); + + push_length_array(p->len); p->checksum = calc_checksum(p); @@ -146,6 +178,7 @@ static void *write_thread(void *threadid) int main(int argc, char *argv[]) { pthread_t tx, rx; + pthread_mutex_init(&length_array_mutex, 0); long int t; struct sched_param s = { .sched_priority = 1 @@ -159,6 +192,10 @@ int main(int argc, char *argv[]) } packet_data_length = atoi(argv[1]); + if(packet_data_length > MAX_PACKET_SIZE) { + printf("Packet size must be smaller than %i\n", MAX_PACKET_SIZE); + exit(-1); + } fp = open("/dev/usrp_e0", O_RDWR); printf("fp = %d\n", fp); -- cgit v1.2.3 From 9348c2764dbbdf01e34a3ec7b5c8e74964b355e0 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 14 Oct 2010 21:41:14 -0400 Subject: usrp_e: back out dynamic send/recv samples calculation. --- host/lib/usrp/usrp_e/io_impl.cpp | 6 +++++- host/lib/usrp/usrp_e/usrp_e_impl.hpp | 5 +++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index 406b7269f..d89a7db07 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -37,7 +37,7 @@ zero_copy_if::sptr usrp_e_make_mmap_zero_copy(usrp_e_iface::sptr iface); **********************************************************************/ static const size_t tx_async_report_sid = 1; static const int underflow_flags = async_metadata_t::EVENT_CODE_UNDERFLOW | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET; -static const bool recv_debug = true; +static const bool recv_debug = false; /*********************************************************************** * io impl details (internal to this file) @@ -205,6 +205,7 @@ bool get_send_buffs( return buffs[0].get() != NULL; } +#if 0 size_t usrp_e_impl::get_max_send_samps_per_packet(void) const{ static const size_t hdr_size = 0 + vrt::max_if_hdr_words32*sizeof(boost::uint32_t) @@ -213,6 +214,7 @@ size_t usrp_e_impl::get_max_send_samps_per_packet(void) const{ size_t bpp = _io_impl->data_xport->get_send_frame_size() - hdr_size; return bpp/_send_otw_type.get_sample_size(); } +#endif size_t usrp_e_impl::send( const std::vector &buffs, size_t num_samps, @@ -234,6 +236,7 @@ size_t usrp_e_impl::send( /*********************************************************************** * Data Recv **********************************************************************/ +#if 0 size_t usrp_e_impl::get_max_recv_samps_per_packet(void) const{ static const size_t hdr_size = 0 + vrt::max_if_hdr_words32*sizeof(boost::uint32_t) @@ -243,6 +246,7 @@ size_t usrp_e_impl::get_max_recv_samps_per_packet(void) const{ size_t bpp = _io_impl->data_xport->get_recv_frame_size() - hdr_size; return bpp/_recv_otw_type.get_sample_size(); } +#endif size_t usrp_e_impl::recv( const std::vector &buffs, size_t num_samps, diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index 95d80fed5..9799cd645 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -86,8 +86,13 @@ public: size_t send(const std::vector &, size_t, const uhd::tx_metadata_t &, const uhd::io_type_t &, send_mode_t, double); size_t recv(const std::vector &, size_t, uhd::rx_metadata_t &, const uhd::io_type_t &, recv_mode_t, double); bool recv_async_msg(uhd::async_metadata_t &, double); +#if 0 size_t get_max_send_samps_per_packet(void) const; size_t get_max_recv_samps_per_packet(void) const; +#else + size_t get_max_send_samps_per_packet(void) const{return 503;} + size_t get_max_recv_samps_per_packet(void) const{return 503;} +#endif private: //interface to ioctls and file descriptor -- cgit v1.2.3 From 6b203950d9583ab882628311402e26cf40838aa0 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 14 Oct 2010 21:42:10 -0400 Subject: usrp_e: Disable debug. --- host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp b/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp index bc18c490b..274bb043e 100644 --- a/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp @@ -29,8 +29,8 @@ using namespace uhd; using namespace uhd::transport; -static const bool fp_verbose = true; //fast-path verbose -static const bool sp_verbose = true; //slow-path verbose +static const bool fp_verbose = false; //fast-path verbose +static const bool sp_verbose = false; //slow-path verbose static const size_t poll_breakout = 10; //how many poll timeouts constitute a full timeout /*********************************************************************** -- cgit v1.2.3 From c347ad973f4b51b00f66d7422cd03e8790de9be3 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 21 Oct 2010 13:57:50 -0400 Subject: usrp_e: Do not install main_test anymore. --- host/test/CMakeLists.txt | 1 - 1 file changed, 1 deletion(-) diff --git a/host/test/CMakeLists.txt b/host/test/CMakeLists.txt index 59a550f98..2cc987f0c 100644 --- a/host/test/CMakeLists.txt +++ b/host/test/CMakeLists.txt @@ -52,6 +52,5 @@ ENDFOREACH(test_source) ADD_LIBRARY(module_test MODULE module_test.cpp) INSTALL(TARGETS - main_test RUNTIME DESTINATION ${PKG_DATA_DIR}/tests ) -- cgit v1.2.3 From 3dc06cddaf0a0cf32f76be7077d1427ff4b71a7e Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 14 Oct 2010 14:47:34 -0400 Subject: usrp-e: Add example that reads data from uhd and sends it over a udp socket. --- host/examples/CMakeLists.txt | 4 ++ host/examples/rx_to_udp.cpp | 167 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 171 insertions(+) create mode 100644 host/examples/rx_to_udp.cpp diff --git a/host/examples/CMakeLists.txt b/host/examples/CMakeLists.txt index fb7777d42..3b36f3e71 100644 --- a/host/examples/CMakeLists.txt +++ b/host/examples/CMakeLists.txt @@ -25,6 +25,9 @@ TARGET_LINK_LIBRARIES(rx_timed_samples uhd) ADD_EXECUTABLE(rx_to_file rx_to_file.cpp) TARGET_LINK_LIBRARIES(rx_to_file uhd) +ADD_EXECUTABLE(rx_to_udp rx_to_udp.cpp) +TARGET_LINK_LIBRARIES(rx_to_udp uhd) + ADD_EXECUTABLE(test_async_messages test_async_messages.cpp) TARGET_LINK_LIBRARIES(test_async_messages uhd) @@ -48,6 +51,7 @@ INSTALL(TARGETS tx_timed_samples tx_from_file rx_to_file + rx_to_udp tx_waveforms RUNTIME DESTINATION ${PKG_DATA_DIR}/examples ) diff --git a/host/examples/rx_to_udp.cpp b/host/examples/rx_to_udp.cpp new file mode 100644 index 000000000..34b278599 --- /dev/null +++ b/host/examples/rx_to_udp.cpp @@ -0,0 +1,167 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sys/types.h" +#include "sys/socket.h" +#include "arpa/inet.h" + +namespace po = boost::program_options; + + +int UHD_SAFE_MAIN(int argc, char *argv[]){ + uhd::set_thread_priority_safe(); + + //variables to be set by po + std::string args; + time_t seconds_in_future; + size_t total_num_samps; + double rx_rate, freq; + short srv_port; + std::string srv_ip; + + //setup the program options + po::options_description desc("Allowed options"); + desc.add_options() + ("help", "help message") + ("args", po::value(&args)->default_value(""), "simple uhd device address args") + ("secs", po::value(&seconds_in_future)->default_value(3), "number of seconds in the future to receive") + ("nsamps", po::value(&total_num_samps)->default_value(1000), "total number of samples to receive") + ("rxrate", po::value(&rx_rate)->default_value(100e6/16), "rate of incoming samples") + ("freq", po::value(&freq)->default_value(0), "rf center frequency in Hz") + ("port", po::value(&srv_port)->default_value(7124), "server port") + ("ip", po::value(&srv_ip)->default_value("192.168.1.10"), "server ip") + ("dilv", "specify to disable inner-loop verbose") + ; + po::variables_map vm; + po::store(po::parse_command_line(argc, argv, desc), vm); + po::notify(vm); + + //print the help message + if (vm.count("help")){ + std::cout << boost::format("UHD RX Timed Samples %s") % desc << std::endl; + return ~0; + } + + bool verbose = vm.count("dilv") == 0; + + //create a usrp device + std::cout << std::endl; + std::cout << boost::format("Creating the usrp device with: %s...") % args << std::endl; + uhd::usrp::simple_usrp::sptr sdev = uhd::usrp::simple_usrp::make(args); + uhd::device::sptr dev = sdev->get_device(); + std::cout << boost::format("Using Device: %s") % sdev->get_pp_string() << std::endl; + + //set properties on the device + std::cout << boost::format("Setting RX Rate: %f Msps...") % (rx_rate/1e6) << std::endl; + sdev->set_rx_rate(rx_rate); + std::cout << boost::format("Actual RX Rate: %f Msps...") % (sdev->get_rx_rate()/1e6) << std::endl; + std::cout << boost::format("Setting device timestamp to 0...") << std::endl; + sdev->set_rx_freq(freq); + sdev->set_time_now(uhd::time_spec_t(0.0)); + + uhd::gain_range_t rx_gain = sdev->get_rx_gain_range(); + std::cout << "Setting RX Gain to: " << rx_gain.max << std::endl; + sdev->set_rx_gain(rx_gain.max); + + sleep(1); + std::cout << "LO Locked = " << sdev->get_rx_lo_locked() << std::endl; + + //setup streaming + std::cout << std::endl; + std::cout << boost::format( + "Begin streaming %u samples, %d seconds in the future..." + ) % total_num_samps % seconds_in_future << std::endl; + uhd::stream_cmd_t stream_cmd(uhd::stream_cmd_t::STREAM_MODE_NUM_SAMPS_AND_DONE); + stream_cmd.num_samps = total_num_samps; + stream_cmd.stream_now = false; + stream_cmd.time_spec = uhd::time_spec_t(seconds_in_future); + sdev->issue_stream_cmd(stream_cmd); + + //loop until total number of samples reached + size_t num_acc_samps = 0; //number of accumulated samples + uhd::rx_metadata_t md; + std::vector > buff(368); + std::ofstream outfile("out.dat", std::ofstream::binary); + + int s; + struct sockaddr_in si_other; + if ((s = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP)) == -1) { + std::cout << "Failid to open socket." << std::endl; + return -1; + } + + memset((char *) &si_other, 0, sizeof(si_other)); + si_other.sin_family = AF_INET; + si_other.sin_port = htons(srv_port); + if (inet_aton(srv_ip.c_str(), &si_other.sin_addr) == 0) { + std::cout << "Bad inet addr: " << srv_ip << std::endl; + return -1; + } + + while(num_acc_samps < total_num_samps){ + size_t num_rx_samps = dev->recv( + &buff.front(), buff.size(), md, + uhd::io_type_t::COMPLEX_FLOAT32, + uhd::device::RECV_MODE_ONE_PACKET + ); + + //handle the error codes + switch(md.error_code){ + case uhd::rx_metadata_t::ERROR_CODE_NONE: + break; + + case uhd::rx_metadata_t::ERROR_CODE_TIMEOUT: + if (num_acc_samps == 0) continue; + std::cout << boost::format( + "Got timeout before all samples received, possible packet loss, exiting loop..." + ) << std::endl; + goto done_loop; + + default: + std::cout << boost::format( + "Got error code 0x%x, exiting loop..." + ) % md.error_code << std::endl; + goto done_loop; + } + +// outfile.write((const char*)&buff[0], num_rx_samps * sizeof(std::complex)); + if (sendto(s, (const char *)&buff[0], num_rx_samps * sizeof(std::complex), 0 , (const sockaddr *)&si_other, sizeof(si_other)) == -1) + std::cout << "Sendto failed." << std::endl; + + if(verbose) std::cout << boost::format( + "Got packet: %u samples, %u full secs, %f frac secs" + ) % num_rx_samps % md.time_spec.get_full_secs() % md.time_spec.get_frac_secs() << std::endl; + + num_acc_samps += num_rx_samps; + } done_loop: + + outfile.close(); + + //finished + std::cout << std::endl << "Done!" << std::endl << std::endl; + + return 0; +} -- cgit v1.2.3 From db0e3e574e9058ad51cacea91ccc42f0baed95fa Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 21 Oct 2010 22:26:53 -0400 Subject: usrp_e: Add driver compatibility ioctl to header file. --- host/apps/omap_debug/usrp_e.h | 3 +++ host/include/linux/usrp_e.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/host/apps/omap_debug/usrp_e.h b/host/apps/omap_debug/usrp_e.h index fd38027d4..f96706c4a 100644 --- a/host/apps/omap_debug/usrp_e.h +++ b/host/apps/omap_debug/usrp_e.h @@ -41,6 +41,9 @@ struct usrp_e_ctl32 { #define UE_SPI_PUSH_FALL UE_SPI_CTRL_TXNEG #define UE_SPI_LATCH_RISE 0 #define UE_SPI_LATCH_FALL UE_SPI_CTRL_RXNEG +#define USRP_E_GET_COMPAT_NUMBER _IO(USRP_E_IOC_MAGIC, 0x28) + +#define USRP_E_COMPAT_NUMBER 1 struct usrp_e_spi { __u8 readback; diff --git a/host/include/linux/usrp_e.h b/host/include/linux/usrp_e.h index cb62d940d..4c6a5dd89 100644 --- a/host/include/linux/usrp_e.h +++ b/host/include/linux/usrp_e.h @@ -65,6 +65,9 @@ struct usrp_e_i2c { #define USRP_E_I2C_READ _IOWR(USRP_E_IOC_MAGIC, 0x25, struct usrp_e_i2c) #define USRP_E_I2C_WRITE _IOW(USRP_E_IOC_MAGIC, 0x26, struct usrp_e_i2c) #define USRP_E_GET_RB_INFO _IOR(USRP_E_IOC_MAGIC, 0x27, struct usrp_e_ring_buffer_size_t) +#define USRP_E_GET_COMPAT_NUMBER _IO(USRP_E_IOC_MAGIC, 0x28) + +#define USRP_E_COMPAT_NUMBER 1 /* Flag defines */ #define RB_USER (1<<0) -- cgit v1.2.3 From fa689c7202a0cab6bf0debc3524f1f46636a7ba0 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 27 Oct 2010 08:31:01 -0700 Subject: usrp_e: fix to get compiling with next branch --- host/lib/usrp/usrp_e/dboard_impl.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/host/lib/usrp/usrp_e/dboard_impl.cpp b/host/lib/usrp/usrp_e/dboard_impl.cpp index d4a27cb72..f2840dcfc 100644 --- a/host/lib/usrp/usrp_e/dboard_impl.cpp +++ b/host/lib/usrp/usrp_e/dboard_impl.cpp @@ -87,6 +87,7 @@ void usrp_e_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){ case DBOARD_PROP_GAIN_GROUP: val = make_gain_group( + _rx_db_eeprom.id, _dboard_manager->get_rx_subdev(key.name), _rx_codec_proxy->get_link(), GAIN_GROUP_POLICY_RX @@ -145,6 +146,7 @@ void usrp_e_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){ case DBOARD_PROP_GAIN_GROUP: val = make_gain_group( + _tx_db_eeprom.id, _dboard_manager->get_tx_subdev(key.name), _tx_codec_proxy->get_link(), GAIN_GROUP_POLICY_TX -- cgit v1.2.3 From 9585a0b6fd88efd2a8bd43c8b034ae21264b9fc4 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 27 Oct 2010 11:42:52 -0700 Subject: usrp_e: added support for building fpga image into images Makefile --- images/Makefile | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/images/Makefile b/images/Makefile index 57277e787..92379271d 100644 --- a/images/Makefile +++ b/images/Makefile @@ -111,6 +111,22 @@ $(_usrp2_fpga_bin): endif +######################################################################## +# USRP-E100 fpga +######################################################################## +ifdef HAS_XTCLSH + +_usrp_e100_fpga_dir = $(TOP_FPGA_DIR)/usrp2/top/u1e +_usrp_e100_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_e100_fpga.bin +IMAGES_LIST += $(_usrp_e100_fpga_bin) + +$(_usrp_e100_fpga_bin): + cd $(_usrp_e100_fpga_dir) && make clean + cd $(_usrp_e100_fpga_dir) && make bin + cp $(_usrp_e100_fpga_dir)/build/u1e.bin $@ + +endif + ######################################################################## # Build rules ######################################################################## -- cgit v1.2.3 From fa7704be20005a705efdc96aa785d80911638107 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 27 Oct 2010 13:10:48 -0700 Subject: usrp-e: implemented fpga loading and compat checking --- host/examples/rx_to_file.cpp | 8 ++-- host/examples/rx_to_udp.cpp | 8 ++-- host/lib/usrp/usrp_e/fpga-downloader.cc | 30 ++++++++------ host/lib/usrp/usrp_e/usrp_e_impl.cpp | 69 ++++++++++++++++++++++++++++++--- host/lib/usrp/usrp_e/usrp_e_impl.hpp | 4 +- host/lib/usrp/usrp_e/usrp_e_regs.hpp | 2 +- 6 files changed, 94 insertions(+), 27 deletions(-) diff --git a/host/examples/rx_to_file.cpp b/host/examples/rx_to_file.cpp index 79d3e9d8b..f08f7cee3 100644 --- a/host/examples/rx_to_file.cpp +++ b/host/examples/rx_to_file.cpp @@ -17,7 +17,7 @@ #include #include -#include +#include #include #include #include @@ -40,7 +40,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ po::options_description desc("Allowed options"); desc.add_options() ("help", "help message") - ("args", po::value(&args)->default_value(""), "simple uhd device address args") + ("args", po::value(&args)->default_value(""), "single uhd device address args") ("secs", po::value(&seconds_in_future)->default_value(3), "number of seconds in the future to receive") ("nsamps", po::value(&total_num_samps)->default_value(1000), "total number of samples to receive") ("rxrate", po::value(&rx_rate)->default_value(100e6/16), "rate of incoming samples") @@ -53,7 +53,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ //print the help message if (vm.count("help")){ - std::cout << boost::format("UHD RX Timed Samples %s") % desc << std::endl; + std::cout << boost::format("UHD RX to File %s") % desc << std::endl; return ~0; } @@ -62,7 +62,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ //create a usrp device std::cout << std::endl; std::cout << boost::format("Creating the usrp device with: %s...") % args << std::endl; - uhd::usrp::simple_usrp::sptr sdev = uhd::usrp::simple_usrp::make(args); + uhd::usrp::single_usrp::sptr sdev = uhd::usrp::single_usrp::make(args); uhd::device::sptr dev = sdev->get_device(); std::cout << boost::format("Using Device: %s") % sdev->get_pp_string() << std::endl; diff --git a/host/examples/rx_to_udp.cpp b/host/examples/rx_to_udp.cpp index 34b278599..c8b3d506b 100644 --- a/host/examples/rx_to_udp.cpp +++ b/host/examples/rx_to_udp.cpp @@ -17,7 +17,7 @@ #include #include -#include +#include #include #include #include @@ -46,7 +46,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ po::options_description desc("Allowed options"); desc.add_options() ("help", "help message") - ("args", po::value(&args)->default_value(""), "simple uhd device address args") + ("args", po::value(&args)->default_value(""), "single uhd device address args") ("secs", po::value(&seconds_in_future)->default_value(3), "number of seconds in the future to receive") ("nsamps", po::value(&total_num_samps)->default_value(1000), "total number of samples to receive") ("rxrate", po::value(&rx_rate)->default_value(100e6/16), "rate of incoming samples") @@ -61,7 +61,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ //print the help message if (vm.count("help")){ - std::cout << boost::format("UHD RX Timed Samples %s") % desc << std::endl; + std::cout << boost::format("UHD RX to UDP %s") % desc << std::endl; return ~0; } @@ -70,7 +70,7 @@ int UHD_SAFE_MAIN(int argc, char *argv[]){ //create a usrp device std::cout << std::endl; std::cout << boost::format("Creating the usrp device with: %s...") % args << std::endl; - uhd::usrp::simple_usrp::sptr sdev = uhd::usrp::simple_usrp::make(args); + uhd::usrp::single_usrp::sptr sdev = uhd::usrp::single_usrp::make(args); uhd::device::sptr dev = sdev->get_device(); std::cout << boost::format("Using Device: %s") % sdev->get_pp_string() << std::endl; diff --git a/host/lib/usrp/usrp_e/fpga-downloader.cc b/host/lib/usrp/usrp_e/fpga-downloader.cc index ff8671e98..b0d56e856 100644 --- a/host/lib/usrp/usrp_e/fpga-downloader.cc +++ b/host/lib/usrp/usrp_e/fpga-downloader.cc @@ -15,11 +15,14 @@ // along with this program. If not, see . // +#include + #include #include #include #include #include +#include #include #include @@ -82,8 +85,9 @@ gpio::gpio(unsigned int gpio_num, gpio_direction pin_direction) std::fstream export_file; export_file.open("/sys/class/gpio/export", std::ios::out); - if (!export_file.is_open()) ///\todo Poor error handling - std::cout << "Failed to open gpio export file." << std::endl; + if (not export_file.is_open()) throw std::runtime_error( + "Failed to open gpio export file." + ); export_file << gpio_num << std::endl; @@ -92,15 +96,17 @@ gpio::gpio(unsigned int gpio_num, gpio_direction pin_direction) std::fstream direction_file; std::string direction_file_name; - direction_file_name = base_path.str() + "/direction"; + if (gpio_num != 114) { + direction_file_name = base_path.str() + "/direction"; - direction_file.open(direction_file_name.c_str()); - if (!direction_file.is_open()) - std::cout << "Failed to open direction file." << std::endl; - if (pin_direction == OUT) - direction_file << "out" << std::endl; - else - direction_file << "in" << std::endl; + direction_file.open(direction_file_name.c_str()); + if (!direction_file.is_open()) + std::cout << "Failed to open direction file." << std::endl; + if (pin_direction == OUT) + direction_file << "out" << std::endl; + else + direction_file << "in" << std::endl; + } std::string value_file_name; @@ -251,11 +257,11 @@ void usrp_e_load_fpga(const std::string &bin_file){ gpio gpio_init_b(INIT_B, IN); gpio gpio_done (DONE, IN); - std::cout << "FPGA config file: " << bin_file << std::endl; + std::cout << "Loading FPGA image: " << bin_file << "... " << std::flush; prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b); - std::cout << "Done = " << gpio_done.get_value() << std::endl; + std::cout << "done = " << gpio_done.get_value() << std::endl; send_file_to_fpga(bin_file, gpio_init_b, gpio_done); } diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.cpp b/host/lib/usrp/usrp_e/usrp_e_impl.cpp index 5c0e1dbb0..0a7295ff9 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.cpp @@ -16,13 +16,17 @@ // #include "usrp_e_impl.hpp" +#include "usrp_e_regs.hpp" #include #include #include #include +#include #include #include +#include #include +#include using namespace uhd; using namespace uhd::usrp; @@ -66,7 +70,64 @@ static device_addrs_t usrp_e_find(const device_addr_t &hint){ * Make **********************************************************************/ static device::sptr usrp_e_make(const device_addr_t &device_addr){ - return device::sptr(new usrp_e_impl(device_addr["node"])); + + //The fpga is loaded when: + // 1) The compatibility number matches. + // 2) The hash in the hash-file matches. + + //setup the main interface into fpga + std::string node = device_addr["node"]; + std::cout << boost::format("Opening USRP-E on %s") % node << std::endl; + usrp_e_iface::sptr iface = usrp_e_iface::make(node); + + //------------------------------------------------------------------ + //-- Handle the FPGA loading... + //-- The image can be confimed as already loaded when: + //-- 1) The compatibility number matches. + //-- 2) The hash in the hash-file matches. + //------------------------------------------------------------------ + + //extract the fpga path for usrp-e + std::string usrp_e_fpga_image = find_image_path( + device_addr.has_key("fpga")? device_addr["fpga"] : "usrp_e100_fpga.bin" + ); + + //calculate a hash of the fpga file + size_t fpga_hash = 0; + { + std::ifstream file(usrp_e_fpga_image.c_str()); + if (not file.good()) throw std::runtime_error( + "cannot open fpga file for read: " + usrp_e_fpga_image + ); + do{ + boost::hash_combine(fpga_hash, file.get()); + } while (file.good()); + file.close(); + } + + //read the compatibility number + boost::uint16_t fpga_compat_num = iface->peek16(UE_REG_MISC_COMPAT); + + //read the hash in the hash-file + size_t loaded_hash = 0; + try{std::ifstream(hash_file_path) >> loaded_hash;}catch(...){} + + //if not loaded: load the fpga image and write the hash-file + if (fpga_compat_num != USRP_E_COMPAT_NUM or loaded_hash != fpga_hash){ + usrp_e_load_fpga(usrp_e_fpga_image); + try{std::ofstream(hash_file_path) << fpga_hash;}catch(...){} + } + + //check that the compatibility is correct + fpga_compat_num = iface->peek16(UE_REG_MISC_COMPAT); + if (fpga_compat_num != USRP_E_COMPAT_NUM){ + throw std::runtime_error(str(boost::format( + "Expected fpga compatibility number 0x%x, but got 0x%x:\n" + "The fpga build is not compatible with the host code build." + ) % USRP_E_COMPAT_NUM % fpga_compat_num)); + } + + return device::sptr(new usrp_e_impl(iface)); } UHD_STATIC_BLOCK(register_usrp_e_device){ @@ -76,11 +137,9 @@ UHD_STATIC_BLOCK(register_usrp_e_device){ /*********************************************************************** * Structors **********************************************************************/ -usrp_e_impl::usrp_e_impl(const std::string &node){ - std::cout << boost::format("Opening USRP-E on %s") % node << std::endl; +usrp_e_impl::usrp_e_impl(usrp_e_iface::sptr iface): _iface(iface){ - //setup various interfaces into hardware - _iface = usrp_e_iface::make(node); + //setup interfaces into hardware _clock_ctrl = usrp_e_clock_ctrl::make(_iface); _codec_ctrl = usrp_e_codec_ctrl::make(_iface); diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index 9799cd645..421a9623d 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -31,6 +31,8 @@ #define INCLUDED_USRP_E_IMPL_HPP static const double MASTER_CLOCK_RATE = 64e6; //TODO get from clock control +static const char *hash_file_path = "/tmp/usrp_e100_hash"; +static const boost::uint16_t USRP_E_COMPAT_NUM = 0x02; //! load an fpga image from a bin file into the usrp-e fpga extern void usrp_e_load_fpga(const std::string &bin_file); @@ -79,7 +81,7 @@ private: class usrp_e_impl : public uhd::device{ public: //structors - usrp_e_impl(const std::string &node); + usrp_e_impl(usrp_e_iface::sptr); ~usrp_e_impl(void); //the io interface diff --git a/host/lib/usrp/usrp_e/usrp_e_regs.hpp b/host/lib/usrp/usrp_e/usrp_e_regs.hpp index a4f42093e..f74358f00 100644 --- a/host/lib/usrp/usrp_e/usrp_e_regs.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_regs.hpp @@ -30,7 +30,7 @@ #define UE_REG_MISC_CGEN_ST UE_REG_MISC_BASE + 6 #define UE_REG_MISC_TEST UE_REG_MISC_BASE + 8 #define UE_REG_MISC_RX_LEN UE_REG_MISC_BASE + 10 -#define UE_REG_MISC_TX_LEN UE_REG_MISC_BASE + 12 +#define UE_REG_MISC_COMPAT UE_REG_MISC_BASE + 12 ///////////////////////////////////////////////////// // Slave 1 -- UART -- cgit v1.2.3 From 0208b28e58e3719dc4dfb8df73fe5ae49e4a6306 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 27 Oct 2010 15:57:35 -0700 Subject: usrp-e: use clock control to get clock rate, removed temporary constant --- host/lib/usrp/usrp_e/dsp_impl.cpp | 16 ++++++++-------- host/lib/usrp/usrp_e/io_impl.cpp | 17 ++++++++--------- host/lib/usrp/usrp_e/mboard_impl.cpp | 2 +- host/lib/usrp/usrp_e/usrp_e_impl.cpp | 5 +---- host/lib/usrp/usrp_e/usrp_e_impl.hpp | 5 ----- 5 files changed, 18 insertions(+), 27 deletions(-) diff --git a/host/lib/usrp/usrp_e/dsp_impl.cpp b/host/lib/usrp/usrp_e/dsp_impl.cpp index 9312bb603..97f173c1a 100644 --- a/host/lib/usrp/usrp_e/dsp_impl.cpp +++ b/host/lib/usrp/usrp_e/dsp_impl.cpp @@ -65,11 +65,11 @@ void usrp_e_impl::rx_ddc_get(const wax::obj &key_, wax::obj &val){ return; case DSP_PROP_CODEC_RATE: - val = MASTER_CLOCK_RATE; + val = _clock_ctrl->get_fpga_clock_rate(); return; case DSP_PROP_HOST_RATE: - val = MASTER_CLOCK_RATE/_ddc_decim; + val = _clock_ctrl->get_fpga_clock_rate()/_ddc_decim; return; default: UHD_THROW_PROP_GET_ERROR(); @@ -87,7 +87,7 @@ void usrp_e_impl::rx_ddc_set(const wax::obj &key_, const wax::obj &val){ case DSP_PROP_FREQ_SHIFT:{ double new_freq = val.as(); _iface->poke32(UE_REG_DSP_RX_FREQ, - dsp_type1::calc_cordic_word_and_update(new_freq, MASTER_CLOCK_RATE) + dsp_type1::calc_cordic_word_and_update(new_freq, _clock_ctrl->get_fpga_clock_rate()) ); _ddc_freq = new_freq; //shadow } @@ -95,7 +95,7 @@ void usrp_e_impl::rx_ddc_set(const wax::obj &key_, const wax::obj &val){ case DSP_PROP_HOST_RATE:{ //set the decimation - _ddc_decim = rint(MASTER_CLOCK_RATE/val.as()); + _ddc_decim = rint(_clock_ctrl->get_fpga_clock_rate()/val.as()); _iface->poke32(UE_REG_DSP_RX_DECIM_RATE, dsp_type1::calc_cic_filter_word(_ddc_decim)); //set the scaling @@ -148,11 +148,11 @@ void usrp_e_impl::tx_duc_get(const wax::obj &key_, wax::obj &val){ return; case DSP_PROP_CODEC_RATE: - val = MASTER_CLOCK_RATE; + val = _clock_ctrl->get_fpga_clock_rate(); return; case DSP_PROP_HOST_RATE: - val = MASTER_CLOCK_RATE/_duc_interp; + val = _clock_ctrl->get_fpga_clock_rate()/_duc_interp; return; default: UHD_THROW_PROP_GET_ERROR(); @@ -170,14 +170,14 @@ void usrp_e_impl::tx_duc_set(const wax::obj &key_, const wax::obj &val){ case DSP_PROP_FREQ_SHIFT:{ double new_freq = val.as(); _iface->poke32(UE_REG_DSP_TX_FREQ, - dsp_type1::calc_cordic_word_and_update(new_freq, MASTER_CLOCK_RATE) + dsp_type1::calc_cordic_word_and_update(new_freq, _clock_ctrl->get_fpga_clock_rate()) ); _duc_freq = new_freq; //shadow } return; case DSP_PROP_HOST_RATE:{ - _duc_interp = rint(MASTER_CLOCK_RATE/val.as()); + _duc_interp = rint(_clock_ctrl->get_fpga_clock_rate()/val.as()); //set the interpolation _iface->poke32(UE_REG_DSP_TX_INTERP_RATE, dsp_type1::calc_cic_filter_word(_duc_interp)); diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index d89a7db07..9996e7172 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -73,7 +73,7 @@ struct usrp_e_impl::io_impl{ } //a pirate's life is the life for me! - void recv_pirate_loop(); + void recv_pirate_loop(usrp_e_clock_ctrl::sptr); typedef bounded_buffer recv_booty_type; recv_booty_type::sptr recv_pirate_booty; bounded_buffer::sptr async_msg_fifo; @@ -86,9 +86,8 @@ struct usrp_e_impl::io_impl{ * - while raiding, loot for recv buffers * - put booty into the alignment buffer **********************************************************************/ -void usrp_e_impl::io_impl::recv_pirate_loop( - -){ +void usrp_e_impl::io_impl::recv_pirate_loop(usrp_e_clock_ctrl::sptr clock_ctrl) +{ set_thread_priority_safe(); recv_pirate_crew_raiding = true; @@ -119,7 +118,7 @@ void usrp_e_impl::io_impl::recv_pirate_loop( metadata.channel = 0; metadata.has_time_spec = if_packet_info.has_tsi and if_packet_info.has_tsf; metadata.time_spec = time_spec_t( - time_t(if_packet_info.tsi), size_t(if_packet_info.tsf), MASTER_CLOCK_RATE + time_t(if_packet_info.tsi), size_t(if_packet_info.tsf), clock_ctrl->get_fpga_clock_rate() ); metadata.event_code = vrt_packet_handler::get_context_code(vrt_hdr, if_packet_info); @@ -172,7 +171,7 @@ void usrp_e_impl::io_init(void){ //spawn a pirate, yarrr! _io_impl->recv_pirate_crew.create_thread(boost::bind( - &usrp_e_impl::io_impl::recv_pirate_loop, _io_impl.get() + &usrp_e_impl::io_impl::recv_pirate_loop, _io_impl.get(), _clock_ctrl )); } @@ -182,7 +181,7 @@ void usrp_e_impl::issue_stream_cmd(const stream_cmd_t &stream_cmd){ stream_cmd, get_max_recv_samps_per_packet() )); _iface->poke32(UE_REG_CTRL_RX_TIME_SECS, boost::uint32_t(stream_cmd.time_spec.get_full_secs())); - _iface->poke32(UE_REG_CTRL_RX_TIME_TICKS, stream_cmd.time_spec.get_tick_count(MASTER_CLOCK_RATE)); + _iface->poke32(UE_REG_CTRL_RX_TIME_TICKS, stream_cmd.time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate())); } void usrp_e_impl::handle_overrun(size_t){ @@ -226,7 +225,7 @@ size_t usrp_e_impl::send( buffs, num_samps, //buffer to fill metadata, send_mode, //samples metadata io_type, _send_otw_type, //input and output types to convert - MASTER_CLOCK_RATE, //master clock tick rate + _clock_ctrl->get_fpga_clock_rate(), //master clock tick rate uhd::transport::vrt::if_hdr_pack_le, boost::bind(&get_send_buffs, _io_impl->data_xport, timeout, _1), get_max_send_samps_per_packet() @@ -258,7 +257,7 @@ size_t usrp_e_impl::recv( buffs, num_samps, //buffer to fill metadata, recv_mode, //samples metadata io_type, _recv_otw_type, //input and output types to convert - MASTER_CLOCK_RATE, //master clock tick rate + _clock_ctrl->get_fpga_clock_rate(), //master clock tick rate uhd::transport::vrt::if_hdr_unpack_le, boost::bind(&usrp_e_impl::io_impl::get_recv_buffs, _io_impl.get(), _1, timeout), boost::bind(&usrp_e_impl::handle_overrun, this, _1) diff --git a/host/lib/usrp/usrp_e/mboard_impl.cpp b/host/lib/usrp/usrp_e/mboard_impl.cpp index 3d4cef069..f0118aa4b 100644 --- a/host/lib/usrp/usrp_e/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e/mboard_impl.cpp @@ -125,7 +125,7 @@ void usrp_e_impl::mboard_set(const wax::obj &key, const wax::obj &val){ case MBOARD_PROP_TIME_NOW: case MBOARD_PROP_TIME_NEXT_PPS:{ time_spec_t time_spec = val.as(); - _iface->poke32(UE_REG_TIME64_TICKS, time_spec.get_tick_count(MASTER_CLOCK_RATE)); + _iface->poke32(UE_REG_TIME64_TICKS, time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate())); boost::uint32_t imm_flags = (key.as() == MBOARD_PROP_TIME_NOW)? 1 : 0; _iface->poke32(UE_REG_TIME64_IMM, imm_flags); _iface->poke32(UE_REG_TIME64_SECS, time_spec.get_full_secs()); diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.cpp b/host/lib/usrp/usrp_e/usrp_e_impl.cpp index 0a7295ff9..1b71c0a52 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.cpp @@ -71,10 +71,6 @@ static device_addrs_t usrp_e_find(const device_addr_t &hint){ **********************************************************************/ static device::sptr usrp_e_make(const device_addr_t &device_addr){ - //The fpga is loaded when: - // 1) The compatibility number matches. - // 2) The hash in the hash-file matches. - //setup the main interface into fpga std::string node = device_addr["node"]; std::cout << boost::format("Opening USRP-E on %s") % node << std::endl; @@ -86,6 +82,7 @@ static device::sptr usrp_e_make(const device_addr_t &device_addr){ //-- 1) The compatibility number matches. //-- 2) The hash in the hash-file matches. //------------------------------------------------------------------ + static const char *hash_file_path = "/tmp/usrp_e100_hash"; //extract the fpga path for usrp-e std::string usrp_e_fpga_image = find_image_path( diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index 421a9623d..e55b46b80 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -30,8 +30,6 @@ #ifndef INCLUDED_USRP_E_IMPL_HPP #define INCLUDED_USRP_E_IMPL_HPP -static const double MASTER_CLOCK_RATE = 64e6; //TODO get from clock control -static const char *hash_file_path = "/tmp/usrp_e100_hash"; static const boost::uint16_t USRP_E_COMPAT_NUM = 0x02; //! load an fpga image from a bin file into the usrp-e fpga @@ -100,9 +98,6 @@ private: //interface to ioctls and file descriptor usrp_e_iface::sptr _iface; - //FIXME fetch from ioctl? - static const size_t _max_num_samples = 2048/sizeof(boost::uint32_t); - //handle io stuff UHD_PIMPL_DECL(io_impl) _io_impl; uhd::otw_type_t _send_otw_type, _recv_otw_type; -- cgit v1.2.3 From a8fcdba5f76d08212835c5966be67248428fe9fa Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 4 Nov 2010 17:43:30 -0400 Subject: usrp_e: Comment out fpga loading until we unload module during load. --- host/lib/usrp/usrp_e/usrp_e_impl.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.cpp b/host/lib/usrp/usrp_e/usrp_e_impl.cpp index 1b71c0a52..cd39dbb07 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.cpp @@ -111,7 +111,8 @@ static device::sptr usrp_e_make(const device_addr_t &device_addr){ //if not loaded: load the fpga image and write the hash-file if (fpga_compat_num != USRP_E_COMPAT_NUM or loaded_hash != fpga_hash){ - usrp_e_load_fpga(usrp_e_fpga_image); +// usrp_e_load_fpga(usrp_e_fpga_image); +std::cout << "Here is where I load the fpga" << std::endl; try{std::ofstream(hash_file_path) << fpga_hash;}catch(...){} } -- cgit v1.2.3 From bab641f4fdf954d6023904ca18c4bb4f6a362e47 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 4 Nov 2010 17:44:08 -0400 Subject: usrp_e : Fix register definitions for COMPAT and others. --- host/lib/usrp/usrp_e/usrp_e_regs.hpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/host/lib/usrp/usrp_e/usrp_e_regs.hpp b/host/lib/usrp/usrp_e/usrp_e_regs.hpp index f74358f00..8bfb08b6f 100644 --- a/host/lib/usrp/usrp_e/usrp_e_regs.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_regs.hpp @@ -30,7 +30,9 @@ #define UE_REG_MISC_CGEN_ST UE_REG_MISC_BASE + 6 #define UE_REG_MISC_TEST UE_REG_MISC_BASE + 8 #define UE_REG_MISC_RX_LEN UE_REG_MISC_BASE + 10 -#define UE_REG_MISC_COMPAT UE_REG_MISC_BASE + 12 +#define UE_REG_MISC_TX_LEN UE_REG_MISC_BASE + 12 +#define UE_REG_MISC_XFER_RATE UE_REG_MISC_BASE + 14 +#define UE_REG_MISC_COMPAT UE_REG_MISC_BASE + 16 ///////////////////////////////////////////////////// // Slave 1 -- UART -- cgit v1.2.3 From 7824f130bd1296c78f5b0311d1c253f0476c6cab Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Tue, 9 Nov 2010 18:13:25 -0800 Subject: usrp_e : Unload the module before loading the FPGA. Reload after the fpga is loaded. --- host/lib/usrp/usrp_e/fpga-downloader.cc | 6 ++++++ host/lib/usrp/usrp_e/usrp_e_impl.cpp | 6 ++++-- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/host/lib/usrp/usrp_e/fpga-downloader.cc b/host/lib/usrp/usrp_e/fpga-downloader.cc index b0d56e856..5fd2c8dd0 100644 --- a/host/lib/usrp/usrp_e/fpga-downloader.cc +++ b/host/lib/usrp/usrp_e/fpga-downloader.cc @@ -259,9 +259,15 @@ void usrp_e_load_fpga(const std::string &bin_file){ std::cout << "Loading FPGA image: " << bin_file << "... " << std::flush; + system("/sbin/rmmod usrp_e"); + prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b); std::cout << "done = " << gpio_done.get_value() << std::endl; send_file_to_fpga(bin_file, gpio_init_b, gpio_done); + + system("/sbin/modprobe usrp_e"); + } + diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.cpp b/host/lib/usrp/usrp_e/usrp_e_impl.cpp index cd39dbb07..70cc399fb 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.cpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.cpp @@ -111,8 +111,10 @@ static device::sptr usrp_e_make(const device_addr_t &device_addr){ //if not loaded: load the fpga image and write the hash-file if (fpga_compat_num != USRP_E_COMPAT_NUM or loaded_hash != fpga_hash){ -// usrp_e_load_fpga(usrp_e_fpga_image); -std::cout << "Here is where I load the fpga" << std::endl; + iface.reset(); + usrp_e_load_fpga(usrp_e_fpga_image); + std::cout << boost::format("re-Opening USRP-E on %s") % node << std::endl; + iface = usrp_e_iface::make(node); try{std::ofstream(hash_file_path) << fpga_hash;}catch(...){} } -- cgit v1.2.3 From 073518083f2c7044d4b0c16948a192c5623d0752 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 9 Nov 2010 18:38:27 -0800 Subject: usrp_e: use the transport to calculate the max spp (with a fix to init the xport first) --- host/lib/usrp/usrp_e/io_impl.cpp | 9 +++------ host/lib/usrp/usrp_e/usrp_e_impl.hpp | 5 ----- 2 files changed, 3 insertions(+), 11 deletions(-) diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp index 9996e7172..e863944e8 100644 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ b/host/lib/usrp/usrp_e/io_impl.cpp @@ -150,6 +150,9 @@ void usrp_e_impl::io_init(void){ _recv_otw_type.shift = 0; _recv_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN; + //setup before the registers (transport called to calculate max spp) + _io_impl = UHD_PIMPL_MAKE(io_impl, (_iface)); + //setup rx data path _iface->poke32(UE_REG_CTRL_RX_NSAMPS_PER_PKT, get_max_recv_samps_per_packet()); _iface->poke32(UE_REG_CTRL_RX_NCHANNELS, 1); @@ -167,8 +170,6 @@ void usrp_e_impl::io_init(void){ _iface->poke32(UE_REG_CTRL_TX_REPORT_SID, tx_async_report_sid); _iface->poke32(UE_REG_CTRL_TX_POLICY, UE_FLAG_CTRL_TX_POLICY_NEXT_PACKET); - _io_impl = UHD_PIMPL_MAKE(io_impl, (_iface)); - //spawn a pirate, yarrr! _io_impl->recv_pirate_crew.create_thread(boost::bind( &usrp_e_impl::io_impl::recv_pirate_loop, _io_impl.get(), _clock_ctrl @@ -204,7 +205,6 @@ bool get_send_buffs( return buffs[0].get() != NULL; } -#if 0 size_t usrp_e_impl::get_max_send_samps_per_packet(void) const{ static const size_t hdr_size = 0 + vrt::max_if_hdr_words32*sizeof(boost::uint32_t) @@ -213,7 +213,6 @@ size_t usrp_e_impl::get_max_send_samps_per_packet(void) const{ size_t bpp = _io_impl->data_xport->get_send_frame_size() - hdr_size; return bpp/_send_otw_type.get_sample_size(); } -#endif size_t usrp_e_impl::send( const std::vector &buffs, size_t num_samps, @@ -235,7 +234,6 @@ size_t usrp_e_impl::send( /*********************************************************************** * Data Recv **********************************************************************/ -#if 0 size_t usrp_e_impl::get_max_recv_samps_per_packet(void) const{ static const size_t hdr_size = 0 + vrt::max_if_hdr_words32*sizeof(boost::uint32_t) @@ -245,7 +243,6 @@ size_t usrp_e_impl::get_max_recv_samps_per_packet(void) const{ size_t bpp = _io_impl->data_xport->get_recv_frame_size() - hdr_size; return bpp/_recv_otw_type.get_sample_size(); } -#endif size_t usrp_e_impl::recv( const std::vector &buffs, size_t num_samps, diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp index e55b46b80..b5f21810d 100644 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ b/host/lib/usrp/usrp_e/usrp_e_impl.hpp @@ -86,13 +86,8 @@ public: size_t send(const std::vector &, size_t, const uhd::tx_metadata_t &, const uhd::io_type_t &, send_mode_t, double); size_t recv(const std::vector &, size_t, uhd::rx_metadata_t &, const uhd::io_type_t &, recv_mode_t, double); bool recv_async_msg(uhd::async_metadata_t &, double); -#if 0 size_t get_max_send_samps_per_packet(void) const; size_t get_max_recv_samps_per_packet(void) const; -#else - size_t get_max_send_samps_per_packet(void) const{return 503;} - size_t get_max_recv_samps_per_packet(void) const{return 503;} -#endif private: //interface to ioctls and file descriptor -- cgit v1.2.3 From 61d9cda7f64e10d8039bf7b6de5ca8068f11e5bb Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 9 Nov 2010 18:44:39 -0800 Subject: usrp-e: check the return code on system call, also removes warnings --- host/lib/usrp/usrp_e/fpga-downloader.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/host/lib/usrp/usrp_e/fpga-downloader.cc b/host/lib/usrp/usrp_e/fpga-downloader.cc index 5fd2c8dd0..4dc537919 100644 --- a/host/lib/usrp/usrp_e/fpga-downloader.cc +++ b/host/lib/usrp/usrp_e/fpga-downloader.cc @@ -16,6 +16,7 @@ // #include +#include #include #include @@ -259,7 +260,7 @@ void usrp_e_load_fpga(const std::string &bin_file){ std::cout << "Loading FPGA image: " << bin_file << "... " << std::flush; - system("/sbin/rmmod usrp_e"); + UHD_ASSERT_THROW(std::system("/sbin/rmmod usrp_e") == 0); prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b); @@ -267,7 +268,7 @@ void usrp_e_load_fpga(const std::string &bin_file){ send_file_to_fpga(bin_file, gpio_init_b, gpio_done); - system("/sbin/modprobe usrp_e"); + UHD_ASSERT_THROW(std::system("/sbin/modprobe usrp_e") == 0); } -- cgit v1.2.3 From d33a6cab6646692e06ef34317f6c831ac9c91148 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 9 Nov 2010 18:48:54 -0800 Subject: usrp_e: renamed directory to usrp_e100 to reflect product name --- host/lib/usrp/CMakeLists.txt | 2 +- host/lib/usrp/usrp_e/CMakeLists.txt | 64 ----- host/lib/usrp/usrp_e/clock_ctrl.cpp | 237 ----------------- host/lib/usrp/usrp_e/clock_ctrl.hpp | 88 ------- host/lib/usrp/usrp_e/codec_ctrl.cpp | 296 --------------------- host/lib/usrp/usrp_e/codec_ctrl.hpp | 90 ------- host/lib/usrp/usrp_e/codec_impl.cpp | 149 ----------- host/lib/usrp/usrp_e/dboard_iface.cpp | 298 ---------------------- host/lib/usrp/usrp_e/dboard_impl.cpp | 172 ------------- host/lib/usrp/usrp_e/dsp_impl.cpp | 192 -------------- host/lib/usrp/usrp_e/fpga-downloader.cc | 274 -------------------- host/lib/usrp/usrp_e/io_impl.cpp | 272 -------------------- host/lib/usrp/usrp_e/mboard_impl.cpp | 159 ------------ host/lib/usrp/usrp_e/usrp_e_iface.cpp | 194 -------------- host/lib/usrp/usrp_e/usrp_e_iface.hpp | 112 -------- host/lib/usrp/usrp_e/usrp_e_impl.cpp | 201 --------------- host/lib/usrp/usrp_e/usrp_e_impl.hpp | 164 ------------ host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp | 215 ---------------- host/lib/usrp/usrp_e/usrp_e_regs.hpp | 198 -------------- host/lib/usrp/usrp_e100/CMakeLists.txt | 64 +++++ host/lib/usrp/usrp_e100/clock_ctrl.cpp | 237 +++++++++++++++++ host/lib/usrp/usrp_e100/clock_ctrl.hpp | 88 +++++++ host/lib/usrp/usrp_e100/codec_ctrl.cpp | 296 +++++++++++++++++++++ host/lib/usrp/usrp_e100/codec_ctrl.hpp | 90 +++++++ host/lib/usrp/usrp_e100/codec_impl.cpp | 149 +++++++++++ host/lib/usrp/usrp_e100/dboard_iface.cpp | 298 ++++++++++++++++++++++ host/lib/usrp/usrp_e100/dboard_impl.cpp | 172 +++++++++++++ host/lib/usrp/usrp_e100/dsp_impl.cpp | 192 ++++++++++++++ host/lib/usrp/usrp_e100/fpga-downloader.cc | 274 ++++++++++++++++++++ host/lib/usrp/usrp_e100/io_impl.cpp | 272 ++++++++++++++++++++ host/lib/usrp/usrp_e100/mboard_impl.cpp | 159 ++++++++++++ host/lib/usrp/usrp_e100/usrp_e_iface.cpp | 194 ++++++++++++++ host/lib/usrp/usrp_e100/usrp_e_iface.hpp | 112 ++++++++ host/lib/usrp/usrp_e100/usrp_e_impl.cpp | 201 +++++++++++++++ host/lib/usrp/usrp_e100/usrp_e_impl.hpp | 164 ++++++++++++ host/lib/usrp/usrp_e100/usrp_e_mmap_zero_copy.cpp | 215 ++++++++++++++++ host/lib/usrp/usrp_e100/usrp_e_regs.hpp | 198 ++++++++++++++ 37 files changed, 3376 insertions(+), 3376 deletions(-) delete mode 100644 host/lib/usrp/usrp_e/CMakeLists.txt delete mode 100644 host/lib/usrp/usrp_e/clock_ctrl.cpp delete mode 100644 host/lib/usrp/usrp_e/clock_ctrl.hpp delete mode 100644 host/lib/usrp/usrp_e/codec_ctrl.cpp delete mode 100644 host/lib/usrp/usrp_e/codec_ctrl.hpp delete mode 100644 host/lib/usrp/usrp_e/codec_impl.cpp delete mode 100644 host/lib/usrp/usrp_e/dboard_iface.cpp delete mode 100644 host/lib/usrp/usrp_e/dboard_impl.cpp delete mode 100644 host/lib/usrp/usrp_e/dsp_impl.cpp delete mode 100644 host/lib/usrp/usrp_e/fpga-downloader.cc delete mode 100644 host/lib/usrp/usrp_e/io_impl.cpp delete mode 100644 host/lib/usrp/usrp_e/mboard_impl.cpp delete mode 100644 host/lib/usrp/usrp_e/usrp_e_iface.cpp delete mode 100644 host/lib/usrp/usrp_e/usrp_e_iface.hpp delete mode 100644 host/lib/usrp/usrp_e/usrp_e_impl.cpp delete mode 100644 host/lib/usrp/usrp_e/usrp_e_impl.hpp delete mode 100644 host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp delete mode 100644 host/lib/usrp/usrp_e/usrp_e_regs.hpp create mode 100644 host/lib/usrp/usrp_e100/CMakeLists.txt create mode 100644 host/lib/usrp/usrp_e100/clock_ctrl.cpp create mode 100644 host/lib/usrp/usrp_e100/clock_ctrl.hpp create mode 100644 host/lib/usrp/usrp_e100/codec_ctrl.cpp create mode 100644 host/lib/usrp/usrp_e100/codec_ctrl.hpp create mode 100644 host/lib/usrp/usrp_e100/codec_impl.cpp create mode 100644 host/lib/usrp/usrp_e100/dboard_iface.cpp create mode 100644 host/lib/usrp/usrp_e100/dboard_impl.cpp create mode 100644 host/lib/usrp/usrp_e100/dsp_impl.cpp create mode 100644 host/lib/usrp/usrp_e100/fpga-downloader.cc create mode 100644 host/lib/usrp/usrp_e100/io_impl.cpp create mode 100644 host/lib/usrp/usrp_e100/mboard_impl.cpp create mode 100644 host/lib/usrp/usrp_e100/usrp_e_iface.cpp create mode 100644 host/lib/usrp/usrp_e100/usrp_e_iface.hpp create mode 100644 host/lib/usrp/usrp_e100/usrp_e_impl.cpp create mode 100644 host/lib/usrp/usrp_e100/usrp_e_impl.hpp create mode 100644 host/lib/usrp/usrp_e100/usrp_e_mmap_zero_copy.cpp create mode 100644 host/lib/usrp/usrp_e100/usrp_e_regs.hpp diff --git a/host/lib/usrp/CMakeLists.txt b/host/lib/usrp/CMakeLists.txt index bb7e83214..073b3c80b 100644 --- a/host/lib/usrp/CMakeLists.txt +++ b/host/lib/usrp/CMakeLists.txt @@ -35,4 +35,4 @@ LIBUHD_APPEND_SOURCES( INCLUDE(${CMAKE_SOURCE_DIR}/lib/usrp/dboard/CMakeLists.txt) INCLUDE(${CMAKE_SOURCE_DIR}/lib/usrp/usrp1/CMakeLists.txt) INCLUDE(${CMAKE_SOURCE_DIR}/lib/usrp/usrp2/CMakeLists.txt) -INCLUDE(${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/CMakeLists.txt) +INCLUDE(${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/CMakeLists.txt) diff --git a/host/lib/usrp/usrp_e/CMakeLists.txt b/host/lib/usrp/usrp_e/CMakeLists.txt deleted file mode 100644 index 6c5d281dd..000000000 --- a/host/lib/usrp/usrp_e/CMakeLists.txt +++ /dev/null @@ -1,64 +0,0 @@ -# -# Copyright 2010 Ettus Research LLC -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# - -#This file will be included by cmake, use absolute paths! - -######################################################################## -# Conditionally configure the USRP-E support -######################################################################## -MESSAGE(STATUS "Configuring usrp-e support...") - -INCLUDE(CheckIncludeFileCXX) -CHECK_INCLUDE_FILE_CXX(linux/usrp_e.h HAVE_LINUX_USRP_E_H) - -SET(ENABLE_USRP_E TRUE) - -IF(DEFINED ENABLE_USRP_E) - IF(ENABLE_USRP_E) - MESSAGE(STATUS "USRP-E support enabled by configure flag") - ELSE(ENABLE_USRP_E) - MESSAGE(STATUS "USRP-E support disabled by configure flag") - ENDIF(ENABLE_USRP_E) -ELSE(DEFINED ENABLE_USRP_E) #not defined: automatic enabling of component - SET(ENABLE_USRP_E ${HAVE_LINUX_USRP_E_H}) -ENDIF(DEFINED ENABLE_USRP_E) -SET(ENABLE_USRP_E ${ENABLE_USRP_E} CACHE BOOL "enable USRP-E support") - -IF(ENABLE_USRP_E) - MESSAGE(STATUS " Building usrp-e support.") - LIBUHD_APPEND_SOURCES( - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/clock_ctrl.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/clock_ctrl.hpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/codec_ctrl.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/codec_ctrl.hpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/codec_impl.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/dboard_impl.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/dboard_iface.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/dsp_impl.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/fpga-downloader.cc - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/io_impl.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/mboard_impl.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_impl.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_impl.hpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_iface.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_iface.hpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e/usrp_e_regs.hpp - ) -ELSE(ENABLE_USRP_E) - MESSAGE(STATUS " Skipping usrp-e support.") -ENDIF(ENABLE_USRP_E) diff --git a/host/lib/usrp/usrp_e/clock_ctrl.cpp b/host/lib/usrp/usrp_e/clock_ctrl.cpp deleted file mode 100644 index 9d4625305..000000000 --- a/host/lib/usrp/usrp_e/clock_ctrl.cpp +++ /dev/null @@ -1,237 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "clock_ctrl.hpp" -#include "ad9522_regs.hpp" -#include -#include -#include "usrp_e_regs.hpp" //spi slave constants -#include -#include -#include -#include - -using namespace uhd; - -template static void set_clock_divider( - size_t divider, div_type &low, div_type &high, bypass_type &bypass -){ - high = divider/2 - 1; - low = divider - high - 2; - bypass = (divider == 1)? 1 : 0; -} - -/*********************************************************************** - * Constants - **********************************************************************/ -static const bool enable_test_clock = false; -static const size_t ref_clock_doubler = 2; //enabled below -static const double ref_clock_rate = 10e6 * ref_clock_doubler; - -static const size_t r_counter = 1; -static const size_t a_counter = 0; -static const size_t b_counter = 20 / ref_clock_doubler; -static const size_t prescaler = 8; //set below with enum, set to 8 when input is under 2400 MHz -static const size_t vco_divider = 5; //set below with enum - -static const size_t n_counter = prescaler * b_counter + a_counter; -static const size_t vco_clock_rate = ref_clock_rate/r_counter * n_counter; //between 1400 and 1800 MHz -static const double master_clock_rate = vco_clock_rate/vco_divider; - -static const size_t fpga_clock_divider = size_t(master_clock_rate/64e6); -static const size_t codec_clock_divider = size_t(master_clock_rate/64e6); - -/*********************************************************************** - * Clock Control Implementation - **********************************************************************/ -class usrp_e_clock_ctrl_impl : public usrp_e_clock_ctrl{ -public: - usrp_e_clock_ctrl_impl(usrp_e_iface::sptr iface){ - _iface = iface; - - //init the clock gen registers - //Note: out0 should already be clocking the FPGA or this isnt going to work - _ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO; - _ad9522_regs.enable_clock_doubler = 1; //enable ref clock doubler - _ad9522_regs.enb_stat_eeprom_at_stat_pin = 0; //use status pin - _ad9522_regs.status_pin_control = 0x1; //n divider - _ad9522_regs.ld_pin_control = 0x00; //dld - _ad9522_regs.refmon_pin_control = 0x12; //show ref2 - - _ad9522_regs.enable_ref2 = 1; - _ad9522_regs.enable_ref1 = 0; - _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF2; - - _ad9522_regs.set_r_counter(r_counter); - _ad9522_regs.a_counter = a_counter; - _ad9522_regs.set_b_counter(b_counter); - _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV8_9; - - _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL; - _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA; - - _ad9522_regs.vco_calibration_now = 1; //calibrate it! - _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5; - _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_VCO; - - //setup fpga master clock - _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; - set_clock_divider(fpga_clock_divider, - _ad9522_regs.divider0_low_cycles, - _ad9522_regs.divider0_high_cycles, - _ad9522_regs.divider0_bypass - ); - - //setup codec clock - _ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS; - set_clock_divider(codec_clock_divider, - _ad9522_regs.divider1_low_cycles, - _ad9522_regs.divider1_high_cycles, - _ad9522_regs.divider1_bypass - ); - - //setup test clock (same divider as codec clock) - _ad9522_regs.out4_format = ad9522_regs_t::OUT4_FORMAT_CMOS; - _ad9522_regs.out4_cmos_configuration = (enable_test_clock)? - ad9522_regs_t::OUT4_CMOS_CONFIGURATION_A_ON : - ad9522_regs_t::OUT4_CMOS_CONFIGURATION_OFF; - - //setup a list of register ranges to write - typedef std::pair range_t; - static const std::vector ranges = boost::assign::list_of - (range_t(0x000, 0x000)) (range_t(0x010, 0x01F)) - (range_t(0x0F0, 0x0FD)) (range_t(0x190, 0x19B)) - (range_t(0x1E0, 0x1E1)) (range_t(0x230, 0x230)) - ; - - //write initial register values and latch/update - BOOST_FOREACH(const range_t &range, ranges){ - for(boost::uint16_t addr = range.first; addr <= range.second; addr++){ - this->send_reg(addr); - } - } - this->latch_regs(); - //test read: - //boost::uint32_t reg = _ad9522_regs.get_read_reg(0x01b); - //boost::uint32_t result = _iface->transact_spi( - // UE_SPI_SS_AD9522, - // spi_config_t::EDGE_RISE, - // reg, 24, true /*no*/ - //); - //std::cout << "result " << std::hex << result << std::endl; - this->enable_rx_dboard_clock(false); - this->enable_tx_dboard_clock(false); - } - - ~usrp_e_clock_ctrl_impl(void){ - this->enable_rx_dboard_clock(false); - this->enable_tx_dboard_clock(false); - } - - double get_fpga_clock_rate(void){ - return master_clock_rate/fpga_clock_divider; - } - - /*********************************************************************** - * RX Dboard Clock Control (output 9, divider 3) - **********************************************************************/ - void enable_rx_dboard_clock(bool enb){ - _ad9522_regs.out9_format = ad9522_regs_t::OUT9_FORMAT_CMOS; - _ad9522_regs.out9_cmos_configuration = (enb)? - ad9522_regs_t::OUT9_CMOS_CONFIGURATION_B_ON : - ad9522_regs_t::OUT9_CMOS_CONFIGURATION_OFF; - this->send_reg(0x0F9); - this->latch_regs(); - } - - std::vector get_rx_dboard_clock_rates(void){ - std::vector rates; - for(size_t div = 1; div <= 16+16; div++) - rates.push_back(master_clock_rate/div); - return rates; - } - - void set_rx_dboard_clock_rate(double rate){ - assert_has(get_rx_dboard_clock_rates(), rate, "rx dboard clock rate"); - size_t divider = size_t(master_clock_rate/rate); - //set the divider registers - set_clock_divider(divider, - _ad9522_regs.divider3_low_cycles, - _ad9522_regs.divider3_high_cycles, - _ad9522_regs.divider3_bypass - ); - this->send_reg(0x199); - this->send_reg(0x19a); - this->latch_regs(); - } - - /*********************************************************************** - * TX Dboard Clock Control (output 6, divider 2) - **********************************************************************/ - void enable_tx_dboard_clock(bool enb){ - _ad9522_regs.out6_format = ad9522_regs_t::OUT6_FORMAT_CMOS; - _ad9522_regs.out6_cmos_configuration = (enb)? - ad9522_regs_t::OUT6_CMOS_CONFIGURATION_B_ON : - ad9522_regs_t::OUT6_CMOS_CONFIGURATION_OFF; - this->send_reg(0x0F6); - this->latch_regs(); - } - - std::vector get_tx_dboard_clock_rates(void){ - return get_rx_dboard_clock_rates(); //same master clock, same dividers... - } - - void set_tx_dboard_clock_rate(double rate){ - assert_has(get_tx_dboard_clock_rates(), rate, "tx dboard clock rate"); - size_t divider = size_t(master_clock_rate/rate); - //set the divider registers - set_clock_divider(divider, - _ad9522_regs.divider2_low_cycles, - _ad9522_regs.divider2_high_cycles, - _ad9522_regs.divider2_bypass - ); - this->send_reg(0x196); - this->send_reg(0x197); - this->latch_regs(); - } - -private: - usrp_e_iface::sptr _iface; - ad9522_regs_t _ad9522_regs; - - void latch_regs(void){ - _ad9522_regs.io_update = 1; - this->send_reg(0x232); - } - - void send_reg(boost::uint16_t addr){ - boost::uint32_t reg = _ad9522_regs.get_write_reg(addr); - //std::cout << "clock control write reg: " << std::hex << reg << std::endl; - _iface->transact_spi( - UE_SPI_SS_AD9522, - spi_config_t::EDGE_RISE, - reg, 24, false /*no rb*/ - ); - } -}; - -/*********************************************************************** - * Clock Control Make - **********************************************************************/ -usrp_e_clock_ctrl::sptr usrp_e_clock_ctrl::make(usrp_e_iface::sptr iface){ - return sptr(new usrp_e_clock_ctrl_impl(iface)); -} diff --git a/host/lib/usrp/usrp_e/clock_ctrl.hpp b/host/lib/usrp/usrp_e/clock_ctrl.hpp deleted file mode 100644 index 3b5103ed1..000000000 --- a/host/lib/usrp/usrp_e/clock_ctrl.hpp +++ /dev/null @@ -1,88 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#ifndef INCLUDED_USRP_E_CLOCK_CTRL_HPP -#define INCLUDED_USRP_E_CLOCK_CTRL_HPP - -#include "usrp_e_iface.hpp" -#include -#include -#include - -/*! - * The usrp-e clock control: - * - Setup system clocks. - * - Disable/enable clock lines. - */ -class usrp_e_clock_ctrl : boost::noncopyable{ -public: - typedef boost::shared_ptr sptr; - - /*! - * Make a new clock control object. - * \param iface the usrp_e iface object - * \return the clock control object - */ - static sptr make(usrp_e_iface::sptr iface); - - /*! - * Get the rate of the fpga clock line. - * \return the fpga clock rate in Hz - */ - virtual double get_fpga_clock_rate(void) = 0; - - /*! - * Get the possible rates of the rx dboard clock. - * \return a vector of clock rates in Hz - */ - virtual std::vector get_rx_dboard_clock_rates(void) = 0; - - /*! - * Get the possible rates of the tx dboard clock. - * \return a vector of clock rates in Hz - */ - virtual std::vector get_tx_dboard_clock_rates(void) = 0; - - /*! - * Set the rx dboard clock rate to a possible rate. - * \param rate the new clock rate in Hz - * \throw exception when rate cannot be achieved - */ - virtual void set_rx_dboard_clock_rate(double rate) = 0; - - /*! - * Set the tx dboard clock rate to a possible rate. - * \param rate the new clock rate in Hz - * \throw exception when rate cannot be achieved - */ - virtual void set_tx_dboard_clock_rate(double rate) = 0; - - /*! - * Enable/disable the rx dboard clock. - * \param enb true to enable - */ - virtual void enable_rx_dboard_clock(bool enb) = 0; - - /*! - * Enable/disable the tx dboard clock. - * \param enb true to enable - */ - virtual void enable_tx_dboard_clock(bool enb) = 0; - -}; - -#endif /* INCLUDED_USRP_E_CLOCK_CTRL_HPP */ diff --git a/host/lib/usrp/usrp_e/codec_ctrl.cpp b/host/lib/usrp/usrp_e/codec_ctrl.cpp deleted file mode 100644 index a728d7e46..000000000 --- a/host/lib/usrp/usrp_e/codec_ctrl.cpp +++ /dev/null @@ -1,296 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "codec_ctrl.hpp" -#include "ad9862_regs.hpp" -#include -#include -#include -#include -#include -#include -#include "usrp_e_regs.hpp" //spi slave constants -#include -#include - -using namespace uhd; - -static const bool codec_debug = false; - -const gain_range_t usrp_e_codec_ctrl::tx_pga_gain_range(-20, 0, float(0.1)); -const gain_range_t usrp_e_codec_ctrl::rx_pga_gain_range(0, 20, 1); - -/*********************************************************************** - * Codec Control Implementation - **********************************************************************/ -class usrp_e_codec_ctrl_impl : public usrp_e_codec_ctrl{ -public: - //structors - usrp_e_codec_ctrl_impl(usrp_e_iface::sptr iface); - ~usrp_e_codec_ctrl_impl(void); - - //aux adc and dac control - float read_aux_adc(aux_adc_t which); - void write_aux_dac(aux_dac_t which, float volts); - - //pga gain control - void set_tx_pga_gain(float); - float get_tx_pga_gain(void); - void set_rx_pga_gain(float, char); - float get_rx_pga_gain(char); - -private: - usrp_e_iface::sptr _iface; - ad9862_regs_t _ad9862_regs; - aux_adc_t _last_aux_adc_a, _last_aux_adc_b; - void send_reg(boost::uint8_t addr); - void recv_reg(boost::uint8_t addr); -}; - -/*********************************************************************** - * Codec Control Structors - **********************************************************************/ -usrp_e_codec_ctrl_impl::usrp_e_codec_ctrl_impl(usrp_e_iface::sptr iface){ - _iface = iface; - - //soft reset - _ad9862_regs.soft_reset = 1; - this->send_reg(0); - - //initialize the codec register settings - _ad9862_regs.sdio_bidir = ad9862_regs_t::SDIO_BIDIR_SDIO_SDO; - _ad9862_regs.lsb_first = ad9862_regs_t::LSB_FIRST_MSB; - _ad9862_regs.soft_reset = 0; - - //setup rx side of codec - _ad9862_regs.byp_buffer_a = 1; - _ad9862_regs.byp_buffer_b = 1; - _ad9862_regs.buffer_a_pd = 1; - _ad9862_regs.buffer_b_pd = 1; - _ad9862_regs.rx_pga_a = 0;//0x1f; //TODO bring under api control - _ad9862_regs.rx_pga_b = 0;//0x1f; //TODO bring under api control - _ad9862_regs.rx_twos_comp = 1; - _ad9862_regs.rx_hilbert = ad9862_regs_t::RX_HILBERT_DIS; - - //setup tx side of codec - _ad9862_regs.two_data_paths = ad9862_regs_t::TWO_DATA_PATHS_BOTH; - _ad9862_regs.interleaved = ad9862_regs_t::INTERLEAVED_INTERLEAVED; - _ad9862_regs.tx_retime = ad9862_regs_t::TX_RETIME_CLKOUT2; - _ad9862_regs.tx_pga_gain = 199; //TODO bring under api control - _ad9862_regs.tx_hilbert = ad9862_regs_t::TX_HILBERT_DIS; - _ad9862_regs.interp = ad9862_regs_t::INTERP_2; - _ad9862_regs.tx_twos_comp = 1; - _ad9862_regs.fine_mode = ad9862_regs_t::FINE_MODE_BYPASS; - _ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_BYPASS; - _ad9862_regs.dac_a_coarse_gain = 0x3; - _ad9862_regs.dac_b_coarse_gain = 0x3; - _ad9862_regs.edges = ad9862_regs_t::EDGES_NORMAL; - - //setup the dll - _ad9862_regs.input_clk_ctrl = ad9862_regs_t::INPUT_CLK_CTRL_EXTERNAL; - _ad9862_regs.dll_mult = ad9862_regs_t::DLL_MULT_2; - _ad9862_regs.dll_mode = ad9862_regs_t::DLL_MODE_FAST; - - //write the register settings to the codec - for (uint8_t addr = 0; addr <= 25; addr++){ - this->send_reg(addr); - } - - //aux adc clock - _ad9862_regs.clk_4 = ad9862_regs_t::CLK_4_1_4; - this->send_reg(34); -} - -usrp_e_codec_ctrl_impl::~usrp_e_codec_ctrl_impl(void){ - //set aux dacs to zero - this->write_aux_dac(AUX_DAC_A, 0); - this->write_aux_dac(AUX_DAC_B, 0); - this->write_aux_dac(AUX_DAC_C, 0); - this->write_aux_dac(AUX_DAC_D, 0); - - //power down - _ad9862_regs.all_rx_pd = 1; - this->send_reg(1); - _ad9862_regs.tx_digital_pd = 1; - _ad9862_regs.tx_analog_pd = ad9862_regs_t::TX_ANALOG_PD_BOTH; - this->send_reg(8); -} - -/*********************************************************************** - * Codec Control Gain Control Methods - **********************************************************************/ -static const int mtpgw = 255; //maximum tx pga gain word - -void usrp_e_codec_ctrl_impl::set_tx_pga_gain(float gain){ - int gain_word = int(mtpgw*(gain - tx_pga_gain_range.min)/(tx_pga_gain_range.max - tx_pga_gain_range.min)); - _ad9862_regs.tx_pga_gain = std::clip(gain_word, 0, mtpgw); - this->send_reg(16); -} - -float usrp_e_codec_ctrl_impl::get_tx_pga_gain(void){ - return (_ad9862_regs.tx_pga_gain*(tx_pga_gain_range.max - tx_pga_gain_range.min)/mtpgw) + tx_pga_gain_range.min; -} - -static const int mrpgw = 0x14; //maximum rx pga gain word - -void usrp_e_codec_ctrl_impl::set_rx_pga_gain(float gain, char which){ - int gain_word = int(mrpgw*(gain - rx_pga_gain_range.min)/(rx_pga_gain_range.max - rx_pga_gain_range.min)); - gain_word = std::clip(gain_word, 0, mrpgw); - switch(which){ - case 'A': - _ad9862_regs.rx_pga_a = gain_word; - this->send_reg(2); - return; - case 'B': - _ad9862_regs.rx_pga_b = gain_word; - this->send_reg(3); - return; - default: UHD_THROW_INVALID_CODE_PATH(); - } -} - -float usrp_e_codec_ctrl_impl::get_rx_pga_gain(char which){ - int gain_word; - switch(which){ - case 'A': gain_word = _ad9862_regs.rx_pga_a; break; - case 'B': gain_word = _ad9862_regs.rx_pga_b; break; - default: UHD_THROW_INVALID_CODE_PATH(); - } - return (gain_word*(rx_pga_gain_range.max - rx_pga_gain_range.min)/mrpgw) + rx_pga_gain_range.min; -} - -/*********************************************************************** - * Codec Control AUX ADC Methods - **********************************************************************/ -static float aux_adc_to_volts(boost::uint8_t high, boost::uint8_t low){ - return float((boost::uint16_t(high) << 2) | low)*3.3/0x3ff; -} - -float usrp_e_codec_ctrl_impl::read_aux_adc(aux_adc_t which){ - //check to see if the switch needs to be set - bool write_switch = false; - switch(which){ - - case AUX_ADC_A1: - case AUX_ADC_A2: - if (which != _last_aux_adc_a){ - _ad9862_regs.select_a = (which == AUX_ADC_A1)? - ad9862_regs_t::SELECT_A_AUX_ADC1: ad9862_regs_t::SELECT_A_AUX_ADC2; - _last_aux_adc_a = which; - write_switch = true; - } - break; - - case AUX_ADC_B1: - case AUX_ADC_B2: - if (which != _last_aux_adc_b){ - _ad9862_regs.select_b = (which == AUX_ADC_B1)? - ad9862_regs_t::SELECT_B_AUX_ADC1: ad9862_regs_t::SELECT_B_AUX_ADC2; - _last_aux_adc_b = which; - write_switch = true; - } - break; - - } - - //write the switch if it changed - if(write_switch) this->send_reg(34); - - //map aux adcs to register values to read - static const uhd::dict aux_dac_to_addr = boost::assign::map_list_of - (AUX_ADC_A2, 26) (AUX_ADC_A1, 28) - (AUX_ADC_B2, 30) (AUX_ADC_B1, 32) - ; - - //read the value - this->recv_reg(aux_dac_to_addr[which]+0); - this->recv_reg(aux_dac_to_addr[which]+1); - - //return the value scaled to volts - switch(which){ - case AUX_ADC_A1: return aux_adc_to_volts(_ad9862_regs.aux_adc_a1_9_2, _ad9862_regs.aux_adc_a1_1_0); - case AUX_ADC_A2: return aux_adc_to_volts(_ad9862_regs.aux_adc_a2_9_2, _ad9862_regs.aux_adc_a2_1_0); - case AUX_ADC_B1: return aux_adc_to_volts(_ad9862_regs.aux_adc_b1_9_2, _ad9862_regs.aux_adc_b1_1_0); - case AUX_ADC_B2: return aux_adc_to_volts(_ad9862_regs.aux_adc_b2_9_2, _ad9862_regs.aux_adc_b2_1_0); - } - UHD_ASSERT_THROW(false); -} - -/*********************************************************************** - * Codec Control AUX DAC Methods - **********************************************************************/ -void usrp_e_codec_ctrl_impl::write_aux_dac(aux_dac_t which, float volts){ - //special case for aux dac d (aka sigma delta word) - if (which == AUX_DAC_D){ - boost::uint16_t dac_word = std::clip(boost::math::iround(volts*0xfff/3.3), 0, 0xfff); - _ad9862_regs.sig_delt_11_4 = boost::uint8_t(dac_word >> 4); - _ad9862_regs.sig_delt_3_0 = boost::uint8_t(dac_word & 0xf); - this->send_reg(42); - this->send_reg(43); - return; - } - - //calculate the dac word for aux dac a, b, c - boost::uint8_t dac_word = std::clip(boost::math::iround(volts*0xff/3.3), 0, 0xff); - - //setup a lookup table for the aux dac params (reg ref, reg addr) - typedef boost::tuple dac_params_t; - uhd::dict aux_dac_to_params = boost::assign::map_list_of - (AUX_DAC_A, dac_params_t(&_ad9862_regs.aux_dac_a, 36)) - (AUX_DAC_B, dac_params_t(&_ad9862_regs.aux_dac_b, 37)) - (AUX_DAC_C, dac_params_t(&_ad9862_regs.aux_dac_c, 38)) - ; - - //set the aux dac register - UHD_ASSERT_THROW(aux_dac_to_params.has_key(which)); - boost::uint8_t *reg_ref, reg_addr; - boost::tie(reg_ref, reg_addr) = aux_dac_to_params[which]; - *reg_ref = dac_word; - this->send_reg(reg_addr); -} - -/*********************************************************************** - * Codec Control SPI Methods - **********************************************************************/ -void usrp_e_codec_ctrl_impl::send_reg(boost::uint8_t addr){ - boost::uint32_t reg = _ad9862_regs.get_write_reg(addr); - if (codec_debug) std::cout << "codec control write reg: " << std::hex << reg << std::endl; - _iface->transact_spi( - UE_SPI_SS_AD9862, - spi_config_t::EDGE_RISE, - reg, 16, false /*no rb*/ - ); -} - -void usrp_e_codec_ctrl_impl::recv_reg(boost::uint8_t addr){ - boost::uint32_t reg = _ad9862_regs.get_read_reg(addr); - if (codec_debug) std::cout << "codec control read reg: " << std::hex << reg << std::endl; - boost::uint32_t ret = _iface->transact_spi( - UE_SPI_SS_AD9862, - spi_config_t::EDGE_RISE, - reg, 16, true /*rb*/ - ); - if (codec_debug) std::cout << "codec control read ret: " << std::hex << ret << std::endl; - _ad9862_regs.set_reg(addr, boost::uint16_t(ret)); -} - -/*********************************************************************** - * Codec Control Make - **********************************************************************/ -usrp_e_codec_ctrl::sptr usrp_e_codec_ctrl::make(usrp_e_iface::sptr iface){ - return sptr(new usrp_e_codec_ctrl_impl(iface)); -} diff --git a/host/lib/usrp/usrp_e/codec_ctrl.hpp b/host/lib/usrp/usrp_e/codec_ctrl.hpp deleted file mode 100644 index 87b6ff951..000000000 --- a/host/lib/usrp/usrp_e/codec_ctrl.hpp +++ /dev/null @@ -1,90 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#ifndef INCLUDED_USRP_E_CODEC_CTRL_HPP -#define INCLUDED_USRP_E_CODEC_CTRL_HPP - -#include "usrp_e_iface.hpp" -#include -#include -#include - -/*! - * The usrp-e codec control: - * - Init/power down codec. - * - Read aux adc, write aux dac. - */ -class usrp_e_codec_ctrl : boost::noncopyable{ -public: - typedef boost::shared_ptr sptr; - - static const uhd::gain_range_t tx_pga_gain_range; - static const uhd::gain_range_t rx_pga_gain_range; - - /*! - * Make a new codec control object. - * \param iface the usrp_e iface object - * \return the codec control object - */ - static sptr make(usrp_e_iface::sptr iface); - - //! aux adc identifier constants - enum aux_adc_t{ - AUX_ADC_A2 = 0xA2, - AUX_ADC_A1 = 0xA1, - AUX_ADC_B2 = 0xB2, - AUX_ADC_B1 = 0xB1 - }; - - /*! - * Read an auxiliary adc: - * The internals remember which aux adc was read last. - * Therefore, the aux adc switch is only changed as needed. - * \param which which of the 4 adcs - * \return a value in volts - */ - virtual float read_aux_adc(aux_adc_t which) = 0; - - //! aux dac identifier constants - enum aux_dac_t{ - AUX_DAC_A = 0xA, - AUX_DAC_B = 0xB, - AUX_DAC_C = 0xC, - AUX_DAC_D = 0xD //really the sigma delta output - }; - - /*! - * Write an auxiliary dac. - * \param which which of the 4 dacs - * \param volts the level in in volts - */ - virtual void write_aux_dac(aux_dac_t which, float volts) = 0; - - //! Set the TX PGA gain - virtual void set_tx_pga_gain(float gain) = 0; - - //! Get the TX PGA gain - virtual float get_tx_pga_gain(void) = 0; - - //! Set the RX PGA gain ('A' or 'B') - virtual void set_rx_pga_gain(float gain, char which) = 0; - - //! Get the RX PGA gain ('A' or 'B') - virtual float get_rx_pga_gain(char which) = 0; -}; - -#endif /* INCLUDED_USRP_E_CODEC_CTRL_HPP */ diff --git a/host/lib/usrp/usrp_e/codec_impl.cpp b/host/lib/usrp/usrp_e/codec_impl.cpp deleted file mode 100644 index 696fb37ec..000000000 --- a/host/lib/usrp/usrp_e/codec_impl.cpp +++ /dev/null @@ -1,149 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "usrp_e_impl.hpp" -#include -#include -#include - -using namespace uhd; -using namespace uhd::usrp; - -/*********************************************************************** - * Helper Methods - **********************************************************************/ -void usrp_e_impl::codec_init(void){ - //make proxies - _rx_codec_proxy = wax_obj_proxy::make( - boost::bind(&usrp_e_impl::rx_codec_get, this, _1, _2), - boost::bind(&usrp_e_impl::rx_codec_set, this, _1, _2) - ); - _tx_codec_proxy = wax_obj_proxy::make( - boost::bind(&usrp_e_impl::tx_codec_get, this, _1, _2), - boost::bind(&usrp_e_impl::tx_codec_set, this, _1, _2) - ); -} - -/*********************************************************************** - * RX Codec Properties - **********************************************************************/ -static const std::string ad9862_pga_gain_name = "ad9862 pga"; - -void usrp_e_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - //handle the get request conditioned on the key - switch(key.as()){ - case CODEC_PROP_NAME: - val = std::string("usrp-e adc - ad9522"); - return; - - case CODEC_PROP_OTHERS: - val = prop_names_t(); - return; - - case CODEC_PROP_GAIN_NAMES: - val = prop_names_t(1, ad9862_pga_gain_name); - return; - - case CODEC_PROP_GAIN_RANGE: - UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); - val = usrp_e_codec_ctrl::rx_pga_gain_range; - return; - - case CODEC_PROP_GAIN_I: - UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); - val = _codec_ctrl->get_rx_pga_gain('A'); - return; - - case CODEC_PROP_GAIN_Q: - UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); - val = _codec_ctrl->get_rx_pga_gain('B'); - return; - - default: UHD_THROW_PROP_GET_ERROR(); - } -} - -void usrp_e_impl::rx_codec_set(const wax::obj &key_, const wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - //handle the set request conditioned on the key - switch(key.as()){ - case CODEC_PROP_GAIN_I: - UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); - _codec_ctrl->set_rx_pga_gain(val.as(), 'A'); - return; - - case CODEC_PROP_GAIN_Q: - UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); - _codec_ctrl->set_rx_pga_gain(val.as(), 'B'); - return; - - default: UHD_THROW_PROP_SET_ERROR(); - } -} - -/*********************************************************************** - * TX Codec Properties - **********************************************************************/ -void usrp_e_impl::tx_codec_get(const wax::obj &key_, wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - //handle the get request conditioned on the key - switch(key.as()){ - case CODEC_PROP_NAME: - val = std::string("usrp-e dac - ad9522"); - return; - - case CODEC_PROP_OTHERS: - val = prop_names_t(); - return; - - case CODEC_PROP_GAIN_NAMES: - val = prop_names_t(1, ad9862_pga_gain_name); - return; - - case CODEC_PROP_GAIN_RANGE: - UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); - val = usrp_e_codec_ctrl::tx_pga_gain_range; - return; - - case CODEC_PROP_GAIN_I: //only one gain for I and Q - case CODEC_PROP_GAIN_Q: - UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); - val = _codec_ctrl->get_tx_pga_gain(); - return; - - default: UHD_THROW_PROP_GET_ERROR(); - } -} - -void usrp_e_impl::tx_codec_set(const wax::obj &key_, const wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - //handle the set request conditioned on the key - switch(key.as()){ - case CODEC_PROP_GAIN_I: //only one gain for I and Q - case CODEC_PROP_GAIN_Q: - UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); - _codec_ctrl->set_tx_pga_gain(val.as()); - return; - - default: UHD_THROW_PROP_SET_ERROR(); - } -} diff --git a/host/lib/usrp/usrp_e/dboard_iface.cpp b/host/lib/usrp/usrp_e/dboard_iface.cpp deleted file mode 100644 index 6898df8df..000000000 --- a/host/lib/usrp/usrp_e/dboard_iface.cpp +++ /dev/null @@ -1,298 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "usrp_e_iface.hpp" -#include "usrp_e_regs.hpp" -#include "clock_ctrl.hpp" -#include "codec_ctrl.hpp" -#include -#include -#include -#include -#include //i2c and spi constants - -using namespace uhd; -using namespace uhd::usrp; -using namespace boost::assign; - -class usrp_e_dboard_iface : public dboard_iface{ -public: - - usrp_e_dboard_iface( - usrp_e_iface::sptr iface, - usrp_e_clock_ctrl::sptr clock, - usrp_e_codec_ctrl::sptr codec - ){ - _iface = iface; - _clock = clock; - _codec = codec; - - //init the clock rate shadows - this->set_clock_rate(UNIT_RX, _clock->get_fpga_clock_rate()); - this->set_clock_rate(UNIT_TX, _clock->get_fpga_clock_rate()); - - _iface->poke16(UE_REG_GPIO_RX_DBG, 0); - _iface->poke16(UE_REG_GPIO_TX_DBG, 0); - } - - ~usrp_e_dboard_iface(void){ - /* NOP */ - } - - special_props_t get_special_props(void){ - special_props_t props; - props.soft_clock_divider = false; - props.mangle_i2c_addrs = false; - return props; - } - - void write_aux_dac(unit_t, aux_dac_t, float); - float read_aux_adc(unit_t, aux_adc_t); - - void set_pin_ctrl(unit_t, boost::uint16_t); - void set_atr_reg(unit_t, atr_reg_t, boost::uint16_t); - void set_gpio_ddr(unit_t, boost::uint16_t); - void write_gpio(unit_t, boost::uint16_t); - void set_gpio_debug(unit_t, int); - boost::uint16_t read_gpio(unit_t); - - void write_i2c(boost::uint8_t, const byte_vector_t &); - byte_vector_t read_i2c(boost::uint8_t, size_t); - - void write_spi( - unit_t unit, - const spi_config_t &config, - boost::uint32_t data, - size_t num_bits - ); - - boost::uint32_t read_write_spi( - unit_t unit, - const spi_config_t &config, - boost::uint32_t data, - size_t num_bits - ); - - void set_clock_rate(unit_t, double); - std::vector get_clock_rates(unit_t); - double get_clock_rate(unit_t); - void set_clock_enabled(unit_t, bool); - double get_codec_rate(unit_t); - -private: - usrp_e_iface::sptr _iface; - usrp_e_clock_ctrl::sptr _clock; - usrp_e_codec_ctrl::sptr _codec; - uhd::dict _clock_rates; -}; - -/*********************************************************************** - * Make Function - **********************************************************************/ -dboard_iface::sptr make_usrp_e_dboard_iface( - usrp_e_iface::sptr iface, - usrp_e_clock_ctrl::sptr clock, - usrp_e_codec_ctrl::sptr codec -){ - return dboard_iface::sptr(new usrp_e_dboard_iface(iface, clock, codec)); -} - -/*********************************************************************** - * Clock Rates - **********************************************************************/ -void usrp_e_dboard_iface::set_clock_rate(unit_t unit, double rate){ - _clock_rates[unit] = rate; - switch(unit){ - case UNIT_RX: return _clock->set_rx_dboard_clock_rate(rate); - case UNIT_TX: return _clock->set_tx_dboard_clock_rate(rate); - } -} - -std::vector usrp_e_dboard_iface::get_clock_rates(unit_t unit){ - switch(unit){ - case UNIT_RX: return _clock->get_rx_dboard_clock_rates(); - case UNIT_TX: return _clock->get_tx_dboard_clock_rates(); - default: UHD_THROW_INVALID_CODE_PATH(); - } -} - -double usrp_e_dboard_iface::get_clock_rate(unit_t unit){ - return _clock_rates[unit]; -} - -void usrp_e_dboard_iface::set_clock_enabled(unit_t unit, bool enb){ - switch(unit){ - case UNIT_RX: return _clock->enable_rx_dboard_clock(enb); - case UNIT_TX: return _clock->enable_tx_dboard_clock(enb); - } -} - -double usrp_e_dboard_iface::get_codec_rate(unit_t){ - return _clock->get_fpga_clock_rate(); -} - -/*********************************************************************** - * GPIO - **********************************************************************/ -void usrp_e_dboard_iface::set_pin_ctrl(unit_t unit, boost::uint16_t value){ - UHD_ASSERT_THROW(GPIO_SEL_ATR == 1); //make this assumption - switch(unit){ - case UNIT_RX: _iface->poke16(UE_REG_GPIO_RX_SEL, value); return; - case UNIT_TX: _iface->poke16(UE_REG_GPIO_TX_SEL, value); return; - } -} - -void usrp_e_dboard_iface::set_gpio_ddr(unit_t unit, boost::uint16_t value){ - switch(unit){ - case UNIT_RX: _iface->poke16(UE_REG_GPIO_RX_DDR, value); return; - case UNIT_TX: _iface->poke16(UE_REG_GPIO_TX_DDR, value); return; - } -} - -void usrp_e_dboard_iface::write_gpio(unit_t unit, boost::uint16_t value){ - switch(unit){ - case UNIT_RX: _iface->poke16(UE_REG_GPIO_RX_IO, value); return; - case UNIT_TX: _iface->poke16(UE_REG_GPIO_TX_IO, value); return; - } -} - -boost::uint16_t usrp_e_dboard_iface::read_gpio(unit_t unit){ - switch(unit){ - case UNIT_RX: return _iface->peek16(UE_REG_GPIO_RX_IO); - case UNIT_TX: return _iface->peek16(UE_REG_GPIO_TX_IO); - default: UHD_THROW_INVALID_CODE_PATH(); - } -} - -void usrp_e_dboard_iface::set_atr_reg(unit_t unit, atr_reg_t atr, boost::uint16_t value){ - //define mapping of unit to atr regs to register address - static const uhd::dict< - unit_t, uhd::dict - > unit_to_atr_to_addr = map_list_of - (UNIT_RX, map_list_of - (ATR_REG_IDLE, UE_REG_ATR_IDLE_RXSIDE) - (ATR_REG_TX_ONLY, UE_REG_ATR_INTX_RXSIDE) - (ATR_REG_RX_ONLY, UE_REG_ATR_INRX_RXSIDE) - (ATR_REG_FULL_DUPLEX, UE_REG_ATR_FULL_RXSIDE) - ) - (UNIT_TX, map_list_of - (ATR_REG_IDLE, UE_REG_ATR_IDLE_TXSIDE) - (ATR_REG_TX_ONLY, UE_REG_ATR_INTX_TXSIDE) - (ATR_REG_RX_ONLY, UE_REG_ATR_INRX_TXSIDE) - (ATR_REG_FULL_DUPLEX, UE_REG_ATR_FULL_TXSIDE) - ) - ; - _iface->poke16(unit_to_atr_to_addr[unit][atr], value); -} - -void usrp_e_dboard_iface::set_gpio_debug(unit_t unit, int which){ - //set this unit to all outputs - this->set_gpio_ddr(unit, 0xffff); - - //calculate the debug selections - boost::uint32_t dbg_sels = 0x0; - int sel = (which == 0)? GPIO_SEL_DEBUG_0 : GPIO_SEL_DEBUG_1; - for(size_t i = 0; i < 16; i++) dbg_sels |= sel << i; - - //set the debug on and which debug selection - switch(unit){ - case UNIT_RX: - _iface->poke16(UE_REG_GPIO_RX_DBG, 0xffff); - _iface->poke16(UE_REG_GPIO_RX_SEL, dbg_sels); - return; - - case UNIT_TX: - _iface->poke16(UE_REG_GPIO_TX_DBG, 0xffff); - _iface->poke16(UE_REG_GPIO_TX_SEL, dbg_sels); - return; - } -} - -/*********************************************************************** - * SPI - **********************************************************************/ -/*! - * Static function to convert a unit type to a spi slave device number. - * \param unit the dboard interface unit type enum - * \return the slave device number - */ -static boost::uint32_t unit_to_otw_spi_dev(dboard_iface::unit_t unit){ - switch(unit){ - case dboard_iface::UNIT_TX: return UE_SPI_SS_TX_DB; - case dboard_iface::UNIT_RX: return UE_SPI_SS_RX_DB; - } - throw std::invalid_argument("unknown unit type"); -} - -void usrp_e_dboard_iface::write_spi( - unit_t unit, - const spi_config_t &config, - boost::uint32_t data, - size_t num_bits -){ - _iface->transact_spi(unit_to_otw_spi_dev(unit), config, data, num_bits, false /*no rb*/); -} - -boost::uint32_t usrp_e_dboard_iface::read_write_spi( - unit_t unit, - const spi_config_t &config, - boost::uint32_t data, - size_t num_bits -){ - return _iface->transact_spi(unit_to_otw_spi_dev(unit), config, data, num_bits, true /*rb*/); -} - -/*********************************************************************** - * I2C - **********************************************************************/ -void usrp_e_dboard_iface::write_i2c(boost::uint8_t addr, const byte_vector_t &bytes){ - return _iface->write_i2c(addr, bytes); -} - -byte_vector_t usrp_e_dboard_iface::read_i2c(boost::uint8_t addr, size_t num_bytes){ - return _iface->read_i2c(addr, num_bytes); -} - -/*********************************************************************** - * Aux DAX/ADC - **********************************************************************/ -void usrp_e_dboard_iface::write_aux_dac(dboard_iface::unit_t, aux_dac_t which, float value){ - //same aux dacs for each unit - static const uhd::dict which_to_aux_dac = map_list_of - (AUX_DAC_A, usrp_e_codec_ctrl::AUX_DAC_A) - (AUX_DAC_B, usrp_e_codec_ctrl::AUX_DAC_B) - (AUX_DAC_C, usrp_e_codec_ctrl::AUX_DAC_C) - (AUX_DAC_D, usrp_e_codec_ctrl::AUX_DAC_D) - ; - _codec->write_aux_dac(which_to_aux_dac[which], value); -} - -float usrp_e_dboard_iface::read_aux_adc(dboard_iface::unit_t unit, aux_adc_t which){ - static const uhd::dict< - unit_t, uhd::dict - > unit_to_which_to_aux_adc = map_list_of - (UNIT_RX, map_list_of - (AUX_ADC_A, usrp_e_codec_ctrl::AUX_ADC_A1) - (AUX_ADC_B, usrp_e_codec_ctrl::AUX_ADC_B1) - ) - (UNIT_TX, map_list_of - (AUX_ADC_A, usrp_e_codec_ctrl::AUX_ADC_A2) - (AUX_ADC_B, usrp_e_codec_ctrl::AUX_ADC_B2) - ) - ; - return _codec->read_aux_adc(unit_to_which_to_aux_adc[unit][which]); -} diff --git a/host/lib/usrp/usrp_e/dboard_impl.cpp b/host/lib/usrp/usrp_e/dboard_impl.cpp deleted file mode 100644 index f2840dcfc..000000000 --- a/host/lib/usrp/usrp_e/dboard_impl.cpp +++ /dev/null @@ -1,172 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "usrp_e_impl.hpp" -#include "usrp_e_regs.hpp" -#include -#include -#include -#include -#include -#include - -using namespace uhd; -using namespace uhd::usrp; - -/*********************************************************************** - * Dboard Initialization - **********************************************************************/ -void usrp_e_impl::dboard_init(void){ - _rx_db_eeprom = dboard_eeprom_t(_iface->read_eeprom(I2C_ADDR_RX_DB, 0, dboard_eeprom_t::num_bytes())); - _tx_db_eeprom = dboard_eeprom_t(_iface->read_eeprom(I2C_ADDR_TX_DB, 0, dboard_eeprom_t::num_bytes())); - - //create a new dboard interface and manager - _dboard_iface = make_usrp_e_dboard_iface( - _iface, _clock_ctrl, _codec_ctrl - ); - _dboard_manager = dboard_manager::make( - _rx_db_eeprom.id, _tx_db_eeprom.id, _dboard_iface - ); - - //setup the dboard proxies - _rx_dboard_proxy = wax_obj_proxy::make( - boost::bind(&usrp_e_impl::rx_dboard_get, this, _1, _2), - boost::bind(&usrp_e_impl::rx_dboard_set, this, _1, _2) - ); - _tx_dboard_proxy = wax_obj_proxy::make( - boost::bind(&usrp_e_impl::tx_dboard_get, this, _1, _2), - boost::bind(&usrp_e_impl::tx_dboard_set, this, _1, _2) - ); -} - -/*********************************************************************** - * RX Dboard Get - **********************************************************************/ -void usrp_e_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - //handle the get request conditioned on the key - switch(key.as()){ - case DBOARD_PROP_NAME: - val = std::string("usrp-e dboard (rx unit)"); - return; - - case DBOARD_PROP_SUBDEV: - val = _dboard_manager->get_rx_subdev(key.name); - return; - - case DBOARD_PROP_SUBDEV_NAMES: - val = _dboard_manager->get_rx_subdev_names(); - return; - - case DBOARD_PROP_DBOARD_ID: - val = _rx_db_eeprom.id; - return; - - case DBOARD_PROP_DBOARD_IFACE: - val = _dboard_iface; - return; - - case DBOARD_PROP_CODEC: - val = _rx_codec_proxy->get_link(); - return; - - case DBOARD_PROP_GAIN_GROUP: - val = make_gain_group( - _rx_db_eeprom.id, - _dboard_manager->get_rx_subdev(key.name), - _rx_codec_proxy->get_link(), - GAIN_GROUP_POLICY_RX - ); - return; - - default: UHD_THROW_PROP_GET_ERROR(); - } -} - -/*********************************************************************** - * RX Dboard Set - **********************************************************************/ -void usrp_e_impl::rx_dboard_set(const wax::obj &key, const wax::obj &val){ - switch(key.as()){ - case DBOARD_PROP_DBOARD_ID: - _rx_db_eeprom.id = val.as(); - _iface->write_eeprom(I2C_ADDR_RX_DB, 0, _rx_db_eeprom.get_eeprom_bytes()); - return; - - default: UHD_THROW_PROP_SET_ERROR(); - } -} - -/*********************************************************************** - * TX Dboard Get - **********************************************************************/ -void usrp_e_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - //handle the get request conditioned on the key - switch(key.as()){ - case DBOARD_PROP_NAME: - val = std::string("usrp-e dboard (tx unit)"); - return; - - case DBOARD_PROP_SUBDEV: - val = _dboard_manager->get_tx_subdev(key.name); - return; - - case DBOARD_PROP_SUBDEV_NAMES: - val = _dboard_manager->get_tx_subdev_names(); - return; - - case DBOARD_PROP_DBOARD_ID: - val = _tx_db_eeprom.id; - return; - - case DBOARD_PROP_DBOARD_IFACE: - val = _dboard_iface; - return; - - case DBOARD_PROP_CODEC: - val = _tx_codec_proxy->get_link(); - return; - - case DBOARD_PROP_GAIN_GROUP: - val = make_gain_group( - _tx_db_eeprom.id, - _dboard_manager->get_tx_subdev(key.name), - _tx_codec_proxy->get_link(), - GAIN_GROUP_POLICY_TX - ); - return; - - default: UHD_THROW_PROP_GET_ERROR(); - } -} - -/*********************************************************************** - * TX Dboard Set - **********************************************************************/ -void usrp_e_impl::tx_dboard_set(const wax::obj &key, const wax::obj &val){ - switch(key.as()){ - case DBOARD_PROP_DBOARD_ID: - _tx_db_eeprom.id = val.as(); - _iface->write_eeprom(I2C_ADDR_TX_DB, 0, _tx_db_eeprom.get_eeprom_bytes()); - return; - - default: UHD_THROW_PROP_SET_ERROR(); - } -} diff --git a/host/lib/usrp/usrp_e/dsp_impl.cpp b/host/lib/usrp/usrp_e/dsp_impl.cpp deleted file mode 100644 index 97f173c1a..000000000 --- a/host/lib/usrp/usrp_e/dsp_impl.cpp +++ /dev/null @@ -1,192 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "usrp_e_impl.hpp" -#include "usrp_e_regs.hpp" -#include -#include -#include -#include - -#define rint boost::math::iround - -using namespace uhd; -using namespace uhd::usrp; - -/*********************************************************************** - * RX DDC Initialization - **********************************************************************/ -void usrp_e_impl::rx_ddc_init(void){ - _rx_ddc_proxy = wax_obj_proxy::make( - boost::bind(&usrp_e_impl::rx_ddc_get, this, _1, _2), - boost::bind(&usrp_e_impl::rx_ddc_set, this, _1, _2) - ); - - //initial config and update - rx_ddc_set(DSP_PROP_FREQ_SHIFT, double(0)); - rx_ddc_set(DSP_PROP_HOST_RATE, double(64e6/10)); -} - -/*********************************************************************** - * RX DDC Get - **********************************************************************/ -void usrp_e_impl::rx_ddc_get(const wax::obj &key_, wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - switch(key.as()){ - case DSP_PROP_NAME: - val = std::string("usrp-e ddc0"); - return; - - case DSP_PROP_OTHERS: - val = prop_names_t(); //empty - return; - - case DSP_PROP_FREQ_SHIFT: - val = _ddc_freq; - return; - - case DSP_PROP_FREQ_SHIFT_NAMES: - val = prop_names_t(1, ""); - return; - - case DSP_PROP_CODEC_RATE: - val = _clock_ctrl->get_fpga_clock_rate(); - return; - - case DSP_PROP_HOST_RATE: - val = _clock_ctrl->get_fpga_clock_rate()/_ddc_decim; - return; - - default: UHD_THROW_PROP_GET_ERROR(); - } -} - -/*********************************************************************** - * RX DDC Set - **********************************************************************/ -void usrp_e_impl::rx_ddc_set(const wax::obj &key_, const wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - switch(key.as()){ - - case DSP_PROP_FREQ_SHIFT:{ - double new_freq = val.as(); - _iface->poke32(UE_REG_DSP_RX_FREQ, - dsp_type1::calc_cordic_word_and_update(new_freq, _clock_ctrl->get_fpga_clock_rate()) - ); - _ddc_freq = new_freq; //shadow - } - return; - - case DSP_PROP_HOST_RATE:{ - //set the decimation - _ddc_decim = rint(_clock_ctrl->get_fpga_clock_rate()/val.as()); - _iface->poke32(UE_REG_DSP_RX_DECIM_RATE, dsp_type1::calc_cic_filter_word(_ddc_decim)); - - //set the scaling - static const boost::int16_t default_rx_scale_iq = 1024; - _iface->poke32(UE_REG_DSP_RX_SCALE_IQ, - dsp_type1::calc_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq) - ); - } - return; - - default: UHD_THROW_PROP_SET_ERROR(); - } -} - -/*********************************************************************** - * TX DUC Initialization - **********************************************************************/ -void usrp_e_impl::tx_duc_init(void){ - _tx_duc_proxy = wax_obj_proxy::make( - boost::bind(&usrp_e_impl::tx_duc_get, this, _1, _2), - boost::bind(&usrp_e_impl::tx_duc_set, this, _1, _2) - ); - - //initial config and update - tx_duc_set(DSP_PROP_FREQ_SHIFT, double(0)); - tx_duc_set(DSP_PROP_HOST_RATE, double(64e6/10)); -} - -/*********************************************************************** - * TX DUC Get - **********************************************************************/ -void usrp_e_impl::tx_duc_get(const wax::obj &key_, wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - switch(key.as()){ - case DSP_PROP_NAME: - val = std::string("usrp-e duc0"); - return; - - case DSP_PROP_OTHERS: - val = prop_names_t(); //empty - return; - - case DSP_PROP_FREQ_SHIFT: - val = _duc_freq; - return; - - case DSP_PROP_FREQ_SHIFT_NAMES: - val = prop_names_t(1, ""); - return; - - case DSP_PROP_CODEC_RATE: - val = _clock_ctrl->get_fpga_clock_rate(); - return; - - case DSP_PROP_HOST_RATE: - val = _clock_ctrl->get_fpga_clock_rate()/_duc_interp; - return; - - default: UHD_THROW_PROP_GET_ERROR(); - } -} - -/*********************************************************************** - * TX DUC Set - **********************************************************************/ -void usrp_e_impl::tx_duc_set(const wax::obj &key_, const wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - switch(key.as()){ - - case DSP_PROP_FREQ_SHIFT:{ - double new_freq = val.as(); - _iface->poke32(UE_REG_DSP_TX_FREQ, - dsp_type1::calc_cordic_word_and_update(new_freq, _clock_ctrl->get_fpga_clock_rate()) - ); - _duc_freq = new_freq; //shadow - } - return; - - case DSP_PROP_HOST_RATE:{ - _duc_interp = rint(_clock_ctrl->get_fpga_clock_rate()/val.as()); - - //set the interpolation - _iface->poke32(UE_REG_DSP_TX_INTERP_RATE, dsp_type1::calc_cic_filter_word(_duc_interp)); - - //set the scaling - _iface->poke32(UE_REG_DSP_TX_SCALE_IQ, dsp_type1::calc_iq_scale_word(_duc_interp)); - } - return; - - default: UHD_THROW_PROP_SET_ERROR(); - } -} diff --git a/host/lib/usrp/usrp_e/fpga-downloader.cc b/host/lib/usrp/usrp_e/fpga-downloader.cc deleted file mode 100644 index 4dc537919..000000000 --- a/host/lib/usrp/usrp_e/fpga-downloader.cc +++ /dev/null @@ -1,274 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -/* - * Configuration connections - * - * CCK - MCSPI1_CLK - * DIN - MCSPI1_MOSI - * PROG_B - GPIO_175 - output (change mux) - * DONE - GPIO_173 - input (change mux) - * INIT_B - GPIO_114 - input (change mux) - * -*/ - -const unsigned int PROG_B = 175; -const unsigned int DONE = 173; -const unsigned int INIT_B = 114; - -//static std::string bit_file = "safe_u1e.bin"; - -const int BUF_SIZE = 4096; - -enum gpio_direction {IN, OUT}; - -class gpio { - public: - - gpio(unsigned int gpio_num, gpio_direction pin_direction); - - bool get_value(); - void set_value(bool state); - - private: - - std::stringstream base_path; - std::fstream value_file; -}; - -class spidev { - public: - - spidev(std::string dev_name); - ~spidev(); - - void send(char *wbuf, char *rbuf, unsigned int nbytes); - - private: - - int fd; - -}; - -gpio::gpio(unsigned int gpio_num, gpio_direction pin_direction) -{ - std::fstream export_file; - - export_file.open("/sys/class/gpio/export", std::ios::out); - if (not export_file.is_open()) throw std::runtime_error( - "Failed to open gpio export file." - ); - - export_file << gpio_num << std::endl; - - base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush; - - std::fstream direction_file; - std::string direction_file_name; - - if (gpio_num != 114) { - direction_file_name = base_path.str() + "/direction"; - - direction_file.open(direction_file_name.c_str()); - if (!direction_file.is_open()) - std::cout << "Failed to open direction file." << std::endl; - if (pin_direction == OUT) - direction_file << "out" << std::endl; - else - direction_file << "in" << std::endl; - } - - std::string value_file_name; - - value_file_name = base_path.str() + "/value"; - - value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out); - if (!value_file.is_open()) - std::cout << "Failed to open value file." << std::endl; -} - -bool gpio::get_value() -{ - - std::string val; - - std::getline(value_file, val); - value_file.seekg(0); - - if (val == "0") - return false; - else if (val == "1") - return true; - else - std::cout << "Data read from value file|" << val << "|" << std::endl; - - return false; -} - -void gpio::set_value(bool state) -{ - - if (state) - value_file << "1" << std::endl; - else - value_file << "0" << std::endl; -} - -static void prepare_fpga_for_configuration(gpio &prog, gpio &)//init) -{ - - prog.set_value(true); - prog.set_value(false); - prog.set_value(true); - -#if 0 - bool ready_to_program(false); - unsigned int count(0); - do { - ready_to_program = init.get_value(); - count++; - - sleep(1); - } while (count < 10 && !ready_to_program); - - if (count == 10) { - std::cout << "FPGA not ready for programming." << std::endl; - exit(-1); - } -#endif -} - -spidev::spidev(std::string fname) -{ - int ret; - int mode = 0; - int speed = 12000000; - int bits = 8; - - fd = open(fname.c_str(), O_RDWR); - - ret = ioctl(fd, SPI_IOC_WR_MODE, &mode); - ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed); - ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits); -} - - -spidev::~spidev() -{ - close(fd); -} - -void spidev::send(char *buf, char *rbuf, unsigned int nbytes) -{ - int ret; - - struct spi_ioc_transfer tr; - tr.tx_buf = (unsigned long) buf; - tr.rx_buf = (unsigned long) rbuf; - tr.len = nbytes; - tr.delay_usecs = 0; - tr.speed_hz = 48000000; - tr.bits_per_word = 8; - - ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); - -} - -static void send_file_to_fpga(const std::string &file_name, gpio &error, gpio &done) -{ - std::ifstream bitstream; - - std::cout << "File name - " << file_name.c_str() << std::endl; - - bitstream.open(file_name.c_str(), std::ios::binary); - if (!bitstream.is_open()) - std::cout << "File " << file_name << " not opened succesfully." << std::endl; - - spidev spi("/dev/spidev1.0"); - char buf[BUF_SIZE]; - char rbuf[BUF_SIZE]; - - do { - bitstream.read(buf, BUF_SIZE); - spi.send(buf, rbuf, bitstream.gcount()); - - if (error.get_value()) - std::cout << "INIT_B went high, error occured." << std::endl; - - if (!done.get_value()) - std::cout << "Configuration complete." << std::endl; - - } while (bitstream.gcount() == BUF_SIZE); -} - -/* -int main(int argc, char *argv[]) -{ - - gpio gpio_prog_b(PROG_B, OUT); - gpio gpio_init_b(INIT_B, IN); - gpio gpio_done (DONE, IN); - - if (argc == 2) - bit_file = argv[1]; - - std::cout << "FPGA config file: " << bit_file << std::endl; - - prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b); - - std::cout << "Done = " << gpio_done.get_value() << std::endl; - - send_file_to_fpga(bit_file, gpio_init_b, gpio_done); -} -*/ - -void usrp_e_load_fpga(const std::string &bin_file){ - gpio gpio_prog_b(PROG_B, OUT); - gpio gpio_init_b(INIT_B, IN); - gpio gpio_done (DONE, IN); - - std::cout << "Loading FPGA image: " << bin_file << "... " << std::flush; - - UHD_ASSERT_THROW(std::system("/sbin/rmmod usrp_e") == 0); - - prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b); - - std::cout << "done = " << gpio_done.get_value() << std::endl; - - send_file_to_fpga(bin_file, gpio_init_b, gpio_done); - - UHD_ASSERT_THROW(std::system("/sbin/modprobe usrp_e") == 0); - -} - diff --git a/host/lib/usrp/usrp_e/io_impl.cpp b/host/lib/usrp/usrp_e/io_impl.cpp deleted file mode 100644 index e863944e8..000000000 --- a/host/lib/usrp/usrp_e/io_impl.cpp +++ /dev/null @@ -1,272 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "usrp_e_impl.hpp" -#include "usrp_e_regs.hpp" -#include -#include -#include -#include "../../transport/vrt_packet_handler.hpp" -#include -#include -#include -#include - -using namespace uhd; -using namespace uhd::usrp; -using namespace uhd::transport; - -zero_copy_if::sptr usrp_e_make_mmap_zero_copy(usrp_e_iface::sptr iface); - -/*********************************************************************** - * Constants - **********************************************************************/ -static const size_t tx_async_report_sid = 1; -static const int underflow_flags = async_metadata_t::EVENT_CODE_UNDERFLOW | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET; -static const bool recv_debug = false; - -/*********************************************************************** - * io impl details (internal to this file) - * - pirate crew of 1 - * - bounded buffer - * - thread loop - * - vrt packet handler states - **********************************************************************/ -struct usrp_e_impl::io_impl{ - //state management for the vrt packet handler code - vrt_packet_handler::recv_state packet_handler_recv_state; - vrt_packet_handler::send_state packet_handler_send_state; - zero_copy_if::sptr data_xport; - bool continuous_streaming; - io_impl(usrp_e_iface::sptr iface): - data_xport(usrp_e_make_mmap_zero_copy(iface)), - recv_pirate_booty(recv_booty_type::make(data_xport->get_num_recv_frames())), - async_msg_fifo(bounded_buffer::make(100/*messages deep*/)) - { - /* NOP */ - } - - ~io_impl(void){ - recv_pirate_crew_raiding = false; - recv_pirate_crew.interrupt_all(); - recv_pirate_crew.join_all(); - } - - bool get_recv_buffs(vrt_packet_handler::managed_recv_buffs_t &buffs, double timeout){ - UHD_ASSERT_THROW(buffs.size() == 1); - boost::this_thread::disable_interruption di; //disable because the wait can throw - return recv_pirate_booty->pop_with_timed_wait(buffs.front(), timeout); - } - - //a pirate's life is the life for me! - void recv_pirate_loop(usrp_e_clock_ctrl::sptr); - typedef bounded_buffer recv_booty_type; - recv_booty_type::sptr recv_pirate_booty; - bounded_buffer::sptr async_msg_fifo; - boost::thread_group recv_pirate_crew; - bool recv_pirate_crew_raiding; -}; - -/*********************************************************************** - * Receive Pirate Loop - * - while raiding, loot for recv buffers - * - put booty into the alignment buffer - **********************************************************************/ -void usrp_e_impl::io_impl::recv_pirate_loop(usrp_e_clock_ctrl::sptr clock_ctrl) -{ - set_thread_priority_safe(); - recv_pirate_crew_raiding = true; - - while(recv_pirate_crew_raiding){ - managed_recv_buffer::sptr buff = this->data_xport->get_recv_buff(); - if (not buff.get()) continue; //ignore timeout/error buffers - - if (recv_debug){ - std::cout << "len " << buff->size() << std::endl; - for (size_t i = 0; i < 9; i++){ - std::cout << boost::format(" 0x%08x") % buff->cast()[i] << std::endl; - } - std::cout << std::endl << std::endl; - } - - try{ - //extract the vrt header packet info - vrt::if_packet_info_t if_packet_info; - if_packet_info.num_packet_words32 = buff->size()/sizeof(boost::uint32_t); - const boost::uint32_t *vrt_hdr = buff->cast(); - vrt::if_hdr_unpack_le(vrt_hdr, if_packet_info); - - //handle a tx async report message - if (if_packet_info.sid == tx_async_report_sid and if_packet_info.packet_type != vrt::if_packet_info_t::PACKET_TYPE_DATA){ - - //fill in the async metadata - async_metadata_t metadata; - metadata.channel = 0; - metadata.has_time_spec = if_packet_info.has_tsi and if_packet_info.has_tsf; - metadata.time_spec = time_spec_t( - time_t(if_packet_info.tsi), size_t(if_packet_info.tsf), clock_ctrl->get_fpga_clock_rate() - ); - metadata.event_code = vrt_packet_handler::get_context_code(vrt_hdr, if_packet_info); - - //print the famous U, and push the metadata into the message queue - if (metadata.event_code & underflow_flags) std::cerr << "U" << std::flush; - async_msg_fifo->push_with_pop_on_full(metadata); - continue; - } - - //same number of frames as the data transport -> always immediate - recv_pirate_booty->push_with_wait(buff); - - }catch(const std::exception &e){ - std::cerr << "Error (usrp-e recv pirate loop): " << e.what() << std::endl; - } - } -} - -/*********************************************************************** - * Helper Functions - **********************************************************************/ -void usrp_e_impl::io_init(void){ - //setup otw types - _send_otw_type.width = 16; - _send_otw_type.shift = 0; - _send_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN; - - _recv_otw_type.width = 16; - _recv_otw_type.shift = 0; - _recv_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN; - - //setup before the registers (transport called to calculate max spp) - _io_impl = UHD_PIMPL_MAKE(io_impl, (_iface)); - - //setup rx data path - _iface->poke32(UE_REG_CTRL_RX_NSAMPS_PER_PKT, get_max_recv_samps_per_packet()); - _iface->poke32(UE_REG_CTRL_RX_NCHANNELS, 1); - _iface->poke32(UE_REG_CTRL_RX_CLEAR_OVERRUN, 1); //reset - _iface->poke32(UE_REG_CTRL_RX_VRT_HEADER, 0 - | (0x1 << 28) //if data with stream id - | (0x1 << 26) //has trailer - | (0x3 << 22) //integer time other - | (0x1 << 20) //fractional time sample count - ); - _iface->poke32(UE_REG_CTRL_RX_VRT_STREAM_ID, 0); - _iface->poke32(UE_REG_CTRL_RX_VRT_TRAILER, 0); - - //setup the tx policy - _iface->poke32(UE_REG_CTRL_TX_REPORT_SID, tx_async_report_sid); - _iface->poke32(UE_REG_CTRL_TX_POLICY, UE_FLAG_CTRL_TX_POLICY_NEXT_PACKET); - - //spawn a pirate, yarrr! - _io_impl->recv_pirate_crew.create_thread(boost::bind( - &usrp_e_impl::io_impl::recv_pirate_loop, _io_impl.get(), _clock_ctrl - )); -} - -void usrp_e_impl::issue_stream_cmd(const stream_cmd_t &stream_cmd){ - _io_impl->continuous_streaming = (stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_START_CONTINUOUS); - _iface->poke32(UE_REG_CTRL_RX_STREAM_CMD, dsp_type1::calc_stream_cmd_word( - stream_cmd, get_max_recv_samps_per_packet() - )); - _iface->poke32(UE_REG_CTRL_RX_TIME_SECS, boost::uint32_t(stream_cmd.time_spec.get_full_secs())); - _iface->poke32(UE_REG_CTRL_RX_TIME_TICKS, stream_cmd.time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate())); -} - -void usrp_e_impl::handle_overrun(size_t){ - std::cerr << "O"; //the famous OOOOOOOOOOO - _iface->poke32(UE_REG_CTRL_RX_CLEAR_OVERRUN, 0); - if (_io_impl->continuous_streaming){ - this->issue_stream_cmd(stream_cmd_t::STREAM_MODE_START_CONTINUOUS); - } -} - -/*********************************************************************** - * Data Send - **********************************************************************/ -bool get_send_buffs( - zero_copy_if::sptr trans, double timeout, - vrt_packet_handler::managed_send_buffs_t &buffs -){ - UHD_ASSERT_THROW(buffs.size() == 1); - buffs[0] = trans->get_send_buff(timeout); - return buffs[0].get() != NULL; -} - -size_t usrp_e_impl::get_max_send_samps_per_packet(void) const{ - static const size_t hdr_size = 0 - + vrt::max_if_hdr_words32*sizeof(boost::uint32_t) - - sizeof(vrt::if_packet_info_t().cid) //no class id ever used - ; - size_t bpp = _io_impl->data_xport->get_send_frame_size() - hdr_size; - return bpp/_send_otw_type.get_sample_size(); -} - -size_t usrp_e_impl::send( - const std::vector &buffs, size_t num_samps, - const tx_metadata_t &metadata, const io_type_t &io_type, - send_mode_t send_mode, double timeout -){ - return vrt_packet_handler::send( - _io_impl->packet_handler_send_state, //last state of the send handler - buffs, num_samps, //buffer to fill - metadata, send_mode, //samples metadata - io_type, _send_otw_type, //input and output types to convert - _clock_ctrl->get_fpga_clock_rate(), //master clock tick rate - uhd::transport::vrt::if_hdr_pack_le, - boost::bind(&get_send_buffs, _io_impl->data_xport, timeout, _1), - get_max_send_samps_per_packet() - ); -} - -/*********************************************************************** - * Data Recv - **********************************************************************/ -size_t usrp_e_impl::get_max_recv_samps_per_packet(void) const{ - static const size_t hdr_size = 0 - + vrt::max_if_hdr_words32*sizeof(boost::uint32_t) - + sizeof(vrt::if_packet_info_t().tlr) //forced to have trailer - - sizeof(vrt::if_packet_info_t().cid) //no class id ever used - ; - size_t bpp = _io_impl->data_xport->get_recv_frame_size() - hdr_size; - return bpp/_recv_otw_type.get_sample_size(); -} - -size_t usrp_e_impl::recv( - const std::vector &buffs, size_t num_samps, - rx_metadata_t &metadata, const io_type_t &io_type, - recv_mode_t recv_mode, double timeout -){ - return vrt_packet_handler::recv( - _io_impl->packet_handler_recv_state, //last state of the recv handler - buffs, num_samps, //buffer to fill - metadata, recv_mode, //samples metadata - io_type, _recv_otw_type, //input and output types to convert - _clock_ctrl->get_fpga_clock_rate(), //master clock tick rate - uhd::transport::vrt::if_hdr_unpack_le, - boost::bind(&usrp_e_impl::io_impl::get_recv_buffs, _io_impl.get(), _1, timeout), - boost::bind(&usrp_e_impl::handle_overrun, this, _1) - ); -} - -/*********************************************************************** - * Async Recv - **********************************************************************/ -bool usrp_e_impl::recv_async_msg( - async_metadata_t &async_metadata, double timeout -){ - boost::this_thread::disable_interruption di; //disable because the wait can throw - return _io_impl->async_msg_fifo->pop_with_timed_wait(async_metadata, timeout); -} diff --git a/host/lib/usrp/usrp_e/mboard_impl.cpp b/host/lib/usrp/usrp_e/mboard_impl.cpp deleted file mode 100644 index f0118aa4b..000000000 --- a/host/lib/usrp/usrp_e/mboard_impl.cpp +++ /dev/null @@ -1,159 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "usrp_e_impl.hpp" -#include "usrp_e_regs.hpp" -#include -#include -#include -#include -#include -#include - -using namespace uhd; -using namespace uhd::usrp; - -/*********************************************************************** - * Mboard Initialization - **********************************************************************/ -void usrp_e_impl::mboard_init(void){ - _mboard_proxy = wax_obj_proxy::make( - boost::bind(&usrp_e_impl::mboard_get, this, _1, _2), - boost::bind(&usrp_e_impl::mboard_set, this, _1, _2) - ); - - //init the clock config - _clock_config.ref_source = clock_config_t::REF_AUTO; - _clock_config.pps_source = clock_config_t::PPS_SMA; - - //TODO poke the clock config regs -} - -/*********************************************************************** - * Mboard Get - **********************************************************************/ -void usrp_e_impl::mboard_get(const wax::obj &key_, wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - //handle the get request conditioned on the key - switch(key.as()){ - case MBOARD_PROP_NAME: - val = std::string("usrp-e mboard"); - return; - - case MBOARD_PROP_OTHERS: - val = prop_names_t(); - return; - - case MBOARD_PROP_RX_DBOARD: - UHD_ASSERT_THROW(key.name == ""); - val = _rx_dboard_proxy->get_link(); - return; - - case MBOARD_PROP_RX_DBOARD_NAMES: - val = prop_names_t(1, ""); //vector of size 1 with empty string - return; - - case MBOARD_PROP_TX_DBOARD: - UHD_ASSERT_THROW(key.name == ""); - val = _tx_dboard_proxy->get_link(); - return; - - case MBOARD_PROP_TX_DBOARD_NAMES: - val = prop_names_t(1, ""); //vector of size 1 with empty string - return; - - case MBOARD_PROP_RX_DSP: - UHD_ASSERT_THROW(key.name == ""); - val = _rx_ddc_proxy->get_link(); - return; - - case MBOARD_PROP_RX_DSP_NAMES: - val = prop_names_t(1, ""); - return; - - case MBOARD_PROP_TX_DSP: - UHD_ASSERT_THROW(key.name == ""); - val = _tx_duc_proxy->get_link(); - return; - - case MBOARD_PROP_TX_DSP_NAMES: - val = prop_names_t(1, ""); - return; - - case MBOARD_PROP_CLOCK_CONFIG: - val = _clock_config; - return; - - case MBOARD_PROP_RX_SUBDEV_SPEC: - val = _rx_subdev_spec; - return; - - case MBOARD_PROP_TX_SUBDEV_SPEC: - val = _tx_subdev_spec; - return; - - default: UHD_THROW_PROP_GET_ERROR(); - } -} - -/*********************************************************************** - * Mboard Set - **********************************************************************/ -void usrp_e_impl::mboard_set(const wax::obj &key, const wax::obj &val){ - //handle the get request conditioned on the key - switch(key.as()){ - - case MBOARD_PROP_STREAM_CMD: - issue_stream_cmd(val.as()); - return; - - case MBOARD_PROP_TIME_NOW: - case MBOARD_PROP_TIME_NEXT_PPS:{ - time_spec_t time_spec = val.as(); - _iface->poke32(UE_REG_TIME64_TICKS, time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate())); - boost::uint32_t imm_flags = (key.as() == MBOARD_PROP_TIME_NOW)? 1 : 0; - _iface->poke32(UE_REG_TIME64_IMM, imm_flags); - _iface->poke32(UE_REG_TIME64_SECS, time_spec.get_full_secs()); - } - return; - - case MBOARD_PROP_RX_SUBDEV_SPEC: - _rx_subdev_spec = val.as(); - verify_rx_subdev_spec(_rx_subdev_spec, _mboard_proxy->get_link()); - //sanity check - UHD_ASSERT_THROW(_rx_subdev_spec.size() == 1); - //set the mux - _iface->poke32(UE_REG_DSP_RX_MUX, dsp_type1::calc_rx_mux_word( - _dboard_manager->get_rx_subdev(_rx_subdev_spec.front().sd_name)[SUBDEV_PROP_CONNECTION].as() - )); - return; - - case MBOARD_PROP_TX_SUBDEV_SPEC: - _tx_subdev_spec = val.as(); - verify_tx_subdev_spec(_tx_subdev_spec, _mboard_proxy->get_link()); - //sanity check - UHD_ASSERT_THROW(_tx_subdev_spec.size() == 1); - //set the mux - _iface->poke32(UE_REG_DSP_TX_MUX, dsp_type1::calc_tx_mux_word( - _dboard_manager->get_tx_subdev(_tx_subdev_spec.front().sd_name)[SUBDEV_PROP_CONNECTION].as() - )); - return; - - default: UHD_THROW_PROP_SET_ERROR(); - } -} diff --git a/host/lib/usrp/usrp_e/usrp_e_iface.cpp b/host/lib/usrp/usrp_e/usrp_e_iface.cpp deleted file mode 100644 index f00e92946..000000000 --- a/host/lib/usrp/usrp_e/usrp_e_iface.cpp +++ /dev/null @@ -1,194 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "usrp_e_iface.hpp" -#include -#include //ioctl -#include //open, close -#include //ioctl structures and constants -#include -#include //mutex -#include - -using namespace uhd; - -class usrp_e_iface_impl : public usrp_e_iface{ -public: - - int get_file_descriptor(void){ - return _node_fd; - } - - /******************************************************************* - * Structors - ******************************************************************/ - usrp_e_iface_impl(const std::string &node){ - //open the device node and check file descriptor - if ((_node_fd = ::open(node.c_str(), O_RDWR)) < 0){ - throw std::runtime_error(str( - boost::format("Failed to open %s") % node - )); - } - } - - ~usrp_e_iface_impl(void){ - //close the device node file descriptor - ::close(_node_fd); - } - - /******************************************************************* - * IOCTL: provides the communication base for all other calls - ******************************************************************/ - void ioctl(int request, void *mem){ - boost::mutex::scoped_lock lock(_ctrl_mutex); - - if (::ioctl(_node_fd, request, mem) < 0){ - throw std::runtime_error(str( - boost::format("ioctl failed with request %d") % request - )); - } - } - - /******************************************************************* - * Peek and Poke - ******************************************************************/ - void poke32(boost::uint32_t addr, boost::uint32_t value){ - //load the data struct - usrp_e_ctl32 data; - data.offset = addr; - data.count = 1; - data.buf[0] = value; - - //call the ioctl - this->ioctl(USRP_E_WRITE_CTL32, &data); - } - - void poke16(boost::uint32_t addr, boost::uint16_t value){ - //load the data struct - usrp_e_ctl16 data; - data.offset = addr; - data.count = 1; - data.buf[0] = value; - - //call the ioctl - this->ioctl(USRP_E_WRITE_CTL16, &data); - } - - boost::uint32_t peek32(boost::uint32_t addr){ - //load the data struct - usrp_e_ctl32 data; - data.offset = addr; - data.count = 1; - - //call the ioctl - this->ioctl(USRP_E_READ_CTL32, &data); - - return data.buf[0]; - } - - boost::uint16_t peek16(boost::uint32_t addr){ - //load the data struct - usrp_e_ctl16 data; - data.offset = addr; - data.count = 1; - - //call the ioctl - this->ioctl(USRP_E_READ_CTL16, &data); - - return data.buf[0]; - } - - /******************************************************************* - * I2C - ******************************************************************/ - static const size_t max_i2c_data_bytes = 10; - - void write_i2c(boost::uint8_t addr, const byte_vector_t &bytes){ - //allocate some memory for this transaction - UHD_ASSERT_THROW(bytes.size() <= max_i2c_data_bytes); - boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; - - //load the data struct - usrp_e_i2c *data = reinterpret_cast(mem); - data->addr = addr; - data->len = bytes.size(); - std::copy(bytes.begin(), bytes.end(), data->data); - - //call the spi ioctl - this->ioctl(USRP_E_I2C_WRITE, data); - } - - byte_vector_t read_i2c(boost::uint8_t addr, size_t num_bytes){ - //allocate some memory for this transaction - UHD_ASSERT_THROW(num_bytes <= max_i2c_data_bytes); - boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; - - //load the data struct - usrp_e_i2c *data = reinterpret_cast(mem); - data->addr = addr; - data->len = num_bytes; - - //call the spi ioctl - this->ioctl(USRP_E_I2C_READ, data); - - //unload the data - byte_vector_t bytes(data->len); - UHD_ASSERT_THROW(bytes.size() == num_bytes); - std::copy(data->data, data->data+bytes.size(), bytes.begin()); - return bytes; - } - - /******************************************************************* - * SPI - ******************************************************************/ - boost::uint32_t transact_spi( - int which_slave, - const spi_config_t &config, - boost::uint32_t bits, - size_t num_bits, - bool readback - ){ - //load data struct - usrp_e_spi data; - data.readback = (readback)? UE_SPI_TXRX : UE_SPI_TXONLY; - data.slave = which_slave; - data.length = num_bits; - data.data = bits; - - //load the flags - data.flags = 0; - data.flags |= (config.miso_edge == spi_config_t::EDGE_RISE)? UE_SPI_LATCH_RISE : UE_SPI_LATCH_FALL; - data.flags |= (config.mosi_edge == spi_config_t::EDGE_RISE)? UE_SPI_PUSH_FALL : UE_SPI_PUSH_RISE; - - //call the spi ioctl - this->ioctl(USRP_E_SPI, &data); - - //unload the data - return data.data; - } - -private: - int _node_fd; - boost::mutex _ctrl_mutex; -}; - -/*********************************************************************** - * Public Make Function - **********************************************************************/ -usrp_e_iface::sptr usrp_e_iface::make(const std::string &node){ - return sptr(new usrp_e_iface_impl(node)); -} diff --git a/host/lib/usrp/usrp_e/usrp_e_iface.hpp b/host/lib/usrp/usrp_e/usrp_e_iface.hpp deleted file mode 100644 index 59aac43d9..000000000 --- a/host/lib/usrp/usrp_e/usrp_e_iface.hpp +++ /dev/null @@ -1,112 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#ifndef INCLUDED_USRP_E_IFACE_HPP -#define INCLUDED_USRP_E_IFACE_HPP - -#include -#include -#include -#include -#include - -//////////////////////////////////////////////////////////////////////// -// I2C addresses -//////////////////////////////////////////////////////////////////////// -#define I2C_DEV_EEPROM 0x50 // 24LC02[45]: 7-bits 1010xxx -#define I2C_ADDR_MBOARD (I2C_DEV_EEPROM | 0x0) -#define I2C_ADDR_TX_DB (I2C_DEV_EEPROM | 0x4) -#define I2C_ADDR_RX_DB (I2C_DEV_EEPROM | 0x5) -//////////////////////////////////////////////////////////////////////// - -/*! - * The usrp-e interface class: - * Provides a set of functions to implementation layer. - * Including spi, peek, poke, control... - */ -class usrp_e_iface : boost::noncopyable, public uhd::i2c_iface{ -public: - typedef boost::shared_ptr sptr; - - /*! - * Make a new usrp-e interface with the control transport. - * \param node the device node name - * \return a new usrp-e interface object - */ - static sptr make(const std::string &node); - - /*! - * Get the underlying file descriptor. - * \return the file descriptor - */ - virtual int get_file_descriptor(void) = 0; - - /*! - * Perform an ioctl call on the device node file descriptor. - * This will throw when the internal ioctl call fails. - * \param request the control word - * \param mem pointer to some memory - */ - virtual void ioctl(int request, void *mem) = 0; - - /*! - * Write a register (32 bits) - * \param addr the address - * \param data the 32bit data - */ - virtual void poke32(boost::uint32_t addr, boost::uint32_t data) = 0; - - /*! - * Read a register (32 bits) - * \param addr the address - * \return the 32bit data - */ - virtual boost::uint32_t peek32(boost::uint32_t addr) = 0; - - /*! - * Write a register (16 bits) - * \param addr the address - * \param data the 16bit data - */ - virtual void poke16(boost::uint32_t addr, boost::uint16_t data) = 0; - - /*! - * Read a register (16 bits) - * \param addr the address - * \return the 16bit data - */ - virtual boost::uint16_t peek16(boost::uint32_t addr) = 0; - - /*! - * Perform an spi transaction. - * \param which_slave the slave device number - * \param config spi config args - * \param data the bits to write - * \param num_bits how many bits in data - * \param readback true to readback a value - * \return spi data if readback set - */ - virtual boost::uint32_t transact_spi( - int which_slave, - const uhd::spi_config_t &config, - boost::uint32_t data, - size_t num_bits, - bool readback - ) = 0; -}; - -#endif /* INCLUDED_USRP_E_IFACE_HPP */ diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.cpp b/host/lib/usrp/usrp_e/usrp_e_impl.cpp deleted file mode 100644 index 70cc399fb..000000000 --- a/host/lib/usrp/usrp_e/usrp_e_impl.cpp +++ /dev/null @@ -1,201 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "usrp_e_impl.hpp" -#include "usrp_e_regs.hpp" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -using namespace uhd; -using namespace uhd::usrp; -namespace fs = boost::filesystem; - -/*********************************************************************** - * Helper Functions - **********************************************************************/ -static std::string abs_path(const std::string &file_path){ - return fs::system_complete(fs::path(file_path)).file_string(); -} - -/*********************************************************************** - * Discovery - **********************************************************************/ -static device_addrs_t usrp_e_find(const device_addr_t &hint){ - device_addrs_t usrp_e_addrs; - - //return an empty list of addresses when type is set to non-usrp-e - if (hint.has_key("type") and hint["type"] != "usrp-e") return usrp_e_addrs; - - //device node not provided, assume its 0 - if (not hint.has_key("node")){ - device_addr_t new_addr = hint; - new_addr["node"] = "/dev/usrp_e0"; - return usrp_e_find(new_addr); - } - - //use the given device node name - if (fs::exists(hint["node"])){ - device_addr_t new_addr; - new_addr["type"] = "usrp-e"; - new_addr["node"] = abs_path(hint["node"]); - usrp_e_addrs.push_back(new_addr); - } - - return usrp_e_addrs; -} - -/*********************************************************************** - * Make - **********************************************************************/ -static device::sptr usrp_e_make(const device_addr_t &device_addr){ - - //setup the main interface into fpga - std::string node = device_addr["node"]; - std::cout << boost::format("Opening USRP-E on %s") % node << std::endl; - usrp_e_iface::sptr iface = usrp_e_iface::make(node); - - //------------------------------------------------------------------ - //-- Handle the FPGA loading... - //-- The image can be confimed as already loaded when: - //-- 1) The compatibility number matches. - //-- 2) The hash in the hash-file matches. - //------------------------------------------------------------------ - static const char *hash_file_path = "/tmp/usrp_e100_hash"; - - //extract the fpga path for usrp-e - std::string usrp_e_fpga_image = find_image_path( - device_addr.has_key("fpga")? device_addr["fpga"] : "usrp_e100_fpga.bin" - ); - - //calculate a hash of the fpga file - size_t fpga_hash = 0; - { - std::ifstream file(usrp_e_fpga_image.c_str()); - if (not file.good()) throw std::runtime_error( - "cannot open fpga file for read: " + usrp_e_fpga_image - ); - do{ - boost::hash_combine(fpga_hash, file.get()); - } while (file.good()); - file.close(); - } - - //read the compatibility number - boost::uint16_t fpga_compat_num = iface->peek16(UE_REG_MISC_COMPAT); - - //read the hash in the hash-file - size_t loaded_hash = 0; - try{std::ifstream(hash_file_path) >> loaded_hash;}catch(...){} - - //if not loaded: load the fpga image and write the hash-file - if (fpga_compat_num != USRP_E_COMPAT_NUM or loaded_hash != fpga_hash){ - iface.reset(); - usrp_e_load_fpga(usrp_e_fpga_image); - std::cout << boost::format("re-Opening USRP-E on %s") % node << std::endl; - iface = usrp_e_iface::make(node); - try{std::ofstream(hash_file_path) << fpga_hash;}catch(...){} - } - - //check that the compatibility is correct - fpga_compat_num = iface->peek16(UE_REG_MISC_COMPAT); - if (fpga_compat_num != USRP_E_COMPAT_NUM){ - throw std::runtime_error(str(boost::format( - "Expected fpga compatibility number 0x%x, but got 0x%x:\n" - "The fpga build is not compatible with the host code build." - ) % USRP_E_COMPAT_NUM % fpga_compat_num)); - } - - return device::sptr(new usrp_e_impl(iface)); -} - -UHD_STATIC_BLOCK(register_usrp_e_device){ - device::register_device(&usrp_e_find, &usrp_e_make); -} - -/*********************************************************************** - * Structors - **********************************************************************/ -usrp_e_impl::usrp_e_impl(usrp_e_iface::sptr iface): _iface(iface){ - - //setup interfaces into hardware - _clock_ctrl = usrp_e_clock_ctrl::make(_iface); - _codec_ctrl = usrp_e_codec_ctrl::make(_iface); - - //initialize the mboard - mboard_init(); - - //initialize the dboards - dboard_init(); - - //initialize the dsps - rx_ddc_init(); - tx_duc_init(); - - //init the codec properties - codec_init(); - - //init the io send/recv - io_init(); - - //set default subdev specs - this->mboard_set(MBOARD_PROP_RX_SUBDEV_SPEC, subdev_spec_t()); - this->mboard_set(MBOARD_PROP_TX_SUBDEV_SPEC, subdev_spec_t()); -} - -usrp_e_impl::~usrp_e_impl(void){ - /* NOP */ -} - -/*********************************************************************** - * Device Get - **********************************************************************/ -void usrp_e_impl::get(const wax::obj &key_, wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - //handle the get request conditioned on the key - switch(key.as()){ - case DEVICE_PROP_NAME: - val = std::string("usrp-e device"); - return; - - case DEVICE_PROP_MBOARD: - UHD_ASSERT_THROW(key.name == ""); - val = _mboard_proxy->get_link(); - return; - - case DEVICE_PROP_MBOARD_NAMES: - val = prop_names_t(1, ""); //vector of size 1 with empty string - return; - - default: UHD_THROW_PROP_GET_ERROR(); - } -} - -/*********************************************************************** - * Device Set - **********************************************************************/ -void usrp_e_impl::set(const wax::obj &, const wax::obj &){ - UHD_THROW_PROP_SET_ERROR(); -} diff --git a/host/lib/usrp/usrp_e/usrp_e_impl.hpp b/host/lib/usrp/usrp_e/usrp_e_impl.hpp deleted file mode 100644 index b5f21810d..000000000 --- a/host/lib/usrp/usrp_e/usrp_e_impl.hpp +++ /dev/null @@ -1,164 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "usrp_e_iface.hpp" -#include "clock_ctrl.hpp" -#include "codec_ctrl.hpp" -#include -#include -#include -#include -#include -#include -#include -#include - -#ifndef INCLUDED_USRP_E_IMPL_HPP -#define INCLUDED_USRP_E_IMPL_HPP - -static const boost::uint16_t USRP_E_COMPAT_NUM = 0x02; - -//! load an fpga image from a bin file into the usrp-e fpga -extern void usrp_e_load_fpga(const std::string &bin_file); - -/*! - * Make a usrp-e dboard interface. - * \param iface the usrp-e interface object - * \param clock the clock control interface - * \param codec the codec control interface - * \return a sptr to a new dboard interface - */ -uhd::usrp::dboard_iface::sptr make_usrp_e_dboard_iface( - usrp_e_iface::sptr iface, - usrp_e_clock_ctrl::sptr clock, - usrp_e_codec_ctrl::sptr codec -); - -/*! - * Simple wax obj proxy class: - * Provides a wax obj interface for a set and a get function. - * This allows us to create nested properties structures - * while maintaining flattened code within the implementation. - */ -class wax_obj_proxy : public wax::obj{ -public: - typedef boost::function get_t; - typedef boost::function set_t; - typedef boost::shared_ptr sptr; - - static sptr make(const get_t &get, const set_t &set){ - return sptr(new wax_obj_proxy(get, set)); - } - -private: - get_t _get; set_t _set; - wax_obj_proxy(const get_t &get, const set_t &set): _get(get), _set(set){}; - void get(const wax::obj &key, wax::obj &val){return _get(key, val);} - void set(const wax::obj &key, const wax::obj &val){return _set(key, val);} -}; - -/*! - * USRP1E implementation guts: - * The implementation details are encapsulated here. - * Handles properties on the mboard, dboard, dsps... - */ -class usrp_e_impl : public uhd::device{ -public: - //structors - usrp_e_impl(usrp_e_iface::sptr); - ~usrp_e_impl(void); - - //the io interface - size_t send(const std::vector &, size_t, const uhd::tx_metadata_t &, const uhd::io_type_t &, send_mode_t, double); - size_t recv(const std::vector &, size_t, uhd::rx_metadata_t &, const uhd::io_type_t &, recv_mode_t, double); - bool recv_async_msg(uhd::async_metadata_t &, double); - size_t get_max_send_samps_per_packet(void) const; - size_t get_max_recv_samps_per_packet(void) const; - -private: - //interface to ioctls and file descriptor - usrp_e_iface::sptr _iface; - - //handle io stuff - UHD_PIMPL_DECL(io_impl) _io_impl; - uhd::otw_type_t _send_otw_type, _recv_otw_type; - void io_init(void); - void issue_stream_cmd(const uhd::stream_cmd_t &stream_cmd); - void handle_overrun(size_t); - - //configuration shadows - uhd::clock_config_t _clock_config; - //TODO otw type recv/send - - //ad9522 clock control - usrp_e_clock_ctrl::sptr _clock_ctrl; - - //ad9862 codec control - usrp_e_codec_ctrl::sptr _codec_ctrl; - - //device functions and settings - void get(const wax::obj &, wax::obj &); - void set(const wax::obj &, const wax::obj &); - - //mboard functions and settings - void mboard_init(void); - void mboard_get(const wax::obj &, wax::obj &); - void mboard_set(const wax::obj &, const wax::obj &); - wax_obj_proxy::sptr _mboard_proxy; - uhd::usrp::subdev_spec_t _rx_subdev_spec, _tx_subdev_spec; - - //xx dboard functions and settings - void dboard_init(void); - uhd::usrp::dboard_manager::sptr _dboard_manager; - uhd::usrp::dboard_iface::sptr _dboard_iface; - - //rx dboard functions and settings - uhd::usrp::dboard_eeprom_t _rx_db_eeprom; - void rx_dboard_get(const wax::obj &, wax::obj &); - void rx_dboard_set(const wax::obj &, const wax::obj &); - wax_obj_proxy::sptr _rx_dboard_proxy; - - //tx dboard functions and settings - uhd::usrp::dboard_eeprom_t _tx_db_eeprom; - void tx_dboard_get(const wax::obj &, wax::obj &); - void tx_dboard_set(const wax::obj &, const wax::obj &); - wax_obj_proxy::sptr _tx_dboard_proxy; - - //rx ddc functions and settings - void rx_ddc_init(void); - void rx_ddc_get(const wax::obj &, wax::obj &); - void rx_ddc_set(const wax::obj &, const wax::obj &); - double _ddc_freq; size_t _ddc_decim; - wax_obj_proxy::sptr _rx_ddc_proxy; - - //tx duc functions and settings - void tx_duc_init(void); - void tx_duc_get(const wax::obj &, wax::obj &); - void tx_duc_set(const wax::obj &, const wax::obj &); - double _duc_freq; size_t _duc_interp; - wax_obj_proxy::sptr _tx_duc_proxy; - - //codec functions and settings - void codec_init(void); - void rx_codec_get(const wax::obj &, wax::obj &); - void rx_codec_set(const wax::obj &, const wax::obj &); - void tx_codec_get(const wax::obj &, wax::obj &); - void tx_codec_set(const wax::obj &, const wax::obj &); - wax_obj_proxy::sptr _rx_codec_proxy, _tx_codec_proxy; -}; - -#endif /* INCLUDED_USRP_E_IMPL_HPP */ diff --git a/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp b/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp deleted file mode 100644 index 274bb043e..000000000 --- a/host/lib/usrp/usrp_e/usrp_e_mmap_zero_copy.cpp +++ /dev/null @@ -1,215 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "usrp_e_iface.hpp" -#include -#include -#include -#include //mmap -#include //getpagesize -#include //poll -#include -#include -#include - -using namespace uhd; -using namespace uhd::transport; - -static const bool fp_verbose = false; //fast-path verbose -static const bool sp_verbose = false; //slow-path verbose -static const size_t poll_breakout = 10; //how many poll timeouts constitute a full timeout - -/*********************************************************************** - * The zero copy interface implementation - **********************************************************************/ -class usrp_e_mmap_zero_copy_impl : public zero_copy_if, public boost::enable_shared_from_this { -public: - usrp_e_mmap_zero_copy_impl(usrp_e_iface::sptr iface): - _fd(iface->get_file_descriptor()), _recv_index(0), _send_index(0) - { - //get system sizes - iface->ioctl(USRP_E_GET_RB_INFO, &_rb_size); - size_t page_size = getpagesize(); - _frame_size = page_size/2; - - //calculate the memory size - _map_size = - (_rb_size.num_pages_rx_flags + _rb_size.num_pages_tx_flags) * page_size + - (_rb_size.num_rx_frames + _rb_size.num_tx_frames) * _frame_size; - - //print sizes summary - if (sp_verbose){ - std::cout << "page_size: " << page_size << std::endl; - std::cout << "frame_size: " << _frame_size << std::endl; - std::cout << "num_pages_rx_flags: " << _rb_size.num_pages_rx_flags << std::endl; - std::cout << "num_rx_frames: " << _rb_size.num_rx_frames << std::endl; - std::cout << "num_pages_tx_flags: " << _rb_size.num_pages_tx_flags << std::endl; - std::cout << "num_tx_frames: " << _rb_size.num_tx_frames << std::endl; - std::cout << "map_size: " << _map_size << std::endl; - } - - //call mmap to get the memory - _mapped_mem = ::mmap( - NULL, _map_size, PROT_READ | PROT_WRITE, MAP_SHARED, _fd, 0 - ); - UHD_ASSERT_THROW(_mapped_mem != MAP_FAILED); - - //calculate the memory offsets for info and buffers - size_t recv_info_off = 0; - size_t recv_buff_off = recv_info_off + (_rb_size.num_pages_rx_flags * page_size); - size_t send_info_off = recv_buff_off + (_rb_size.num_rx_frames * _frame_size); - size_t send_buff_off = send_info_off + (_rb_size.num_pages_tx_flags * page_size); - - //print offset summary - if (sp_verbose){ - std::cout << "recv_info_off: " << recv_info_off << std::endl; - std::cout << "recv_buff_off: " << recv_buff_off << std::endl; - std::cout << "send_info_off: " << send_info_off << std::endl; - std::cout << "send_buff_off: " << send_buff_off << std::endl; - } - - //set the internal pointers for info and buffers - typedef ring_buffer_info (*rbi_pta)[]; - char *rb_ptr = reinterpret_cast(_mapped_mem); - _recv_info = reinterpret_cast(rb_ptr + recv_info_off); - _recv_buff = rb_ptr + recv_buff_off; - _send_info = reinterpret_cast(rb_ptr + send_info_off); - _send_buff = rb_ptr + send_buff_off; - } - - ~usrp_e_mmap_zero_copy_impl(void){ - if (sp_verbose) std::cout << "cleanup: munmap" << std::endl; - ::munmap(_mapped_mem, _map_size); - } - - managed_recv_buffer::sptr get_recv_buff(double timeout){ - if (fp_verbose) std::cout << "get_recv_buff: " << _recv_index << std::endl; - - //grab pointers to the info and buffer - ring_buffer_info *info = (*_recv_info) + _recv_index; - void *mem = _recv_buff + _frame_size*_recv_index; - - //poll/wait for a ready frame - if (not (info->flags & RB_USER)){ - for (size_t i = 0; i < poll_breakout; i++){ - pollfd pfd; - pfd.fd = _fd; - pfd.events = POLLIN; - ssize_t poll_ret = ::poll(&pfd, 1, size_t(timeout*1e3/poll_breakout)); - if (fp_verbose) std::cout << " POLLIN: " << poll_ret << std::endl; - if (poll_ret > 0) goto found_user_frame; //good poll, continue on - } - return managed_recv_buffer::sptr(); //timed-out for real - } found_user_frame: - - //the process has claimed the frame - info->flags = RB_USER_PROCESS; - - //increment the index for the next call - if (++_recv_index == size_t(_rb_size.num_rx_frames)) _recv_index = 0; - - //return the managed buffer for this frame - if (fp_verbose) std::cout << " make_recv_buff: " << info->len << std::endl; - return managed_recv_buffer::make_safe( - boost::asio::const_buffer(mem, info->len), - boost::bind(&usrp_e_mmap_zero_copy_impl::release, shared_from_this(), info) - ); - } - - size_t get_num_recv_frames(void) const{ - return _rb_size.num_rx_frames; - } - - size_t get_recv_frame_size(void) const{ - return _frame_size; - } - - managed_send_buffer::sptr get_send_buff(double timeout){ - if (fp_verbose) std::cout << "get_send_buff: " << _send_index << std::endl; - - //grab pointers to the info and buffer - ring_buffer_info *info = (*_send_info) + _send_index; - void *mem = _send_buff + _frame_size*_send_index; - - //poll/wait for a ready frame - if (not (info->flags & RB_KERNEL)){ - pollfd pfd; - pfd.fd = _fd; - pfd.events = POLLOUT; - ssize_t poll_ret = ::poll(&pfd, 1, size_t(timeout*1e3)); - if (fp_verbose) std::cout << " POLLOUT: " << poll_ret << std::endl; - if (poll_ret <= 0) return managed_send_buffer::sptr(); - } - - //increment the index for the next call - if (++_send_index == size_t(_rb_size.num_tx_frames)) _send_index = 0; - - //return the managed buffer for this frame - if (fp_verbose) std::cout << " make_send_buff: " << _frame_size << std::endl; - return managed_send_buffer::make_safe( - boost::asio::mutable_buffer(mem, _frame_size), - boost::bind(&usrp_e_mmap_zero_copy_impl::commit, shared_from_this(), info, _1) - ); - } - - size_t get_num_send_frames(void) const{ - return _rb_size.num_tx_frames; - } - - size_t get_send_frame_size(void) const{ - return _frame_size; - } - -private: - - void release(ring_buffer_info *info){ - if (fp_verbose) std::cout << "recv buff: release" << std::endl; - info->flags = RB_KERNEL; - } - - void commit(ring_buffer_info *info, size_t len){ - if (fp_verbose) std::cout << "send buff: commit " << len << std::endl; - info->len = len; - info->flags = RB_USER; - if (::write(_fd, NULL, 0) < 0){ - std::cerr << UHD_THROW_SITE_INFO("write error") << std::endl; - } - } - - int _fd; - - //the mapped memory itself - void *_mapped_mem; - - //mapped memory sizes - usrp_e_ring_buffer_size_t _rb_size; - size_t _frame_size, _map_size; - - //pointers to sections in the mapped memory - ring_buffer_info (*_recv_info)[], (*_send_info)[]; - char *_recv_buff, *_send_buff; - - //indexes into sub-sections of mapped memory - size_t _recv_index, _send_index; -}; - -/*********************************************************************** - * The zero copy interface make function - **********************************************************************/ -zero_copy_if::sptr usrp_e_make_mmap_zero_copy(usrp_e_iface::sptr iface){ - return zero_copy_if::sptr(new usrp_e_mmap_zero_copy_impl(iface)); -} diff --git a/host/lib/usrp/usrp_e/usrp_e_regs.hpp b/host/lib/usrp/usrp_e/usrp_e_regs.hpp deleted file mode 100644 index 8bfb08b6f..000000000 --- a/host/lib/usrp/usrp_e/usrp_e_regs.hpp +++ /dev/null @@ -1,198 +0,0 @@ - - -//////////////////////////////////////////////////////////////// -// -// Memory map for embedded wishbone bus -// -//////////////////////////////////////////////////////////////// - -// All addresses are byte addresses. All accesses are word (16-bit) accesses. -// This means that address bit 0 is usually 0. -// There are 11 bits of address for the control. - -#ifndef __USRP_E_REGS_H -#define __USRP_E_REGS_H - -///////////////////////////////////////////////////// -// Slave pointers - -#define UE_REG_SLAVE(n) ((n)<<7) -#define UE_REG_SR_ADDR(n) ((UE_REG_SLAVE(5)) + (4*(n))) - -///////////////////////////////////////////////////// -// Slave 0 -- Misc Regs - -#define UE_REG_MISC_BASE UE_REG_SLAVE(0) - -#define UE_REG_MISC_LED UE_REG_MISC_BASE + 0 -#define UE_REG_MISC_SW UE_REG_MISC_BASE + 2 -#define UE_REG_MISC_CGEN_CTRL UE_REG_MISC_BASE + 4 -#define UE_REG_MISC_CGEN_ST UE_REG_MISC_BASE + 6 -#define UE_REG_MISC_TEST UE_REG_MISC_BASE + 8 -#define UE_REG_MISC_RX_LEN UE_REG_MISC_BASE + 10 -#define UE_REG_MISC_TX_LEN UE_REG_MISC_BASE + 12 -#define UE_REG_MISC_XFER_RATE UE_REG_MISC_BASE + 14 -#define UE_REG_MISC_COMPAT UE_REG_MISC_BASE + 16 - -///////////////////////////////////////////////////// -// Slave 1 -- UART -// CLKDIV is 16 bits, others are only 8 - -#define UE_REG_UART_BASE UE_REG_SLAVE(1) - -#define UE_REG_UART_CLKDIV UE_REG_UART_BASE + 0 -#define UE_REG_UART_TXLEVEL UE_REG_UART_BASE + 2 -#define UE_REG_UART_RXLEVEL UE_REG_UART_BASE + 4 -#define UE_REG_UART_TXCHAR UE_REG_UART_BASE + 6 -#define UE_REG_UART_RXCHAR UE_REG_UART_BASE + 8 - -///////////////////////////////////////////////////// -// Slave 2 -- SPI Core -// This should be accessed through the IOCTL -// Users should not touch directly - -#define UE_REG_SPI_BASE UE_REG_SLAVE(2) - -//spi slave constants -#define UE_SPI_SS_AD9522 (1 << 3) -#define UE_SPI_SS_AD9862 (1 << 2) -#define UE_SPI_SS_TX_DB (1 << 1) -#define UE_SPI_SS_RX_DB (1 << 0) - -//////////////////////////////////////////////// -// Slave 3 -- I2C Core -// This should be accessed through the IOCTL -// Users should not touch directly - -#define UE_REG_I2C_BASE UE_REG_SLAVE(3) - - -//////////////////////////////////////////////// -// Slave 4 -- GPIO - -#define UE_REG_GPIO_BASE UE_REG_SLAVE(4) - -#define UE_REG_GPIO_RX_IO UE_REG_GPIO_BASE + 0 -#define UE_REG_GPIO_TX_IO UE_REG_GPIO_BASE + 2 -#define UE_REG_GPIO_RX_DDR UE_REG_GPIO_BASE + 4 -#define UE_REG_GPIO_TX_DDR UE_REG_GPIO_BASE + 6 -#define UE_REG_GPIO_RX_SEL UE_REG_GPIO_BASE + 8 -#define UE_REG_GPIO_TX_SEL UE_REG_GPIO_BASE + 10 -#define UE_REG_GPIO_RX_DBG UE_REG_GPIO_BASE + 12 -#define UE_REG_GPIO_TX_DBG UE_REG_GPIO_BASE + 14 - -//possible bit values for sel when dbg is 0: -#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg -#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic - -//possible bit values for sel when dbg is 1: -#define GPIO_SEL_DEBUG_0 0 // if pin is an output, debug lines from FPGA fabric -#define GPIO_SEL_DEBUG_1 1 // if pin is an output, debug lines from FPGA fabric - - -//////////////////////////////////////////////////// -// Slave 5 -- Settings Bus -// -// Output-only, no readback, 32 registers total -// Each register must be written 32 bits at a time -// First the address xxx_xx00 and then xxx_xx10 - -#define UE_REG_SETTINGS_BASE UE_REG_SLAVE(5) - -/////////////////////////////////////////////////// -// Slave 6 -- ATR Controller -// 16 regs - -#define UE_REG_ATR_BASE UE_REG_SLAVE(6) - -#define UE_REG_ATR_IDLE_RXSIDE UE_REG_ATR_BASE + 0 -#define UE_REG_ATR_IDLE_TXSIDE UE_REG_ATR_BASE + 2 -#define UE_REG_ATR_INTX_RXSIDE UE_REG_ATR_BASE + 4 -#define UE_REG_ATR_INTX_TXSIDE UE_REG_ATR_BASE + 6 -#define UE_REG_ATR_INRX_RXSIDE UE_REG_ATR_BASE + 8 -#define UE_REG_ATR_INRX_TXSIDE UE_REG_ATR_BASE + 10 -#define UE_REG_ATR_FULL_RXSIDE UE_REG_ATR_BASE + 12 -#define UE_REG_ATR_FULL_TXSIDE UE_REG_ATR_BASE + 14 - -///////////////////////////////////////////////// -// DSP RX Regs -//////////////////////////////////////////////// -#define UE_REG_DSP_RX_FREQ UE_REG_SR_ADDR(0) -#define UE_REG_DSP_RX_SCALE_IQ UE_REG_SR_ADDR(1) // {scale_i,scale_q} -#define UE_REG_DSP_RX_DECIM_RATE UE_REG_SR_ADDR(2) // hb and decim rate -#define UE_REG_DSP_RX_DCOFFSET_I UE_REG_SR_ADDR(3) // Bit 31 high sets fixed offset mode, using lower 14 bits, // otherwise it is automatic -#define UE_REG_DSP_RX_DCOFFSET_Q UE_REG_SR_ADDR(4) // Bit 31 high sets fixed offset mode, using lower 14 bits -#define UE_REG_DSP_RX_MUX UE_REG_SR_ADDR(5) - -/////////////////////////////////////////////////// -// VITA RX CTRL regs -/////////////////////////////////////////////////// -// The following 3 are logically a single command register. -// They are clocked into the underlying fifo when time_ticks is written. -#define UE_REG_CTRL_RX_STREAM_CMD UE_REG_SR_ADDR(8) // {now, chain, num_samples(30) -#define UE_REG_CTRL_RX_TIME_SECS UE_REG_SR_ADDR(9) -#define UE_REG_CTRL_RX_TIME_TICKS UE_REG_SR_ADDR(10) -#define UE_REG_CTRL_RX_CLEAR_OVERRUN UE_REG_SR_ADDR(11) // write anything to clear overrun -#define UE_REG_CTRL_RX_VRT_HEADER UE_REG_SR_ADDR(12) // word 0 of packet. FPGA fills in packet counter -#define UE_REG_CTRL_RX_VRT_STREAM_ID UE_REG_SR_ADDR(13) // word 1 of packet. -#define UE_REG_CTRL_RX_VRT_TRAILER UE_REG_SR_ADDR(14) -#define UE_REG_CTRL_RX_NSAMPS_PER_PKT UE_REG_SR_ADDR(15) -#define UE_REG_CTRL_RX_NCHANNELS UE_REG_SR_ADDR(16) // 1 in basic case, up to 4 for vector sources - -///////////////////////////////////////////////// -// DSP TX Regs -//////////////////////////////////////////////// -#define UE_REG_DSP_TX_FREQ UE_REG_SR_ADDR(17) -#define UE_REG_DSP_TX_SCALE_IQ UE_REG_SR_ADDR(18) // {scale_i,scale_q} -#define UE_REG_DSP_TX_INTERP_RATE UE_REG_SR_ADDR(19) -#define UE_REG_DSP_TX_UNUSED UE_REG_SR_ADDR(20) -#define UE_REG_DSP_TX_MUX UE_REG_SR_ADDR(21) - -///////////////////////////////////////////////// -// VITA TX CTRL regs -//////////////////////////////////////////////// -#define UE_REG_CTRL_TX_NCHANNELS UE_REG_SR_ADDR(24) -#define UE_REG_CTRL_TX_CLEAR_UNDERRUN UE_REG_SR_ADDR(25) -#define UE_REG_CTRL_TX_REPORT_SID UE_REG_SR_ADDR(26) -#define UE_REG_CTRL_TX_POLICY UE_REG_SR_ADDR(27) - -#define UE_FLAG_CTRL_TX_POLICY_WAIT (0x1 << 0) -#define UE_FLAG_CTRL_TX_POLICY_NEXT_PACKET (0x1 << 1) -#define UE_FLAG_CTRL_TX_POLICY_NEXT_BURST (0x1 << 2) - -///////////////////////////////////////////////// -// VITA49 64 bit time (write only) -//////////////////////////////////////////////// - /*! - * \brief Time 64 flags - * - * 
-   *
-   *    3                   2                   1
-   *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
-   * +-----------------------------------------------------------+-+-+
-   * |                                                           |S|P|
-   * +-----------------------------------------------------------+-+-+
-   *
-   * P - PPS edge selection (0=negedge, 1=posedge, default=0)
-   * S - Source (0=sma, 1=mimo, 0=default)
-   *
-   *
- */ -#define UE_REG_TIME64_SECS UE_REG_SR_ADDR(28) // value to set absolute secs to on next PPS -#define UE_REG_TIME64_TICKS UE_REG_SR_ADDR(29) // value to set absolute ticks to on next PPS -#define UE_REG_TIME64_FLAGS UE_REG_SR_ADDR(30) // flags - see chart above -#define UE_REG_TIME64_IMM UE_REG_SR_ADDR(31) // set immediate (0=latch on next pps, 1=latch immediate, default=0) -#define UE_REG_TIME64_TPS UE_REG_SR_ADDR(31) // clock ticks per second (counter rollover) - -//pps flags (see above) -#define UE_FLAG_TIME64_PPS_NEGEDGE (0 << 0) -#define UE_FLAG_TIME64_PPS_POSEDGE (1 << 0) -#define UE_FLAG_TIME64_PPS_SMA (0 << 1) -#define UE_FLAG_TIME64_PPS_MIMO (1 << 1) - -#define UE_FLAG_TIME64_LATCH_NOW 1 -#define UE_FLAG_TIME64_LATCH_NEXT_PPS 0 - -#endif - diff --git a/host/lib/usrp/usrp_e100/CMakeLists.txt b/host/lib/usrp/usrp_e100/CMakeLists.txt new file mode 100644 index 000000000..17ef53152 --- /dev/null +++ b/host/lib/usrp/usrp_e100/CMakeLists.txt @@ -0,0 +1,64 @@ +# +# Copyright 2010 Ettus Research LLC +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + +#This file will be included by cmake, use absolute paths! + +######################################################################## +# Conditionally configure the USRP-E100 support +######################################################################## +MESSAGE(STATUS "Configuring USRP-E100 support...") + +INCLUDE(CheckIncludeFileCXX) +CHECK_INCLUDE_FILE_CXX(linux/usrp_e.h HAVE_LINUX_USRP_E_H) + +SET(ENABLE_USRP_E TRUE) + +IF(DEFINED ENABLE_USRP_E100) + IF(ENABLE_USRP_E100) + MESSAGE(STATUS "USRP-E100 support enabled by configure flag") + ELSE(ENABLE_USRP_E100) + MESSAGE(STATUS "USRP-E100 support disabled by configure flag") + ENDIF(ENABLE_USRP_E100) +ELSE(DEFINED ENABLE_USRP_E100) #not defined: automatic enabling of component + SET(ENABLE_USRP_E100 ${HAVE_LINUX_USRP_E_H}) +ENDIF(DEFINED ENABLE_USRP_E100) +SET(ENABLE_USRP_E100 ${ENABLE_USRP_E100} CACHE BOOL "enable USRP-E100 support") + +IF(ENABLE_USRP_E100) + MESSAGE(STATUS " Building USRP-E100 support.") + LIBUHD_APPEND_SOURCES( + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/clock_ctrl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/clock_ctrl.hpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/codec_ctrl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/codec_ctrl.hpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/codec_impl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/dboard_impl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/dboard_iface.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/dsp_impl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/fpga-downloader.cc + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/io_impl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/mboard_impl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e_impl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e_impl.hpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e_iface.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e_iface.hpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e_mmap_zero_copy.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e_regs.hpp + ) +ELSE(ENABLE_USRP_E100) + MESSAGE(STATUS " Skipping USRP-E100 support.") +ENDIF(ENABLE_USRP_E100) diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp new file mode 100644 index 000000000..9d4625305 --- /dev/null +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -0,0 +1,237 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "clock_ctrl.hpp" +#include "ad9522_regs.hpp" +#include +#include +#include "usrp_e_regs.hpp" //spi slave constants +#include +#include +#include +#include + +using namespace uhd; + +template static void set_clock_divider( + size_t divider, div_type &low, div_type &high, bypass_type &bypass +){ + high = divider/2 - 1; + low = divider - high - 2; + bypass = (divider == 1)? 1 : 0; +} + +/*********************************************************************** + * Constants + **********************************************************************/ +static const bool enable_test_clock = false; +static const size_t ref_clock_doubler = 2; //enabled below +static const double ref_clock_rate = 10e6 * ref_clock_doubler; + +static const size_t r_counter = 1; +static const size_t a_counter = 0; +static const size_t b_counter = 20 / ref_clock_doubler; +static const size_t prescaler = 8; //set below with enum, set to 8 when input is under 2400 MHz +static const size_t vco_divider = 5; //set below with enum + +static const size_t n_counter = prescaler * b_counter + a_counter; +static const size_t vco_clock_rate = ref_clock_rate/r_counter * n_counter; //between 1400 and 1800 MHz +static const double master_clock_rate = vco_clock_rate/vco_divider; + +static const size_t fpga_clock_divider = size_t(master_clock_rate/64e6); +static const size_t codec_clock_divider = size_t(master_clock_rate/64e6); + +/*********************************************************************** + * Clock Control Implementation + **********************************************************************/ +class usrp_e_clock_ctrl_impl : public usrp_e_clock_ctrl{ +public: + usrp_e_clock_ctrl_impl(usrp_e_iface::sptr iface){ + _iface = iface; + + //init the clock gen registers + //Note: out0 should already be clocking the FPGA or this isnt going to work + _ad9522_regs.sdo_active = ad9522_regs_t::SDO_ACTIVE_SDO_SDIO; + _ad9522_regs.enable_clock_doubler = 1; //enable ref clock doubler + _ad9522_regs.enb_stat_eeprom_at_stat_pin = 0; //use status pin + _ad9522_regs.status_pin_control = 0x1; //n divider + _ad9522_regs.ld_pin_control = 0x00; //dld + _ad9522_regs.refmon_pin_control = 0x12; //show ref2 + + _ad9522_regs.enable_ref2 = 1; + _ad9522_regs.enable_ref1 = 0; + _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF2; + + _ad9522_regs.set_r_counter(r_counter); + _ad9522_regs.a_counter = a_counter; + _ad9522_regs.set_b_counter(b_counter); + _ad9522_regs.prescaler_p = ad9522_regs_t::PRESCALER_P_DIV8_9; + + _ad9522_regs.pll_power_down = ad9522_regs_t::PLL_POWER_DOWN_NORMAL; + _ad9522_regs.cp_current = ad9522_regs_t::CP_CURRENT_1_2MA; + + _ad9522_regs.vco_calibration_now = 1; //calibrate it! + _ad9522_regs.vco_divider = ad9522_regs_t::VCO_DIVIDER_DIV5; + _ad9522_regs.select_vco_or_clock = ad9522_regs_t::SELECT_VCO_OR_CLOCK_VCO; + + //setup fpga master clock + _ad9522_regs.out0_format = ad9522_regs_t::OUT0_FORMAT_LVDS; + set_clock_divider(fpga_clock_divider, + _ad9522_regs.divider0_low_cycles, + _ad9522_regs.divider0_high_cycles, + _ad9522_regs.divider0_bypass + ); + + //setup codec clock + _ad9522_regs.out3_format = ad9522_regs_t::OUT3_FORMAT_LVDS; + set_clock_divider(codec_clock_divider, + _ad9522_regs.divider1_low_cycles, + _ad9522_regs.divider1_high_cycles, + _ad9522_regs.divider1_bypass + ); + + //setup test clock (same divider as codec clock) + _ad9522_regs.out4_format = ad9522_regs_t::OUT4_FORMAT_CMOS; + _ad9522_regs.out4_cmos_configuration = (enable_test_clock)? + ad9522_regs_t::OUT4_CMOS_CONFIGURATION_A_ON : + ad9522_regs_t::OUT4_CMOS_CONFIGURATION_OFF; + + //setup a list of register ranges to write + typedef std::pair range_t; + static const std::vector ranges = boost::assign::list_of + (range_t(0x000, 0x000)) (range_t(0x010, 0x01F)) + (range_t(0x0F0, 0x0FD)) (range_t(0x190, 0x19B)) + (range_t(0x1E0, 0x1E1)) (range_t(0x230, 0x230)) + ; + + //write initial register values and latch/update + BOOST_FOREACH(const range_t &range, ranges){ + for(boost::uint16_t addr = range.first; addr <= range.second; addr++){ + this->send_reg(addr); + } + } + this->latch_regs(); + //test read: + //boost::uint32_t reg = _ad9522_regs.get_read_reg(0x01b); + //boost::uint32_t result = _iface->transact_spi( + // UE_SPI_SS_AD9522, + // spi_config_t::EDGE_RISE, + // reg, 24, true /*no*/ + //); + //std::cout << "result " << std::hex << result << std::endl; + this->enable_rx_dboard_clock(false); + this->enable_tx_dboard_clock(false); + } + + ~usrp_e_clock_ctrl_impl(void){ + this->enable_rx_dboard_clock(false); + this->enable_tx_dboard_clock(false); + } + + double get_fpga_clock_rate(void){ + return master_clock_rate/fpga_clock_divider; + } + + /*********************************************************************** + * RX Dboard Clock Control (output 9, divider 3) + **********************************************************************/ + void enable_rx_dboard_clock(bool enb){ + _ad9522_regs.out9_format = ad9522_regs_t::OUT9_FORMAT_CMOS; + _ad9522_regs.out9_cmos_configuration = (enb)? + ad9522_regs_t::OUT9_CMOS_CONFIGURATION_B_ON : + ad9522_regs_t::OUT9_CMOS_CONFIGURATION_OFF; + this->send_reg(0x0F9); + this->latch_regs(); + } + + std::vector get_rx_dboard_clock_rates(void){ + std::vector rates; + for(size_t div = 1; div <= 16+16; div++) + rates.push_back(master_clock_rate/div); + return rates; + } + + void set_rx_dboard_clock_rate(double rate){ + assert_has(get_rx_dboard_clock_rates(), rate, "rx dboard clock rate"); + size_t divider = size_t(master_clock_rate/rate); + //set the divider registers + set_clock_divider(divider, + _ad9522_regs.divider3_low_cycles, + _ad9522_regs.divider3_high_cycles, + _ad9522_regs.divider3_bypass + ); + this->send_reg(0x199); + this->send_reg(0x19a); + this->latch_regs(); + } + + /*********************************************************************** + * TX Dboard Clock Control (output 6, divider 2) + **********************************************************************/ + void enable_tx_dboard_clock(bool enb){ + _ad9522_regs.out6_format = ad9522_regs_t::OUT6_FORMAT_CMOS; + _ad9522_regs.out6_cmos_configuration = (enb)? + ad9522_regs_t::OUT6_CMOS_CONFIGURATION_B_ON : + ad9522_regs_t::OUT6_CMOS_CONFIGURATION_OFF; + this->send_reg(0x0F6); + this->latch_regs(); + } + + std::vector get_tx_dboard_clock_rates(void){ + return get_rx_dboard_clock_rates(); //same master clock, same dividers... + } + + void set_tx_dboard_clock_rate(double rate){ + assert_has(get_tx_dboard_clock_rates(), rate, "tx dboard clock rate"); + size_t divider = size_t(master_clock_rate/rate); + //set the divider registers + set_clock_divider(divider, + _ad9522_regs.divider2_low_cycles, + _ad9522_regs.divider2_high_cycles, + _ad9522_regs.divider2_bypass + ); + this->send_reg(0x196); + this->send_reg(0x197); + this->latch_regs(); + } + +private: + usrp_e_iface::sptr _iface; + ad9522_regs_t _ad9522_regs; + + void latch_regs(void){ + _ad9522_regs.io_update = 1; + this->send_reg(0x232); + } + + void send_reg(boost::uint16_t addr){ + boost::uint32_t reg = _ad9522_regs.get_write_reg(addr); + //std::cout << "clock control write reg: " << std::hex << reg << std::endl; + _iface->transact_spi( + UE_SPI_SS_AD9522, + spi_config_t::EDGE_RISE, + reg, 24, false /*no rb*/ + ); + } +}; + +/*********************************************************************** + * Clock Control Make + **********************************************************************/ +usrp_e_clock_ctrl::sptr usrp_e_clock_ctrl::make(usrp_e_iface::sptr iface){ + return sptr(new usrp_e_clock_ctrl_impl(iface)); +} diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.hpp b/host/lib/usrp/usrp_e100/clock_ctrl.hpp new file mode 100644 index 000000000..3b5103ed1 --- /dev/null +++ b/host/lib/usrp/usrp_e100/clock_ctrl.hpp @@ -0,0 +1,88 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_USRP_E_CLOCK_CTRL_HPP +#define INCLUDED_USRP_E_CLOCK_CTRL_HPP + +#include "usrp_e_iface.hpp" +#include +#include +#include + +/*! + * The usrp-e clock control: + * - Setup system clocks. + * - Disable/enable clock lines. + */ +class usrp_e_clock_ctrl : boost::noncopyable{ +public: + typedef boost::shared_ptr sptr; + + /*! + * Make a new clock control object. + * \param iface the usrp_e iface object + * \return the clock control object + */ + static sptr make(usrp_e_iface::sptr iface); + + /*! + * Get the rate of the fpga clock line. + * \return the fpga clock rate in Hz + */ + virtual double get_fpga_clock_rate(void) = 0; + + /*! + * Get the possible rates of the rx dboard clock. + * \return a vector of clock rates in Hz + */ + virtual std::vector get_rx_dboard_clock_rates(void) = 0; + + /*! + * Get the possible rates of the tx dboard clock. + * \return a vector of clock rates in Hz + */ + virtual std::vector get_tx_dboard_clock_rates(void) = 0; + + /*! + * Set the rx dboard clock rate to a possible rate. + * \param rate the new clock rate in Hz + * \throw exception when rate cannot be achieved + */ + virtual void set_rx_dboard_clock_rate(double rate) = 0; + + /*! + * Set the tx dboard clock rate to a possible rate. + * \param rate the new clock rate in Hz + * \throw exception when rate cannot be achieved + */ + virtual void set_tx_dboard_clock_rate(double rate) = 0; + + /*! + * Enable/disable the rx dboard clock. + * \param enb true to enable + */ + virtual void enable_rx_dboard_clock(bool enb) = 0; + + /*! + * Enable/disable the tx dboard clock. + * \param enb true to enable + */ + virtual void enable_tx_dboard_clock(bool enb) = 0; + +}; + +#endif /* INCLUDED_USRP_E_CLOCK_CTRL_HPP */ diff --git a/host/lib/usrp/usrp_e100/codec_ctrl.cpp b/host/lib/usrp/usrp_e100/codec_ctrl.cpp new file mode 100644 index 000000000..a728d7e46 --- /dev/null +++ b/host/lib/usrp/usrp_e100/codec_ctrl.cpp @@ -0,0 +1,296 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "codec_ctrl.hpp" +#include "ad9862_regs.hpp" +#include +#include +#include +#include +#include +#include +#include "usrp_e_regs.hpp" //spi slave constants +#include +#include + +using namespace uhd; + +static const bool codec_debug = false; + +const gain_range_t usrp_e_codec_ctrl::tx_pga_gain_range(-20, 0, float(0.1)); +const gain_range_t usrp_e_codec_ctrl::rx_pga_gain_range(0, 20, 1); + +/*********************************************************************** + * Codec Control Implementation + **********************************************************************/ +class usrp_e_codec_ctrl_impl : public usrp_e_codec_ctrl{ +public: + //structors + usrp_e_codec_ctrl_impl(usrp_e_iface::sptr iface); + ~usrp_e_codec_ctrl_impl(void); + + //aux adc and dac control + float read_aux_adc(aux_adc_t which); + void write_aux_dac(aux_dac_t which, float volts); + + //pga gain control + void set_tx_pga_gain(float); + float get_tx_pga_gain(void); + void set_rx_pga_gain(float, char); + float get_rx_pga_gain(char); + +private: + usrp_e_iface::sptr _iface; + ad9862_regs_t _ad9862_regs; + aux_adc_t _last_aux_adc_a, _last_aux_adc_b; + void send_reg(boost::uint8_t addr); + void recv_reg(boost::uint8_t addr); +}; + +/*********************************************************************** + * Codec Control Structors + **********************************************************************/ +usrp_e_codec_ctrl_impl::usrp_e_codec_ctrl_impl(usrp_e_iface::sptr iface){ + _iface = iface; + + //soft reset + _ad9862_regs.soft_reset = 1; + this->send_reg(0); + + //initialize the codec register settings + _ad9862_regs.sdio_bidir = ad9862_regs_t::SDIO_BIDIR_SDIO_SDO; + _ad9862_regs.lsb_first = ad9862_regs_t::LSB_FIRST_MSB; + _ad9862_regs.soft_reset = 0; + + //setup rx side of codec + _ad9862_regs.byp_buffer_a = 1; + _ad9862_regs.byp_buffer_b = 1; + _ad9862_regs.buffer_a_pd = 1; + _ad9862_regs.buffer_b_pd = 1; + _ad9862_regs.rx_pga_a = 0;//0x1f; //TODO bring under api control + _ad9862_regs.rx_pga_b = 0;//0x1f; //TODO bring under api control + _ad9862_regs.rx_twos_comp = 1; + _ad9862_regs.rx_hilbert = ad9862_regs_t::RX_HILBERT_DIS; + + //setup tx side of codec + _ad9862_regs.two_data_paths = ad9862_regs_t::TWO_DATA_PATHS_BOTH; + _ad9862_regs.interleaved = ad9862_regs_t::INTERLEAVED_INTERLEAVED; + _ad9862_regs.tx_retime = ad9862_regs_t::TX_RETIME_CLKOUT2; + _ad9862_regs.tx_pga_gain = 199; //TODO bring under api control + _ad9862_regs.tx_hilbert = ad9862_regs_t::TX_HILBERT_DIS; + _ad9862_regs.interp = ad9862_regs_t::INTERP_2; + _ad9862_regs.tx_twos_comp = 1; + _ad9862_regs.fine_mode = ad9862_regs_t::FINE_MODE_BYPASS; + _ad9862_regs.coarse_mod = ad9862_regs_t::COARSE_MOD_BYPASS; + _ad9862_regs.dac_a_coarse_gain = 0x3; + _ad9862_regs.dac_b_coarse_gain = 0x3; + _ad9862_regs.edges = ad9862_regs_t::EDGES_NORMAL; + + //setup the dll + _ad9862_regs.input_clk_ctrl = ad9862_regs_t::INPUT_CLK_CTRL_EXTERNAL; + _ad9862_regs.dll_mult = ad9862_regs_t::DLL_MULT_2; + _ad9862_regs.dll_mode = ad9862_regs_t::DLL_MODE_FAST; + + //write the register settings to the codec + for (uint8_t addr = 0; addr <= 25; addr++){ + this->send_reg(addr); + } + + //aux adc clock + _ad9862_regs.clk_4 = ad9862_regs_t::CLK_4_1_4; + this->send_reg(34); +} + +usrp_e_codec_ctrl_impl::~usrp_e_codec_ctrl_impl(void){ + //set aux dacs to zero + this->write_aux_dac(AUX_DAC_A, 0); + this->write_aux_dac(AUX_DAC_B, 0); + this->write_aux_dac(AUX_DAC_C, 0); + this->write_aux_dac(AUX_DAC_D, 0); + + //power down + _ad9862_regs.all_rx_pd = 1; + this->send_reg(1); + _ad9862_regs.tx_digital_pd = 1; + _ad9862_regs.tx_analog_pd = ad9862_regs_t::TX_ANALOG_PD_BOTH; + this->send_reg(8); +} + +/*********************************************************************** + * Codec Control Gain Control Methods + **********************************************************************/ +static const int mtpgw = 255; //maximum tx pga gain word + +void usrp_e_codec_ctrl_impl::set_tx_pga_gain(float gain){ + int gain_word = int(mtpgw*(gain - tx_pga_gain_range.min)/(tx_pga_gain_range.max - tx_pga_gain_range.min)); + _ad9862_regs.tx_pga_gain = std::clip(gain_word, 0, mtpgw); + this->send_reg(16); +} + +float usrp_e_codec_ctrl_impl::get_tx_pga_gain(void){ + return (_ad9862_regs.tx_pga_gain*(tx_pga_gain_range.max - tx_pga_gain_range.min)/mtpgw) + tx_pga_gain_range.min; +} + +static const int mrpgw = 0x14; //maximum rx pga gain word + +void usrp_e_codec_ctrl_impl::set_rx_pga_gain(float gain, char which){ + int gain_word = int(mrpgw*(gain - rx_pga_gain_range.min)/(rx_pga_gain_range.max - rx_pga_gain_range.min)); + gain_word = std::clip(gain_word, 0, mrpgw); + switch(which){ + case 'A': + _ad9862_regs.rx_pga_a = gain_word; + this->send_reg(2); + return; + case 'B': + _ad9862_regs.rx_pga_b = gain_word; + this->send_reg(3); + return; + default: UHD_THROW_INVALID_CODE_PATH(); + } +} + +float usrp_e_codec_ctrl_impl::get_rx_pga_gain(char which){ + int gain_word; + switch(which){ + case 'A': gain_word = _ad9862_regs.rx_pga_a; break; + case 'B': gain_word = _ad9862_regs.rx_pga_b; break; + default: UHD_THROW_INVALID_CODE_PATH(); + } + return (gain_word*(rx_pga_gain_range.max - rx_pga_gain_range.min)/mrpgw) + rx_pga_gain_range.min; +} + +/*********************************************************************** + * Codec Control AUX ADC Methods + **********************************************************************/ +static float aux_adc_to_volts(boost::uint8_t high, boost::uint8_t low){ + return float((boost::uint16_t(high) << 2) | low)*3.3/0x3ff; +} + +float usrp_e_codec_ctrl_impl::read_aux_adc(aux_adc_t which){ + //check to see if the switch needs to be set + bool write_switch = false; + switch(which){ + + case AUX_ADC_A1: + case AUX_ADC_A2: + if (which != _last_aux_adc_a){ + _ad9862_regs.select_a = (which == AUX_ADC_A1)? + ad9862_regs_t::SELECT_A_AUX_ADC1: ad9862_regs_t::SELECT_A_AUX_ADC2; + _last_aux_adc_a = which; + write_switch = true; + } + break; + + case AUX_ADC_B1: + case AUX_ADC_B2: + if (which != _last_aux_adc_b){ + _ad9862_regs.select_b = (which == AUX_ADC_B1)? + ad9862_regs_t::SELECT_B_AUX_ADC1: ad9862_regs_t::SELECT_B_AUX_ADC2; + _last_aux_adc_b = which; + write_switch = true; + } + break; + + } + + //write the switch if it changed + if(write_switch) this->send_reg(34); + + //map aux adcs to register values to read + static const uhd::dict aux_dac_to_addr = boost::assign::map_list_of + (AUX_ADC_A2, 26) (AUX_ADC_A1, 28) + (AUX_ADC_B2, 30) (AUX_ADC_B1, 32) + ; + + //read the value + this->recv_reg(aux_dac_to_addr[which]+0); + this->recv_reg(aux_dac_to_addr[which]+1); + + //return the value scaled to volts + switch(which){ + case AUX_ADC_A1: return aux_adc_to_volts(_ad9862_regs.aux_adc_a1_9_2, _ad9862_regs.aux_adc_a1_1_0); + case AUX_ADC_A2: return aux_adc_to_volts(_ad9862_regs.aux_adc_a2_9_2, _ad9862_regs.aux_adc_a2_1_0); + case AUX_ADC_B1: return aux_adc_to_volts(_ad9862_regs.aux_adc_b1_9_2, _ad9862_regs.aux_adc_b1_1_0); + case AUX_ADC_B2: return aux_adc_to_volts(_ad9862_regs.aux_adc_b2_9_2, _ad9862_regs.aux_adc_b2_1_0); + } + UHD_ASSERT_THROW(false); +} + +/*********************************************************************** + * Codec Control AUX DAC Methods + **********************************************************************/ +void usrp_e_codec_ctrl_impl::write_aux_dac(aux_dac_t which, float volts){ + //special case for aux dac d (aka sigma delta word) + if (which == AUX_DAC_D){ + boost::uint16_t dac_word = std::clip(boost::math::iround(volts*0xfff/3.3), 0, 0xfff); + _ad9862_regs.sig_delt_11_4 = boost::uint8_t(dac_word >> 4); + _ad9862_regs.sig_delt_3_0 = boost::uint8_t(dac_word & 0xf); + this->send_reg(42); + this->send_reg(43); + return; + } + + //calculate the dac word for aux dac a, b, c + boost::uint8_t dac_word = std::clip(boost::math::iround(volts*0xff/3.3), 0, 0xff); + + //setup a lookup table for the aux dac params (reg ref, reg addr) + typedef boost::tuple dac_params_t; + uhd::dict aux_dac_to_params = boost::assign::map_list_of + (AUX_DAC_A, dac_params_t(&_ad9862_regs.aux_dac_a, 36)) + (AUX_DAC_B, dac_params_t(&_ad9862_regs.aux_dac_b, 37)) + (AUX_DAC_C, dac_params_t(&_ad9862_regs.aux_dac_c, 38)) + ; + + //set the aux dac register + UHD_ASSERT_THROW(aux_dac_to_params.has_key(which)); + boost::uint8_t *reg_ref, reg_addr; + boost::tie(reg_ref, reg_addr) = aux_dac_to_params[which]; + *reg_ref = dac_word; + this->send_reg(reg_addr); +} + +/*********************************************************************** + * Codec Control SPI Methods + **********************************************************************/ +void usrp_e_codec_ctrl_impl::send_reg(boost::uint8_t addr){ + boost::uint32_t reg = _ad9862_regs.get_write_reg(addr); + if (codec_debug) std::cout << "codec control write reg: " << std::hex << reg << std::endl; + _iface->transact_spi( + UE_SPI_SS_AD9862, + spi_config_t::EDGE_RISE, + reg, 16, false /*no rb*/ + ); +} + +void usrp_e_codec_ctrl_impl::recv_reg(boost::uint8_t addr){ + boost::uint32_t reg = _ad9862_regs.get_read_reg(addr); + if (codec_debug) std::cout << "codec control read reg: " << std::hex << reg << std::endl; + boost::uint32_t ret = _iface->transact_spi( + UE_SPI_SS_AD9862, + spi_config_t::EDGE_RISE, + reg, 16, true /*rb*/ + ); + if (codec_debug) std::cout << "codec control read ret: " << std::hex << ret << std::endl; + _ad9862_regs.set_reg(addr, boost::uint16_t(ret)); +} + +/*********************************************************************** + * Codec Control Make + **********************************************************************/ +usrp_e_codec_ctrl::sptr usrp_e_codec_ctrl::make(usrp_e_iface::sptr iface){ + return sptr(new usrp_e_codec_ctrl_impl(iface)); +} diff --git a/host/lib/usrp/usrp_e100/codec_ctrl.hpp b/host/lib/usrp/usrp_e100/codec_ctrl.hpp new file mode 100644 index 000000000..87b6ff951 --- /dev/null +++ b/host/lib/usrp/usrp_e100/codec_ctrl.hpp @@ -0,0 +1,90 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_USRP_E_CODEC_CTRL_HPP +#define INCLUDED_USRP_E_CODEC_CTRL_HPP + +#include "usrp_e_iface.hpp" +#include +#include +#include + +/*! + * The usrp-e codec control: + * - Init/power down codec. + * - Read aux adc, write aux dac. + */ +class usrp_e_codec_ctrl : boost::noncopyable{ +public: + typedef boost::shared_ptr sptr; + + static const uhd::gain_range_t tx_pga_gain_range; + static const uhd::gain_range_t rx_pga_gain_range; + + /*! + * Make a new codec control object. + * \param iface the usrp_e iface object + * \return the codec control object + */ + static sptr make(usrp_e_iface::sptr iface); + + //! aux adc identifier constants + enum aux_adc_t{ + AUX_ADC_A2 = 0xA2, + AUX_ADC_A1 = 0xA1, + AUX_ADC_B2 = 0xB2, + AUX_ADC_B1 = 0xB1 + }; + + /*! + * Read an auxiliary adc: + * The internals remember which aux adc was read last. + * Therefore, the aux adc switch is only changed as needed. + * \param which which of the 4 adcs + * \return a value in volts + */ + virtual float read_aux_adc(aux_adc_t which) = 0; + + //! aux dac identifier constants + enum aux_dac_t{ + AUX_DAC_A = 0xA, + AUX_DAC_B = 0xB, + AUX_DAC_C = 0xC, + AUX_DAC_D = 0xD //really the sigma delta output + }; + + /*! + * Write an auxiliary dac. + * \param which which of the 4 dacs + * \param volts the level in in volts + */ + virtual void write_aux_dac(aux_dac_t which, float volts) = 0; + + //! Set the TX PGA gain + virtual void set_tx_pga_gain(float gain) = 0; + + //! Get the TX PGA gain + virtual float get_tx_pga_gain(void) = 0; + + //! Set the RX PGA gain ('A' or 'B') + virtual void set_rx_pga_gain(float gain, char which) = 0; + + //! Get the RX PGA gain ('A' or 'B') + virtual float get_rx_pga_gain(char which) = 0; +}; + +#endif /* INCLUDED_USRP_E_CODEC_CTRL_HPP */ diff --git a/host/lib/usrp/usrp_e100/codec_impl.cpp b/host/lib/usrp/usrp_e100/codec_impl.cpp new file mode 100644 index 000000000..696fb37ec --- /dev/null +++ b/host/lib/usrp/usrp_e100/codec_impl.cpp @@ -0,0 +1,149 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "usrp_e_impl.hpp" +#include +#include +#include + +using namespace uhd; +using namespace uhd::usrp; + +/*********************************************************************** + * Helper Methods + **********************************************************************/ +void usrp_e_impl::codec_init(void){ + //make proxies + _rx_codec_proxy = wax_obj_proxy::make( + boost::bind(&usrp_e_impl::rx_codec_get, this, _1, _2), + boost::bind(&usrp_e_impl::rx_codec_set, this, _1, _2) + ); + _tx_codec_proxy = wax_obj_proxy::make( + boost::bind(&usrp_e_impl::tx_codec_get, this, _1, _2), + boost::bind(&usrp_e_impl::tx_codec_set, this, _1, _2) + ); +} + +/*********************************************************************** + * RX Codec Properties + **********************************************************************/ +static const std::string ad9862_pga_gain_name = "ad9862 pga"; + +void usrp_e_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case CODEC_PROP_NAME: + val = std::string("usrp-e adc - ad9522"); + return; + + case CODEC_PROP_OTHERS: + val = prop_names_t(); + return; + + case CODEC_PROP_GAIN_NAMES: + val = prop_names_t(1, ad9862_pga_gain_name); + return; + + case CODEC_PROP_GAIN_RANGE: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + val = usrp_e_codec_ctrl::rx_pga_gain_range; + return; + + case CODEC_PROP_GAIN_I: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + val = _codec_ctrl->get_rx_pga_gain('A'); + return; + + case CODEC_PROP_GAIN_Q: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + val = _codec_ctrl->get_rx_pga_gain('B'); + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +void usrp_e_impl::rx_codec_set(const wax::obj &key_, const wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the set request conditioned on the key + switch(key.as()){ + case CODEC_PROP_GAIN_I: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + _codec_ctrl->set_rx_pga_gain(val.as(), 'A'); + return; + + case CODEC_PROP_GAIN_Q: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + _codec_ctrl->set_rx_pga_gain(val.as(), 'B'); + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } +} + +/*********************************************************************** + * TX Codec Properties + **********************************************************************/ +void usrp_e_impl::tx_codec_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case CODEC_PROP_NAME: + val = std::string("usrp-e dac - ad9522"); + return; + + case CODEC_PROP_OTHERS: + val = prop_names_t(); + return; + + case CODEC_PROP_GAIN_NAMES: + val = prop_names_t(1, ad9862_pga_gain_name); + return; + + case CODEC_PROP_GAIN_RANGE: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + val = usrp_e_codec_ctrl::tx_pga_gain_range; + return; + + case CODEC_PROP_GAIN_I: //only one gain for I and Q + case CODEC_PROP_GAIN_Q: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + val = _codec_ctrl->get_tx_pga_gain(); + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +void usrp_e_impl::tx_codec_set(const wax::obj &key_, const wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the set request conditioned on the key + switch(key.as()){ + case CODEC_PROP_GAIN_I: //only one gain for I and Q + case CODEC_PROP_GAIN_Q: + UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); + _codec_ctrl->set_tx_pga_gain(val.as()); + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } +} diff --git a/host/lib/usrp/usrp_e100/dboard_iface.cpp b/host/lib/usrp/usrp_e100/dboard_iface.cpp new file mode 100644 index 000000000..6898df8df --- /dev/null +++ b/host/lib/usrp/usrp_e100/dboard_iface.cpp @@ -0,0 +1,298 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "usrp_e_iface.hpp" +#include "usrp_e_regs.hpp" +#include "clock_ctrl.hpp" +#include "codec_ctrl.hpp" +#include +#include +#include +#include +#include //i2c and spi constants + +using namespace uhd; +using namespace uhd::usrp; +using namespace boost::assign; + +class usrp_e_dboard_iface : public dboard_iface{ +public: + + usrp_e_dboard_iface( + usrp_e_iface::sptr iface, + usrp_e_clock_ctrl::sptr clock, + usrp_e_codec_ctrl::sptr codec + ){ + _iface = iface; + _clock = clock; + _codec = codec; + + //init the clock rate shadows + this->set_clock_rate(UNIT_RX, _clock->get_fpga_clock_rate()); + this->set_clock_rate(UNIT_TX, _clock->get_fpga_clock_rate()); + + _iface->poke16(UE_REG_GPIO_RX_DBG, 0); + _iface->poke16(UE_REG_GPIO_TX_DBG, 0); + } + + ~usrp_e_dboard_iface(void){ + /* NOP */ + } + + special_props_t get_special_props(void){ + special_props_t props; + props.soft_clock_divider = false; + props.mangle_i2c_addrs = false; + return props; + } + + void write_aux_dac(unit_t, aux_dac_t, float); + float read_aux_adc(unit_t, aux_adc_t); + + void set_pin_ctrl(unit_t, boost::uint16_t); + void set_atr_reg(unit_t, atr_reg_t, boost::uint16_t); + void set_gpio_ddr(unit_t, boost::uint16_t); + void write_gpio(unit_t, boost::uint16_t); + void set_gpio_debug(unit_t, int); + boost::uint16_t read_gpio(unit_t); + + void write_i2c(boost::uint8_t, const byte_vector_t &); + byte_vector_t read_i2c(boost::uint8_t, size_t); + + void write_spi( + unit_t unit, + const spi_config_t &config, + boost::uint32_t data, + size_t num_bits + ); + + boost::uint32_t read_write_spi( + unit_t unit, + const spi_config_t &config, + boost::uint32_t data, + size_t num_bits + ); + + void set_clock_rate(unit_t, double); + std::vector get_clock_rates(unit_t); + double get_clock_rate(unit_t); + void set_clock_enabled(unit_t, bool); + double get_codec_rate(unit_t); + +private: + usrp_e_iface::sptr _iface; + usrp_e_clock_ctrl::sptr _clock; + usrp_e_codec_ctrl::sptr _codec; + uhd::dict _clock_rates; +}; + +/*********************************************************************** + * Make Function + **********************************************************************/ +dboard_iface::sptr make_usrp_e_dboard_iface( + usrp_e_iface::sptr iface, + usrp_e_clock_ctrl::sptr clock, + usrp_e_codec_ctrl::sptr codec +){ + return dboard_iface::sptr(new usrp_e_dboard_iface(iface, clock, codec)); +} + +/*********************************************************************** + * Clock Rates + **********************************************************************/ +void usrp_e_dboard_iface::set_clock_rate(unit_t unit, double rate){ + _clock_rates[unit] = rate; + switch(unit){ + case UNIT_RX: return _clock->set_rx_dboard_clock_rate(rate); + case UNIT_TX: return _clock->set_tx_dboard_clock_rate(rate); + } +} + +std::vector usrp_e_dboard_iface::get_clock_rates(unit_t unit){ + switch(unit){ + case UNIT_RX: return _clock->get_rx_dboard_clock_rates(); + case UNIT_TX: return _clock->get_tx_dboard_clock_rates(); + default: UHD_THROW_INVALID_CODE_PATH(); + } +} + +double usrp_e_dboard_iface::get_clock_rate(unit_t unit){ + return _clock_rates[unit]; +} + +void usrp_e_dboard_iface::set_clock_enabled(unit_t unit, bool enb){ + switch(unit){ + case UNIT_RX: return _clock->enable_rx_dboard_clock(enb); + case UNIT_TX: return _clock->enable_tx_dboard_clock(enb); + } +} + +double usrp_e_dboard_iface::get_codec_rate(unit_t){ + return _clock->get_fpga_clock_rate(); +} + +/*********************************************************************** + * GPIO + **********************************************************************/ +void usrp_e_dboard_iface::set_pin_ctrl(unit_t unit, boost::uint16_t value){ + UHD_ASSERT_THROW(GPIO_SEL_ATR == 1); //make this assumption + switch(unit){ + case UNIT_RX: _iface->poke16(UE_REG_GPIO_RX_SEL, value); return; + case UNIT_TX: _iface->poke16(UE_REG_GPIO_TX_SEL, value); return; + } +} + +void usrp_e_dboard_iface::set_gpio_ddr(unit_t unit, boost::uint16_t value){ + switch(unit){ + case UNIT_RX: _iface->poke16(UE_REG_GPIO_RX_DDR, value); return; + case UNIT_TX: _iface->poke16(UE_REG_GPIO_TX_DDR, value); return; + } +} + +void usrp_e_dboard_iface::write_gpio(unit_t unit, boost::uint16_t value){ + switch(unit){ + case UNIT_RX: _iface->poke16(UE_REG_GPIO_RX_IO, value); return; + case UNIT_TX: _iface->poke16(UE_REG_GPIO_TX_IO, value); return; + } +} + +boost::uint16_t usrp_e_dboard_iface::read_gpio(unit_t unit){ + switch(unit){ + case UNIT_RX: return _iface->peek16(UE_REG_GPIO_RX_IO); + case UNIT_TX: return _iface->peek16(UE_REG_GPIO_TX_IO); + default: UHD_THROW_INVALID_CODE_PATH(); + } +} + +void usrp_e_dboard_iface::set_atr_reg(unit_t unit, atr_reg_t atr, boost::uint16_t value){ + //define mapping of unit to atr regs to register address + static const uhd::dict< + unit_t, uhd::dict + > unit_to_atr_to_addr = map_list_of + (UNIT_RX, map_list_of + (ATR_REG_IDLE, UE_REG_ATR_IDLE_RXSIDE) + (ATR_REG_TX_ONLY, UE_REG_ATR_INTX_RXSIDE) + (ATR_REG_RX_ONLY, UE_REG_ATR_INRX_RXSIDE) + (ATR_REG_FULL_DUPLEX, UE_REG_ATR_FULL_RXSIDE) + ) + (UNIT_TX, map_list_of + (ATR_REG_IDLE, UE_REG_ATR_IDLE_TXSIDE) + (ATR_REG_TX_ONLY, UE_REG_ATR_INTX_TXSIDE) + (ATR_REG_RX_ONLY, UE_REG_ATR_INRX_TXSIDE) + (ATR_REG_FULL_DUPLEX, UE_REG_ATR_FULL_TXSIDE) + ) + ; + _iface->poke16(unit_to_atr_to_addr[unit][atr], value); +} + +void usrp_e_dboard_iface::set_gpio_debug(unit_t unit, int which){ + //set this unit to all outputs + this->set_gpio_ddr(unit, 0xffff); + + //calculate the debug selections + boost::uint32_t dbg_sels = 0x0; + int sel = (which == 0)? GPIO_SEL_DEBUG_0 : GPIO_SEL_DEBUG_1; + for(size_t i = 0; i < 16; i++) dbg_sels |= sel << i; + + //set the debug on and which debug selection + switch(unit){ + case UNIT_RX: + _iface->poke16(UE_REG_GPIO_RX_DBG, 0xffff); + _iface->poke16(UE_REG_GPIO_RX_SEL, dbg_sels); + return; + + case UNIT_TX: + _iface->poke16(UE_REG_GPIO_TX_DBG, 0xffff); + _iface->poke16(UE_REG_GPIO_TX_SEL, dbg_sels); + return; + } +} + +/*********************************************************************** + * SPI + **********************************************************************/ +/*! + * Static function to convert a unit type to a spi slave device number. + * \param unit the dboard interface unit type enum + * \return the slave device number + */ +static boost::uint32_t unit_to_otw_spi_dev(dboard_iface::unit_t unit){ + switch(unit){ + case dboard_iface::UNIT_TX: return UE_SPI_SS_TX_DB; + case dboard_iface::UNIT_RX: return UE_SPI_SS_RX_DB; + } + throw std::invalid_argument("unknown unit type"); +} + +void usrp_e_dboard_iface::write_spi( + unit_t unit, + const spi_config_t &config, + boost::uint32_t data, + size_t num_bits +){ + _iface->transact_spi(unit_to_otw_spi_dev(unit), config, data, num_bits, false /*no rb*/); +} + +boost::uint32_t usrp_e_dboard_iface::read_write_spi( + unit_t unit, + const spi_config_t &config, + boost::uint32_t data, + size_t num_bits +){ + return _iface->transact_spi(unit_to_otw_spi_dev(unit), config, data, num_bits, true /*rb*/); +} + +/*********************************************************************** + * I2C + **********************************************************************/ +void usrp_e_dboard_iface::write_i2c(boost::uint8_t addr, const byte_vector_t &bytes){ + return _iface->write_i2c(addr, bytes); +} + +byte_vector_t usrp_e_dboard_iface::read_i2c(boost::uint8_t addr, size_t num_bytes){ + return _iface->read_i2c(addr, num_bytes); +} + +/*********************************************************************** + * Aux DAX/ADC + **********************************************************************/ +void usrp_e_dboard_iface::write_aux_dac(dboard_iface::unit_t, aux_dac_t which, float value){ + //same aux dacs for each unit + static const uhd::dict which_to_aux_dac = map_list_of + (AUX_DAC_A, usrp_e_codec_ctrl::AUX_DAC_A) + (AUX_DAC_B, usrp_e_codec_ctrl::AUX_DAC_B) + (AUX_DAC_C, usrp_e_codec_ctrl::AUX_DAC_C) + (AUX_DAC_D, usrp_e_codec_ctrl::AUX_DAC_D) + ; + _codec->write_aux_dac(which_to_aux_dac[which], value); +} + +float usrp_e_dboard_iface::read_aux_adc(dboard_iface::unit_t unit, aux_adc_t which){ + static const uhd::dict< + unit_t, uhd::dict + > unit_to_which_to_aux_adc = map_list_of + (UNIT_RX, map_list_of + (AUX_ADC_A, usrp_e_codec_ctrl::AUX_ADC_A1) + (AUX_ADC_B, usrp_e_codec_ctrl::AUX_ADC_B1) + ) + (UNIT_TX, map_list_of + (AUX_ADC_A, usrp_e_codec_ctrl::AUX_ADC_A2) + (AUX_ADC_B, usrp_e_codec_ctrl::AUX_ADC_B2) + ) + ; + return _codec->read_aux_adc(unit_to_which_to_aux_adc[unit][which]); +} diff --git a/host/lib/usrp/usrp_e100/dboard_impl.cpp b/host/lib/usrp/usrp_e100/dboard_impl.cpp new file mode 100644 index 000000000..f2840dcfc --- /dev/null +++ b/host/lib/usrp/usrp_e100/dboard_impl.cpp @@ -0,0 +1,172 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "usrp_e_impl.hpp" +#include "usrp_e_regs.hpp" +#include +#include +#include +#include +#include +#include + +using namespace uhd; +using namespace uhd::usrp; + +/*********************************************************************** + * Dboard Initialization + **********************************************************************/ +void usrp_e_impl::dboard_init(void){ + _rx_db_eeprom = dboard_eeprom_t(_iface->read_eeprom(I2C_ADDR_RX_DB, 0, dboard_eeprom_t::num_bytes())); + _tx_db_eeprom = dboard_eeprom_t(_iface->read_eeprom(I2C_ADDR_TX_DB, 0, dboard_eeprom_t::num_bytes())); + + //create a new dboard interface and manager + _dboard_iface = make_usrp_e_dboard_iface( + _iface, _clock_ctrl, _codec_ctrl + ); + _dboard_manager = dboard_manager::make( + _rx_db_eeprom.id, _tx_db_eeprom.id, _dboard_iface + ); + + //setup the dboard proxies + _rx_dboard_proxy = wax_obj_proxy::make( + boost::bind(&usrp_e_impl::rx_dboard_get, this, _1, _2), + boost::bind(&usrp_e_impl::rx_dboard_set, this, _1, _2) + ); + _tx_dboard_proxy = wax_obj_proxy::make( + boost::bind(&usrp_e_impl::tx_dboard_get, this, _1, _2), + boost::bind(&usrp_e_impl::tx_dboard_set, this, _1, _2) + ); +} + +/*********************************************************************** + * RX Dboard Get + **********************************************************************/ +void usrp_e_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case DBOARD_PROP_NAME: + val = std::string("usrp-e dboard (rx unit)"); + return; + + case DBOARD_PROP_SUBDEV: + val = _dboard_manager->get_rx_subdev(key.name); + return; + + case DBOARD_PROP_SUBDEV_NAMES: + val = _dboard_manager->get_rx_subdev_names(); + return; + + case DBOARD_PROP_DBOARD_ID: + val = _rx_db_eeprom.id; + return; + + case DBOARD_PROP_DBOARD_IFACE: + val = _dboard_iface; + return; + + case DBOARD_PROP_CODEC: + val = _rx_codec_proxy->get_link(); + return; + + case DBOARD_PROP_GAIN_GROUP: + val = make_gain_group( + _rx_db_eeprom.id, + _dboard_manager->get_rx_subdev(key.name), + _rx_codec_proxy->get_link(), + GAIN_GROUP_POLICY_RX + ); + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +/*********************************************************************** + * RX Dboard Set + **********************************************************************/ +void usrp_e_impl::rx_dboard_set(const wax::obj &key, const wax::obj &val){ + switch(key.as()){ + case DBOARD_PROP_DBOARD_ID: + _rx_db_eeprom.id = val.as(); + _iface->write_eeprom(I2C_ADDR_RX_DB, 0, _rx_db_eeprom.get_eeprom_bytes()); + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } +} + +/*********************************************************************** + * TX Dboard Get + **********************************************************************/ +void usrp_e_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case DBOARD_PROP_NAME: + val = std::string("usrp-e dboard (tx unit)"); + return; + + case DBOARD_PROP_SUBDEV: + val = _dboard_manager->get_tx_subdev(key.name); + return; + + case DBOARD_PROP_SUBDEV_NAMES: + val = _dboard_manager->get_tx_subdev_names(); + return; + + case DBOARD_PROP_DBOARD_ID: + val = _tx_db_eeprom.id; + return; + + case DBOARD_PROP_DBOARD_IFACE: + val = _dboard_iface; + return; + + case DBOARD_PROP_CODEC: + val = _tx_codec_proxy->get_link(); + return; + + case DBOARD_PROP_GAIN_GROUP: + val = make_gain_group( + _tx_db_eeprom.id, + _dboard_manager->get_tx_subdev(key.name), + _tx_codec_proxy->get_link(), + GAIN_GROUP_POLICY_TX + ); + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +/*********************************************************************** + * TX Dboard Set + **********************************************************************/ +void usrp_e_impl::tx_dboard_set(const wax::obj &key, const wax::obj &val){ + switch(key.as()){ + case DBOARD_PROP_DBOARD_ID: + _tx_db_eeprom.id = val.as(); + _iface->write_eeprom(I2C_ADDR_TX_DB, 0, _tx_db_eeprom.get_eeprom_bytes()); + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } +} diff --git a/host/lib/usrp/usrp_e100/dsp_impl.cpp b/host/lib/usrp/usrp_e100/dsp_impl.cpp new file mode 100644 index 000000000..97f173c1a --- /dev/null +++ b/host/lib/usrp/usrp_e100/dsp_impl.cpp @@ -0,0 +1,192 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "usrp_e_impl.hpp" +#include "usrp_e_regs.hpp" +#include +#include +#include +#include + +#define rint boost::math::iround + +using namespace uhd; +using namespace uhd::usrp; + +/*********************************************************************** + * RX DDC Initialization + **********************************************************************/ +void usrp_e_impl::rx_ddc_init(void){ + _rx_ddc_proxy = wax_obj_proxy::make( + boost::bind(&usrp_e_impl::rx_ddc_get, this, _1, _2), + boost::bind(&usrp_e_impl::rx_ddc_set, this, _1, _2) + ); + + //initial config and update + rx_ddc_set(DSP_PROP_FREQ_SHIFT, double(0)); + rx_ddc_set(DSP_PROP_HOST_RATE, double(64e6/10)); +} + +/*********************************************************************** + * RX DDC Get + **********************************************************************/ +void usrp_e_impl::rx_ddc_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + switch(key.as()){ + case DSP_PROP_NAME: + val = std::string("usrp-e ddc0"); + return; + + case DSP_PROP_OTHERS: + val = prop_names_t(); //empty + return; + + case DSP_PROP_FREQ_SHIFT: + val = _ddc_freq; + return; + + case DSP_PROP_FREQ_SHIFT_NAMES: + val = prop_names_t(1, ""); + return; + + case DSP_PROP_CODEC_RATE: + val = _clock_ctrl->get_fpga_clock_rate(); + return; + + case DSP_PROP_HOST_RATE: + val = _clock_ctrl->get_fpga_clock_rate()/_ddc_decim; + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +/*********************************************************************** + * RX DDC Set + **********************************************************************/ +void usrp_e_impl::rx_ddc_set(const wax::obj &key_, const wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + switch(key.as()){ + + case DSP_PROP_FREQ_SHIFT:{ + double new_freq = val.as(); + _iface->poke32(UE_REG_DSP_RX_FREQ, + dsp_type1::calc_cordic_word_and_update(new_freq, _clock_ctrl->get_fpga_clock_rate()) + ); + _ddc_freq = new_freq; //shadow + } + return; + + case DSP_PROP_HOST_RATE:{ + //set the decimation + _ddc_decim = rint(_clock_ctrl->get_fpga_clock_rate()/val.as()); + _iface->poke32(UE_REG_DSP_RX_DECIM_RATE, dsp_type1::calc_cic_filter_word(_ddc_decim)); + + //set the scaling + static const boost::int16_t default_rx_scale_iq = 1024; + _iface->poke32(UE_REG_DSP_RX_SCALE_IQ, + dsp_type1::calc_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq) + ); + } + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } +} + +/*********************************************************************** + * TX DUC Initialization + **********************************************************************/ +void usrp_e_impl::tx_duc_init(void){ + _tx_duc_proxy = wax_obj_proxy::make( + boost::bind(&usrp_e_impl::tx_duc_get, this, _1, _2), + boost::bind(&usrp_e_impl::tx_duc_set, this, _1, _2) + ); + + //initial config and update + tx_duc_set(DSP_PROP_FREQ_SHIFT, double(0)); + tx_duc_set(DSP_PROP_HOST_RATE, double(64e6/10)); +} + +/*********************************************************************** + * TX DUC Get + **********************************************************************/ +void usrp_e_impl::tx_duc_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + switch(key.as()){ + case DSP_PROP_NAME: + val = std::string("usrp-e duc0"); + return; + + case DSP_PROP_OTHERS: + val = prop_names_t(); //empty + return; + + case DSP_PROP_FREQ_SHIFT: + val = _duc_freq; + return; + + case DSP_PROP_FREQ_SHIFT_NAMES: + val = prop_names_t(1, ""); + return; + + case DSP_PROP_CODEC_RATE: + val = _clock_ctrl->get_fpga_clock_rate(); + return; + + case DSP_PROP_HOST_RATE: + val = _clock_ctrl->get_fpga_clock_rate()/_duc_interp; + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +/*********************************************************************** + * TX DUC Set + **********************************************************************/ +void usrp_e_impl::tx_duc_set(const wax::obj &key_, const wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + switch(key.as()){ + + case DSP_PROP_FREQ_SHIFT:{ + double new_freq = val.as(); + _iface->poke32(UE_REG_DSP_TX_FREQ, + dsp_type1::calc_cordic_word_and_update(new_freq, _clock_ctrl->get_fpga_clock_rate()) + ); + _duc_freq = new_freq; //shadow + } + return; + + case DSP_PROP_HOST_RATE:{ + _duc_interp = rint(_clock_ctrl->get_fpga_clock_rate()/val.as()); + + //set the interpolation + _iface->poke32(UE_REG_DSP_TX_INTERP_RATE, dsp_type1::calc_cic_filter_word(_duc_interp)); + + //set the scaling + _iface->poke32(UE_REG_DSP_TX_SCALE_IQ, dsp_type1::calc_iq_scale_word(_duc_interp)); + } + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } +} diff --git a/host/lib/usrp/usrp_e100/fpga-downloader.cc b/host/lib/usrp/usrp_e100/fpga-downloader.cc new file mode 100644 index 000000000..4dc537919 --- /dev/null +++ b/host/lib/usrp/usrp_e100/fpga-downloader.cc @@ -0,0 +1,274 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +/* + * Configuration connections + * + * CCK - MCSPI1_CLK + * DIN - MCSPI1_MOSI + * PROG_B - GPIO_175 - output (change mux) + * DONE - GPIO_173 - input (change mux) + * INIT_B - GPIO_114 - input (change mux) + * +*/ + +const unsigned int PROG_B = 175; +const unsigned int DONE = 173; +const unsigned int INIT_B = 114; + +//static std::string bit_file = "safe_u1e.bin"; + +const int BUF_SIZE = 4096; + +enum gpio_direction {IN, OUT}; + +class gpio { + public: + + gpio(unsigned int gpio_num, gpio_direction pin_direction); + + bool get_value(); + void set_value(bool state); + + private: + + std::stringstream base_path; + std::fstream value_file; +}; + +class spidev { + public: + + spidev(std::string dev_name); + ~spidev(); + + void send(char *wbuf, char *rbuf, unsigned int nbytes); + + private: + + int fd; + +}; + +gpio::gpio(unsigned int gpio_num, gpio_direction pin_direction) +{ + std::fstream export_file; + + export_file.open("/sys/class/gpio/export", std::ios::out); + if (not export_file.is_open()) throw std::runtime_error( + "Failed to open gpio export file." + ); + + export_file << gpio_num << std::endl; + + base_path << "/sys/class/gpio/gpio" << gpio_num << std::flush; + + std::fstream direction_file; + std::string direction_file_name; + + if (gpio_num != 114) { + direction_file_name = base_path.str() + "/direction"; + + direction_file.open(direction_file_name.c_str()); + if (!direction_file.is_open()) + std::cout << "Failed to open direction file." << std::endl; + if (pin_direction == OUT) + direction_file << "out" << std::endl; + else + direction_file << "in" << std::endl; + } + + std::string value_file_name; + + value_file_name = base_path.str() + "/value"; + + value_file.open(value_file_name.c_str(), std::ios_base::in | std::ios_base::out); + if (!value_file.is_open()) + std::cout << "Failed to open value file." << std::endl; +} + +bool gpio::get_value() +{ + + std::string val; + + std::getline(value_file, val); + value_file.seekg(0); + + if (val == "0") + return false; + else if (val == "1") + return true; + else + std::cout << "Data read from value file|" << val << "|" << std::endl; + + return false; +} + +void gpio::set_value(bool state) +{ + + if (state) + value_file << "1" << std::endl; + else + value_file << "0" << std::endl; +} + +static void prepare_fpga_for_configuration(gpio &prog, gpio &)//init) +{ + + prog.set_value(true); + prog.set_value(false); + prog.set_value(true); + +#if 0 + bool ready_to_program(false); + unsigned int count(0); + do { + ready_to_program = init.get_value(); + count++; + + sleep(1); + } while (count < 10 && !ready_to_program); + + if (count == 10) { + std::cout << "FPGA not ready for programming." << std::endl; + exit(-1); + } +#endif +} + +spidev::spidev(std::string fname) +{ + int ret; + int mode = 0; + int speed = 12000000; + int bits = 8; + + fd = open(fname.c_str(), O_RDWR); + + ret = ioctl(fd, SPI_IOC_WR_MODE, &mode); + ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed); + ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits); +} + + +spidev::~spidev() +{ + close(fd); +} + +void spidev::send(char *buf, char *rbuf, unsigned int nbytes) +{ + int ret; + + struct spi_ioc_transfer tr; + tr.tx_buf = (unsigned long) buf; + tr.rx_buf = (unsigned long) rbuf; + tr.len = nbytes; + tr.delay_usecs = 0; + tr.speed_hz = 48000000; + tr.bits_per_word = 8; + + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + +} + +static void send_file_to_fpga(const std::string &file_name, gpio &error, gpio &done) +{ + std::ifstream bitstream; + + std::cout << "File name - " << file_name.c_str() << std::endl; + + bitstream.open(file_name.c_str(), std::ios::binary); + if (!bitstream.is_open()) + std::cout << "File " << file_name << " not opened succesfully." << std::endl; + + spidev spi("/dev/spidev1.0"); + char buf[BUF_SIZE]; + char rbuf[BUF_SIZE]; + + do { + bitstream.read(buf, BUF_SIZE); + spi.send(buf, rbuf, bitstream.gcount()); + + if (error.get_value()) + std::cout << "INIT_B went high, error occured." << std::endl; + + if (!done.get_value()) + std::cout << "Configuration complete." << std::endl; + + } while (bitstream.gcount() == BUF_SIZE); +} + +/* +int main(int argc, char *argv[]) +{ + + gpio gpio_prog_b(PROG_B, OUT); + gpio gpio_init_b(INIT_B, IN); + gpio gpio_done (DONE, IN); + + if (argc == 2) + bit_file = argv[1]; + + std::cout << "FPGA config file: " << bit_file << std::endl; + + prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b); + + std::cout << "Done = " << gpio_done.get_value() << std::endl; + + send_file_to_fpga(bit_file, gpio_init_b, gpio_done); +} +*/ + +void usrp_e_load_fpga(const std::string &bin_file){ + gpio gpio_prog_b(PROG_B, OUT); + gpio gpio_init_b(INIT_B, IN); + gpio gpio_done (DONE, IN); + + std::cout << "Loading FPGA image: " << bin_file << "... " << std::flush; + + UHD_ASSERT_THROW(std::system("/sbin/rmmod usrp_e") == 0); + + prepare_fpga_for_configuration(gpio_prog_b, gpio_init_b); + + std::cout << "done = " << gpio_done.get_value() << std::endl; + + send_file_to_fpga(bin_file, gpio_init_b, gpio_done); + + UHD_ASSERT_THROW(std::system("/sbin/modprobe usrp_e") == 0); + +} + diff --git a/host/lib/usrp/usrp_e100/io_impl.cpp b/host/lib/usrp/usrp_e100/io_impl.cpp new file mode 100644 index 000000000..e863944e8 --- /dev/null +++ b/host/lib/usrp/usrp_e100/io_impl.cpp @@ -0,0 +1,272 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "usrp_e_impl.hpp" +#include "usrp_e_regs.hpp" +#include +#include +#include +#include "../../transport/vrt_packet_handler.hpp" +#include +#include +#include +#include + +using namespace uhd; +using namespace uhd::usrp; +using namespace uhd::transport; + +zero_copy_if::sptr usrp_e_make_mmap_zero_copy(usrp_e_iface::sptr iface); + +/*********************************************************************** + * Constants + **********************************************************************/ +static const size_t tx_async_report_sid = 1; +static const int underflow_flags = async_metadata_t::EVENT_CODE_UNDERFLOW | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET; +static const bool recv_debug = false; + +/*********************************************************************** + * io impl details (internal to this file) + * - pirate crew of 1 + * - bounded buffer + * - thread loop + * - vrt packet handler states + **********************************************************************/ +struct usrp_e_impl::io_impl{ + //state management for the vrt packet handler code + vrt_packet_handler::recv_state packet_handler_recv_state; + vrt_packet_handler::send_state packet_handler_send_state; + zero_copy_if::sptr data_xport; + bool continuous_streaming; + io_impl(usrp_e_iface::sptr iface): + data_xport(usrp_e_make_mmap_zero_copy(iface)), + recv_pirate_booty(recv_booty_type::make(data_xport->get_num_recv_frames())), + async_msg_fifo(bounded_buffer::make(100/*messages deep*/)) + { + /* NOP */ + } + + ~io_impl(void){ + recv_pirate_crew_raiding = false; + recv_pirate_crew.interrupt_all(); + recv_pirate_crew.join_all(); + } + + bool get_recv_buffs(vrt_packet_handler::managed_recv_buffs_t &buffs, double timeout){ + UHD_ASSERT_THROW(buffs.size() == 1); + boost::this_thread::disable_interruption di; //disable because the wait can throw + return recv_pirate_booty->pop_with_timed_wait(buffs.front(), timeout); + } + + //a pirate's life is the life for me! + void recv_pirate_loop(usrp_e_clock_ctrl::sptr); + typedef bounded_buffer recv_booty_type; + recv_booty_type::sptr recv_pirate_booty; + bounded_buffer::sptr async_msg_fifo; + boost::thread_group recv_pirate_crew; + bool recv_pirate_crew_raiding; +}; + +/*********************************************************************** + * Receive Pirate Loop + * - while raiding, loot for recv buffers + * - put booty into the alignment buffer + **********************************************************************/ +void usrp_e_impl::io_impl::recv_pirate_loop(usrp_e_clock_ctrl::sptr clock_ctrl) +{ + set_thread_priority_safe(); + recv_pirate_crew_raiding = true; + + while(recv_pirate_crew_raiding){ + managed_recv_buffer::sptr buff = this->data_xport->get_recv_buff(); + if (not buff.get()) continue; //ignore timeout/error buffers + + if (recv_debug){ + std::cout << "len " << buff->size() << std::endl; + for (size_t i = 0; i < 9; i++){ + std::cout << boost::format(" 0x%08x") % buff->cast()[i] << std::endl; + } + std::cout << std::endl << std::endl; + } + + try{ + //extract the vrt header packet info + vrt::if_packet_info_t if_packet_info; + if_packet_info.num_packet_words32 = buff->size()/sizeof(boost::uint32_t); + const boost::uint32_t *vrt_hdr = buff->cast(); + vrt::if_hdr_unpack_le(vrt_hdr, if_packet_info); + + //handle a tx async report message + if (if_packet_info.sid == tx_async_report_sid and if_packet_info.packet_type != vrt::if_packet_info_t::PACKET_TYPE_DATA){ + + //fill in the async metadata + async_metadata_t metadata; + metadata.channel = 0; + metadata.has_time_spec = if_packet_info.has_tsi and if_packet_info.has_tsf; + metadata.time_spec = time_spec_t( + time_t(if_packet_info.tsi), size_t(if_packet_info.tsf), clock_ctrl->get_fpga_clock_rate() + ); + metadata.event_code = vrt_packet_handler::get_context_code(vrt_hdr, if_packet_info); + + //print the famous U, and push the metadata into the message queue + if (metadata.event_code & underflow_flags) std::cerr << "U" << std::flush; + async_msg_fifo->push_with_pop_on_full(metadata); + continue; + } + + //same number of frames as the data transport -> always immediate + recv_pirate_booty->push_with_wait(buff); + + }catch(const std::exception &e){ + std::cerr << "Error (usrp-e recv pirate loop): " << e.what() << std::endl; + } + } +} + +/*********************************************************************** + * Helper Functions + **********************************************************************/ +void usrp_e_impl::io_init(void){ + //setup otw types + _send_otw_type.width = 16; + _send_otw_type.shift = 0; + _send_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN; + + _recv_otw_type.width = 16; + _recv_otw_type.shift = 0; + _recv_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN; + + //setup before the registers (transport called to calculate max spp) + _io_impl = UHD_PIMPL_MAKE(io_impl, (_iface)); + + //setup rx data path + _iface->poke32(UE_REG_CTRL_RX_NSAMPS_PER_PKT, get_max_recv_samps_per_packet()); + _iface->poke32(UE_REG_CTRL_RX_NCHANNELS, 1); + _iface->poke32(UE_REG_CTRL_RX_CLEAR_OVERRUN, 1); //reset + _iface->poke32(UE_REG_CTRL_RX_VRT_HEADER, 0 + | (0x1 << 28) //if data with stream id + | (0x1 << 26) //has trailer + | (0x3 << 22) //integer time other + | (0x1 << 20) //fractional time sample count + ); + _iface->poke32(UE_REG_CTRL_RX_VRT_STREAM_ID, 0); + _iface->poke32(UE_REG_CTRL_RX_VRT_TRAILER, 0); + + //setup the tx policy + _iface->poke32(UE_REG_CTRL_TX_REPORT_SID, tx_async_report_sid); + _iface->poke32(UE_REG_CTRL_TX_POLICY, UE_FLAG_CTRL_TX_POLICY_NEXT_PACKET); + + //spawn a pirate, yarrr! + _io_impl->recv_pirate_crew.create_thread(boost::bind( + &usrp_e_impl::io_impl::recv_pirate_loop, _io_impl.get(), _clock_ctrl + )); +} + +void usrp_e_impl::issue_stream_cmd(const stream_cmd_t &stream_cmd){ + _io_impl->continuous_streaming = (stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_START_CONTINUOUS); + _iface->poke32(UE_REG_CTRL_RX_STREAM_CMD, dsp_type1::calc_stream_cmd_word( + stream_cmd, get_max_recv_samps_per_packet() + )); + _iface->poke32(UE_REG_CTRL_RX_TIME_SECS, boost::uint32_t(stream_cmd.time_spec.get_full_secs())); + _iface->poke32(UE_REG_CTRL_RX_TIME_TICKS, stream_cmd.time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate())); +} + +void usrp_e_impl::handle_overrun(size_t){ + std::cerr << "O"; //the famous OOOOOOOOOOO + _iface->poke32(UE_REG_CTRL_RX_CLEAR_OVERRUN, 0); + if (_io_impl->continuous_streaming){ + this->issue_stream_cmd(stream_cmd_t::STREAM_MODE_START_CONTINUOUS); + } +} + +/*********************************************************************** + * Data Send + **********************************************************************/ +bool get_send_buffs( + zero_copy_if::sptr trans, double timeout, + vrt_packet_handler::managed_send_buffs_t &buffs +){ + UHD_ASSERT_THROW(buffs.size() == 1); + buffs[0] = trans->get_send_buff(timeout); + return buffs[0].get() != NULL; +} + +size_t usrp_e_impl::get_max_send_samps_per_packet(void) const{ + static const size_t hdr_size = 0 + + vrt::max_if_hdr_words32*sizeof(boost::uint32_t) + - sizeof(vrt::if_packet_info_t().cid) //no class id ever used + ; + size_t bpp = _io_impl->data_xport->get_send_frame_size() - hdr_size; + return bpp/_send_otw_type.get_sample_size(); +} + +size_t usrp_e_impl::send( + const std::vector &buffs, size_t num_samps, + const tx_metadata_t &metadata, const io_type_t &io_type, + send_mode_t send_mode, double timeout +){ + return vrt_packet_handler::send( + _io_impl->packet_handler_send_state, //last state of the send handler + buffs, num_samps, //buffer to fill + metadata, send_mode, //samples metadata + io_type, _send_otw_type, //input and output types to convert + _clock_ctrl->get_fpga_clock_rate(), //master clock tick rate + uhd::transport::vrt::if_hdr_pack_le, + boost::bind(&get_send_buffs, _io_impl->data_xport, timeout, _1), + get_max_send_samps_per_packet() + ); +} + +/*********************************************************************** + * Data Recv + **********************************************************************/ +size_t usrp_e_impl::get_max_recv_samps_per_packet(void) const{ + static const size_t hdr_size = 0 + + vrt::max_if_hdr_words32*sizeof(boost::uint32_t) + + sizeof(vrt::if_packet_info_t().tlr) //forced to have trailer + - sizeof(vrt::if_packet_info_t().cid) //no class id ever used + ; + size_t bpp = _io_impl->data_xport->get_recv_frame_size() - hdr_size; + return bpp/_recv_otw_type.get_sample_size(); +} + +size_t usrp_e_impl::recv( + const std::vector &buffs, size_t num_samps, + rx_metadata_t &metadata, const io_type_t &io_type, + recv_mode_t recv_mode, double timeout +){ + return vrt_packet_handler::recv( + _io_impl->packet_handler_recv_state, //last state of the recv handler + buffs, num_samps, //buffer to fill + metadata, recv_mode, //samples metadata + io_type, _recv_otw_type, //input and output types to convert + _clock_ctrl->get_fpga_clock_rate(), //master clock tick rate + uhd::transport::vrt::if_hdr_unpack_le, + boost::bind(&usrp_e_impl::io_impl::get_recv_buffs, _io_impl.get(), _1, timeout), + boost::bind(&usrp_e_impl::handle_overrun, this, _1) + ); +} + +/*********************************************************************** + * Async Recv + **********************************************************************/ +bool usrp_e_impl::recv_async_msg( + async_metadata_t &async_metadata, double timeout +){ + boost::this_thread::disable_interruption di; //disable because the wait can throw + return _io_impl->async_msg_fifo->pop_with_timed_wait(async_metadata, timeout); +} diff --git a/host/lib/usrp/usrp_e100/mboard_impl.cpp b/host/lib/usrp/usrp_e100/mboard_impl.cpp new file mode 100644 index 000000000..f0118aa4b --- /dev/null +++ b/host/lib/usrp/usrp_e100/mboard_impl.cpp @@ -0,0 +1,159 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "usrp_e_impl.hpp" +#include "usrp_e_regs.hpp" +#include +#include +#include +#include +#include +#include + +using namespace uhd; +using namespace uhd::usrp; + +/*********************************************************************** + * Mboard Initialization + **********************************************************************/ +void usrp_e_impl::mboard_init(void){ + _mboard_proxy = wax_obj_proxy::make( + boost::bind(&usrp_e_impl::mboard_get, this, _1, _2), + boost::bind(&usrp_e_impl::mboard_set, this, _1, _2) + ); + + //init the clock config + _clock_config.ref_source = clock_config_t::REF_AUTO; + _clock_config.pps_source = clock_config_t::PPS_SMA; + + //TODO poke the clock config regs +} + +/*********************************************************************** + * Mboard Get + **********************************************************************/ +void usrp_e_impl::mboard_get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case MBOARD_PROP_NAME: + val = std::string("usrp-e mboard"); + return; + + case MBOARD_PROP_OTHERS: + val = prop_names_t(); + return; + + case MBOARD_PROP_RX_DBOARD: + UHD_ASSERT_THROW(key.name == ""); + val = _rx_dboard_proxy->get_link(); + return; + + case MBOARD_PROP_RX_DBOARD_NAMES: + val = prop_names_t(1, ""); //vector of size 1 with empty string + return; + + case MBOARD_PROP_TX_DBOARD: + UHD_ASSERT_THROW(key.name == ""); + val = _tx_dboard_proxy->get_link(); + return; + + case MBOARD_PROP_TX_DBOARD_NAMES: + val = prop_names_t(1, ""); //vector of size 1 with empty string + return; + + case MBOARD_PROP_RX_DSP: + UHD_ASSERT_THROW(key.name == ""); + val = _rx_ddc_proxy->get_link(); + return; + + case MBOARD_PROP_RX_DSP_NAMES: + val = prop_names_t(1, ""); + return; + + case MBOARD_PROP_TX_DSP: + UHD_ASSERT_THROW(key.name == ""); + val = _tx_duc_proxy->get_link(); + return; + + case MBOARD_PROP_TX_DSP_NAMES: + val = prop_names_t(1, ""); + return; + + case MBOARD_PROP_CLOCK_CONFIG: + val = _clock_config; + return; + + case MBOARD_PROP_RX_SUBDEV_SPEC: + val = _rx_subdev_spec; + return; + + case MBOARD_PROP_TX_SUBDEV_SPEC: + val = _tx_subdev_spec; + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +/*********************************************************************** + * Mboard Set + **********************************************************************/ +void usrp_e_impl::mboard_set(const wax::obj &key, const wax::obj &val){ + //handle the get request conditioned on the key + switch(key.as()){ + + case MBOARD_PROP_STREAM_CMD: + issue_stream_cmd(val.as()); + return; + + case MBOARD_PROP_TIME_NOW: + case MBOARD_PROP_TIME_NEXT_PPS:{ + time_spec_t time_spec = val.as(); + _iface->poke32(UE_REG_TIME64_TICKS, time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate())); + boost::uint32_t imm_flags = (key.as() == MBOARD_PROP_TIME_NOW)? 1 : 0; + _iface->poke32(UE_REG_TIME64_IMM, imm_flags); + _iface->poke32(UE_REG_TIME64_SECS, time_spec.get_full_secs()); + } + return; + + case MBOARD_PROP_RX_SUBDEV_SPEC: + _rx_subdev_spec = val.as(); + verify_rx_subdev_spec(_rx_subdev_spec, _mboard_proxy->get_link()); + //sanity check + UHD_ASSERT_THROW(_rx_subdev_spec.size() == 1); + //set the mux + _iface->poke32(UE_REG_DSP_RX_MUX, dsp_type1::calc_rx_mux_word( + _dboard_manager->get_rx_subdev(_rx_subdev_spec.front().sd_name)[SUBDEV_PROP_CONNECTION].as() + )); + return; + + case MBOARD_PROP_TX_SUBDEV_SPEC: + _tx_subdev_spec = val.as(); + verify_tx_subdev_spec(_tx_subdev_spec, _mboard_proxy->get_link()); + //sanity check + UHD_ASSERT_THROW(_tx_subdev_spec.size() == 1); + //set the mux + _iface->poke32(UE_REG_DSP_TX_MUX, dsp_type1::calc_tx_mux_word( + _dboard_manager->get_tx_subdev(_tx_subdev_spec.front().sd_name)[SUBDEV_PROP_CONNECTION].as() + )); + return; + + default: UHD_THROW_PROP_SET_ERROR(); + } +} diff --git a/host/lib/usrp/usrp_e100/usrp_e_iface.cpp b/host/lib/usrp/usrp_e100/usrp_e_iface.cpp new file mode 100644 index 000000000..f00e92946 --- /dev/null +++ b/host/lib/usrp/usrp_e100/usrp_e_iface.cpp @@ -0,0 +1,194 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "usrp_e_iface.hpp" +#include +#include //ioctl +#include //open, close +#include //ioctl structures and constants +#include +#include //mutex +#include + +using namespace uhd; + +class usrp_e_iface_impl : public usrp_e_iface{ +public: + + int get_file_descriptor(void){ + return _node_fd; + } + + /******************************************************************* + * Structors + ******************************************************************/ + usrp_e_iface_impl(const std::string &node){ + //open the device node and check file descriptor + if ((_node_fd = ::open(node.c_str(), O_RDWR)) < 0){ + throw std::runtime_error(str( + boost::format("Failed to open %s") % node + )); + } + } + + ~usrp_e_iface_impl(void){ + //close the device node file descriptor + ::close(_node_fd); + } + + /******************************************************************* + * IOCTL: provides the communication base for all other calls + ******************************************************************/ + void ioctl(int request, void *mem){ + boost::mutex::scoped_lock lock(_ctrl_mutex); + + if (::ioctl(_node_fd, request, mem) < 0){ + throw std::runtime_error(str( + boost::format("ioctl failed with request %d") % request + )); + } + } + + /******************************************************************* + * Peek and Poke + ******************************************************************/ + void poke32(boost::uint32_t addr, boost::uint32_t value){ + //load the data struct + usrp_e_ctl32 data; + data.offset = addr; + data.count = 1; + data.buf[0] = value; + + //call the ioctl + this->ioctl(USRP_E_WRITE_CTL32, &data); + } + + void poke16(boost::uint32_t addr, boost::uint16_t value){ + //load the data struct + usrp_e_ctl16 data; + data.offset = addr; + data.count = 1; + data.buf[0] = value; + + //call the ioctl + this->ioctl(USRP_E_WRITE_CTL16, &data); + } + + boost::uint32_t peek32(boost::uint32_t addr){ + //load the data struct + usrp_e_ctl32 data; + data.offset = addr; + data.count = 1; + + //call the ioctl + this->ioctl(USRP_E_READ_CTL32, &data); + + return data.buf[0]; + } + + boost::uint16_t peek16(boost::uint32_t addr){ + //load the data struct + usrp_e_ctl16 data; + data.offset = addr; + data.count = 1; + + //call the ioctl + this->ioctl(USRP_E_READ_CTL16, &data); + + return data.buf[0]; + } + + /******************************************************************* + * I2C + ******************************************************************/ + static const size_t max_i2c_data_bytes = 10; + + void write_i2c(boost::uint8_t addr, const byte_vector_t &bytes){ + //allocate some memory for this transaction + UHD_ASSERT_THROW(bytes.size() <= max_i2c_data_bytes); + boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; + + //load the data struct + usrp_e_i2c *data = reinterpret_cast(mem); + data->addr = addr; + data->len = bytes.size(); + std::copy(bytes.begin(), bytes.end(), data->data); + + //call the spi ioctl + this->ioctl(USRP_E_I2C_WRITE, data); + } + + byte_vector_t read_i2c(boost::uint8_t addr, size_t num_bytes){ + //allocate some memory for this transaction + UHD_ASSERT_THROW(num_bytes <= max_i2c_data_bytes); + boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; + + //load the data struct + usrp_e_i2c *data = reinterpret_cast(mem); + data->addr = addr; + data->len = num_bytes; + + //call the spi ioctl + this->ioctl(USRP_E_I2C_READ, data); + + //unload the data + byte_vector_t bytes(data->len); + UHD_ASSERT_THROW(bytes.size() == num_bytes); + std::copy(data->data, data->data+bytes.size(), bytes.begin()); + return bytes; + } + + /******************************************************************* + * SPI + ******************************************************************/ + boost::uint32_t transact_spi( + int which_slave, + const spi_config_t &config, + boost::uint32_t bits, + size_t num_bits, + bool readback + ){ + //load data struct + usrp_e_spi data; + data.readback = (readback)? UE_SPI_TXRX : UE_SPI_TXONLY; + data.slave = which_slave; + data.length = num_bits; + data.data = bits; + + //load the flags + data.flags = 0; + data.flags |= (config.miso_edge == spi_config_t::EDGE_RISE)? UE_SPI_LATCH_RISE : UE_SPI_LATCH_FALL; + data.flags |= (config.mosi_edge == spi_config_t::EDGE_RISE)? UE_SPI_PUSH_FALL : UE_SPI_PUSH_RISE; + + //call the spi ioctl + this->ioctl(USRP_E_SPI, &data); + + //unload the data + return data.data; + } + +private: + int _node_fd; + boost::mutex _ctrl_mutex; +}; + +/*********************************************************************** + * Public Make Function + **********************************************************************/ +usrp_e_iface::sptr usrp_e_iface::make(const std::string &node){ + return sptr(new usrp_e_iface_impl(node)); +} diff --git a/host/lib/usrp/usrp_e100/usrp_e_iface.hpp b/host/lib/usrp/usrp_e100/usrp_e_iface.hpp new file mode 100644 index 000000000..59aac43d9 --- /dev/null +++ b/host/lib/usrp/usrp_e100/usrp_e_iface.hpp @@ -0,0 +1,112 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_USRP_E_IFACE_HPP +#define INCLUDED_USRP_E_IFACE_HPP + +#include +#include +#include +#include +#include + +//////////////////////////////////////////////////////////////////////// +// I2C addresses +//////////////////////////////////////////////////////////////////////// +#define I2C_DEV_EEPROM 0x50 // 24LC02[45]: 7-bits 1010xxx +#define I2C_ADDR_MBOARD (I2C_DEV_EEPROM | 0x0) +#define I2C_ADDR_TX_DB (I2C_DEV_EEPROM | 0x4) +#define I2C_ADDR_RX_DB (I2C_DEV_EEPROM | 0x5) +//////////////////////////////////////////////////////////////////////// + +/*! + * The usrp-e interface class: + * Provides a set of functions to implementation layer. + * Including spi, peek, poke, control... + */ +class usrp_e_iface : boost::noncopyable, public uhd::i2c_iface{ +public: + typedef boost::shared_ptr sptr; + + /*! + * Make a new usrp-e interface with the control transport. + * \param node the device node name + * \return a new usrp-e interface object + */ + static sptr make(const std::string &node); + + /*! + * Get the underlying file descriptor. + * \return the file descriptor + */ + virtual int get_file_descriptor(void) = 0; + + /*! + * Perform an ioctl call on the device node file descriptor. + * This will throw when the internal ioctl call fails. + * \param request the control word + * \param mem pointer to some memory + */ + virtual void ioctl(int request, void *mem) = 0; + + /*! + * Write a register (32 bits) + * \param addr the address + * \param data the 32bit data + */ + virtual void poke32(boost::uint32_t addr, boost::uint32_t data) = 0; + + /*! + * Read a register (32 bits) + * \param addr the address + * \return the 32bit data + */ + virtual boost::uint32_t peek32(boost::uint32_t addr) = 0; + + /*! + * Write a register (16 bits) + * \param addr the address + * \param data the 16bit data + */ + virtual void poke16(boost::uint32_t addr, boost::uint16_t data) = 0; + + /*! + * Read a register (16 bits) + * \param addr the address + * \return the 16bit data + */ + virtual boost::uint16_t peek16(boost::uint32_t addr) = 0; + + /*! + * Perform an spi transaction. + * \param which_slave the slave device number + * \param config spi config args + * \param data the bits to write + * \param num_bits how many bits in data + * \param readback true to readback a value + * \return spi data if readback set + */ + virtual boost::uint32_t transact_spi( + int which_slave, + const uhd::spi_config_t &config, + boost::uint32_t data, + size_t num_bits, + bool readback + ) = 0; +}; + +#endif /* INCLUDED_USRP_E_IFACE_HPP */ diff --git a/host/lib/usrp/usrp_e100/usrp_e_impl.cpp b/host/lib/usrp/usrp_e100/usrp_e_impl.cpp new file mode 100644 index 000000000..70cc399fb --- /dev/null +++ b/host/lib/usrp/usrp_e100/usrp_e_impl.cpp @@ -0,0 +1,201 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "usrp_e_impl.hpp" +#include "usrp_e_regs.hpp" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +using namespace uhd; +using namespace uhd::usrp; +namespace fs = boost::filesystem; + +/*********************************************************************** + * Helper Functions + **********************************************************************/ +static std::string abs_path(const std::string &file_path){ + return fs::system_complete(fs::path(file_path)).file_string(); +} + +/*********************************************************************** + * Discovery + **********************************************************************/ +static device_addrs_t usrp_e_find(const device_addr_t &hint){ + device_addrs_t usrp_e_addrs; + + //return an empty list of addresses when type is set to non-usrp-e + if (hint.has_key("type") and hint["type"] != "usrp-e") return usrp_e_addrs; + + //device node not provided, assume its 0 + if (not hint.has_key("node")){ + device_addr_t new_addr = hint; + new_addr["node"] = "/dev/usrp_e0"; + return usrp_e_find(new_addr); + } + + //use the given device node name + if (fs::exists(hint["node"])){ + device_addr_t new_addr; + new_addr["type"] = "usrp-e"; + new_addr["node"] = abs_path(hint["node"]); + usrp_e_addrs.push_back(new_addr); + } + + return usrp_e_addrs; +} + +/*********************************************************************** + * Make + **********************************************************************/ +static device::sptr usrp_e_make(const device_addr_t &device_addr){ + + //setup the main interface into fpga + std::string node = device_addr["node"]; + std::cout << boost::format("Opening USRP-E on %s") % node << std::endl; + usrp_e_iface::sptr iface = usrp_e_iface::make(node); + + //------------------------------------------------------------------ + //-- Handle the FPGA loading... + //-- The image can be confimed as already loaded when: + //-- 1) The compatibility number matches. + //-- 2) The hash in the hash-file matches. + //------------------------------------------------------------------ + static const char *hash_file_path = "/tmp/usrp_e100_hash"; + + //extract the fpga path for usrp-e + std::string usrp_e_fpga_image = find_image_path( + device_addr.has_key("fpga")? device_addr["fpga"] : "usrp_e100_fpga.bin" + ); + + //calculate a hash of the fpga file + size_t fpga_hash = 0; + { + std::ifstream file(usrp_e_fpga_image.c_str()); + if (not file.good()) throw std::runtime_error( + "cannot open fpga file for read: " + usrp_e_fpga_image + ); + do{ + boost::hash_combine(fpga_hash, file.get()); + } while (file.good()); + file.close(); + } + + //read the compatibility number + boost::uint16_t fpga_compat_num = iface->peek16(UE_REG_MISC_COMPAT); + + //read the hash in the hash-file + size_t loaded_hash = 0; + try{std::ifstream(hash_file_path) >> loaded_hash;}catch(...){} + + //if not loaded: load the fpga image and write the hash-file + if (fpga_compat_num != USRP_E_COMPAT_NUM or loaded_hash != fpga_hash){ + iface.reset(); + usrp_e_load_fpga(usrp_e_fpga_image); + std::cout << boost::format("re-Opening USRP-E on %s") % node << std::endl; + iface = usrp_e_iface::make(node); + try{std::ofstream(hash_file_path) << fpga_hash;}catch(...){} + } + + //check that the compatibility is correct + fpga_compat_num = iface->peek16(UE_REG_MISC_COMPAT); + if (fpga_compat_num != USRP_E_COMPAT_NUM){ + throw std::runtime_error(str(boost::format( + "Expected fpga compatibility number 0x%x, but got 0x%x:\n" + "The fpga build is not compatible with the host code build." + ) % USRP_E_COMPAT_NUM % fpga_compat_num)); + } + + return device::sptr(new usrp_e_impl(iface)); +} + +UHD_STATIC_BLOCK(register_usrp_e_device){ + device::register_device(&usrp_e_find, &usrp_e_make); +} + +/*********************************************************************** + * Structors + **********************************************************************/ +usrp_e_impl::usrp_e_impl(usrp_e_iface::sptr iface): _iface(iface){ + + //setup interfaces into hardware + _clock_ctrl = usrp_e_clock_ctrl::make(_iface); + _codec_ctrl = usrp_e_codec_ctrl::make(_iface); + + //initialize the mboard + mboard_init(); + + //initialize the dboards + dboard_init(); + + //initialize the dsps + rx_ddc_init(); + tx_duc_init(); + + //init the codec properties + codec_init(); + + //init the io send/recv + io_init(); + + //set default subdev specs + this->mboard_set(MBOARD_PROP_RX_SUBDEV_SPEC, subdev_spec_t()); + this->mboard_set(MBOARD_PROP_TX_SUBDEV_SPEC, subdev_spec_t()); +} + +usrp_e_impl::~usrp_e_impl(void){ + /* NOP */ +} + +/*********************************************************************** + * Device Get + **********************************************************************/ +void usrp_e_impl::get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case DEVICE_PROP_NAME: + val = std::string("usrp-e device"); + return; + + case DEVICE_PROP_MBOARD: + UHD_ASSERT_THROW(key.name == ""); + val = _mboard_proxy->get_link(); + return; + + case DEVICE_PROP_MBOARD_NAMES: + val = prop_names_t(1, ""); //vector of size 1 with empty string + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +/*********************************************************************** + * Device Set + **********************************************************************/ +void usrp_e_impl::set(const wax::obj &, const wax::obj &){ + UHD_THROW_PROP_SET_ERROR(); +} diff --git a/host/lib/usrp/usrp_e100/usrp_e_impl.hpp b/host/lib/usrp/usrp_e100/usrp_e_impl.hpp new file mode 100644 index 000000000..b5f21810d --- /dev/null +++ b/host/lib/usrp/usrp_e100/usrp_e_impl.hpp @@ -0,0 +1,164 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "usrp_e_iface.hpp" +#include "clock_ctrl.hpp" +#include "codec_ctrl.hpp" +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef INCLUDED_USRP_E_IMPL_HPP +#define INCLUDED_USRP_E_IMPL_HPP + +static const boost::uint16_t USRP_E_COMPAT_NUM = 0x02; + +//! load an fpga image from a bin file into the usrp-e fpga +extern void usrp_e_load_fpga(const std::string &bin_file); + +/*! + * Make a usrp-e dboard interface. + * \param iface the usrp-e interface object + * \param clock the clock control interface + * \param codec the codec control interface + * \return a sptr to a new dboard interface + */ +uhd::usrp::dboard_iface::sptr make_usrp_e_dboard_iface( + usrp_e_iface::sptr iface, + usrp_e_clock_ctrl::sptr clock, + usrp_e_codec_ctrl::sptr codec +); + +/*! + * Simple wax obj proxy class: + * Provides a wax obj interface for a set and a get function. + * This allows us to create nested properties structures + * while maintaining flattened code within the implementation. + */ +class wax_obj_proxy : public wax::obj{ +public: + typedef boost::function get_t; + typedef boost::function set_t; + typedef boost::shared_ptr sptr; + + static sptr make(const get_t &get, const set_t &set){ + return sptr(new wax_obj_proxy(get, set)); + } + +private: + get_t _get; set_t _set; + wax_obj_proxy(const get_t &get, const set_t &set): _get(get), _set(set){}; + void get(const wax::obj &key, wax::obj &val){return _get(key, val);} + void set(const wax::obj &key, const wax::obj &val){return _set(key, val);} +}; + +/*! + * USRP1E implementation guts: + * The implementation details are encapsulated here. + * Handles properties on the mboard, dboard, dsps... + */ +class usrp_e_impl : public uhd::device{ +public: + //structors + usrp_e_impl(usrp_e_iface::sptr); + ~usrp_e_impl(void); + + //the io interface + size_t send(const std::vector &, size_t, const uhd::tx_metadata_t &, const uhd::io_type_t &, send_mode_t, double); + size_t recv(const std::vector &, size_t, uhd::rx_metadata_t &, const uhd::io_type_t &, recv_mode_t, double); + bool recv_async_msg(uhd::async_metadata_t &, double); + size_t get_max_send_samps_per_packet(void) const; + size_t get_max_recv_samps_per_packet(void) const; + +private: + //interface to ioctls and file descriptor + usrp_e_iface::sptr _iface; + + //handle io stuff + UHD_PIMPL_DECL(io_impl) _io_impl; + uhd::otw_type_t _send_otw_type, _recv_otw_type; + void io_init(void); + void issue_stream_cmd(const uhd::stream_cmd_t &stream_cmd); + void handle_overrun(size_t); + + //configuration shadows + uhd::clock_config_t _clock_config; + //TODO otw type recv/send + + //ad9522 clock control + usrp_e_clock_ctrl::sptr _clock_ctrl; + + //ad9862 codec control + usrp_e_codec_ctrl::sptr _codec_ctrl; + + //device functions and settings + void get(const wax::obj &, wax::obj &); + void set(const wax::obj &, const wax::obj &); + + //mboard functions and settings + void mboard_init(void); + void mboard_get(const wax::obj &, wax::obj &); + void mboard_set(const wax::obj &, const wax::obj &); + wax_obj_proxy::sptr _mboard_proxy; + uhd::usrp::subdev_spec_t _rx_subdev_spec, _tx_subdev_spec; + + //xx dboard functions and settings + void dboard_init(void); + uhd::usrp::dboard_manager::sptr _dboard_manager; + uhd::usrp::dboard_iface::sptr _dboard_iface; + + //rx dboard functions and settings + uhd::usrp::dboard_eeprom_t _rx_db_eeprom; + void rx_dboard_get(const wax::obj &, wax::obj &); + void rx_dboard_set(const wax::obj &, const wax::obj &); + wax_obj_proxy::sptr _rx_dboard_proxy; + + //tx dboard functions and settings + uhd::usrp::dboard_eeprom_t _tx_db_eeprom; + void tx_dboard_get(const wax::obj &, wax::obj &); + void tx_dboard_set(const wax::obj &, const wax::obj &); + wax_obj_proxy::sptr _tx_dboard_proxy; + + //rx ddc functions and settings + void rx_ddc_init(void); + void rx_ddc_get(const wax::obj &, wax::obj &); + void rx_ddc_set(const wax::obj &, const wax::obj &); + double _ddc_freq; size_t _ddc_decim; + wax_obj_proxy::sptr _rx_ddc_proxy; + + //tx duc functions and settings + void tx_duc_init(void); + void tx_duc_get(const wax::obj &, wax::obj &); + void tx_duc_set(const wax::obj &, const wax::obj &); + double _duc_freq; size_t _duc_interp; + wax_obj_proxy::sptr _tx_duc_proxy; + + //codec functions and settings + void codec_init(void); + void rx_codec_get(const wax::obj &, wax::obj &); + void rx_codec_set(const wax::obj &, const wax::obj &); + void tx_codec_get(const wax::obj &, wax::obj &); + void tx_codec_set(const wax::obj &, const wax::obj &); + wax_obj_proxy::sptr _rx_codec_proxy, _tx_codec_proxy; +}; + +#endif /* INCLUDED_USRP_E_IMPL_HPP */ diff --git a/host/lib/usrp/usrp_e100/usrp_e_mmap_zero_copy.cpp b/host/lib/usrp/usrp_e100/usrp_e_mmap_zero_copy.cpp new file mode 100644 index 000000000..274bb043e --- /dev/null +++ b/host/lib/usrp/usrp_e100/usrp_e_mmap_zero_copy.cpp @@ -0,0 +1,215 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "usrp_e_iface.hpp" +#include +#include +#include +#include //mmap +#include //getpagesize +#include //poll +#include +#include +#include + +using namespace uhd; +using namespace uhd::transport; + +static const bool fp_verbose = false; //fast-path verbose +static const bool sp_verbose = false; //slow-path verbose +static const size_t poll_breakout = 10; //how many poll timeouts constitute a full timeout + +/*********************************************************************** + * The zero copy interface implementation + **********************************************************************/ +class usrp_e_mmap_zero_copy_impl : public zero_copy_if, public boost::enable_shared_from_this { +public: + usrp_e_mmap_zero_copy_impl(usrp_e_iface::sptr iface): + _fd(iface->get_file_descriptor()), _recv_index(0), _send_index(0) + { + //get system sizes + iface->ioctl(USRP_E_GET_RB_INFO, &_rb_size); + size_t page_size = getpagesize(); + _frame_size = page_size/2; + + //calculate the memory size + _map_size = + (_rb_size.num_pages_rx_flags + _rb_size.num_pages_tx_flags) * page_size + + (_rb_size.num_rx_frames + _rb_size.num_tx_frames) * _frame_size; + + //print sizes summary + if (sp_verbose){ + std::cout << "page_size: " << page_size << std::endl; + std::cout << "frame_size: " << _frame_size << std::endl; + std::cout << "num_pages_rx_flags: " << _rb_size.num_pages_rx_flags << std::endl; + std::cout << "num_rx_frames: " << _rb_size.num_rx_frames << std::endl; + std::cout << "num_pages_tx_flags: " << _rb_size.num_pages_tx_flags << std::endl; + std::cout << "num_tx_frames: " << _rb_size.num_tx_frames << std::endl; + std::cout << "map_size: " << _map_size << std::endl; + } + + //call mmap to get the memory + _mapped_mem = ::mmap( + NULL, _map_size, PROT_READ | PROT_WRITE, MAP_SHARED, _fd, 0 + ); + UHD_ASSERT_THROW(_mapped_mem != MAP_FAILED); + + //calculate the memory offsets for info and buffers + size_t recv_info_off = 0; + size_t recv_buff_off = recv_info_off + (_rb_size.num_pages_rx_flags * page_size); + size_t send_info_off = recv_buff_off + (_rb_size.num_rx_frames * _frame_size); + size_t send_buff_off = send_info_off + (_rb_size.num_pages_tx_flags * page_size); + + //print offset summary + if (sp_verbose){ + std::cout << "recv_info_off: " << recv_info_off << std::endl; + std::cout << "recv_buff_off: " << recv_buff_off << std::endl; + std::cout << "send_info_off: " << send_info_off << std::endl; + std::cout << "send_buff_off: " << send_buff_off << std::endl; + } + + //set the internal pointers for info and buffers + typedef ring_buffer_info (*rbi_pta)[]; + char *rb_ptr = reinterpret_cast(_mapped_mem); + _recv_info = reinterpret_cast(rb_ptr + recv_info_off); + _recv_buff = rb_ptr + recv_buff_off; + _send_info = reinterpret_cast(rb_ptr + send_info_off); + _send_buff = rb_ptr + send_buff_off; + } + + ~usrp_e_mmap_zero_copy_impl(void){ + if (sp_verbose) std::cout << "cleanup: munmap" << std::endl; + ::munmap(_mapped_mem, _map_size); + } + + managed_recv_buffer::sptr get_recv_buff(double timeout){ + if (fp_verbose) std::cout << "get_recv_buff: " << _recv_index << std::endl; + + //grab pointers to the info and buffer + ring_buffer_info *info = (*_recv_info) + _recv_index; + void *mem = _recv_buff + _frame_size*_recv_index; + + //poll/wait for a ready frame + if (not (info->flags & RB_USER)){ + for (size_t i = 0; i < poll_breakout; i++){ + pollfd pfd; + pfd.fd = _fd; + pfd.events = POLLIN; + ssize_t poll_ret = ::poll(&pfd, 1, size_t(timeout*1e3/poll_breakout)); + if (fp_verbose) std::cout << " POLLIN: " << poll_ret << std::endl; + if (poll_ret > 0) goto found_user_frame; //good poll, continue on + } + return managed_recv_buffer::sptr(); //timed-out for real + } found_user_frame: + + //the process has claimed the frame + info->flags = RB_USER_PROCESS; + + //increment the index for the next call + if (++_recv_index == size_t(_rb_size.num_rx_frames)) _recv_index = 0; + + //return the managed buffer for this frame + if (fp_verbose) std::cout << " make_recv_buff: " << info->len << std::endl; + return managed_recv_buffer::make_safe( + boost::asio::const_buffer(mem, info->len), + boost::bind(&usrp_e_mmap_zero_copy_impl::release, shared_from_this(), info) + ); + } + + size_t get_num_recv_frames(void) const{ + return _rb_size.num_rx_frames; + } + + size_t get_recv_frame_size(void) const{ + return _frame_size; + } + + managed_send_buffer::sptr get_send_buff(double timeout){ + if (fp_verbose) std::cout << "get_send_buff: " << _send_index << std::endl; + + //grab pointers to the info and buffer + ring_buffer_info *info = (*_send_info) + _send_index; + void *mem = _send_buff + _frame_size*_send_index; + + //poll/wait for a ready frame + if (not (info->flags & RB_KERNEL)){ + pollfd pfd; + pfd.fd = _fd; + pfd.events = POLLOUT; + ssize_t poll_ret = ::poll(&pfd, 1, size_t(timeout*1e3)); + if (fp_verbose) std::cout << " POLLOUT: " << poll_ret << std::endl; + if (poll_ret <= 0) return managed_send_buffer::sptr(); + } + + //increment the index for the next call + if (++_send_index == size_t(_rb_size.num_tx_frames)) _send_index = 0; + + //return the managed buffer for this frame + if (fp_verbose) std::cout << " make_send_buff: " << _frame_size << std::endl; + return managed_send_buffer::make_safe( + boost::asio::mutable_buffer(mem, _frame_size), + boost::bind(&usrp_e_mmap_zero_copy_impl::commit, shared_from_this(), info, _1) + ); + } + + size_t get_num_send_frames(void) const{ + return _rb_size.num_tx_frames; + } + + size_t get_send_frame_size(void) const{ + return _frame_size; + } + +private: + + void release(ring_buffer_info *info){ + if (fp_verbose) std::cout << "recv buff: release" << std::endl; + info->flags = RB_KERNEL; + } + + void commit(ring_buffer_info *info, size_t len){ + if (fp_verbose) std::cout << "send buff: commit " << len << std::endl; + info->len = len; + info->flags = RB_USER; + if (::write(_fd, NULL, 0) < 0){ + std::cerr << UHD_THROW_SITE_INFO("write error") << std::endl; + } + } + + int _fd; + + //the mapped memory itself + void *_mapped_mem; + + //mapped memory sizes + usrp_e_ring_buffer_size_t _rb_size; + size_t _frame_size, _map_size; + + //pointers to sections in the mapped memory + ring_buffer_info (*_recv_info)[], (*_send_info)[]; + char *_recv_buff, *_send_buff; + + //indexes into sub-sections of mapped memory + size_t _recv_index, _send_index; +}; + +/*********************************************************************** + * The zero copy interface make function + **********************************************************************/ +zero_copy_if::sptr usrp_e_make_mmap_zero_copy(usrp_e_iface::sptr iface){ + return zero_copy_if::sptr(new usrp_e_mmap_zero_copy_impl(iface)); +} diff --git a/host/lib/usrp/usrp_e100/usrp_e_regs.hpp b/host/lib/usrp/usrp_e100/usrp_e_regs.hpp new file mode 100644 index 000000000..8bfb08b6f --- /dev/null +++ b/host/lib/usrp/usrp_e100/usrp_e_regs.hpp @@ -0,0 +1,198 @@ + + +//////////////////////////////////////////////////////////////// +// +// Memory map for embedded wishbone bus +// +//////////////////////////////////////////////////////////////// + +// All addresses are byte addresses. All accesses are word (16-bit) accesses. +// This means that address bit 0 is usually 0. +// There are 11 bits of address for the control. + +#ifndef __USRP_E_REGS_H +#define __USRP_E_REGS_H + +///////////////////////////////////////////////////// +// Slave pointers + +#define UE_REG_SLAVE(n) ((n)<<7) +#define UE_REG_SR_ADDR(n) ((UE_REG_SLAVE(5)) + (4*(n))) + +///////////////////////////////////////////////////// +// Slave 0 -- Misc Regs + +#define UE_REG_MISC_BASE UE_REG_SLAVE(0) + +#define UE_REG_MISC_LED UE_REG_MISC_BASE + 0 +#define UE_REG_MISC_SW UE_REG_MISC_BASE + 2 +#define UE_REG_MISC_CGEN_CTRL UE_REG_MISC_BASE + 4 +#define UE_REG_MISC_CGEN_ST UE_REG_MISC_BASE + 6 +#define UE_REG_MISC_TEST UE_REG_MISC_BASE + 8 +#define UE_REG_MISC_RX_LEN UE_REG_MISC_BASE + 10 +#define UE_REG_MISC_TX_LEN UE_REG_MISC_BASE + 12 +#define UE_REG_MISC_XFER_RATE UE_REG_MISC_BASE + 14 +#define UE_REG_MISC_COMPAT UE_REG_MISC_BASE + 16 + +///////////////////////////////////////////////////// +// Slave 1 -- UART +// CLKDIV is 16 bits, others are only 8 + +#define UE_REG_UART_BASE UE_REG_SLAVE(1) + +#define UE_REG_UART_CLKDIV UE_REG_UART_BASE + 0 +#define UE_REG_UART_TXLEVEL UE_REG_UART_BASE + 2 +#define UE_REG_UART_RXLEVEL UE_REG_UART_BASE + 4 +#define UE_REG_UART_TXCHAR UE_REG_UART_BASE + 6 +#define UE_REG_UART_RXCHAR UE_REG_UART_BASE + 8 + +///////////////////////////////////////////////////// +// Slave 2 -- SPI Core +// This should be accessed through the IOCTL +// Users should not touch directly + +#define UE_REG_SPI_BASE UE_REG_SLAVE(2) + +//spi slave constants +#define UE_SPI_SS_AD9522 (1 << 3) +#define UE_SPI_SS_AD9862 (1 << 2) +#define UE_SPI_SS_TX_DB (1 << 1) +#define UE_SPI_SS_RX_DB (1 << 0) + +//////////////////////////////////////////////// +// Slave 3 -- I2C Core +// This should be accessed through the IOCTL +// Users should not touch directly + +#define UE_REG_I2C_BASE UE_REG_SLAVE(3) + + +//////////////////////////////////////////////// +// Slave 4 -- GPIO + +#define UE_REG_GPIO_BASE UE_REG_SLAVE(4) + +#define UE_REG_GPIO_RX_IO UE_REG_GPIO_BASE + 0 +#define UE_REG_GPIO_TX_IO UE_REG_GPIO_BASE + 2 +#define UE_REG_GPIO_RX_DDR UE_REG_GPIO_BASE + 4 +#define UE_REG_GPIO_TX_DDR UE_REG_GPIO_BASE + 6 +#define UE_REG_GPIO_RX_SEL UE_REG_GPIO_BASE + 8 +#define UE_REG_GPIO_TX_SEL UE_REG_GPIO_BASE + 10 +#define UE_REG_GPIO_RX_DBG UE_REG_GPIO_BASE + 12 +#define UE_REG_GPIO_TX_DBG UE_REG_GPIO_BASE + 14 + +//possible bit values for sel when dbg is 0: +#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg +#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic + +//possible bit values for sel when dbg is 1: +#define GPIO_SEL_DEBUG_0 0 // if pin is an output, debug lines from FPGA fabric +#define GPIO_SEL_DEBUG_1 1 // if pin is an output, debug lines from FPGA fabric + + +//////////////////////////////////////////////////// +// Slave 5 -- Settings Bus +// +// Output-only, no readback, 32 registers total +// Each register must be written 32 bits at a time +// First the address xxx_xx00 and then xxx_xx10 + +#define UE_REG_SETTINGS_BASE UE_REG_SLAVE(5) + +/////////////////////////////////////////////////// +// Slave 6 -- ATR Controller +// 16 regs + +#define UE_REG_ATR_BASE UE_REG_SLAVE(6) + +#define UE_REG_ATR_IDLE_RXSIDE UE_REG_ATR_BASE + 0 +#define UE_REG_ATR_IDLE_TXSIDE UE_REG_ATR_BASE + 2 +#define UE_REG_ATR_INTX_RXSIDE UE_REG_ATR_BASE + 4 +#define UE_REG_ATR_INTX_TXSIDE UE_REG_ATR_BASE + 6 +#define UE_REG_ATR_INRX_RXSIDE UE_REG_ATR_BASE + 8 +#define UE_REG_ATR_INRX_TXSIDE UE_REG_ATR_BASE + 10 +#define UE_REG_ATR_FULL_RXSIDE UE_REG_ATR_BASE + 12 +#define UE_REG_ATR_FULL_TXSIDE UE_REG_ATR_BASE + 14 + +///////////////////////////////////////////////// +// DSP RX Regs +//////////////////////////////////////////////// +#define UE_REG_DSP_RX_FREQ UE_REG_SR_ADDR(0) +#define UE_REG_DSP_RX_SCALE_IQ UE_REG_SR_ADDR(1) // {scale_i,scale_q} +#define UE_REG_DSP_RX_DECIM_RATE UE_REG_SR_ADDR(2) // hb and decim rate +#define UE_REG_DSP_RX_DCOFFSET_I UE_REG_SR_ADDR(3) // Bit 31 high sets fixed offset mode, using lower 14 bits, // otherwise it is automatic +#define UE_REG_DSP_RX_DCOFFSET_Q UE_REG_SR_ADDR(4) // Bit 31 high sets fixed offset mode, using lower 14 bits +#define UE_REG_DSP_RX_MUX UE_REG_SR_ADDR(5) + +/////////////////////////////////////////////////// +// VITA RX CTRL regs +/////////////////////////////////////////////////// +// The following 3 are logically a single command register. +// They are clocked into the underlying fifo when time_ticks is written. +#define UE_REG_CTRL_RX_STREAM_CMD UE_REG_SR_ADDR(8) // {now, chain, num_samples(30) +#define UE_REG_CTRL_RX_TIME_SECS UE_REG_SR_ADDR(9) +#define UE_REG_CTRL_RX_TIME_TICKS UE_REG_SR_ADDR(10) +#define UE_REG_CTRL_RX_CLEAR_OVERRUN UE_REG_SR_ADDR(11) // write anything to clear overrun +#define UE_REG_CTRL_RX_VRT_HEADER UE_REG_SR_ADDR(12) // word 0 of packet. FPGA fills in packet counter +#define UE_REG_CTRL_RX_VRT_STREAM_ID UE_REG_SR_ADDR(13) // word 1 of packet. +#define UE_REG_CTRL_RX_VRT_TRAILER UE_REG_SR_ADDR(14) +#define UE_REG_CTRL_RX_NSAMPS_PER_PKT UE_REG_SR_ADDR(15) +#define UE_REG_CTRL_RX_NCHANNELS UE_REG_SR_ADDR(16) // 1 in basic case, up to 4 for vector sources + +///////////////////////////////////////////////// +// DSP TX Regs +//////////////////////////////////////////////// +#define UE_REG_DSP_TX_FREQ UE_REG_SR_ADDR(17) +#define UE_REG_DSP_TX_SCALE_IQ UE_REG_SR_ADDR(18) // {scale_i,scale_q} +#define UE_REG_DSP_TX_INTERP_RATE UE_REG_SR_ADDR(19) +#define UE_REG_DSP_TX_UNUSED UE_REG_SR_ADDR(20) +#define UE_REG_DSP_TX_MUX UE_REG_SR_ADDR(21) + +///////////////////////////////////////////////// +// VITA TX CTRL regs +//////////////////////////////////////////////// +#define UE_REG_CTRL_TX_NCHANNELS UE_REG_SR_ADDR(24) +#define UE_REG_CTRL_TX_CLEAR_UNDERRUN UE_REG_SR_ADDR(25) +#define UE_REG_CTRL_TX_REPORT_SID UE_REG_SR_ADDR(26) +#define UE_REG_CTRL_TX_POLICY UE_REG_SR_ADDR(27) + +#define UE_FLAG_CTRL_TX_POLICY_WAIT (0x1 << 0) +#define UE_FLAG_CTRL_TX_POLICY_NEXT_PACKET (0x1 << 1) +#define UE_FLAG_CTRL_TX_POLICY_NEXT_BURST (0x1 << 2) + +///////////////////////////////////////////////// +// VITA49 64 bit time (write only) +//////////////////////////////////////////////// + /*! + * \brief Time 64 flags + * + * 
+   *
+   *    3                   2                   1
+   *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   * +-----------------------------------------------------------+-+-+
+   * |                                                           |S|P|
+   * +-----------------------------------------------------------+-+-+
+   *
+   * P - PPS edge selection (0=negedge, 1=posedge, default=0)
+   * S - Source (0=sma, 1=mimo, 0=default)
+   *
+   *
+ */ +#define UE_REG_TIME64_SECS UE_REG_SR_ADDR(28) // value to set absolute secs to on next PPS +#define UE_REG_TIME64_TICKS UE_REG_SR_ADDR(29) // value to set absolute ticks to on next PPS +#define UE_REG_TIME64_FLAGS UE_REG_SR_ADDR(30) // flags - see chart above +#define UE_REG_TIME64_IMM UE_REG_SR_ADDR(31) // set immediate (0=latch on next pps, 1=latch immediate, default=0) +#define UE_REG_TIME64_TPS UE_REG_SR_ADDR(31) // clock ticks per second (counter rollover) + +//pps flags (see above) +#define UE_FLAG_TIME64_PPS_NEGEDGE (0 << 0) +#define UE_FLAG_TIME64_PPS_POSEDGE (1 << 0) +#define UE_FLAG_TIME64_PPS_SMA (0 << 1) +#define UE_FLAG_TIME64_PPS_MIMO (1 << 1) + +#define UE_FLAG_TIME64_LATCH_NOW 1 +#define UE_FLAG_TIME64_LATCH_NEXT_PPS 0 + +#endif + -- cgit v1.2.3 From 5f2c71383a2b5dd0f2f469f6ad8c4720358f2a12 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 9 Nov 2010 19:02:11 -0800 Subject: usrp-e100: renamed files and classes in usrp-e100 to e100 name --- host/lib/usrp/usrp_e100/CMakeLists.txt | 12 +- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 14 +- host/lib/usrp/usrp_e100/clock_ctrl.hpp | 16 +- host/lib/usrp/usrp_e100/codec_ctrl.cpp | 38 ++-- host/lib/usrp/usrp_e100/codec_ctrl.hpp | 16 +- host/lib/usrp/usrp_e100/codec_impl.cpp | 24 +-- host/lib/usrp/usrp_e100/dboard_iface.cpp | 86 ++++----- host/lib/usrp/usrp_e100/dboard_impl.cpp | 24 +-- host/lib/usrp/usrp_e100/dsp_impl.cpp | 24 +-- host/lib/usrp/usrp_e100/fpga-downloader.cc | 2 +- host/lib/usrp/usrp_e100/io_impl.cpp | 38 ++-- host/lib/usrp/usrp_e100/mboard_impl.cpp | 14 +- host/lib/usrp/usrp_e100/usrp_e100_iface.cpp | 194 +++++++++++++++++++ host/lib/usrp/usrp_e100/usrp_e100_iface.hpp | 112 +++++++++++ host/lib/usrp/usrp_e100/usrp_e100_impl.cpp | 201 +++++++++++++++++++ host/lib/usrp/usrp_e100/usrp_e100_impl.hpp | 164 ++++++++++++++++ .../usrp/usrp_e100/usrp_e100_mmap_zero_copy.cpp | 215 +++++++++++++++++++++ host/lib/usrp/usrp_e100/usrp_e100_regs.hpp | 198 +++++++++++++++++++ host/lib/usrp/usrp_e100/usrp_e_iface.cpp | 194 ------------------- host/lib/usrp/usrp_e100/usrp_e_iface.hpp | 112 ----------- host/lib/usrp/usrp_e100/usrp_e_impl.cpp | 201 ------------------- host/lib/usrp/usrp_e100/usrp_e_impl.hpp | 164 ---------------- host/lib/usrp/usrp_e100/usrp_e_mmap_zero_copy.cpp | 215 --------------------- host/lib/usrp/usrp_e100/usrp_e_regs.hpp | 198 ------------------- 24 files changed, 1238 insertions(+), 1238 deletions(-) create mode 100644 host/lib/usrp/usrp_e100/usrp_e100_iface.cpp create mode 100644 host/lib/usrp/usrp_e100/usrp_e100_iface.hpp create mode 100644 host/lib/usrp/usrp_e100/usrp_e100_impl.cpp create mode 100644 host/lib/usrp/usrp_e100/usrp_e100_impl.hpp create mode 100644 host/lib/usrp/usrp_e100/usrp_e100_mmap_zero_copy.cpp create mode 100644 host/lib/usrp/usrp_e100/usrp_e100_regs.hpp delete mode 100644 host/lib/usrp/usrp_e100/usrp_e_iface.cpp delete mode 100644 host/lib/usrp/usrp_e100/usrp_e_iface.hpp delete mode 100644 host/lib/usrp/usrp_e100/usrp_e_impl.cpp delete mode 100644 host/lib/usrp/usrp_e100/usrp_e_impl.hpp delete mode 100644 host/lib/usrp/usrp_e100/usrp_e_mmap_zero_copy.cpp delete mode 100644 host/lib/usrp/usrp_e100/usrp_e_regs.hpp diff --git a/host/lib/usrp/usrp_e100/CMakeLists.txt b/host/lib/usrp/usrp_e100/CMakeLists.txt index 17ef53152..97a3d5d9a 100644 --- a/host/lib/usrp/usrp_e100/CMakeLists.txt +++ b/host/lib/usrp/usrp_e100/CMakeLists.txt @@ -52,12 +52,12 @@ IF(ENABLE_USRP_E100) ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/fpga-downloader.cc ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/io_impl.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/mboard_impl.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e_impl.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e_impl.hpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e_iface.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e_iface.hpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e_mmap_zero_copy.cpp - ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e_regs.hpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e100_impl.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e100_impl.hpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e100_iface.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e100_iface.hpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e100_mmap_zero_copy.cpp + ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/usrp_e100_regs.hpp ) ELSE(ENABLE_USRP_E100) MESSAGE(STATUS " Skipping USRP-E100 support.") diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index 9d4625305..e99560540 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -19,7 +19,7 @@ #include "ad9522_regs.hpp" #include #include -#include "usrp_e_regs.hpp" //spi slave constants +#include "usrp_e100_regs.hpp" //spi slave constants #include #include #include @@ -58,9 +58,9 @@ static const size_t codec_clock_divider = size_t(master_clock_rate/64e6); /*********************************************************************** * Clock Control Implementation **********************************************************************/ -class usrp_e_clock_ctrl_impl : public usrp_e_clock_ctrl{ +class usrp_e100_clock_ctrl_impl : public usrp_e100_clock_ctrl{ public: - usrp_e_clock_ctrl_impl(usrp_e_iface::sptr iface){ + usrp_e100_clock_ctrl_impl(usrp_e100_iface::sptr iface){ _iface = iface; //init the clock gen registers @@ -137,7 +137,7 @@ public: this->enable_tx_dboard_clock(false); } - ~usrp_e_clock_ctrl_impl(void){ + ~usrp_e100_clock_ctrl_impl(void){ this->enable_rx_dboard_clock(false); this->enable_tx_dboard_clock(false); } @@ -210,7 +210,7 @@ public: } private: - usrp_e_iface::sptr _iface; + usrp_e100_iface::sptr _iface; ad9522_regs_t _ad9522_regs; void latch_regs(void){ @@ -232,6 +232,6 @@ private: /*********************************************************************** * Clock Control Make **********************************************************************/ -usrp_e_clock_ctrl::sptr usrp_e_clock_ctrl::make(usrp_e_iface::sptr iface){ - return sptr(new usrp_e_clock_ctrl_impl(iface)); +usrp_e100_clock_ctrl::sptr usrp_e100_clock_ctrl::make(usrp_e100_iface::sptr iface){ + return sptr(new usrp_e100_clock_ctrl_impl(iface)); } diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.hpp b/host/lib/usrp/usrp_e100/clock_ctrl.hpp index 3b5103ed1..0ae68728e 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.hpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.hpp @@ -15,10 +15,10 @@ // along with this program. If not, see . // -#ifndef INCLUDED_USRP_E_CLOCK_CTRL_HPP -#define INCLUDED_USRP_E_CLOCK_CTRL_HPP +#ifndef INCLUDED_USRP_E100_CLOCK_CTRL_HPP +#define INCLUDED_USRP_E100_CLOCK_CTRL_HPP -#include "usrp_e_iface.hpp" +#include "usrp_e100_iface.hpp" #include #include #include @@ -28,16 +28,16 @@ * - Setup system clocks. * - Disable/enable clock lines. */ -class usrp_e_clock_ctrl : boost::noncopyable{ +class usrp_e100_clock_ctrl : boost::noncopyable{ public: - typedef boost::shared_ptr sptr; + typedef boost::shared_ptr sptr; /*! * Make a new clock control object. - * \param iface the usrp_e iface object + * \param iface the usrp_e100 iface object * \return the clock control object */ - static sptr make(usrp_e_iface::sptr iface); + static sptr make(usrp_e100_iface::sptr iface); /*! * Get the rate of the fpga clock line. @@ -85,4 +85,4 @@ public: }; -#endif /* INCLUDED_USRP_E_CLOCK_CTRL_HPP */ +#endif /* INCLUDED_USRP_E100_CLOCK_CTRL_HPP */ diff --git a/host/lib/usrp/usrp_e100/codec_ctrl.cpp b/host/lib/usrp/usrp_e100/codec_ctrl.cpp index a728d7e46..e7fd9792e 100644 --- a/host/lib/usrp/usrp_e100/codec_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/codec_ctrl.cpp @@ -23,7 +23,7 @@ #include #include #include -#include "usrp_e_regs.hpp" //spi slave constants +#include "usrp_e100_regs.hpp" //spi slave constants #include #include @@ -31,17 +31,17 @@ using namespace uhd; static const bool codec_debug = false; -const gain_range_t usrp_e_codec_ctrl::tx_pga_gain_range(-20, 0, float(0.1)); -const gain_range_t usrp_e_codec_ctrl::rx_pga_gain_range(0, 20, 1); +const gain_range_t usrp_e100_codec_ctrl::tx_pga_gain_range(-20, 0, float(0.1)); +const gain_range_t usrp_e100_codec_ctrl::rx_pga_gain_range(0, 20, 1); /*********************************************************************** * Codec Control Implementation **********************************************************************/ -class usrp_e_codec_ctrl_impl : public usrp_e_codec_ctrl{ +class usrp_e100_codec_ctrl_impl : public usrp_e100_codec_ctrl{ public: //structors - usrp_e_codec_ctrl_impl(usrp_e_iface::sptr iface); - ~usrp_e_codec_ctrl_impl(void); + usrp_e100_codec_ctrl_impl(usrp_e100_iface::sptr iface); + ~usrp_e100_codec_ctrl_impl(void); //aux adc and dac control float read_aux_adc(aux_adc_t which); @@ -54,7 +54,7 @@ public: float get_rx_pga_gain(char); private: - usrp_e_iface::sptr _iface; + usrp_e100_iface::sptr _iface; ad9862_regs_t _ad9862_regs; aux_adc_t _last_aux_adc_a, _last_aux_adc_b; void send_reg(boost::uint8_t addr); @@ -64,7 +64,7 @@ private: /*********************************************************************** * Codec Control Structors **********************************************************************/ -usrp_e_codec_ctrl_impl::usrp_e_codec_ctrl_impl(usrp_e_iface::sptr iface){ +usrp_e100_codec_ctrl_impl::usrp_e100_codec_ctrl_impl(usrp_e100_iface::sptr iface){ _iface = iface; //soft reset @@ -115,7 +115,7 @@ usrp_e_codec_ctrl_impl::usrp_e_codec_ctrl_impl(usrp_e_iface::sptr iface){ this->send_reg(34); } -usrp_e_codec_ctrl_impl::~usrp_e_codec_ctrl_impl(void){ +usrp_e100_codec_ctrl_impl::~usrp_e100_codec_ctrl_impl(void){ //set aux dacs to zero this->write_aux_dac(AUX_DAC_A, 0); this->write_aux_dac(AUX_DAC_B, 0); @@ -135,19 +135,19 @@ usrp_e_codec_ctrl_impl::~usrp_e_codec_ctrl_impl(void){ **********************************************************************/ static const int mtpgw = 255; //maximum tx pga gain word -void usrp_e_codec_ctrl_impl::set_tx_pga_gain(float gain){ +void usrp_e100_codec_ctrl_impl::set_tx_pga_gain(float gain){ int gain_word = int(mtpgw*(gain - tx_pga_gain_range.min)/(tx_pga_gain_range.max - tx_pga_gain_range.min)); _ad9862_regs.tx_pga_gain = std::clip(gain_word, 0, mtpgw); this->send_reg(16); } -float usrp_e_codec_ctrl_impl::get_tx_pga_gain(void){ +float usrp_e100_codec_ctrl_impl::get_tx_pga_gain(void){ return (_ad9862_regs.tx_pga_gain*(tx_pga_gain_range.max - tx_pga_gain_range.min)/mtpgw) + tx_pga_gain_range.min; } static const int mrpgw = 0x14; //maximum rx pga gain word -void usrp_e_codec_ctrl_impl::set_rx_pga_gain(float gain, char which){ +void usrp_e100_codec_ctrl_impl::set_rx_pga_gain(float gain, char which){ int gain_word = int(mrpgw*(gain - rx_pga_gain_range.min)/(rx_pga_gain_range.max - rx_pga_gain_range.min)); gain_word = std::clip(gain_word, 0, mrpgw); switch(which){ @@ -163,7 +163,7 @@ void usrp_e_codec_ctrl_impl::set_rx_pga_gain(float gain, char which){ } } -float usrp_e_codec_ctrl_impl::get_rx_pga_gain(char which){ +float usrp_e100_codec_ctrl_impl::get_rx_pga_gain(char which){ int gain_word; switch(which){ case 'A': gain_word = _ad9862_regs.rx_pga_a; break; @@ -180,7 +180,7 @@ static float aux_adc_to_volts(boost::uint8_t high, boost::uint8_t low){ return float((boost::uint16_t(high) << 2) | low)*3.3/0x3ff; } -float usrp_e_codec_ctrl_impl::read_aux_adc(aux_adc_t which){ +float usrp_e100_codec_ctrl_impl::read_aux_adc(aux_adc_t which){ //check to see if the switch needs to be set bool write_switch = false; switch(which){ @@ -233,7 +233,7 @@ float usrp_e_codec_ctrl_impl::read_aux_adc(aux_adc_t which){ /*********************************************************************** * Codec Control AUX DAC Methods **********************************************************************/ -void usrp_e_codec_ctrl_impl::write_aux_dac(aux_dac_t which, float volts){ +void usrp_e100_codec_ctrl_impl::write_aux_dac(aux_dac_t which, float volts){ //special case for aux dac d (aka sigma delta word) if (which == AUX_DAC_D){ boost::uint16_t dac_word = std::clip(boost::math::iround(volts*0xfff/3.3), 0, 0xfff); @@ -266,7 +266,7 @@ void usrp_e_codec_ctrl_impl::write_aux_dac(aux_dac_t which, float volts){ /*********************************************************************** * Codec Control SPI Methods **********************************************************************/ -void usrp_e_codec_ctrl_impl::send_reg(boost::uint8_t addr){ +void usrp_e100_codec_ctrl_impl::send_reg(boost::uint8_t addr){ boost::uint32_t reg = _ad9862_regs.get_write_reg(addr); if (codec_debug) std::cout << "codec control write reg: " << std::hex << reg << std::endl; _iface->transact_spi( @@ -276,7 +276,7 @@ void usrp_e_codec_ctrl_impl::send_reg(boost::uint8_t addr){ ); } -void usrp_e_codec_ctrl_impl::recv_reg(boost::uint8_t addr){ +void usrp_e100_codec_ctrl_impl::recv_reg(boost::uint8_t addr){ boost::uint32_t reg = _ad9862_regs.get_read_reg(addr); if (codec_debug) std::cout << "codec control read reg: " << std::hex << reg << std::endl; boost::uint32_t ret = _iface->transact_spi( @@ -291,6 +291,6 @@ void usrp_e_codec_ctrl_impl::recv_reg(boost::uint8_t addr){ /*********************************************************************** * Codec Control Make **********************************************************************/ -usrp_e_codec_ctrl::sptr usrp_e_codec_ctrl::make(usrp_e_iface::sptr iface){ - return sptr(new usrp_e_codec_ctrl_impl(iface)); +usrp_e100_codec_ctrl::sptr usrp_e100_codec_ctrl::make(usrp_e100_iface::sptr iface){ + return sptr(new usrp_e100_codec_ctrl_impl(iface)); } diff --git a/host/lib/usrp/usrp_e100/codec_ctrl.hpp b/host/lib/usrp/usrp_e100/codec_ctrl.hpp index 87b6ff951..74ce9bd9a 100644 --- a/host/lib/usrp/usrp_e100/codec_ctrl.hpp +++ b/host/lib/usrp/usrp_e100/codec_ctrl.hpp @@ -15,10 +15,10 @@ // along with this program. If not, see . // -#ifndef INCLUDED_USRP_E_CODEC_CTRL_HPP -#define INCLUDED_USRP_E_CODEC_CTRL_HPP +#ifndef INCLUDED_USRP_E100_CODEC_CTRL_HPP +#define INCLUDED_USRP_E100_CODEC_CTRL_HPP -#include "usrp_e_iface.hpp" +#include "usrp_e100_iface.hpp" #include #include #include @@ -28,19 +28,19 @@ * - Init/power down codec. * - Read aux adc, write aux dac. */ -class usrp_e_codec_ctrl : boost::noncopyable{ +class usrp_e100_codec_ctrl : boost::noncopyable{ public: - typedef boost::shared_ptr sptr; + typedef boost::shared_ptr sptr; static const uhd::gain_range_t tx_pga_gain_range; static const uhd::gain_range_t rx_pga_gain_range; /*! * Make a new codec control object. - * \param iface the usrp_e iface object + * \param iface the usrp_e100 iface object * \return the codec control object */ - static sptr make(usrp_e_iface::sptr iface); + static sptr make(usrp_e100_iface::sptr iface); //! aux adc identifier constants enum aux_adc_t{ @@ -87,4 +87,4 @@ public: virtual float get_rx_pga_gain(char which) = 0; }; -#endif /* INCLUDED_USRP_E_CODEC_CTRL_HPP */ +#endif /* INCLUDED_USRP_E100_CODEC_CTRL_HPP */ diff --git a/host/lib/usrp/usrp_e100/codec_impl.cpp b/host/lib/usrp/usrp_e100/codec_impl.cpp index 696fb37ec..6fd44bad3 100644 --- a/host/lib/usrp/usrp_e100/codec_impl.cpp +++ b/host/lib/usrp/usrp_e100/codec_impl.cpp @@ -15,7 +15,7 @@ // along with this program. If not, see . // -#include "usrp_e_impl.hpp" +#include "usrp_e100_impl.hpp" #include #include #include @@ -26,15 +26,15 @@ using namespace uhd::usrp; /*********************************************************************** * Helper Methods **********************************************************************/ -void usrp_e_impl::codec_init(void){ +void usrp_e100_impl::codec_init(void){ //make proxies _rx_codec_proxy = wax_obj_proxy::make( - boost::bind(&usrp_e_impl::rx_codec_get, this, _1, _2), - boost::bind(&usrp_e_impl::rx_codec_set, this, _1, _2) + boost::bind(&usrp_e100_impl::rx_codec_get, this, _1, _2), + boost::bind(&usrp_e100_impl::rx_codec_set, this, _1, _2) ); _tx_codec_proxy = wax_obj_proxy::make( - boost::bind(&usrp_e_impl::tx_codec_get, this, _1, _2), - boost::bind(&usrp_e_impl::tx_codec_set, this, _1, _2) + boost::bind(&usrp_e100_impl::tx_codec_get, this, _1, _2), + boost::bind(&usrp_e100_impl::tx_codec_set, this, _1, _2) ); } @@ -43,7 +43,7 @@ void usrp_e_impl::codec_init(void){ **********************************************************************/ static const std::string ad9862_pga_gain_name = "ad9862 pga"; -void usrp_e_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){ +void usrp_e100_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){ named_prop_t key = named_prop_t::extract(key_); //handle the get request conditioned on the key @@ -62,7 +62,7 @@ void usrp_e_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){ case CODEC_PROP_GAIN_RANGE: UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); - val = usrp_e_codec_ctrl::rx_pga_gain_range; + val = usrp_e100_codec_ctrl::rx_pga_gain_range; return; case CODEC_PROP_GAIN_I: @@ -79,7 +79,7 @@ void usrp_e_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){ } } -void usrp_e_impl::rx_codec_set(const wax::obj &key_, const wax::obj &val){ +void usrp_e100_impl::rx_codec_set(const wax::obj &key_, const wax::obj &val){ named_prop_t key = named_prop_t::extract(key_); //handle the set request conditioned on the key @@ -101,7 +101,7 @@ void usrp_e_impl::rx_codec_set(const wax::obj &key_, const wax::obj &val){ /*********************************************************************** * TX Codec Properties **********************************************************************/ -void usrp_e_impl::tx_codec_get(const wax::obj &key_, wax::obj &val){ +void usrp_e100_impl::tx_codec_get(const wax::obj &key_, wax::obj &val){ named_prop_t key = named_prop_t::extract(key_); //handle the get request conditioned on the key @@ -120,7 +120,7 @@ void usrp_e_impl::tx_codec_get(const wax::obj &key_, wax::obj &val){ case CODEC_PROP_GAIN_RANGE: UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name); - val = usrp_e_codec_ctrl::tx_pga_gain_range; + val = usrp_e100_codec_ctrl::tx_pga_gain_range; return; case CODEC_PROP_GAIN_I: //only one gain for I and Q @@ -133,7 +133,7 @@ void usrp_e_impl::tx_codec_get(const wax::obj &key_, wax::obj &val){ } } -void usrp_e_impl::tx_codec_set(const wax::obj &key_, const wax::obj &val){ +void usrp_e100_impl::tx_codec_set(const wax::obj &key_, const wax::obj &val){ named_prop_t key = named_prop_t::extract(key_); //handle the set request conditioned on the key diff --git a/host/lib/usrp/usrp_e100/dboard_iface.cpp b/host/lib/usrp/usrp_e100/dboard_iface.cpp index 6898df8df..aa96171d6 100644 --- a/host/lib/usrp/usrp_e100/dboard_iface.cpp +++ b/host/lib/usrp/usrp_e100/dboard_iface.cpp @@ -15,8 +15,8 @@ // along with this program. If not, see . // -#include "usrp_e_iface.hpp" -#include "usrp_e_regs.hpp" +#include "usrp_e100_iface.hpp" +#include "usrp_e100_regs.hpp" #include "clock_ctrl.hpp" #include "codec_ctrl.hpp" #include @@ -29,13 +29,13 @@ using namespace uhd; using namespace uhd::usrp; using namespace boost::assign; -class usrp_e_dboard_iface : public dboard_iface{ +class usrp_e100_dboard_iface : public dboard_iface{ public: - usrp_e_dboard_iface( - usrp_e_iface::sptr iface, - usrp_e_clock_ctrl::sptr clock, - usrp_e_codec_ctrl::sptr codec + usrp_e100_dboard_iface( + usrp_e100_iface::sptr iface, + usrp_e100_clock_ctrl::sptr clock, + usrp_e100_codec_ctrl::sptr codec ){ _iface = iface; _clock = clock; @@ -49,7 +49,7 @@ public: _iface->poke16(UE_REG_GPIO_TX_DBG, 0); } - ~usrp_e_dboard_iface(void){ + ~usrp_e100_dboard_iface(void){ /* NOP */ } @@ -94,27 +94,27 @@ public: double get_codec_rate(unit_t); private: - usrp_e_iface::sptr _iface; - usrp_e_clock_ctrl::sptr _clock; - usrp_e_codec_ctrl::sptr _codec; + usrp_e100_iface::sptr _iface; + usrp_e100_clock_ctrl::sptr _clock; + usrp_e100_codec_ctrl::sptr _codec; uhd::dict _clock_rates; }; /*********************************************************************** * Make Function **********************************************************************/ -dboard_iface::sptr make_usrp_e_dboard_iface( - usrp_e_iface::sptr iface, - usrp_e_clock_ctrl::sptr clock, - usrp_e_codec_ctrl::sptr codec +dboard_iface::sptr make_usrp_e100_dboard_iface( + usrp_e100_iface::sptr iface, + usrp_e100_clock_ctrl::sptr clock, + usrp_e100_codec_ctrl::sptr codec ){ - return dboard_iface::sptr(new usrp_e_dboard_iface(iface, clock, codec)); + return dboard_iface::sptr(new usrp_e100_dboard_iface(iface, clock, codec)); } /*********************************************************************** * Clock Rates **********************************************************************/ -void usrp_e_dboard_iface::set_clock_rate(unit_t unit, double rate){ +void usrp_e100_dboard_iface::set_clock_rate(unit_t unit, double rate){ _clock_rates[unit] = rate; switch(unit){ case UNIT_RX: return _clock->set_rx_dboard_clock_rate(rate); @@ -122,7 +122,7 @@ void usrp_e_dboard_iface::set_clock_rate(unit_t unit, double rate){ } } -std::vector usrp_e_dboard_iface::get_clock_rates(unit_t unit){ +std::vector usrp_e100_dboard_iface::get_clock_rates(unit_t unit){ switch(unit){ case UNIT_RX: return _clock->get_rx_dboard_clock_rates(); case UNIT_TX: return _clock->get_tx_dboard_clock_rates(); @@ -130,25 +130,25 @@ std::vector usrp_e_dboard_iface::get_clock_rates(unit_t unit){ } } -double usrp_e_dboard_iface::get_clock_rate(unit_t unit){ +double usrp_e100_dboard_iface::get_clock_rate(unit_t unit){ return _clock_rates[unit]; } -void usrp_e_dboard_iface::set_clock_enabled(unit_t unit, bool enb){ +void usrp_e100_dboard_iface::set_clock_enabled(unit_t unit, bool enb){ switch(unit){ case UNIT_RX: return _clock->enable_rx_dboard_clock(enb); case UNIT_TX: return _clock->enable_tx_dboard_clock(enb); } } -double usrp_e_dboard_iface::get_codec_rate(unit_t){ +double usrp_e100_dboard_iface::get_codec_rate(unit_t){ return _clock->get_fpga_clock_rate(); } /*********************************************************************** * GPIO **********************************************************************/ -void usrp_e_dboard_iface::set_pin_ctrl(unit_t unit, boost::uint16_t value){ +void usrp_e100_dboard_iface::set_pin_ctrl(unit_t unit, boost::uint16_t value){ UHD_ASSERT_THROW(GPIO_SEL_ATR == 1); //make this assumption switch(unit){ case UNIT_RX: _iface->poke16(UE_REG_GPIO_RX_SEL, value); return; @@ -156,21 +156,21 @@ void usrp_e_dboard_iface::set_pin_ctrl(unit_t unit, boost::uint16_t value){ } } -void usrp_e_dboard_iface::set_gpio_ddr(unit_t unit, boost::uint16_t value){ +void usrp_e100_dboard_iface::set_gpio_ddr(unit_t unit, boost::uint16_t value){ switch(unit){ case UNIT_RX: _iface->poke16(UE_REG_GPIO_RX_DDR, value); return; case UNIT_TX: _iface->poke16(UE_REG_GPIO_TX_DDR, value); return; } } -void usrp_e_dboard_iface::write_gpio(unit_t unit, boost::uint16_t value){ +void usrp_e100_dboard_iface::write_gpio(unit_t unit, boost::uint16_t value){ switch(unit){ case UNIT_RX: _iface->poke16(UE_REG_GPIO_RX_IO, value); return; case UNIT_TX: _iface->poke16(UE_REG_GPIO_TX_IO, value); return; } } -boost::uint16_t usrp_e_dboard_iface::read_gpio(unit_t unit){ +boost::uint16_t usrp_e100_dboard_iface::read_gpio(unit_t unit){ switch(unit){ case UNIT_RX: return _iface->peek16(UE_REG_GPIO_RX_IO); case UNIT_TX: return _iface->peek16(UE_REG_GPIO_TX_IO); @@ -178,7 +178,7 @@ boost::uint16_t usrp_e_dboard_iface::read_gpio(unit_t unit){ } } -void usrp_e_dboard_iface::set_atr_reg(unit_t unit, atr_reg_t atr, boost::uint16_t value){ +void usrp_e100_dboard_iface::set_atr_reg(unit_t unit, atr_reg_t atr, boost::uint16_t value){ //define mapping of unit to atr regs to register address static const uhd::dict< unit_t, uhd::dict @@ -199,7 +199,7 @@ void usrp_e_dboard_iface::set_atr_reg(unit_t unit, atr_reg_t atr, boost::uint16_ _iface->poke16(unit_to_atr_to_addr[unit][atr], value); } -void usrp_e_dboard_iface::set_gpio_debug(unit_t unit, int which){ +void usrp_e100_dboard_iface::set_gpio_debug(unit_t unit, int which){ //set this unit to all outputs this->set_gpio_ddr(unit, 0xffff); @@ -238,7 +238,7 @@ static boost::uint32_t unit_to_otw_spi_dev(dboard_iface::unit_t unit){ throw std::invalid_argument("unknown unit type"); } -void usrp_e_dboard_iface::write_spi( +void usrp_e100_dboard_iface::write_spi( unit_t unit, const spi_config_t &config, boost::uint32_t data, @@ -247,7 +247,7 @@ void usrp_e_dboard_iface::write_spi( _iface->transact_spi(unit_to_otw_spi_dev(unit), config, data, num_bits, false /*no rb*/); } -boost::uint32_t usrp_e_dboard_iface::read_write_spi( +boost::uint32_t usrp_e100_dboard_iface::read_write_spi( unit_t unit, const spi_config_t &config, boost::uint32_t data, @@ -259,39 +259,39 @@ boost::uint32_t usrp_e_dboard_iface::read_write_spi( /*********************************************************************** * I2C **********************************************************************/ -void usrp_e_dboard_iface::write_i2c(boost::uint8_t addr, const byte_vector_t &bytes){ +void usrp_e100_dboard_iface::write_i2c(boost::uint8_t addr, const byte_vector_t &bytes){ return _iface->write_i2c(addr, bytes); } -byte_vector_t usrp_e_dboard_iface::read_i2c(boost::uint8_t addr, size_t num_bytes){ +byte_vector_t usrp_e100_dboard_iface::read_i2c(boost::uint8_t addr, size_t num_bytes){ return _iface->read_i2c(addr, num_bytes); } /*********************************************************************** * Aux DAX/ADC **********************************************************************/ -void usrp_e_dboard_iface::write_aux_dac(dboard_iface::unit_t, aux_dac_t which, float value){ +void usrp_e100_dboard_iface::write_aux_dac(dboard_iface::unit_t, aux_dac_t which, float value){ //same aux dacs for each unit - static const uhd::dict which_to_aux_dac = map_list_of - (AUX_DAC_A, usrp_e_codec_ctrl::AUX_DAC_A) - (AUX_DAC_B, usrp_e_codec_ctrl::AUX_DAC_B) - (AUX_DAC_C, usrp_e_codec_ctrl::AUX_DAC_C) - (AUX_DAC_D, usrp_e_codec_ctrl::AUX_DAC_D) + static const uhd::dict which_to_aux_dac = map_list_of + (AUX_DAC_A, usrp_e100_codec_ctrl::AUX_DAC_A) + (AUX_DAC_B, usrp_e100_codec_ctrl::AUX_DAC_B) + (AUX_DAC_C, usrp_e100_codec_ctrl::AUX_DAC_C) + (AUX_DAC_D, usrp_e100_codec_ctrl::AUX_DAC_D) ; _codec->write_aux_dac(which_to_aux_dac[which], value); } -float usrp_e_dboard_iface::read_aux_adc(dboard_iface::unit_t unit, aux_adc_t which){ +float usrp_e100_dboard_iface::read_aux_adc(dboard_iface::unit_t unit, aux_adc_t which){ static const uhd::dict< - unit_t, uhd::dict + unit_t, uhd::dict > unit_to_which_to_aux_adc = map_list_of (UNIT_RX, map_list_of - (AUX_ADC_A, usrp_e_codec_ctrl::AUX_ADC_A1) - (AUX_ADC_B, usrp_e_codec_ctrl::AUX_ADC_B1) + (AUX_ADC_A, usrp_e100_codec_ctrl::AUX_ADC_A1) + (AUX_ADC_B, usrp_e100_codec_ctrl::AUX_ADC_B1) ) (UNIT_TX, map_list_of - (AUX_ADC_A, usrp_e_codec_ctrl::AUX_ADC_A2) - (AUX_ADC_B, usrp_e_codec_ctrl::AUX_ADC_B2) + (AUX_ADC_A, usrp_e100_codec_ctrl::AUX_ADC_A2) + (AUX_ADC_B, usrp_e100_codec_ctrl::AUX_ADC_B2) ) ; return _codec->read_aux_adc(unit_to_which_to_aux_adc[unit][which]); diff --git a/host/lib/usrp/usrp_e100/dboard_impl.cpp b/host/lib/usrp/usrp_e100/dboard_impl.cpp index f2840dcfc..9f2bfb8ae 100644 --- a/host/lib/usrp/usrp_e100/dboard_impl.cpp +++ b/host/lib/usrp/usrp_e100/dboard_impl.cpp @@ -15,8 +15,8 @@ // along with this program. If not, see . // -#include "usrp_e_impl.hpp" -#include "usrp_e_regs.hpp" +#include "usrp_e100_impl.hpp" +#include "usrp_e100_regs.hpp" #include #include #include @@ -30,12 +30,12 @@ using namespace uhd::usrp; /*********************************************************************** * Dboard Initialization **********************************************************************/ -void usrp_e_impl::dboard_init(void){ +void usrp_e100_impl::dboard_init(void){ _rx_db_eeprom = dboard_eeprom_t(_iface->read_eeprom(I2C_ADDR_RX_DB, 0, dboard_eeprom_t::num_bytes())); _tx_db_eeprom = dboard_eeprom_t(_iface->read_eeprom(I2C_ADDR_TX_DB, 0, dboard_eeprom_t::num_bytes())); //create a new dboard interface and manager - _dboard_iface = make_usrp_e_dboard_iface( + _dboard_iface = make_usrp_e100_dboard_iface( _iface, _clock_ctrl, _codec_ctrl ); _dboard_manager = dboard_manager::make( @@ -44,19 +44,19 @@ void usrp_e_impl::dboard_init(void){ //setup the dboard proxies _rx_dboard_proxy = wax_obj_proxy::make( - boost::bind(&usrp_e_impl::rx_dboard_get, this, _1, _2), - boost::bind(&usrp_e_impl::rx_dboard_set, this, _1, _2) + boost::bind(&usrp_e100_impl::rx_dboard_get, this, _1, _2), + boost::bind(&usrp_e100_impl::rx_dboard_set, this, _1, _2) ); _tx_dboard_proxy = wax_obj_proxy::make( - boost::bind(&usrp_e_impl::tx_dboard_get, this, _1, _2), - boost::bind(&usrp_e_impl::tx_dboard_set, this, _1, _2) + boost::bind(&usrp_e100_impl::tx_dboard_get, this, _1, _2), + boost::bind(&usrp_e100_impl::tx_dboard_set, this, _1, _2) ); } /*********************************************************************** * RX Dboard Get **********************************************************************/ -void usrp_e_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){ +void usrp_e100_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){ named_prop_t key = named_prop_t::extract(key_); //handle the get request conditioned on the key @@ -101,7 +101,7 @@ void usrp_e_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){ /*********************************************************************** * RX Dboard Set **********************************************************************/ -void usrp_e_impl::rx_dboard_set(const wax::obj &key, const wax::obj &val){ +void usrp_e100_impl::rx_dboard_set(const wax::obj &key, const wax::obj &val){ switch(key.as()){ case DBOARD_PROP_DBOARD_ID: _rx_db_eeprom.id = val.as(); @@ -115,7 +115,7 @@ void usrp_e_impl::rx_dboard_set(const wax::obj &key, const wax::obj &val){ /*********************************************************************** * TX Dboard Get **********************************************************************/ -void usrp_e_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){ +void usrp_e100_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){ named_prop_t key = named_prop_t::extract(key_); //handle the get request conditioned on the key @@ -160,7 +160,7 @@ void usrp_e_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){ /*********************************************************************** * TX Dboard Set **********************************************************************/ -void usrp_e_impl::tx_dboard_set(const wax::obj &key, const wax::obj &val){ +void usrp_e100_impl::tx_dboard_set(const wax::obj &key, const wax::obj &val){ switch(key.as()){ case DBOARD_PROP_DBOARD_ID: _tx_db_eeprom.id = val.as(); diff --git a/host/lib/usrp/usrp_e100/dsp_impl.cpp b/host/lib/usrp/usrp_e100/dsp_impl.cpp index 97f173c1a..43a3bd3be 100644 --- a/host/lib/usrp/usrp_e100/dsp_impl.cpp +++ b/host/lib/usrp/usrp_e100/dsp_impl.cpp @@ -15,8 +15,8 @@ // along with this program. If not, see . // -#include "usrp_e_impl.hpp" -#include "usrp_e_regs.hpp" +#include "usrp_e100_impl.hpp" +#include "usrp_e100_regs.hpp" #include #include #include @@ -30,10 +30,10 @@ using namespace uhd::usrp; /*********************************************************************** * RX DDC Initialization **********************************************************************/ -void usrp_e_impl::rx_ddc_init(void){ +void usrp_e100_impl::rx_ddc_init(void){ _rx_ddc_proxy = wax_obj_proxy::make( - boost::bind(&usrp_e_impl::rx_ddc_get, this, _1, _2), - boost::bind(&usrp_e_impl::rx_ddc_set, this, _1, _2) + boost::bind(&usrp_e100_impl::rx_ddc_get, this, _1, _2), + boost::bind(&usrp_e100_impl::rx_ddc_set, this, _1, _2) ); //initial config and update @@ -44,7 +44,7 @@ void usrp_e_impl::rx_ddc_init(void){ /*********************************************************************** * RX DDC Get **********************************************************************/ -void usrp_e_impl::rx_ddc_get(const wax::obj &key_, wax::obj &val){ +void usrp_e100_impl::rx_ddc_get(const wax::obj &key_, wax::obj &val){ named_prop_t key = named_prop_t::extract(key_); switch(key.as()){ @@ -79,7 +79,7 @@ void usrp_e_impl::rx_ddc_get(const wax::obj &key_, wax::obj &val){ /*********************************************************************** * RX DDC Set **********************************************************************/ -void usrp_e_impl::rx_ddc_set(const wax::obj &key_, const wax::obj &val){ +void usrp_e100_impl::rx_ddc_set(const wax::obj &key_, const wax::obj &val){ named_prop_t key = named_prop_t::extract(key_); switch(key.as()){ @@ -113,10 +113,10 @@ void usrp_e_impl::rx_ddc_set(const wax::obj &key_, const wax::obj &val){ /*********************************************************************** * TX DUC Initialization **********************************************************************/ -void usrp_e_impl::tx_duc_init(void){ +void usrp_e100_impl::tx_duc_init(void){ _tx_duc_proxy = wax_obj_proxy::make( - boost::bind(&usrp_e_impl::tx_duc_get, this, _1, _2), - boost::bind(&usrp_e_impl::tx_duc_set, this, _1, _2) + boost::bind(&usrp_e100_impl::tx_duc_get, this, _1, _2), + boost::bind(&usrp_e100_impl::tx_duc_set, this, _1, _2) ); //initial config and update @@ -127,7 +127,7 @@ void usrp_e_impl::tx_duc_init(void){ /*********************************************************************** * TX DUC Get **********************************************************************/ -void usrp_e_impl::tx_duc_get(const wax::obj &key_, wax::obj &val){ +void usrp_e100_impl::tx_duc_get(const wax::obj &key_, wax::obj &val){ named_prop_t key = named_prop_t::extract(key_); switch(key.as()){ @@ -162,7 +162,7 @@ void usrp_e_impl::tx_duc_get(const wax::obj &key_, wax::obj &val){ /*********************************************************************** * TX DUC Set **********************************************************************/ -void usrp_e_impl::tx_duc_set(const wax::obj &key_, const wax::obj &val){ +void usrp_e100_impl::tx_duc_set(const wax::obj &key_, const wax::obj &val){ named_prop_t key = named_prop_t::extract(key_); switch(key.as()){ diff --git a/host/lib/usrp/usrp_e100/fpga-downloader.cc b/host/lib/usrp/usrp_e100/fpga-downloader.cc index 4dc537919..4a3d3b9af 100644 --- a/host/lib/usrp/usrp_e100/fpga-downloader.cc +++ b/host/lib/usrp/usrp_e100/fpga-downloader.cc @@ -253,7 +253,7 @@ int main(int argc, char *argv[]) } */ -void usrp_e_load_fpga(const std::string &bin_file){ +void usrp_e100_load_fpga(const std::string &bin_file){ gpio gpio_prog_b(PROG_B, OUT); gpio gpio_init_b(INIT_B, IN); gpio gpio_done (DONE, IN); diff --git a/host/lib/usrp/usrp_e100/io_impl.cpp b/host/lib/usrp/usrp_e100/io_impl.cpp index e863944e8..7cb3e25e5 100644 --- a/host/lib/usrp/usrp_e100/io_impl.cpp +++ b/host/lib/usrp/usrp_e100/io_impl.cpp @@ -15,8 +15,8 @@ // along with this program. If not, see . // -#include "usrp_e_impl.hpp" -#include "usrp_e_regs.hpp" +#include "usrp_e100_impl.hpp" +#include "usrp_e100_regs.hpp" #include #include #include @@ -30,7 +30,7 @@ using namespace uhd; using namespace uhd::usrp; using namespace uhd::transport; -zero_copy_if::sptr usrp_e_make_mmap_zero_copy(usrp_e_iface::sptr iface); +zero_copy_if::sptr usrp_e100_make_mmap_zero_copy(usrp_e100_iface::sptr iface); /*********************************************************************** * Constants @@ -46,14 +46,14 @@ static const bool recv_debug = false; * - thread loop * - vrt packet handler states **********************************************************************/ -struct usrp_e_impl::io_impl{ +struct usrp_e100_impl::io_impl{ //state management for the vrt packet handler code vrt_packet_handler::recv_state packet_handler_recv_state; vrt_packet_handler::send_state packet_handler_send_state; zero_copy_if::sptr data_xport; bool continuous_streaming; - io_impl(usrp_e_iface::sptr iface): - data_xport(usrp_e_make_mmap_zero_copy(iface)), + io_impl(usrp_e100_iface::sptr iface): + data_xport(usrp_e100_make_mmap_zero_copy(iface)), recv_pirate_booty(recv_booty_type::make(data_xport->get_num_recv_frames())), async_msg_fifo(bounded_buffer::make(100/*messages deep*/)) { @@ -73,7 +73,7 @@ struct usrp_e_impl::io_impl{ } //a pirate's life is the life for me! - void recv_pirate_loop(usrp_e_clock_ctrl::sptr); + void recv_pirate_loop(usrp_e100_clock_ctrl::sptr); typedef bounded_buffer recv_booty_type; recv_booty_type::sptr recv_pirate_booty; bounded_buffer::sptr async_msg_fifo; @@ -86,7 +86,7 @@ struct usrp_e_impl::io_impl{ * - while raiding, loot for recv buffers * - put booty into the alignment buffer **********************************************************************/ -void usrp_e_impl::io_impl::recv_pirate_loop(usrp_e_clock_ctrl::sptr clock_ctrl) +void usrp_e100_impl::io_impl::recv_pirate_loop(usrp_e100_clock_ctrl::sptr clock_ctrl) { set_thread_priority_safe(); recv_pirate_crew_raiding = true; @@ -140,7 +140,7 @@ void usrp_e_impl::io_impl::recv_pirate_loop(usrp_e_clock_ctrl::sptr clock_ctrl) /*********************************************************************** * Helper Functions **********************************************************************/ -void usrp_e_impl::io_init(void){ +void usrp_e100_impl::io_init(void){ //setup otw types _send_otw_type.width = 16; _send_otw_type.shift = 0; @@ -172,11 +172,11 @@ void usrp_e_impl::io_init(void){ //spawn a pirate, yarrr! _io_impl->recv_pirate_crew.create_thread(boost::bind( - &usrp_e_impl::io_impl::recv_pirate_loop, _io_impl.get(), _clock_ctrl + &usrp_e100_impl::io_impl::recv_pirate_loop, _io_impl.get(), _clock_ctrl )); } -void usrp_e_impl::issue_stream_cmd(const stream_cmd_t &stream_cmd){ +void usrp_e100_impl::issue_stream_cmd(const stream_cmd_t &stream_cmd){ _io_impl->continuous_streaming = (stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_START_CONTINUOUS); _iface->poke32(UE_REG_CTRL_RX_STREAM_CMD, dsp_type1::calc_stream_cmd_word( stream_cmd, get_max_recv_samps_per_packet() @@ -185,7 +185,7 @@ void usrp_e_impl::issue_stream_cmd(const stream_cmd_t &stream_cmd){ _iface->poke32(UE_REG_CTRL_RX_TIME_TICKS, stream_cmd.time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate())); } -void usrp_e_impl::handle_overrun(size_t){ +void usrp_e100_impl::handle_overrun(size_t){ std::cerr << "O"; //the famous OOOOOOOOOOO _iface->poke32(UE_REG_CTRL_RX_CLEAR_OVERRUN, 0); if (_io_impl->continuous_streaming){ @@ -205,7 +205,7 @@ bool get_send_buffs( return buffs[0].get() != NULL; } -size_t usrp_e_impl::get_max_send_samps_per_packet(void) const{ +size_t usrp_e100_impl::get_max_send_samps_per_packet(void) const{ static const size_t hdr_size = 0 + vrt::max_if_hdr_words32*sizeof(boost::uint32_t) - sizeof(vrt::if_packet_info_t().cid) //no class id ever used @@ -214,7 +214,7 @@ size_t usrp_e_impl::get_max_send_samps_per_packet(void) const{ return bpp/_send_otw_type.get_sample_size(); } -size_t usrp_e_impl::send( +size_t usrp_e100_impl::send( const std::vector &buffs, size_t num_samps, const tx_metadata_t &metadata, const io_type_t &io_type, send_mode_t send_mode, double timeout @@ -234,7 +234,7 @@ size_t usrp_e_impl::send( /*********************************************************************** * Data Recv **********************************************************************/ -size_t usrp_e_impl::get_max_recv_samps_per_packet(void) const{ +size_t usrp_e100_impl::get_max_recv_samps_per_packet(void) const{ static const size_t hdr_size = 0 + vrt::max_if_hdr_words32*sizeof(boost::uint32_t) + sizeof(vrt::if_packet_info_t().tlr) //forced to have trailer @@ -244,7 +244,7 @@ size_t usrp_e_impl::get_max_recv_samps_per_packet(void) const{ return bpp/_recv_otw_type.get_sample_size(); } -size_t usrp_e_impl::recv( +size_t usrp_e100_impl::recv( const std::vector &buffs, size_t num_samps, rx_metadata_t &metadata, const io_type_t &io_type, recv_mode_t recv_mode, double timeout @@ -256,15 +256,15 @@ size_t usrp_e_impl::recv( io_type, _recv_otw_type, //input and output types to convert _clock_ctrl->get_fpga_clock_rate(), //master clock tick rate uhd::transport::vrt::if_hdr_unpack_le, - boost::bind(&usrp_e_impl::io_impl::get_recv_buffs, _io_impl.get(), _1, timeout), - boost::bind(&usrp_e_impl::handle_overrun, this, _1) + boost::bind(&usrp_e100_impl::io_impl::get_recv_buffs, _io_impl.get(), _1, timeout), + boost::bind(&usrp_e100_impl::handle_overrun, this, _1) ); } /*********************************************************************** * Async Recv **********************************************************************/ -bool usrp_e_impl::recv_async_msg( +bool usrp_e100_impl::recv_async_msg( async_metadata_t &async_metadata, double timeout ){ boost::this_thread::disable_interruption di; //disable because the wait can throw diff --git a/host/lib/usrp/usrp_e100/mboard_impl.cpp b/host/lib/usrp/usrp_e100/mboard_impl.cpp index f0118aa4b..2d5d028e6 100644 --- a/host/lib/usrp/usrp_e100/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e100/mboard_impl.cpp @@ -15,8 +15,8 @@ // along with this program. If not, see . // -#include "usrp_e_impl.hpp" -#include "usrp_e_regs.hpp" +#include "usrp_e100_impl.hpp" +#include "usrp_e100_regs.hpp" #include #include #include @@ -30,10 +30,10 @@ using namespace uhd::usrp; /*********************************************************************** * Mboard Initialization **********************************************************************/ -void usrp_e_impl::mboard_init(void){ +void usrp_e100_impl::mboard_init(void){ _mboard_proxy = wax_obj_proxy::make( - boost::bind(&usrp_e_impl::mboard_get, this, _1, _2), - boost::bind(&usrp_e_impl::mboard_set, this, _1, _2) + boost::bind(&usrp_e100_impl::mboard_get, this, _1, _2), + boost::bind(&usrp_e100_impl::mboard_set, this, _1, _2) ); //init the clock config @@ -46,7 +46,7 @@ void usrp_e_impl::mboard_init(void){ /*********************************************************************** * Mboard Get **********************************************************************/ -void usrp_e_impl::mboard_get(const wax::obj &key_, wax::obj &val){ +void usrp_e100_impl::mboard_get(const wax::obj &key_, wax::obj &val){ named_prop_t key = named_prop_t::extract(key_); //handle the get request conditioned on the key @@ -114,7 +114,7 @@ void usrp_e_impl::mboard_get(const wax::obj &key_, wax::obj &val){ /*********************************************************************** * Mboard Set **********************************************************************/ -void usrp_e_impl::mboard_set(const wax::obj &key, const wax::obj &val){ +void usrp_e100_impl::mboard_set(const wax::obj &key, const wax::obj &val){ //handle the get request conditioned on the key switch(key.as()){ diff --git a/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp b/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp new file mode 100644 index 000000000..ad623777e --- /dev/null +++ b/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp @@ -0,0 +1,194 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "usrp_e100_iface.hpp" +#include +#include //ioctl +#include //open, close +#include //ioctl structures and constants +#include +#include //mutex +#include + +using namespace uhd; + +class usrp_e100_iface_impl : public usrp_e100_iface{ +public: + + int get_file_descriptor(void){ + return _node_fd; + } + + /******************************************************************* + * Structors + ******************************************************************/ + usrp_e100_iface_impl(const std::string &node){ + //open the device node and check file descriptor + if ((_node_fd = ::open(node.c_str(), O_RDWR)) < 0){ + throw std::runtime_error(str( + boost::format("Failed to open %s") % node + )); + } + } + + ~usrp_e100_iface_impl(void){ + //close the device node file descriptor + ::close(_node_fd); + } + + /******************************************************************* + * IOCTL: provides the communication base for all other calls + ******************************************************************/ + void ioctl(int request, void *mem){ + boost::mutex::scoped_lock lock(_ctrl_mutex); + + if (::ioctl(_node_fd, request, mem) < 0){ + throw std::runtime_error(str( + boost::format("ioctl failed with request %d") % request + )); + } + } + + /******************************************************************* + * Peek and Poke + ******************************************************************/ + void poke32(boost::uint32_t addr, boost::uint32_t value){ + //load the data struct + usrp_e_ctl32 data; + data.offset = addr; + data.count = 1; + data.buf[0] = value; + + //call the ioctl + this->ioctl(USRP_E_WRITE_CTL32, &data); + } + + void poke16(boost::uint32_t addr, boost::uint16_t value){ + //load the data struct + usrp_e_ctl16 data; + data.offset = addr; + data.count = 1; + data.buf[0] = value; + + //call the ioctl + this->ioctl(USRP_E_WRITE_CTL16, &data); + } + + boost::uint32_t peek32(boost::uint32_t addr){ + //load the data struct + usrp_e_ctl32 data; + data.offset = addr; + data.count = 1; + + //call the ioctl + this->ioctl(USRP_E_READ_CTL32, &data); + + return data.buf[0]; + } + + boost::uint16_t peek16(boost::uint32_t addr){ + //load the data struct + usrp_e_ctl16 data; + data.offset = addr; + data.count = 1; + + //call the ioctl + this->ioctl(USRP_E_READ_CTL16, &data); + + return data.buf[0]; + } + + /******************************************************************* + * I2C + ******************************************************************/ + static const size_t max_i2c_data_bytes = 10; + + void write_i2c(boost::uint8_t addr, const byte_vector_t &bytes){ + //allocate some memory for this transaction + UHD_ASSERT_THROW(bytes.size() <= max_i2c_data_bytes); + boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; + + //load the data struct + usrp_e_i2c *data = reinterpret_cast(mem); + data->addr = addr; + data->len = bytes.size(); + std::copy(bytes.begin(), bytes.end(), data->data); + + //call the spi ioctl + this->ioctl(USRP_E_I2C_WRITE, data); + } + + byte_vector_t read_i2c(boost::uint8_t addr, size_t num_bytes){ + //allocate some memory for this transaction + UHD_ASSERT_THROW(num_bytes <= max_i2c_data_bytes); + boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; + + //load the data struct + usrp_e_i2c *data = reinterpret_cast(mem); + data->addr = addr; + data->len = num_bytes; + + //call the spi ioctl + this->ioctl(USRP_E_I2C_READ, data); + + //unload the data + byte_vector_t bytes(data->len); + UHD_ASSERT_THROW(bytes.size() == num_bytes); + std::copy(data->data, data->data+bytes.size(), bytes.begin()); + return bytes; + } + + /******************************************************************* + * SPI + ******************************************************************/ + boost::uint32_t transact_spi( + int which_slave, + const spi_config_t &config, + boost::uint32_t bits, + size_t num_bits, + bool readback + ){ + //load data struct + usrp_e_spi data; + data.readback = (readback)? UE_SPI_TXRX : UE_SPI_TXONLY; + data.slave = which_slave; + data.length = num_bits; + data.data = bits; + + //load the flags + data.flags = 0; + data.flags |= (config.miso_edge == spi_config_t::EDGE_RISE)? UE_SPI_LATCH_RISE : UE_SPI_LATCH_FALL; + data.flags |= (config.mosi_edge == spi_config_t::EDGE_RISE)? UE_SPI_PUSH_FALL : UE_SPI_PUSH_RISE; + + //call the spi ioctl + this->ioctl(USRP_E_SPI, &data); + + //unload the data + return data.data; + } + +private: + int _node_fd; + boost::mutex _ctrl_mutex; +}; + +/*********************************************************************** + * Public Make Function + **********************************************************************/ +usrp_e100_iface::sptr usrp_e100_iface::make(const std::string &node){ + return sptr(new usrp_e100_iface_impl(node)); +} diff --git a/host/lib/usrp/usrp_e100/usrp_e100_iface.hpp b/host/lib/usrp/usrp_e100/usrp_e100_iface.hpp new file mode 100644 index 000000000..b52209a42 --- /dev/null +++ b/host/lib/usrp/usrp_e100/usrp_e100_iface.hpp @@ -0,0 +1,112 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_USRP_E100_IFACE_HPP +#define INCLUDED_USRP_E100_IFACE_HPP + +#include +#include +#include +#include +#include + +//////////////////////////////////////////////////////////////////////// +// I2C addresses +//////////////////////////////////////////////////////////////////////// +#define I2C_DEV_EEPROM 0x50 // 24LC02[45]: 7-bits 1010xxx +#define I2C_ADDR_MBOARD (I2C_DEV_EEPROM | 0x0) +#define I2C_ADDR_TX_DB (I2C_DEV_EEPROM | 0x4) +#define I2C_ADDR_RX_DB (I2C_DEV_EEPROM | 0x5) +//////////////////////////////////////////////////////////////////////// + +/*! + * The usrp-e interface class: + * Provides a set of functions to implementation layer. + * Including spi, peek, poke, control... + */ +class usrp_e100_iface : boost::noncopyable, public uhd::i2c_iface{ +public: + typedef boost::shared_ptr sptr; + + /*! + * Make a new usrp-e interface with the control transport. + * \param node the device node name + * \return a new usrp-e interface object + */ + static sptr make(const std::string &node); + + /*! + * Get the underlying file descriptor. + * \return the file descriptor + */ + virtual int get_file_descriptor(void) = 0; + + /*! + * Perform an ioctl call on the device node file descriptor. + * This will throw when the internal ioctl call fails. + * \param request the control word + * \param mem pointer to some memory + */ + virtual void ioctl(int request, void *mem) = 0; + + /*! + * Write a register (32 bits) + * \param addr the address + * \param data the 32bit data + */ + virtual void poke32(boost::uint32_t addr, boost::uint32_t data) = 0; + + /*! + * Read a register (32 bits) + * \param addr the address + * \return the 32bit data + */ + virtual boost::uint32_t peek32(boost::uint32_t addr) = 0; + + /*! + * Write a register (16 bits) + * \param addr the address + * \param data the 16bit data + */ + virtual void poke16(boost::uint32_t addr, boost::uint16_t data) = 0; + + /*! + * Read a register (16 bits) + * \param addr the address + * \return the 16bit data + */ + virtual boost::uint16_t peek16(boost::uint32_t addr) = 0; + + /*! + * Perform an spi transaction. + * \param which_slave the slave device number + * \param config spi config args + * \param data the bits to write + * \param num_bits how many bits in data + * \param readback true to readback a value + * \return spi data if readback set + */ + virtual boost::uint32_t transact_spi( + int which_slave, + const uhd::spi_config_t &config, + boost::uint32_t data, + size_t num_bits, + bool readback + ) = 0; +}; + +#endif /* INCLUDED_USRP_E100_IFACE_HPP */ diff --git a/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp b/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp new file mode 100644 index 000000000..73cb1f285 --- /dev/null +++ b/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp @@ -0,0 +1,201 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "usrp_e100_impl.hpp" +#include "usrp_e100_regs.hpp" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +using namespace uhd; +using namespace uhd::usrp; +namespace fs = boost::filesystem; + +/*********************************************************************** + * Helper Functions + **********************************************************************/ +static std::string abs_path(const std::string &file_path){ + return fs::system_complete(fs::path(file_path)).file_string(); +} + +/*********************************************************************** + * Discovery + **********************************************************************/ +static device_addrs_t usrp_e100_find(const device_addr_t &hint){ + device_addrs_t usrp_e100_addrs; + + //return an empty list of addresses when type is set to non-usrp-e + if (hint.has_key("type") and hint["type"] != "usrp-e") return usrp_e100_addrs; + + //device node not provided, assume its 0 + if (not hint.has_key("node")){ + device_addr_t new_addr = hint; + new_addr["node"] = "/dev/usrp_e1000"; + return usrp_e100_find(new_addr); + } + + //use the given device node name + if (fs::exists(hint["node"])){ + device_addr_t new_addr; + new_addr["type"] = "usrp-e"; + new_addr["node"] = abs_path(hint["node"]); + usrp_e100_addrs.push_back(new_addr); + } + + return usrp_e100_addrs; +} + +/*********************************************************************** + * Make + **********************************************************************/ +static device::sptr usrp_e100_make(const device_addr_t &device_addr){ + + //setup the main interface into fpga + std::string node = device_addr["node"]; + std::cout << boost::format("Opening USRP-E on %s") % node << std::endl; + usrp_e100_iface::sptr iface = usrp_e100_iface::make(node); + + //------------------------------------------------------------------ + //-- Handle the FPGA loading... + //-- The image can be confimed as already loaded when: + //-- 1) The compatibility number matches. + //-- 2) The hash in the hash-file matches. + //------------------------------------------------------------------ + static const char *hash_file_path = "/tmp/usrp_e100100_hash"; + + //extract the fpga path for usrp-e + std::string usrp_e100_fpga_image = find_image_path( + device_addr.has_key("fpga")? device_addr["fpga"] : "usrp_e100100_fpga.bin" + ); + + //calculate a hash of the fpga file + size_t fpga_hash = 0; + { + std::ifstream file(usrp_e100_fpga_image.c_str()); + if (not file.good()) throw std::runtime_error( + "cannot open fpga file for read: " + usrp_e100_fpga_image + ); + do{ + boost::hash_combine(fpga_hash, file.get()); + } while (file.good()); + file.close(); + } + + //read the compatibility number + boost::uint16_t fpga_compat_num = iface->peek16(UE_REG_MISC_COMPAT); + + //read the hash in the hash-file + size_t loaded_hash = 0; + try{std::ifstream(hash_file_path) >> loaded_hash;}catch(...){} + + //if not loaded: load the fpga image and write the hash-file + if (fpga_compat_num != USRP_E_COMPAT_NUM or loaded_hash != fpga_hash){ + iface.reset(); + usrp_e100_load_fpga(usrp_e100_fpga_image); + std::cout << boost::format("re-Opening USRP-E on %s") % node << std::endl; + iface = usrp_e100_iface::make(node); + try{std::ofstream(hash_file_path) << fpga_hash;}catch(...){} + } + + //check that the compatibility is correct + fpga_compat_num = iface->peek16(UE_REG_MISC_COMPAT); + if (fpga_compat_num != USRP_E_COMPAT_NUM){ + throw std::runtime_error(str(boost::format( + "Expected fpga compatibility number 0x%x, but got 0x%x:\n" + "The fpga build is not compatible with the host code build." + ) % USRP_E_COMPAT_NUM % fpga_compat_num)); + } + + return device::sptr(new usrp_e100_impl(iface)); +} + +UHD_STATIC_BLOCK(register_usrp_e100_device){ + device::register_device(&usrp_e100_find, &usrp_e100_make); +} + +/*********************************************************************** + * Structors + **********************************************************************/ +usrp_e100_impl::usrp_e100_impl(usrp_e100_iface::sptr iface): _iface(iface){ + + //setup interfaces into hardware + _clock_ctrl = usrp_e100_clock_ctrl::make(_iface); + _codec_ctrl = usrp_e100_codec_ctrl::make(_iface); + + //initialize the mboard + mboard_init(); + + //initialize the dboards + dboard_init(); + + //initialize the dsps + rx_ddc_init(); + tx_duc_init(); + + //init the codec properties + codec_init(); + + //init the io send/recv + io_init(); + + //set default subdev specs + this->mboard_set(MBOARD_PROP_RX_SUBDEV_SPEC, subdev_spec_t()); + this->mboard_set(MBOARD_PROP_TX_SUBDEV_SPEC, subdev_spec_t()); +} + +usrp_e100_impl::~usrp_e100_impl(void){ + /* NOP */ +} + +/*********************************************************************** + * Device Get + **********************************************************************/ +void usrp_e100_impl::get(const wax::obj &key_, wax::obj &val){ + named_prop_t key = named_prop_t::extract(key_); + + //handle the get request conditioned on the key + switch(key.as()){ + case DEVICE_PROP_NAME: + val = std::string("usrp-e device"); + return; + + case DEVICE_PROP_MBOARD: + UHD_ASSERT_THROW(key.name == ""); + val = _mboard_proxy->get_link(); + return; + + case DEVICE_PROP_MBOARD_NAMES: + val = prop_names_t(1, ""); //vector of size 1 with empty string + return; + + default: UHD_THROW_PROP_GET_ERROR(); + } +} + +/*********************************************************************** + * Device Set + **********************************************************************/ +void usrp_e100_impl::set(const wax::obj &, const wax::obj &){ + UHD_THROW_PROP_SET_ERROR(); +} diff --git a/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp b/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp new file mode 100644 index 000000000..fe60ac0be --- /dev/null +++ b/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp @@ -0,0 +1,164 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "usrp_e100_iface.hpp" +#include "clock_ctrl.hpp" +#include "codec_ctrl.hpp" +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef INCLUDED_USRP_E100_IMPL_HPP +#define INCLUDED_USRP_E100_IMPL_HPP + +static const boost::uint16_t USRP_E_COMPAT_NUM = 0x02; + +//! load an fpga image from a bin file into the usrp-e fpga +extern void usrp_e100_load_fpga(const std::string &bin_file); + +/*! + * Make a usrp-e dboard interface. + * \param iface the usrp-e interface object + * \param clock the clock control interface + * \param codec the codec control interface + * \return a sptr to a new dboard interface + */ +uhd::usrp::dboard_iface::sptr make_usrp_e100_dboard_iface( + usrp_e100_iface::sptr iface, + usrp_e100_clock_ctrl::sptr clock, + usrp_e100_codec_ctrl::sptr codec +); + +/*! + * Simple wax obj proxy class: + * Provides a wax obj interface for a set and a get function. + * This allows us to create nested properties structures + * while maintaining flattened code within the implementation. + */ +class wax_obj_proxy : public wax::obj{ +public: + typedef boost::function get_t; + typedef boost::function set_t; + typedef boost::shared_ptr sptr; + + static sptr make(const get_t &get, const set_t &set){ + return sptr(new wax_obj_proxy(get, set)); + } + +private: + get_t _get; set_t _set; + wax_obj_proxy(const get_t &get, const set_t &set): _get(get), _set(set){}; + void get(const wax::obj &key, wax::obj &val){return _get(key, val);} + void set(const wax::obj &key, const wax::obj &val){return _set(key, val);} +}; + +/*! + * USRP-E100 implementation guts: + * The implementation details are encapsulated here. + * Handles properties on the mboard, dboard, dsps... + */ +class usrp_e100_impl : public uhd::device{ +public: + //structors + usrp_e100_impl(usrp_e100_iface::sptr); + ~usrp_e100_impl(void); + + //the io interface + size_t send(const std::vector &, size_t, const uhd::tx_metadata_t &, const uhd::io_type_t &, send_mode_t, double); + size_t recv(const std::vector &, size_t, uhd::rx_metadata_t &, const uhd::io_type_t &, recv_mode_t, double); + bool recv_async_msg(uhd::async_metadata_t &, double); + size_t get_max_send_samps_per_packet(void) const; + size_t get_max_recv_samps_per_packet(void) const; + +private: + //interface to ioctls and file descriptor + usrp_e100_iface::sptr _iface; + + //handle io stuff + UHD_PIMPL_DECL(io_impl) _io_impl; + uhd::otw_type_t _send_otw_type, _recv_otw_type; + void io_init(void); + void issue_stream_cmd(const uhd::stream_cmd_t &stream_cmd); + void handle_overrun(size_t); + + //configuration shadows + uhd::clock_config_t _clock_config; + //TODO otw type recv/send + + //ad9522 clock control + usrp_e100_clock_ctrl::sptr _clock_ctrl; + + //ad9862 codec control + usrp_e100_codec_ctrl::sptr _codec_ctrl; + + //device functions and settings + void get(const wax::obj &, wax::obj &); + void set(const wax::obj &, const wax::obj &); + + //mboard functions and settings + void mboard_init(void); + void mboard_get(const wax::obj &, wax::obj &); + void mboard_set(const wax::obj &, const wax::obj &); + wax_obj_proxy::sptr _mboard_proxy; + uhd::usrp::subdev_spec_t _rx_subdev_spec, _tx_subdev_spec; + + //xx dboard functions and settings + void dboard_init(void); + uhd::usrp::dboard_manager::sptr _dboard_manager; + uhd::usrp::dboard_iface::sptr _dboard_iface; + + //rx dboard functions and settings + uhd::usrp::dboard_eeprom_t _rx_db_eeprom; + void rx_dboard_get(const wax::obj &, wax::obj &); + void rx_dboard_set(const wax::obj &, const wax::obj &); + wax_obj_proxy::sptr _rx_dboard_proxy; + + //tx dboard functions and settings + uhd::usrp::dboard_eeprom_t _tx_db_eeprom; + void tx_dboard_get(const wax::obj &, wax::obj &); + void tx_dboard_set(const wax::obj &, const wax::obj &); + wax_obj_proxy::sptr _tx_dboard_proxy; + + //rx ddc functions and settings + void rx_ddc_init(void); + void rx_ddc_get(const wax::obj &, wax::obj &); + void rx_ddc_set(const wax::obj &, const wax::obj &); + double _ddc_freq; size_t _ddc_decim; + wax_obj_proxy::sptr _rx_ddc_proxy; + + //tx duc functions and settings + void tx_duc_init(void); + void tx_duc_get(const wax::obj &, wax::obj &); + void tx_duc_set(const wax::obj &, const wax::obj &); + double _duc_freq; size_t _duc_interp; + wax_obj_proxy::sptr _tx_duc_proxy; + + //codec functions and settings + void codec_init(void); + void rx_codec_get(const wax::obj &, wax::obj &); + void rx_codec_set(const wax::obj &, const wax::obj &); + void tx_codec_get(const wax::obj &, wax::obj &); + void tx_codec_set(const wax::obj &, const wax::obj &); + wax_obj_proxy::sptr _rx_codec_proxy, _tx_codec_proxy; +}; + +#endif /* INCLUDED_USRP_E100_IMPL_HPP */ diff --git a/host/lib/usrp/usrp_e100/usrp_e100_mmap_zero_copy.cpp b/host/lib/usrp/usrp_e100/usrp_e100_mmap_zero_copy.cpp new file mode 100644 index 000000000..bf378a9b1 --- /dev/null +++ b/host/lib/usrp/usrp_e100/usrp_e100_mmap_zero_copy.cpp @@ -0,0 +1,215 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "usrp_e100_iface.hpp" +#include +#include +#include +#include //mmap +#include //getpagesize +#include //poll +#include +#include +#include + +using namespace uhd; +using namespace uhd::transport; + +static const bool fp_verbose = false; //fast-path verbose +static const bool sp_verbose = false; //slow-path verbose +static const size_t poll_breakout = 10; //how many poll timeouts constitute a full timeout + +/*********************************************************************** + * The zero copy interface implementation + **********************************************************************/ +class usrp_e100_mmap_zero_copy_impl : public zero_copy_if, public boost::enable_shared_from_this { +public: + usrp_e100_mmap_zero_copy_impl(usrp_e100_iface::sptr iface): + _fd(iface->get_file_descriptor()), _recv_index(0), _send_index(0) + { + //get system sizes + iface->ioctl(USRP_E_GET_RB_INFO, &_rb_size); + size_t page_size = getpagesize(); + _frame_size = page_size/2; + + //calculate the memory size + _map_size = + (_rb_size.num_pages_rx_flags + _rb_size.num_pages_tx_flags) * page_size + + (_rb_size.num_rx_frames + _rb_size.num_tx_frames) * _frame_size; + + //print sizes summary + if (sp_verbose){ + std::cout << "page_size: " << page_size << std::endl; + std::cout << "frame_size: " << _frame_size << std::endl; + std::cout << "num_pages_rx_flags: " << _rb_size.num_pages_rx_flags << std::endl; + std::cout << "num_rx_frames: " << _rb_size.num_rx_frames << std::endl; + std::cout << "num_pages_tx_flags: " << _rb_size.num_pages_tx_flags << std::endl; + std::cout << "num_tx_frames: " << _rb_size.num_tx_frames << std::endl; + std::cout << "map_size: " << _map_size << std::endl; + } + + //call mmap to get the memory + _mapped_mem = ::mmap( + NULL, _map_size, PROT_READ | PROT_WRITE, MAP_SHARED, _fd, 0 + ); + UHD_ASSERT_THROW(_mapped_mem != MAP_FAILED); + + //calculate the memory offsets for info and buffers + size_t recv_info_off = 0; + size_t recv_buff_off = recv_info_off + (_rb_size.num_pages_rx_flags * page_size); + size_t send_info_off = recv_buff_off + (_rb_size.num_rx_frames * _frame_size); + size_t send_buff_off = send_info_off + (_rb_size.num_pages_tx_flags * page_size); + + //print offset summary + if (sp_verbose){ + std::cout << "recv_info_off: " << recv_info_off << std::endl; + std::cout << "recv_buff_off: " << recv_buff_off << std::endl; + std::cout << "send_info_off: " << send_info_off << std::endl; + std::cout << "send_buff_off: " << send_buff_off << std::endl; + } + + //set the internal pointers for info and buffers + typedef ring_buffer_info (*rbi_pta)[]; + char *rb_ptr = reinterpret_cast(_mapped_mem); + _recv_info = reinterpret_cast(rb_ptr + recv_info_off); + _recv_buff = rb_ptr + recv_buff_off; + _send_info = reinterpret_cast(rb_ptr + send_info_off); + _send_buff = rb_ptr + send_buff_off; + } + + ~usrp_e100_mmap_zero_copy_impl(void){ + if (sp_verbose) std::cout << "cleanup: munmap" << std::endl; + ::munmap(_mapped_mem, _map_size); + } + + managed_recv_buffer::sptr get_recv_buff(double timeout){ + if (fp_verbose) std::cout << "get_recv_buff: " << _recv_index << std::endl; + + //grab pointers to the info and buffer + ring_buffer_info *info = (*_recv_info) + _recv_index; + void *mem = _recv_buff + _frame_size*_recv_index; + + //poll/wait for a ready frame + if (not (info->flags & RB_USER)){ + for (size_t i = 0; i < poll_breakout; i++){ + pollfd pfd; + pfd.fd = _fd; + pfd.events = POLLIN; + ssize_t poll_ret = ::poll(&pfd, 1, size_t(timeout*1e3/poll_breakout)); + if (fp_verbose) std::cout << " POLLIN: " << poll_ret << std::endl; + if (poll_ret > 0) goto found_user_frame; //good poll, continue on + } + return managed_recv_buffer::sptr(); //timed-out for real + } found_user_frame: + + //the process has claimed the frame + info->flags = RB_USER_PROCESS; + + //increment the index for the next call + if (++_recv_index == size_t(_rb_size.num_rx_frames)) _recv_index = 0; + + //return the managed buffer for this frame + if (fp_verbose) std::cout << " make_recv_buff: " << info->len << std::endl; + return managed_recv_buffer::make_safe( + boost::asio::const_buffer(mem, info->len), + boost::bind(&usrp_e100_mmap_zero_copy_impl::release, shared_from_this(), info) + ); + } + + size_t get_num_recv_frames(void) const{ + return _rb_size.num_rx_frames; + } + + size_t get_recv_frame_size(void) const{ + return _frame_size; + } + + managed_send_buffer::sptr get_send_buff(double timeout){ + if (fp_verbose) std::cout << "get_send_buff: " << _send_index << std::endl; + + //grab pointers to the info and buffer + ring_buffer_info *info = (*_send_info) + _send_index; + void *mem = _send_buff + _frame_size*_send_index; + + //poll/wait for a ready frame + if (not (info->flags & RB_KERNEL)){ + pollfd pfd; + pfd.fd = _fd; + pfd.events = POLLOUT; + ssize_t poll_ret = ::poll(&pfd, 1, size_t(timeout*1e3)); + if (fp_verbose) std::cout << " POLLOUT: " << poll_ret << std::endl; + if (poll_ret <= 0) return managed_send_buffer::sptr(); + } + + //increment the index for the next call + if (++_send_index == size_t(_rb_size.num_tx_frames)) _send_index = 0; + + //return the managed buffer for this frame + if (fp_verbose) std::cout << " make_send_buff: " << _frame_size << std::endl; + return managed_send_buffer::make_safe( + boost::asio::mutable_buffer(mem, _frame_size), + boost::bind(&usrp_e100_mmap_zero_copy_impl::commit, shared_from_this(), info, _1) + ); + } + + size_t get_num_send_frames(void) const{ + return _rb_size.num_tx_frames; + } + + size_t get_send_frame_size(void) const{ + return _frame_size; + } + +private: + + void release(ring_buffer_info *info){ + if (fp_verbose) std::cout << "recv buff: release" << std::endl; + info->flags = RB_KERNEL; + } + + void commit(ring_buffer_info *info, size_t len){ + if (fp_verbose) std::cout << "send buff: commit " << len << std::endl; + info->len = len; + info->flags = RB_USER; + if (::write(_fd, NULL, 0) < 0){ + std::cerr << UHD_THROW_SITE_INFO("write error") << std::endl; + } + } + + int _fd; + + //the mapped memory itself + void *_mapped_mem; + + //mapped memory sizes + usrp_e_ring_buffer_size_t _rb_size; + size_t _frame_size, _map_size; + + //pointers to sections in the mapped memory + ring_buffer_info (*_recv_info)[], (*_send_info)[]; + char *_recv_buff, *_send_buff; + + //indexes into sub-sections of mapped memory + size_t _recv_index, _send_index; +}; + +/*********************************************************************** + * The zero copy interface make function + **********************************************************************/ +zero_copy_if::sptr usrp_e100_make_mmap_zero_copy(usrp_e100_iface::sptr iface){ + return zero_copy_if::sptr(new usrp_e100_mmap_zero_copy_impl(iface)); +} diff --git a/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp b/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp new file mode 100644 index 000000000..625fb2c35 --- /dev/null +++ b/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp @@ -0,0 +1,198 @@ + + +//////////////////////////////////////////////////////////////// +// +// Memory map for embedded wishbone bus +// +//////////////////////////////////////////////////////////////// + +// All addresses are byte addresses. All accesses are word (16-bit) accesses. +// This means that address bit 0 is usually 0. +// There are 11 bits of address for the control. + +#ifndef INCLUDED_USRP_E100_REGS_HPP +#define INCLUDED_USRP_E100_REGS_HPP + +///////////////////////////////////////////////////// +// Slave pointers + +#define UE_REG_SLAVE(n) ((n)<<7) +#define UE_REG_SR_ADDR(n) ((UE_REG_SLAVE(5)) + (4*(n))) + +///////////////////////////////////////////////////// +// Slave 0 -- Misc Regs + +#define UE_REG_MISC_BASE UE_REG_SLAVE(0) + +#define UE_REG_MISC_LED UE_REG_MISC_BASE + 0 +#define UE_REG_MISC_SW UE_REG_MISC_BASE + 2 +#define UE_REG_MISC_CGEN_CTRL UE_REG_MISC_BASE + 4 +#define UE_REG_MISC_CGEN_ST UE_REG_MISC_BASE + 6 +#define UE_REG_MISC_TEST UE_REG_MISC_BASE + 8 +#define UE_REG_MISC_RX_LEN UE_REG_MISC_BASE + 10 +#define UE_REG_MISC_TX_LEN UE_REG_MISC_BASE + 12 +#define UE_REG_MISC_XFER_RATE UE_REG_MISC_BASE + 14 +#define UE_REG_MISC_COMPAT UE_REG_MISC_BASE + 16 + +///////////////////////////////////////////////////// +// Slave 1 -- UART +// CLKDIV is 16 bits, others are only 8 + +#define UE_REG_UART_BASE UE_REG_SLAVE(1) + +#define UE_REG_UART_CLKDIV UE_REG_UART_BASE + 0 +#define UE_REG_UART_TXLEVEL UE_REG_UART_BASE + 2 +#define UE_REG_UART_RXLEVEL UE_REG_UART_BASE + 4 +#define UE_REG_UART_TXCHAR UE_REG_UART_BASE + 6 +#define UE_REG_UART_RXCHAR UE_REG_UART_BASE + 8 + +///////////////////////////////////////////////////// +// Slave 2 -- SPI Core +// This should be accessed through the IOCTL +// Users should not touch directly + +#define UE_REG_SPI_BASE UE_REG_SLAVE(2) + +//spi slave constants +#define UE_SPI_SS_AD9522 (1 << 3) +#define UE_SPI_SS_AD9862 (1 << 2) +#define UE_SPI_SS_TX_DB (1 << 1) +#define UE_SPI_SS_RX_DB (1 << 0) + +//////////////////////////////////////////////// +// Slave 3 -- I2C Core +// This should be accessed through the IOCTL +// Users should not touch directly + +#define UE_REG_I2C_BASE UE_REG_SLAVE(3) + + +//////////////////////////////////////////////// +// Slave 4 -- GPIO + +#define UE_REG_GPIO_BASE UE_REG_SLAVE(4) + +#define UE_REG_GPIO_RX_IO UE_REG_GPIO_BASE + 0 +#define UE_REG_GPIO_TX_IO UE_REG_GPIO_BASE + 2 +#define UE_REG_GPIO_RX_DDR UE_REG_GPIO_BASE + 4 +#define UE_REG_GPIO_TX_DDR UE_REG_GPIO_BASE + 6 +#define UE_REG_GPIO_RX_SEL UE_REG_GPIO_BASE + 8 +#define UE_REG_GPIO_TX_SEL UE_REG_GPIO_BASE + 10 +#define UE_REG_GPIO_RX_DBG UE_REG_GPIO_BASE + 12 +#define UE_REG_GPIO_TX_DBG UE_REG_GPIO_BASE + 14 + +//possible bit values for sel when dbg is 0: +#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg +#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic + +//possible bit values for sel when dbg is 1: +#define GPIO_SEL_DEBUG_0 0 // if pin is an output, debug lines from FPGA fabric +#define GPIO_SEL_DEBUG_1 1 // if pin is an output, debug lines from FPGA fabric + + +//////////////////////////////////////////////////// +// Slave 5 -- Settings Bus +// +// Output-only, no readback, 32 registers total +// Each register must be written 32 bits at a time +// First the address xxx_xx00 and then xxx_xx10 + +#define UE_REG_SETTINGS_BASE UE_REG_SLAVE(5) + +/////////////////////////////////////////////////// +// Slave 6 -- ATR Controller +// 16 regs + +#define UE_REG_ATR_BASE UE_REG_SLAVE(6) + +#define UE_REG_ATR_IDLE_RXSIDE UE_REG_ATR_BASE + 0 +#define UE_REG_ATR_IDLE_TXSIDE UE_REG_ATR_BASE + 2 +#define UE_REG_ATR_INTX_RXSIDE UE_REG_ATR_BASE + 4 +#define UE_REG_ATR_INTX_TXSIDE UE_REG_ATR_BASE + 6 +#define UE_REG_ATR_INRX_RXSIDE UE_REG_ATR_BASE + 8 +#define UE_REG_ATR_INRX_TXSIDE UE_REG_ATR_BASE + 10 +#define UE_REG_ATR_FULL_RXSIDE UE_REG_ATR_BASE + 12 +#define UE_REG_ATR_FULL_TXSIDE UE_REG_ATR_BASE + 14 + +///////////////////////////////////////////////// +// DSP RX Regs +//////////////////////////////////////////////// +#define UE_REG_DSP_RX_FREQ UE_REG_SR_ADDR(0) +#define UE_REG_DSP_RX_SCALE_IQ UE_REG_SR_ADDR(1) // {scale_i,scale_q} +#define UE_REG_DSP_RX_DECIM_RATE UE_REG_SR_ADDR(2) // hb and decim rate +#define UE_REG_DSP_RX_DCOFFSET_I UE_REG_SR_ADDR(3) // Bit 31 high sets fixed offset mode, using lower 14 bits, // otherwise it is automatic +#define UE_REG_DSP_RX_DCOFFSET_Q UE_REG_SR_ADDR(4) // Bit 31 high sets fixed offset mode, using lower 14 bits +#define UE_REG_DSP_RX_MUX UE_REG_SR_ADDR(5) + +/////////////////////////////////////////////////// +// VITA RX CTRL regs +/////////////////////////////////////////////////// +// The following 3 are logically a single command register. +// They are clocked into the underlying fifo when time_ticks is written. +#define UE_REG_CTRL_RX_STREAM_CMD UE_REG_SR_ADDR(8) // {now, chain, num_samples(30) +#define UE_REG_CTRL_RX_TIME_SECS UE_REG_SR_ADDR(9) +#define UE_REG_CTRL_RX_TIME_TICKS UE_REG_SR_ADDR(10) +#define UE_REG_CTRL_RX_CLEAR_OVERRUN UE_REG_SR_ADDR(11) // write anything to clear overrun +#define UE_REG_CTRL_RX_VRT_HEADER UE_REG_SR_ADDR(12) // word 0 of packet. FPGA fills in packet counter +#define UE_REG_CTRL_RX_VRT_STREAM_ID UE_REG_SR_ADDR(13) // word 1 of packet. +#define UE_REG_CTRL_RX_VRT_TRAILER UE_REG_SR_ADDR(14) +#define UE_REG_CTRL_RX_NSAMPS_PER_PKT UE_REG_SR_ADDR(15) +#define UE_REG_CTRL_RX_NCHANNELS UE_REG_SR_ADDR(16) // 1 in basic case, up to 4 for vector sources + +///////////////////////////////////////////////// +// DSP TX Regs +//////////////////////////////////////////////// +#define UE_REG_DSP_TX_FREQ UE_REG_SR_ADDR(17) +#define UE_REG_DSP_TX_SCALE_IQ UE_REG_SR_ADDR(18) // {scale_i,scale_q} +#define UE_REG_DSP_TX_INTERP_RATE UE_REG_SR_ADDR(19) +#define UE_REG_DSP_TX_UNUSED UE_REG_SR_ADDR(20) +#define UE_REG_DSP_TX_MUX UE_REG_SR_ADDR(21) + +///////////////////////////////////////////////// +// VITA TX CTRL regs +//////////////////////////////////////////////// +#define UE_REG_CTRL_TX_NCHANNELS UE_REG_SR_ADDR(24) +#define UE_REG_CTRL_TX_CLEAR_UNDERRUN UE_REG_SR_ADDR(25) +#define UE_REG_CTRL_TX_REPORT_SID UE_REG_SR_ADDR(26) +#define UE_REG_CTRL_TX_POLICY UE_REG_SR_ADDR(27) + +#define UE_FLAG_CTRL_TX_POLICY_WAIT (0x1 << 0) +#define UE_FLAG_CTRL_TX_POLICY_NEXT_PACKET (0x1 << 1) +#define UE_FLAG_CTRL_TX_POLICY_NEXT_BURST (0x1 << 2) + +///////////////////////////////////////////////// +// VITA49 64 bit time (write only) +//////////////////////////////////////////////// + /*! + * \brief Time 64 flags + * + * 
+   *
+   *    3                   2                   1
+   *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   * +-----------------------------------------------------------+-+-+
+   * |                                                           |S|P|
+   * +-----------------------------------------------------------+-+-+
+   *
+   * P - PPS edge selection (0=negedge, 1=posedge, default=0)
+   * S - Source (0=sma, 1=mimo, 0=default)
+   *
+   *
+ */ +#define UE_REG_TIME64_SECS UE_REG_SR_ADDR(28) // value to set absolute secs to on next PPS +#define UE_REG_TIME64_TICKS UE_REG_SR_ADDR(29) // value to set absolute ticks to on next PPS +#define UE_REG_TIME64_FLAGS UE_REG_SR_ADDR(30) // flags - see chart above +#define UE_REG_TIME64_IMM UE_REG_SR_ADDR(31) // set immediate (0=latch on next pps, 1=latch immediate, default=0) +#define UE_REG_TIME64_TPS UE_REG_SR_ADDR(31) // clock ticks per second (counter rollover) + +//pps flags (see above) +#define UE_FLAG_TIME64_PPS_NEGEDGE (0 << 0) +#define UE_FLAG_TIME64_PPS_POSEDGE (1 << 0) +#define UE_FLAG_TIME64_PPS_SMA (0 << 1) +#define UE_FLAG_TIME64_PPS_MIMO (1 << 1) + +#define UE_FLAG_TIME64_LATCH_NOW 1 +#define UE_FLAG_TIME64_LATCH_NEXT_PPS 0 + +#endif + diff --git a/host/lib/usrp/usrp_e100/usrp_e_iface.cpp b/host/lib/usrp/usrp_e100/usrp_e_iface.cpp deleted file mode 100644 index f00e92946..000000000 --- a/host/lib/usrp/usrp_e100/usrp_e_iface.cpp +++ /dev/null @@ -1,194 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "usrp_e_iface.hpp" -#include -#include //ioctl -#include //open, close -#include //ioctl structures and constants -#include -#include //mutex -#include - -using namespace uhd; - -class usrp_e_iface_impl : public usrp_e_iface{ -public: - - int get_file_descriptor(void){ - return _node_fd; - } - - /******************************************************************* - * Structors - ******************************************************************/ - usrp_e_iface_impl(const std::string &node){ - //open the device node and check file descriptor - if ((_node_fd = ::open(node.c_str(), O_RDWR)) < 0){ - throw std::runtime_error(str( - boost::format("Failed to open %s") % node - )); - } - } - - ~usrp_e_iface_impl(void){ - //close the device node file descriptor - ::close(_node_fd); - } - - /******************************************************************* - * IOCTL: provides the communication base for all other calls - ******************************************************************/ - void ioctl(int request, void *mem){ - boost::mutex::scoped_lock lock(_ctrl_mutex); - - if (::ioctl(_node_fd, request, mem) < 0){ - throw std::runtime_error(str( - boost::format("ioctl failed with request %d") % request - )); - } - } - - /******************************************************************* - * Peek and Poke - ******************************************************************/ - void poke32(boost::uint32_t addr, boost::uint32_t value){ - //load the data struct - usrp_e_ctl32 data; - data.offset = addr; - data.count = 1; - data.buf[0] = value; - - //call the ioctl - this->ioctl(USRP_E_WRITE_CTL32, &data); - } - - void poke16(boost::uint32_t addr, boost::uint16_t value){ - //load the data struct - usrp_e_ctl16 data; - data.offset = addr; - data.count = 1; - data.buf[0] = value; - - //call the ioctl - this->ioctl(USRP_E_WRITE_CTL16, &data); - } - - boost::uint32_t peek32(boost::uint32_t addr){ - //load the data struct - usrp_e_ctl32 data; - data.offset = addr; - data.count = 1; - - //call the ioctl - this->ioctl(USRP_E_READ_CTL32, &data); - - return data.buf[0]; - } - - boost::uint16_t peek16(boost::uint32_t addr){ - //load the data struct - usrp_e_ctl16 data; - data.offset = addr; - data.count = 1; - - //call the ioctl - this->ioctl(USRP_E_READ_CTL16, &data); - - return data.buf[0]; - } - - /******************************************************************* - * I2C - ******************************************************************/ - static const size_t max_i2c_data_bytes = 10; - - void write_i2c(boost::uint8_t addr, const byte_vector_t &bytes){ - //allocate some memory for this transaction - UHD_ASSERT_THROW(bytes.size() <= max_i2c_data_bytes); - boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; - - //load the data struct - usrp_e_i2c *data = reinterpret_cast(mem); - data->addr = addr; - data->len = bytes.size(); - std::copy(bytes.begin(), bytes.end(), data->data); - - //call the spi ioctl - this->ioctl(USRP_E_I2C_WRITE, data); - } - - byte_vector_t read_i2c(boost::uint8_t addr, size_t num_bytes){ - //allocate some memory for this transaction - UHD_ASSERT_THROW(num_bytes <= max_i2c_data_bytes); - boost::uint8_t mem[sizeof(usrp_e_i2c) + max_i2c_data_bytes]; - - //load the data struct - usrp_e_i2c *data = reinterpret_cast(mem); - data->addr = addr; - data->len = num_bytes; - - //call the spi ioctl - this->ioctl(USRP_E_I2C_READ, data); - - //unload the data - byte_vector_t bytes(data->len); - UHD_ASSERT_THROW(bytes.size() == num_bytes); - std::copy(data->data, data->data+bytes.size(), bytes.begin()); - return bytes; - } - - /******************************************************************* - * SPI - ******************************************************************/ - boost::uint32_t transact_spi( - int which_slave, - const spi_config_t &config, - boost::uint32_t bits, - size_t num_bits, - bool readback - ){ - //load data struct - usrp_e_spi data; - data.readback = (readback)? UE_SPI_TXRX : UE_SPI_TXONLY; - data.slave = which_slave; - data.length = num_bits; - data.data = bits; - - //load the flags - data.flags = 0; - data.flags |= (config.miso_edge == spi_config_t::EDGE_RISE)? UE_SPI_LATCH_RISE : UE_SPI_LATCH_FALL; - data.flags |= (config.mosi_edge == spi_config_t::EDGE_RISE)? UE_SPI_PUSH_FALL : UE_SPI_PUSH_RISE; - - //call the spi ioctl - this->ioctl(USRP_E_SPI, &data); - - //unload the data - return data.data; - } - -private: - int _node_fd; - boost::mutex _ctrl_mutex; -}; - -/*********************************************************************** - * Public Make Function - **********************************************************************/ -usrp_e_iface::sptr usrp_e_iface::make(const std::string &node){ - return sptr(new usrp_e_iface_impl(node)); -} diff --git a/host/lib/usrp/usrp_e100/usrp_e_iface.hpp b/host/lib/usrp/usrp_e100/usrp_e_iface.hpp deleted file mode 100644 index 59aac43d9..000000000 --- a/host/lib/usrp/usrp_e100/usrp_e_iface.hpp +++ /dev/null @@ -1,112 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#ifndef INCLUDED_USRP_E_IFACE_HPP -#define INCLUDED_USRP_E_IFACE_HPP - -#include -#include -#include -#include -#include - -//////////////////////////////////////////////////////////////////////// -// I2C addresses -//////////////////////////////////////////////////////////////////////// -#define I2C_DEV_EEPROM 0x50 // 24LC02[45]: 7-bits 1010xxx -#define I2C_ADDR_MBOARD (I2C_DEV_EEPROM | 0x0) -#define I2C_ADDR_TX_DB (I2C_DEV_EEPROM | 0x4) -#define I2C_ADDR_RX_DB (I2C_DEV_EEPROM | 0x5) -//////////////////////////////////////////////////////////////////////// - -/*! - * The usrp-e interface class: - * Provides a set of functions to implementation layer. - * Including spi, peek, poke, control... - */ -class usrp_e_iface : boost::noncopyable, public uhd::i2c_iface{ -public: - typedef boost::shared_ptr sptr; - - /*! - * Make a new usrp-e interface with the control transport. - * \param node the device node name - * \return a new usrp-e interface object - */ - static sptr make(const std::string &node); - - /*! - * Get the underlying file descriptor. - * \return the file descriptor - */ - virtual int get_file_descriptor(void) = 0; - - /*! - * Perform an ioctl call on the device node file descriptor. - * This will throw when the internal ioctl call fails. - * \param request the control word - * \param mem pointer to some memory - */ - virtual void ioctl(int request, void *mem) = 0; - - /*! - * Write a register (32 bits) - * \param addr the address - * \param data the 32bit data - */ - virtual void poke32(boost::uint32_t addr, boost::uint32_t data) = 0; - - /*! - * Read a register (32 bits) - * \param addr the address - * \return the 32bit data - */ - virtual boost::uint32_t peek32(boost::uint32_t addr) = 0; - - /*! - * Write a register (16 bits) - * \param addr the address - * \param data the 16bit data - */ - virtual void poke16(boost::uint32_t addr, boost::uint16_t data) = 0; - - /*! - * Read a register (16 bits) - * \param addr the address - * \return the 16bit data - */ - virtual boost::uint16_t peek16(boost::uint32_t addr) = 0; - - /*! - * Perform an spi transaction. - * \param which_slave the slave device number - * \param config spi config args - * \param data the bits to write - * \param num_bits how many bits in data - * \param readback true to readback a value - * \return spi data if readback set - */ - virtual boost::uint32_t transact_spi( - int which_slave, - const uhd::spi_config_t &config, - boost::uint32_t data, - size_t num_bits, - bool readback - ) = 0; -}; - -#endif /* INCLUDED_USRP_E_IFACE_HPP */ diff --git a/host/lib/usrp/usrp_e100/usrp_e_impl.cpp b/host/lib/usrp/usrp_e100/usrp_e_impl.cpp deleted file mode 100644 index 70cc399fb..000000000 --- a/host/lib/usrp/usrp_e100/usrp_e_impl.cpp +++ /dev/null @@ -1,201 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "usrp_e_impl.hpp" -#include "usrp_e_regs.hpp" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -using namespace uhd; -using namespace uhd::usrp; -namespace fs = boost::filesystem; - -/*********************************************************************** - * Helper Functions - **********************************************************************/ -static std::string abs_path(const std::string &file_path){ - return fs::system_complete(fs::path(file_path)).file_string(); -} - -/*********************************************************************** - * Discovery - **********************************************************************/ -static device_addrs_t usrp_e_find(const device_addr_t &hint){ - device_addrs_t usrp_e_addrs; - - //return an empty list of addresses when type is set to non-usrp-e - if (hint.has_key("type") and hint["type"] != "usrp-e") return usrp_e_addrs; - - //device node not provided, assume its 0 - if (not hint.has_key("node")){ - device_addr_t new_addr = hint; - new_addr["node"] = "/dev/usrp_e0"; - return usrp_e_find(new_addr); - } - - //use the given device node name - if (fs::exists(hint["node"])){ - device_addr_t new_addr; - new_addr["type"] = "usrp-e"; - new_addr["node"] = abs_path(hint["node"]); - usrp_e_addrs.push_back(new_addr); - } - - return usrp_e_addrs; -} - -/*********************************************************************** - * Make - **********************************************************************/ -static device::sptr usrp_e_make(const device_addr_t &device_addr){ - - //setup the main interface into fpga - std::string node = device_addr["node"]; - std::cout << boost::format("Opening USRP-E on %s") % node << std::endl; - usrp_e_iface::sptr iface = usrp_e_iface::make(node); - - //------------------------------------------------------------------ - //-- Handle the FPGA loading... - //-- The image can be confimed as already loaded when: - //-- 1) The compatibility number matches. - //-- 2) The hash in the hash-file matches. - //------------------------------------------------------------------ - static const char *hash_file_path = "/tmp/usrp_e100_hash"; - - //extract the fpga path for usrp-e - std::string usrp_e_fpga_image = find_image_path( - device_addr.has_key("fpga")? device_addr["fpga"] : "usrp_e100_fpga.bin" - ); - - //calculate a hash of the fpga file - size_t fpga_hash = 0; - { - std::ifstream file(usrp_e_fpga_image.c_str()); - if (not file.good()) throw std::runtime_error( - "cannot open fpga file for read: " + usrp_e_fpga_image - ); - do{ - boost::hash_combine(fpga_hash, file.get()); - } while (file.good()); - file.close(); - } - - //read the compatibility number - boost::uint16_t fpga_compat_num = iface->peek16(UE_REG_MISC_COMPAT); - - //read the hash in the hash-file - size_t loaded_hash = 0; - try{std::ifstream(hash_file_path) >> loaded_hash;}catch(...){} - - //if not loaded: load the fpga image and write the hash-file - if (fpga_compat_num != USRP_E_COMPAT_NUM or loaded_hash != fpga_hash){ - iface.reset(); - usrp_e_load_fpga(usrp_e_fpga_image); - std::cout << boost::format("re-Opening USRP-E on %s") % node << std::endl; - iface = usrp_e_iface::make(node); - try{std::ofstream(hash_file_path) << fpga_hash;}catch(...){} - } - - //check that the compatibility is correct - fpga_compat_num = iface->peek16(UE_REG_MISC_COMPAT); - if (fpga_compat_num != USRP_E_COMPAT_NUM){ - throw std::runtime_error(str(boost::format( - "Expected fpga compatibility number 0x%x, but got 0x%x:\n" - "The fpga build is not compatible with the host code build." - ) % USRP_E_COMPAT_NUM % fpga_compat_num)); - } - - return device::sptr(new usrp_e_impl(iface)); -} - -UHD_STATIC_BLOCK(register_usrp_e_device){ - device::register_device(&usrp_e_find, &usrp_e_make); -} - -/*********************************************************************** - * Structors - **********************************************************************/ -usrp_e_impl::usrp_e_impl(usrp_e_iface::sptr iface): _iface(iface){ - - //setup interfaces into hardware - _clock_ctrl = usrp_e_clock_ctrl::make(_iface); - _codec_ctrl = usrp_e_codec_ctrl::make(_iface); - - //initialize the mboard - mboard_init(); - - //initialize the dboards - dboard_init(); - - //initialize the dsps - rx_ddc_init(); - tx_duc_init(); - - //init the codec properties - codec_init(); - - //init the io send/recv - io_init(); - - //set default subdev specs - this->mboard_set(MBOARD_PROP_RX_SUBDEV_SPEC, subdev_spec_t()); - this->mboard_set(MBOARD_PROP_TX_SUBDEV_SPEC, subdev_spec_t()); -} - -usrp_e_impl::~usrp_e_impl(void){ - /* NOP */ -} - -/*********************************************************************** - * Device Get - **********************************************************************/ -void usrp_e_impl::get(const wax::obj &key_, wax::obj &val){ - named_prop_t key = named_prop_t::extract(key_); - - //handle the get request conditioned on the key - switch(key.as()){ - case DEVICE_PROP_NAME: - val = std::string("usrp-e device"); - return; - - case DEVICE_PROP_MBOARD: - UHD_ASSERT_THROW(key.name == ""); - val = _mboard_proxy->get_link(); - return; - - case DEVICE_PROP_MBOARD_NAMES: - val = prop_names_t(1, ""); //vector of size 1 with empty string - return; - - default: UHD_THROW_PROP_GET_ERROR(); - } -} - -/*********************************************************************** - * Device Set - **********************************************************************/ -void usrp_e_impl::set(const wax::obj &, const wax::obj &){ - UHD_THROW_PROP_SET_ERROR(); -} diff --git a/host/lib/usrp/usrp_e100/usrp_e_impl.hpp b/host/lib/usrp/usrp_e100/usrp_e_impl.hpp deleted file mode 100644 index b5f21810d..000000000 --- a/host/lib/usrp/usrp_e100/usrp_e_impl.hpp +++ /dev/null @@ -1,164 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "usrp_e_iface.hpp" -#include "clock_ctrl.hpp" -#include "codec_ctrl.hpp" -#include -#include -#include -#include -#include -#include -#include -#include - -#ifndef INCLUDED_USRP_E_IMPL_HPP -#define INCLUDED_USRP_E_IMPL_HPP - -static const boost::uint16_t USRP_E_COMPAT_NUM = 0x02; - -//! load an fpga image from a bin file into the usrp-e fpga -extern void usrp_e_load_fpga(const std::string &bin_file); - -/*! - * Make a usrp-e dboard interface. - * \param iface the usrp-e interface object - * \param clock the clock control interface - * \param codec the codec control interface - * \return a sptr to a new dboard interface - */ -uhd::usrp::dboard_iface::sptr make_usrp_e_dboard_iface( - usrp_e_iface::sptr iface, - usrp_e_clock_ctrl::sptr clock, - usrp_e_codec_ctrl::sptr codec -); - -/*! - * Simple wax obj proxy class: - * Provides a wax obj interface for a set and a get function. - * This allows us to create nested properties structures - * while maintaining flattened code within the implementation. - */ -class wax_obj_proxy : public wax::obj{ -public: - typedef boost::function get_t; - typedef boost::function set_t; - typedef boost::shared_ptr sptr; - - static sptr make(const get_t &get, const set_t &set){ - return sptr(new wax_obj_proxy(get, set)); - } - -private: - get_t _get; set_t _set; - wax_obj_proxy(const get_t &get, const set_t &set): _get(get), _set(set){}; - void get(const wax::obj &key, wax::obj &val){return _get(key, val);} - void set(const wax::obj &key, const wax::obj &val){return _set(key, val);} -}; - -/*! - * USRP1E implementation guts: - * The implementation details are encapsulated here. - * Handles properties on the mboard, dboard, dsps... - */ -class usrp_e_impl : public uhd::device{ -public: - //structors - usrp_e_impl(usrp_e_iface::sptr); - ~usrp_e_impl(void); - - //the io interface - size_t send(const std::vector &, size_t, const uhd::tx_metadata_t &, const uhd::io_type_t &, send_mode_t, double); - size_t recv(const std::vector &, size_t, uhd::rx_metadata_t &, const uhd::io_type_t &, recv_mode_t, double); - bool recv_async_msg(uhd::async_metadata_t &, double); - size_t get_max_send_samps_per_packet(void) const; - size_t get_max_recv_samps_per_packet(void) const; - -private: - //interface to ioctls and file descriptor - usrp_e_iface::sptr _iface; - - //handle io stuff - UHD_PIMPL_DECL(io_impl) _io_impl; - uhd::otw_type_t _send_otw_type, _recv_otw_type; - void io_init(void); - void issue_stream_cmd(const uhd::stream_cmd_t &stream_cmd); - void handle_overrun(size_t); - - //configuration shadows - uhd::clock_config_t _clock_config; - //TODO otw type recv/send - - //ad9522 clock control - usrp_e_clock_ctrl::sptr _clock_ctrl; - - //ad9862 codec control - usrp_e_codec_ctrl::sptr _codec_ctrl; - - //device functions and settings - void get(const wax::obj &, wax::obj &); - void set(const wax::obj &, const wax::obj &); - - //mboard functions and settings - void mboard_init(void); - void mboard_get(const wax::obj &, wax::obj &); - void mboard_set(const wax::obj &, const wax::obj &); - wax_obj_proxy::sptr _mboard_proxy; - uhd::usrp::subdev_spec_t _rx_subdev_spec, _tx_subdev_spec; - - //xx dboard functions and settings - void dboard_init(void); - uhd::usrp::dboard_manager::sptr _dboard_manager; - uhd::usrp::dboard_iface::sptr _dboard_iface; - - //rx dboard functions and settings - uhd::usrp::dboard_eeprom_t _rx_db_eeprom; - void rx_dboard_get(const wax::obj &, wax::obj &); - void rx_dboard_set(const wax::obj &, const wax::obj &); - wax_obj_proxy::sptr _rx_dboard_proxy; - - //tx dboard functions and settings - uhd::usrp::dboard_eeprom_t _tx_db_eeprom; - void tx_dboard_get(const wax::obj &, wax::obj &); - void tx_dboard_set(const wax::obj &, const wax::obj &); - wax_obj_proxy::sptr _tx_dboard_proxy; - - //rx ddc functions and settings - void rx_ddc_init(void); - void rx_ddc_get(const wax::obj &, wax::obj &); - void rx_ddc_set(const wax::obj &, const wax::obj &); - double _ddc_freq; size_t _ddc_decim; - wax_obj_proxy::sptr _rx_ddc_proxy; - - //tx duc functions and settings - void tx_duc_init(void); - void tx_duc_get(const wax::obj &, wax::obj &); - void tx_duc_set(const wax::obj &, const wax::obj &); - double _duc_freq; size_t _duc_interp; - wax_obj_proxy::sptr _tx_duc_proxy; - - //codec functions and settings - void codec_init(void); - void rx_codec_get(const wax::obj &, wax::obj &); - void rx_codec_set(const wax::obj &, const wax::obj &); - void tx_codec_get(const wax::obj &, wax::obj &); - void tx_codec_set(const wax::obj &, const wax::obj &); - wax_obj_proxy::sptr _rx_codec_proxy, _tx_codec_proxy; -}; - -#endif /* INCLUDED_USRP_E_IMPL_HPP */ diff --git a/host/lib/usrp/usrp_e100/usrp_e_mmap_zero_copy.cpp b/host/lib/usrp/usrp_e100/usrp_e_mmap_zero_copy.cpp deleted file mode 100644 index 274bb043e..000000000 --- a/host/lib/usrp/usrp_e100/usrp_e_mmap_zero_copy.cpp +++ /dev/null @@ -1,215 +0,0 @@ -// -// Copyright 2010 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -#include "usrp_e_iface.hpp" -#include -#include -#include -#include //mmap -#include //getpagesize -#include //poll -#include -#include -#include - -using namespace uhd; -using namespace uhd::transport; - -static const bool fp_verbose = false; //fast-path verbose -static const bool sp_verbose = false; //slow-path verbose -static const size_t poll_breakout = 10; //how many poll timeouts constitute a full timeout - -/*********************************************************************** - * The zero copy interface implementation - **********************************************************************/ -class usrp_e_mmap_zero_copy_impl : public zero_copy_if, public boost::enable_shared_from_this { -public: - usrp_e_mmap_zero_copy_impl(usrp_e_iface::sptr iface): - _fd(iface->get_file_descriptor()), _recv_index(0), _send_index(0) - { - //get system sizes - iface->ioctl(USRP_E_GET_RB_INFO, &_rb_size); - size_t page_size = getpagesize(); - _frame_size = page_size/2; - - //calculate the memory size - _map_size = - (_rb_size.num_pages_rx_flags + _rb_size.num_pages_tx_flags) * page_size + - (_rb_size.num_rx_frames + _rb_size.num_tx_frames) * _frame_size; - - //print sizes summary - if (sp_verbose){ - std::cout << "page_size: " << page_size << std::endl; - std::cout << "frame_size: " << _frame_size << std::endl; - std::cout << "num_pages_rx_flags: " << _rb_size.num_pages_rx_flags << std::endl; - std::cout << "num_rx_frames: " << _rb_size.num_rx_frames << std::endl; - std::cout << "num_pages_tx_flags: " << _rb_size.num_pages_tx_flags << std::endl; - std::cout << "num_tx_frames: " << _rb_size.num_tx_frames << std::endl; - std::cout << "map_size: " << _map_size << std::endl; - } - - //call mmap to get the memory - _mapped_mem = ::mmap( - NULL, _map_size, PROT_READ | PROT_WRITE, MAP_SHARED, _fd, 0 - ); - UHD_ASSERT_THROW(_mapped_mem != MAP_FAILED); - - //calculate the memory offsets for info and buffers - size_t recv_info_off = 0; - size_t recv_buff_off = recv_info_off + (_rb_size.num_pages_rx_flags * page_size); - size_t send_info_off = recv_buff_off + (_rb_size.num_rx_frames * _frame_size); - size_t send_buff_off = send_info_off + (_rb_size.num_pages_tx_flags * page_size); - - //print offset summary - if (sp_verbose){ - std::cout << "recv_info_off: " << recv_info_off << std::endl; - std::cout << "recv_buff_off: " << recv_buff_off << std::endl; - std::cout << "send_info_off: " << send_info_off << std::endl; - std::cout << "send_buff_off: " << send_buff_off << std::endl; - } - - //set the internal pointers for info and buffers - typedef ring_buffer_info (*rbi_pta)[]; - char *rb_ptr = reinterpret_cast(_mapped_mem); - _recv_info = reinterpret_cast(rb_ptr + recv_info_off); - _recv_buff = rb_ptr + recv_buff_off; - _send_info = reinterpret_cast(rb_ptr + send_info_off); - _send_buff = rb_ptr + send_buff_off; - } - - ~usrp_e_mmap_zero_copy_impl(void){ - if (sp_verbose) std::cout << "cleanup: munmap" << std::endl; - ::munmap(_mapped_mem, _map_size); - } - - managed_recv_buffer::sptr get_recv_buff(double timeout){ - if (fp_verbose) std::cout << "get_recv_buff: " << _recv_index << std::endl; - - //grab pointers to the info and buffer - ring_buffer_info *info = (*_recv_info) + _recv_index; - void *mem = _recv_buff + _frame_size*_recv_index; - - //poll/wait for a ready frame - if (not (info->flags & RB_USER)){ - for (size_t i = 0; i < poll_breakout; i++){ - pollfd pfd; - pfd.fd = _fd; - pfd.events = POLLIN; - ssize_t poll_ret = ::poll(&pfd, 1, size_t(timeout*1e3/poll_breakout)); - if (fp_verbose) std::cout << " POLLIN: " << poll_ret << std::endl; - if (poll_ret > 0) goto found_user_frame; //good poll, continue on - } - return managed_recv_buffer::sptr(); //timed-out for real - } found_user_frame: - - //the process has claimed the frame - info->flags = RB_USER_PROCESS; - - //increment the index for the next call - if (++_recv_index == size_t(_rb_size.num_rx_frames)) _recv_index = 0; - - //return the managed buffer for this frame - if (fp_verbose) std::cout << " make_recv_buff: " << info->len << std::endl; - return managed_recv_buffer::make_safe( - boost::asio::const_buffer(mem, info->len), - boost::bind(&usrp_e_mmap_zero_copy_impl::release, shared_from_this(), info) - ); - } - - size_t get_num_recv_frames(void) const{ - return _rb_size.num_rx_frames; - } - - size_t get_recv_frame_size(void) const{ - return _frame_size; - } - - managed_send_buffer::sptr get_send_buff(double timeout){ - if (fp_verbose) std::cout << "get_send_buff: " << _send_index << std::endl; - - //grab pointers to the info and buffer - ring_buffer_info *info = (*_send_info) + _send_index; - void *mem = _send_buff + _frame_size*_send_index; - - //poll/wait for a ready frame - if (not (info->flags & RB_KERNEL)){ - pollfd pfd; - pfd.fd = _fd; - pfd.events = POLLOUT; - ssize_t poll_ret = ::poll(&pfd, 1, size_t(timeout*1e3)); - if (fp_verbose) std::cout << " POLLOUT: " << poll_ret << std::endl; - if (poll_ret <= 0) return managed_send_buffer::sptr(); - } - - //increment the index for the next call - if (++_send_index == size_t(_rb_size.num_tx_frames)) _send_index = 0; - - //return the managed buffer for this frame - if (fp_verbose) std::cout << " make_send_buff: " << _frame_size << std::endl; - return managed_send_buffer::make_safe( - boost::asio::mutable_buffer(mem, _frame_size), - boost::bind(&usrp_e_mmap_zero_copy_impl::commit, shared_from_this(), info, _1) - ); - } - - size_t get_num_send_frames(void) const{ - return _rb_size.num_tx_frames; - } - - size_t get_send_frame_size(void) const{ - return _frame_size; - } - -private: - - void release(ring_buffer_info *info){ - if (fp_verbose) std::cout << "recv buff: release" << std::endl; - info->flags = RB_KERNEL; - } - - void commit(ring_buffer_info *info, size_t len){ - if (fp_verbose) std::cout << "send buff: commit " << len << std::endl; - info->len = len; - info->flags = RB_USER; - if (::write(_fd, NULL, 0) < 0){ - std::cerr << UHD_THROW_SITE_INFO("write error") << std::endl; - } - } - - int _fd; - - //the mapped memory itself - void *_mapped_mem; - - //mapped memory sizes - usrp_e_ring_buffer_size_t _rb_size; - size_t _frame_size, _map_size; - - //pointers to sections in the mapped memory - ring_buffer_info (*_recv_info)[], (*_send_info)[]; - char *_recv_buff, *_send_buff; - - //indexes into sub-sections of mapped memory - size_t _recv_index, _send_index; -}; - -/*********************************************************************** - * The zero copy interface make function - **********************************************************************/ -zero_copy_if::sptr usrp_e_make_mmap_zero_copy(usrp_e_iface::sptr iface){ - return zero_copy_if::sptr(new usrp_e_mmap_zero_copy_impl(iface)); -} diff --git a/host/lib/usrp/usrp_e100/usrp_e_regs.hpp b/host/lib/usrp/usrp_e100/usrp_e_regs.hpp deleted file mode 100644 index 8bfb08b6f..000000000 --- a/host/lib/usrp/usrp_e100/usrp_e_regs.hpp +++ /dev/null @@ -1,198 +0,0 @@ - - -//////////////////////////////////////////////////////////////// -// -// Memory map for embedded wishbone bus -// -//////////////////////////////////////////////////////////////// - -// All addresses are byte addresses. All accesses are word (16-bit) accesses. -// This means that address bit 0 is usually 0. -// There are 11 bits of address for the control. - -#ifndef __USRP_E_REGS_H -#define __USRP_E_REGS_H - -///////////////////////////////////////////////////// -// Slave pointers - -#define UE_REG_SLAVE(n) ((n)<<7) -#define UE_REG_SR_ADDR(n) ((UE_REG_SLAVE(5)) + (4*(n))) - -///////////////////////////////////////////////////// -// Slave 0 -- Misc Regs - -#define UE_REG_MISC_BASE UE_REG_SLAVE(0) - -#define UE_REG_MISC_LED UE_REG_MISC_BASE + 0 -#define UE_REG_MISC_SW UE_REG_MISC_BASE + 2 -#define UE_REG_MISC_CGEN_CTRL UE_REG_MISC_BASE + 4 -#define UE_REG_MISC_CGEN_ST UE_REG_MISC_BASE + 6 -#define UE_REG_MISC_TEST UE_REG_MISC_BASE + 8 -#define UE_REG_MISC_RX_LEN UE_REG_MISC_BASE + 10 -#define UE_REG_MISC_TX_LEN UE_REG_MISC_BASE + 12 -#define UE_REG_MISC_XFER_RATE UE_REG_MISC_BASE + 14 -#define UE_REG_MISC_COMPAT UE_REG_MISC_BASE + 16 - -///////////////////////////////////////////////////// -// Slave 1 -- UART -// CLKDIV is 16 bits, others are only 8 - -#define UE_REG_UART_BASE UE_REG_SLAVE(1) - -#define UE_REG_UART_CLKDIV UE_REG_UART_BASE + 0 -#define UE_REG_UART_TXLEVEL UE_REG_UART_BASE + 2 -#define UE_REG_UART_RXLEVEL UE_REG_UART_BASE + 4 -#define UE_REG_UART_TXCHAR UE_REG_UART_BASE + 6 -#define UE_REG_UART_RXCHAR UE_REG_UART_BASE + 8 - -///////////////////////////////////////////////////// -// Slave 2 -- SPI Core -// This should be accessed through the IOCTL -// Users should not touch directly - -#define UE_REG_SPI_BASE UE_REG_SLAVE(2) - -//spi slave constants -#define UE_SPI_SS_AD9522 (1 << 3) -#define UE_SPI_SS_AD9862 (1 << 2) -#define UE_SPI_SS_TX_DB (1 << 1) -#define UE_SPI_SS_RX_DB (1 << 0) - -//////////////////////////////////////////////// -// Slave 3 -- I2C Core -// This should be accessed through the IOCTL -// Users should not touch directly - -#define UE_REG_I2C_BASE UE_REG_SLAVE(3) - - -//////////////////////////////////////////////// -// Slave 4 -- GPIO - -#define UE_REG_GPIO_BASE UE_REG_SLAVE(4) - -#define UE_REG_GPIO_RX_IO UE_REG_GPIO_BASE + 0 -#define UE_REG_GPIO_TX_IO UE_REG_GPIO_BASE + 2 -#define UE_REG_GPIO_RX_DDR UE_REG_GPIO_BASE + 4 -#define UE_REG_GPIO_TX_DDR UE_REG_GPIO_BASE + 6 -#define UE_REG_GPIO_RX_SEL UE_REG_GPIO_BASE + 8 -#define UE_REG_GPIO_TX_SEL UE_REG_GPIO_BASE + 10 -#define UE_REG_GPIO_RX_DBG UE_REG_GPIO_BASE + 12 -#define UE_REG_GPIO_TX_DBG UE_REG_GPIO_BASE + 14 - -//possible bit values for sel when dbg is 0: -#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg -#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic - -//possible bit values for sel when dbg is 1: -#define GPIO_SEL_DEBUG_0 0 // if pin is an output, debug lines from FPGA fabric -#define GPIO_SEL_DEBUG_1 1 // if pin is an output, debug lines from FPGA fabric - - -//////////////////////////////////////////////////// -// Slave 5 -- Settings Bus -// -// Output-only, no readback, 32 registers total -// Each register must be written 32 bits at a time -// First the address xxx_xx00 and then xxx_xx10 - -#define UE_REG_SETTINGS_BASE UE_REG_SLAVE(5) - -/////////////////////////////////////////////////// -// Slave 6 -- ATR Controller -// 16 regs - -#define UE_REG_ATR_BASE UE_REG_SLAVE(6) - -#define UE_REG_ATR_IDLE_RXSIDE UE_REG_ATR_BASE + 0 -#define UE_REG_ATR_IDLE_TXSIDE UE_REG_ATR_BASE + 2 -#define UE_REG_ATR_INTX_RXSIDE UE_REG_ATR_BASE + 4 -#define UE_REG_ATR_INTX_TXSIDE UE_REG_ATR_BASE + 6 -#define UE_REG_ATR_INRX_RXSIDE UE_REG_ATR_BASE + 8 -#define UE_REG_ATR_INRX_TXSIDE UE_REG_ATR_BASE + 10 -#define UE_REG_ATR_FULL_RXSIDE UE_REG_ATR_BASE + 12 -#define UE_REG_ATR_FULL_TXSIDE UE_REG_ATR_BASE + 14 - -///////////////////////////////////////////////// -// DSP RX Regs -//////////////////////////////////////////////// -#define UE_REG_DSP_RX_FREQ UE_REG_SR_ADDR(0) -#define UE_REG_DSP_RX_SCALE_IQ UE_REG_SR_ADDR(1) // {scale_i,scale_q} -#define UE_REG_DSP_RX_DECIM_RATE UE_REG_SR_ADDR(2) // hb and decim rate -#define UE_REG_DSP_RX_DCOFFSET_I UE_REG_SR_ADDR(3) // Bit 31 high sets fixed offset mode, using lower 14 bits, // otherwise it is automatic -#define UE_REG_DSP_RX_DCOFFSET_Q UE_REG_SR_ADDR(4) // Bit 31 high sets fixed offset mode, using lower 14 bits -#define UE_REG_DSP_RX_MUX UE_REG_SR_ADDR(5) - -/////////////////////////////////////////////////// -// VITA RX CTRL regs -/////////////////////////////////////////////////// -// The following 3 are logically a single command register. -// They are clocked into the underlying fifo when time_ticks is written. -#define UE_REG_CTRL_RX_STREAM_CMD UE_REG_SR_ADDR(8) // {now, chain, num_samples(30) -#define UE_REG_CTRL_RX_TIME_SECS UE_REG_SR_ADDR(9) -#define UE_REG_CTRL_RX_TIME_TICKS UE_REG_SR_ADDR(10) -#define UE_REG_CTRL_RX_CLEAR_OVERRUN UE_REG_SR_ADDR(11) // write anything to clear overrun -#define UE_REG_CTRL_RX_VRT_HEADER UE_REG_SR_ADDR(12) // word 0 of packet. FPGA fills in packet counter -#define UE_REG_CTRL_RX_VRT_STREAM_ID UE_REG_SR_ADDR(13) // word 1 of packet. -#define UE_REG_CTRL_RX_VRT_TRAILER UE_REG_SR_ADDR(14) -#define UE_REG_CTRL_RX_NSAMPS_PER_PKT UE_REG_SR_ADDR(15) -#define UE_REG_CTRL_RX_NCHANNELS UE_REG_SR_ADDR(16) // 1 in basic case, up to 4 for vector sources - -///////////////////////////////////////////////// -// DSP TX Regs -//////////////////////////////////////////////// -#define UE_REG_DSP_TX_FREQ UE_REG_SR_ADDR(17) -#define UE_REG_DSP_TX_SCALE_IQ UE_REG_SR_ADDR(18) // {scale_i,scale_q} -#define UE_REG_DSP_TX_INTERP_RATE UE_REG_SR_ADDR(19) -#define UE_REG_DSP_TX_UNUSED UE_REG_SR_ADDR(20) -#define UE_REG_DSP_TX_MUX UE_REG_SR_ADDR(21) - -///////////////////////////////////////////////// -// VITA TX CTRL regs -//////////////////////////////////////////////// -#define UE_REG_CTRL_TX_NCHANNELS UE_REG_SR_ADDR(24) -#define UE_REG_CTRL_TX_CLEAR_UNDERRUN UE_REG_SR_ADDR(25) -#define UE_REG_CTRL_TX_REPORT_SID UE_REG_SR_ADDR(26) -#define UE_REG_CTRL_TX_POLICY UE_REG_SR_ADDR(27) - -#define UE_FLAG_CTRL_TX_POLICY_WAIT (0x1 << 0) -#define UE_FLAG_CTRL_TX_POLICY_NEXT_PACKET (0x1 << 1) -#define UE_FLAG_CTRL_TX_POLICY_NEXT_BURST (0x1 << 2) - -///////////////////////////////////////////////// -// VITA49 64 bit time (write only) -//////////////////////////////////////////////// - /*! - * \brief Time 64 flags - * - * 
-   *
-   *    3                   2                   1
-   *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
-   * +-----------------------------------------------------------+-+-+
-   * |                                                           |S|P|
-   * +-----------------------------------------------------------+-+-+
-   *
-   * P - PPS edge selection (0=negedge, 1=posedge, default=0)
-   * S - Source (0=sma, 1=mimo, 0=default)
-   *
-   *
- */ -#define UE_REG_TIME64_SECS UE_REG_SR_ADDR(28) // value to set absolute secs to on next PPS -#define UE_REG_TIME64_TICKS UE_REG_SR_ADDR(29) // value to set absolute ticks to on next PPS -#define UE_REG_TIME64_FLAGS UE_REG_SR_ADDR(30) // flags - see chart above -#define UE_REG_TIME64_IMM UE_REG_SR_ADDR(31) // set immediate (0=latch on next pps, 1=latch immediate, default=0) -#define UE_REG_TIME64_TPS UE_REG_SR_ADDR(31) // clock ticks per second (counter rollover) - -//pps flags (see above) -#define UE_FLAG_TIME64_PPS_NEGEDGE (0 << 0) -#define UE_FLAG_TIME64_PPS_POSEDGE (1 << 0) -#define UE_FLAG_TIME64_PPS_SMA (0 << 1) -#define UE_FLAG_TIME64_PPS_MIMO (1 << 1) - -#define UE_FLAG_TIME64_LATCH_NOW 1 -#define UE_FLAG_TIME64_LATCH_NEXT_PPS 0 - -#endif - -- cgit v1.2.3 From b43a1a9d5e01566457d9c9ee478d13e899a46e77 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 9 Nov 2010 19:23:17 -0800 Subject: usrp-e100: moved kernel header to lib dir, remove the header check, default enable to false --- host/include/linux/usrp_e.h | 91 -------------------------- host/lib/usrp/usrp_e100/CMakeLists.txt | 10 +-- host/lib/usrp/usrp_e100/include/linux/usrp_e.h | 91 ++++++++++++++++++++++++++ host/lib/usrp/usrp_e100/usrp_e100_impl.cpp | 2 +- 4 files changed, 95 insertions(+), 99 deletions(-) delete mode 100644 host/include/linux/usrp_e.h create mode 100644 host/lib/usrp/usrp_e100/include/linux/usrp_e.h diff --git a/host/include/linux/usrp_e.h b/host/include/linux/usrp_e.h deleted file mode 100644 index 4c6a5dd89..000000000 --- a/host/include/linux/usrp_e.h +++ /dev/null @@ -1,91 +0,0 @@ - -/* - * Copyright (C) 2010 Ettus Research, LLC - * - * Written by Philip Balister - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef __USRP_E_H -#define __USRP_E_H - -#include -#include - -struct usrp_e_ctl16 { - __u32 offset; - __u32 count; - __u16 buf[20]; -}; - -struct usrp_e_ctl32 { - __u32 offset; - __u32 count; - __u32 buf[10]; -}; - -/* SPI interface */ - -#define UE_SPI_TXONLY 0 -#define UE_SPI_TXRX 1 - -/* Defines for spi ctrl register */ -#define UE_SPI_CTRL_TXNEG (1<<10) -#define UE_SPI_CTRL_RXNEG (1<<9) - -#define UE_SPI_PUSH_RISE 0 -#define UE_SPI_PUSH_FALL UE_SPI_CTRL_TXNEG -#define UE_SPI_LATCH_RISE 0 -#define UE_SPI_LATCH_FALL UE_SPI_CTRL_RXNEG - -struct usrp_e_spi { - __u8 readback; - __u32 slave; - __u32 data; - __u32 length; - __u32 flags; -}; - -struct usrp_e_i2c { - __u8 addr; - __u32 len; - __u8 data[]; -}; - -#define USRP_E_IOC_MAGIC 'u' -#define USRP_E_WRITE_CTL16 _IOW(USRP_E_IOC_MAGIC, 0x20, struct usrp_e_ctl16) -#define USRP_E_READ_CTL16 _IOWR(USRP_E_IOC_MAGIC, 0x21, struct usrp_e_ctl16) -#define USRP_E_WRITE_CTL32 _IOW(USRP_E_IOC_MAGIC, 0x22, struct usrp_e_ctl32) -#define USRP_E_READ_CTL32 _IOWR(USRP_E_IOC_MAGIC, 0x23, struct usrp_e_ctl32) -#define USRP_E_SPI _IOWR(USRP_E_IOC_MAGIC, 0x24, struct usrp_e_spi) -#define USRP_E_I2C_READ _IOWR(USRP_E_IOC_MAGIC, 0x25, struct usrp_e_i2c) -#define USRP_E_I2C_WRITE _IOW(USRP_E_IOC_MAGIC, 0x26, struct usrp_e_i2c) -#define USRP_E_GET_RB_INFO _IOR(USRP_E_IOC_MAGIC, 0x27, struct usrp_e_ring_buffer_size_t) -#define USRP_E_GET_COMPAT_NUMBER _IO(USRP_E_IOC_MAGIC, 0x28) - -#define USRP_E_COMPAT_NUMBER 1 - -/* Flag defines */ -#define RB_USER (1<<0) -#define RB_KERNEL (1<<1) -#define RB_OVERRUN (1<<2) -#define RB_DMA_ACTIVE (1<<3) -#define RB_USER_PROCESS (1<<4) - -struct ring_buffer_info { - int flags; - int len; -}; - -struct usrp_e_ring_buffer_size_t { - int num_pages_rx_flags; - int num_rx_frames; - int num_pages_tx_flags; - int num_tx_frames; -}; - -#endif diff --git a/host/lib/usrp/usrp_e100/CMakeLists.txt b/host/lib/usrp/usrp_e100/CMakeLists.txt index 97a3d5d9a..66c87e0d8 100644 --- a/host/lib/usrp/usrp_e100/CMakeLists.txt +++ b/host/lib/usrp/usrp_e100/CMakeLists.txt @@ -22,24 +22,20 @@ ######################################################################## MESSAGE(STATUS "Configuring USRP-E100 support...") -INCLUDE(CheckIncludeFileCXX) -CHECK_INCLUDE_FILE_CXX(linux/usrp_e.h HAVE_LINUX_USRP_E_H) - -SET(ENABLE_USRP_E TRUE) - IF(DEFINED ENABLE_USRP_E100) IF(ENABLE_USRP_E100) MESSAGE(STATUS "USRP-E100 support enabled by configure flag") ELSE(ENABLE_USRP_E100) MESSAGE(STATUS "USRP-E100 support disabled by configure flag") ENDIF(ENABLE_USRP_E100) -ELSE(DEFINED ENABLE_USRP_E100) #not defined: automatic enabling of component - SET(ENABLE_USRP_E100 ${HAVE_LINUX_USRP_E_H}) +ELSE(DEFINED ENABLE_USRP_E100) #not defined: automatic disabling of component + SET(ENABLE_USRP_E100 FALSE) ENDIF(DEFINED ENABLE_USRP_E100) SET(ENABLE_USRP_E100 ${ENABLE_USRP_E100} CACHE BOOL "enable USRP-E100 support") IF(ENABLE_USRP_E100) MESSAGE(STATUS " Building USRP-E100 support.") + INCLUDE_DIRECTORIES(${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/include) LIBUHD_APPEND_SOURCES( ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/clock_ctrl.cpp ${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/clock_ctrl.hpp diff --git a/host/lib/usrp/usrp_e100/include/linux/usrp_e.h b/host/lib/usrp/usrp_e100/include/linux/usrp_e.h new file mode 100644 index 000000000..4c6a5dd89 --- /dev/null +++ b/host/lib/usrp/usrp_e100/include/linux/usrp_e.h @@ -0,0 +1,91 @@ + +/* + * Copyright (C) 2010 Ettus Research, LLC + * + * Written by Philip Balister + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __USRP_E_H +#define __USRP_E_H + +#include +#include + +struct usrp_e_ctl16 { + __u32 offset; + __u32 count; + __u16 buf[20]; +}; + +struct usrp_e_ctl32 { + __u32 offset; + __u32 count; + __u32 buf[10]; +}; + +/* SPI interface */ + +#define UE_SPI_TXONLY 0 +#define UE_SPI_TXRX 1 + +/* Defines for spi ctrl register */ +#define UE_SPI_CTRL_TXNEG (1<<10) +#define UE_SPI_CTRL_RXNEG (1<<9) + +#define UE_SPI_PUSH_RISE 0 +#define UE_SPI_PUSH_FALL UE_SPI_CTRL_TXNEG +#define UE_SPI_LATCH_RISE 0 +#define UE_SPI_LATCH_FALL UE_SPI_CTRL_RXNEG + +struct usrp_e_spi { + __u8 readback; + __u32 slave; + __u32 data; + __u32 length; + __u32 flags; +}; + +struct usrp_e_i2c { + __u8 addr; + __u32 len; + __u8 data[]; +}; + +#define USRP_E_IOC_MAGIC 'u' +#define USRP_E_WRITE_CTL16 _IOW(USRP_E_IOC_MAGIC, 0x20, struct usrp_e_ctl16) +#define USRP_E_READ_CTL16 _IOWR(USRP_E_IOC_MAGIC, 0x21, struct usrp_e_ctl16) +#define USRP_E_WRITE_CTL32 _IOW(USRP_E_IOC_MAGIC, 0x22, struct usrp_e_ctl32) +#define USRP_E_READ_CTL32 _IOWR(USRP_E_IOC_MAGIC, 0x23, struct usrp_e_ctl32) +#define USRP_E_SPI _IOWR(USRP_E_IOC_MAGIC, 0x24, struct usrp_e_spi) +#define USRP_E_I2C_READ _IOWR(USRP_E_IOC_MAGIC, 0x25, struct usrp_e_i2c) +#define USRP_E_I2C_WRITE _IOW(USRP_E_IOC_MAGIC, 0x26, struct usrp_e_i2c) +#define USRP_E_GET_RB_INFO _IOR(USRP_E_IOC_MAGIC, 0x27, struct usrp_e_ring_buffer_size_t) +#define USRP_E_GET_COMPAT_NUMBER _IO(USRP_E_IOC_MAGIC, 0x28) + +#define USRP_E_COMPAT_NUMBER 1 + +/* Flag defines */ +#define RB_USER (1<<0) +#define RB_KERNEL (1<<1) +#define RB_OVERRUN (1<<2) +#define RB_DMA_ACTIVE (1<<3) +#define RB_USER_PROCESS (1<<4) + +struct ring_buffer_info { + int flags; + int len; +}; + +struct usrp_e_ring_buffer_size_t { + int num_pages_rx_flags; + int num_rx_frames; + int num_pages_tx_flags; + int num_tx_frames; +}; + +#endif diff --git a/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp b/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp index 73cb1f285..1ff135eac 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp @@ -51,7 +51,7 @@ static device_addrs_t usrp_e100_find(const device_addr_t &hint){ //device node not provided, assume its 0 if (not hint.has_key("node")){ device_addr_t new_addr = hint; - new_addr["node"] = "/dev/usrp_e1000"; + new_addr["node"] = "/dev/usrp_e0"; return usrp_e100_find(new_addr); } -- cgit v1.2.3 From 3aba990a4f35c0bb58f037897f3100be77f517c1 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Tue, 9 Nov 2010 20:10:25 -0800 Subject: usrp-e100: add header path for the utils directory as well --- host/utils/CMakeLists.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/host/utils/CMakeLists.txt b/host/utils/CMakeLists.txt index a9148de6d..39f5257af 100644 --- a/host/utils/CMakeLists.txt +++ b/host/utils/CMakeLists.txt @@ -18,6 +18,9 @@ ######################################################################## # Utilities that get installed into the runtime path ######################################################################## +#TODO needed by USRP-E100 utils, whats the best way to handle this +INCLUDE_DIRECTORIES(${CMAKE_SOURCE_DIR}/lib/usrp/usrp_e100/include) + ADD_EXECUTABLE(uhd_find_devices uhd_find_devices.cpp) TARGET_LINK_LIBRARIES(uhd_find_devices uhd) -- cgit v1.2.3 From 3e695d1c0026383fd0509da8e4ebbf5ce5dd1fa3 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 10 Nov 2010 10:09:40 -0800 Subject: fixed string constants find and replace typo --- host/lib/usrp/usrp_e100/usrp_e100_impl.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp b/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp index 1ff135eac..8e40458d5 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp @@ -82,11 +82,11 @@ static device::sptr usrp_e100_make(const device_addr_t &device_addr){ //-- 1) The compatibility number matches. //-- 2) The hash in the hash-file matches. //------------------------------------------------------------------ - static const char *hash_file_path = "/tmp/usrp_e100100_hash"; + static const char *hash_file_path = "/tmp/usrp_e100_hash"; //extract the fpga path for usrp-e std::string usrp_e100_fpga_image = find_image_path( - device_addr.has_key("fpga")? device_addr["fpga"] : "usrp_e100100_fpga.bin" + device_addr.has_key("fpga")? device_addr["fpga"] : "usrp_e100_fpga.bin" ); //calculate a hash of the fpga file -- cgit v1.2.3 From 57a2fa2e0654226c8a13c7eddad2fcdb43f72703 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 10 Nov 2010 10:30:41 -0800 Subject: usrp-e100: added empty eeprom for eeprom get property --- host/lib/usrp/usrp_e100/mboard_impl.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/host/lib/usrp/usrp_e100/mboard_impl.cpp b/host/lib/usrp/usrp_e100/mboard_impl.cpp index 2d5d028e6..e45d7c5a0 100644 --- a/host/lib/usrp/usrp_e100/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e100/mboard_impl.cpp @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -107,6 +108,10 @@ void usrp_e100_impl::mboard_get(const wax::obj &key_, wax::obj &val){ val = _tx_subdev_spec; return; + case MBOARD_PROP_EEPROM_MAP: + val = mboard_eeprom_t(); + return; + default: UHD_THROW_PROP_GET_ERROR(); } } -- cgit v1.2.3 From a724f4b7262c6da6d24dccdbd64e08da61cb87fc Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 10 Nov 2010 16:48:02 -0800 Subject: usrp-e100: implemented wrapper for i2c device node + ioctls, implemented e100 eeprom map --- host/include/uhd/usrp/mboard_eeprom.hpp | 3 +- host/lib/usrp/mboard_eeprom.cpp | 77 +++++++++++++++++++++++++++ host/lib/usrp/usrp_e100/mboard_impl.cpp | 10 +++- host/lib/usrp/usrp_e100/usrp_e100_iface.cpp | 82 +++++++++++++++++++++++++++-- host/lib/usrp/usrp_e100/usrp_e100_iface.hpp | 7 +++ 5 files changed, 172 insertions(+), 7 deletions(-) diff --git a/host/include/uhd/usrp/mboard_eeprom.hpp b/host/include/uhd/usrp/mboard_eeprom.hpp index 530b177be..52363b95c 100644 --- a/host/include/uhd/usrp/mboard_eeprom.hpp +++ b/host/include/uhd/usrp/mboard_eeprom.hpp @@ -37,7 +37,8 @@ namespace uhd{ namespace usrp{ //! Possible EEPROM maps types enum map_type{ MAP_N100, - MAP_B000 + MAP_B000, + MAP_E100 }; //! Make a new empty mboard eeprom diff --git a/host/lib/usrp/mboard_eeprom.cpp b/host/lib/usrp/mboard_eeprom.cpp index 661030aa7..444057ad9 100644 --- a/host/lib/usrp/mboard_eeprom.cpp +++ b/host/lib/usrp/mboard_eeprom.cpp @@ -22,6 +22,7 @@ #include #include #include +#include using namespace uhd; using namespace uhd::usrp; @@ -171,6 +172,80 @@ static void store_b000(const mboard_eeprom_t &mb_eeprom, i2c_iface &iface){ string_to_bytes(mb_eeprom["name"], NAME_MAX_LEN) ); } +/*********************************************************************** + * Implementation of E100 load/store + **********************************************************************/ +static const boost::uint8_t E100_EEPROM_ADDR = 0x51; + +struct e100_eeprom_map{ + unsigned int device_vendor; + unsigned char revision; + unsigned char content; + unsigned char fab_revision[8]; + unsigned char env_var[16]; + unsigned char env_setting[64]; + unsigned char serial[10]; + unsigned char name[NAME_MAX_LEN]; +}; + +template static const byte_vector_t to_bytes(const T &item){ + return byte_vector_t( + reinterpret_cast(&item), + reinterpret_cast(&item)+sizeof(item) + ); +} + +static void load_e100(mboard_eeprom_t &mb_eeprom, i2c_iface &iface){ + const size_t num_bytes = offsetof(e100_eeprom_map, fab_revision); + byte_vector_t map_bytes = iface.read_eeprom(E100_EEPROM_ADDR, 0, num_bytes); + e100_eeprom_map map; std::memcpy(&map, &map_bytes[0], map_bytes.size()); + + mb_eeprom["device_vendor"] = boost::lexical_cast(map.device_vendor); + mb_eeprom["revision"] = boost::lexical_cast(map.revision); + mb_eeprom["content"] = boost::lexical_cast(map.content); + + #define load_e100_string_xx(key) mb_eeprom[#key] = bytes_to_string(iface.read_eeprom( \ + E100_EEPROM_ADDR, offsetof(e100_eeprom_map, key), sizeof(e100_eeprom_map::key) \ + )); + + load_e100_string_xx(fab_revision); + load_e100_string_xx(env_var); + load_e100_string_xx(env_setting); + load_e100_string_xx(serial); + load_e100_string_xx(fab_revision); + load_e100_string_xx(name); +} + +static void store_e100(const mboard_eeprom_t &mb_eeprom, i2c_iface &iface){ + + if (mb_eeprom.has_key("device_vendor")) iface.write_eeprom( + E100_EEPROM_ADDR, offsetof(e100_eeprom_map, device_vendor), + to_bytes(boost::lexical_cast(mb_eeprom["device_vendor"])) + ); + + if (mb_eeprom.has_key("revision")) iface.write_eeprom( + E100_EEPROM_ADDR, offsetof(e100_eeprom_map, revision), + to_bytes(boost::lexical_cast(mb_eeprom["revision"])) + ); + + if (mb_eeprom.has_key("content")) iface.write_eeprom( + E100_EEPROM_ADDR, offsetof(e100_eeprom_map, content), + to_bytes(boost::lexical_cast(mb_eeprom["content"])) + ); + + #define store_e100_string_xx(key) if (mb_eeprom.has_key(#key)) iface.write_eeprom( \ + E100_EEPROM_ADDR, offsetof(e100_eeprom_map, key), \ + string_to_bytes(mb_eeprom[#key], sizeof(e100_eeprom_map::key)) \ + ); + + store_e100_string_xx(fab_revision); + store_e100_string_xx(env_var); + store_e100_string_xx(env_setting); + store_e100_string_xx(serial); + store_e100_string_xx(fab_revision); + store_e100_string_xx(name); + +} /*********************************************************************** * Implementation of mboard eeprom @@ -183,6 +258,7 @@ mboard_eeprom_t::mboard_eeprom_t(i2c_iface &iface, map_type map){ switch(map){ case MAP_N100: load_n100(*this, iface); break; case MAP_B000: load_b000(*this, iface); break; + case MAP_E100: load_e100(*this, iface); break; } } @@ -190,5 +266,6 @@ void mboard_eeprom_t::commit(i2c_iface &iface, map_type map){ switch(map){ case MAP_N100: store_n100(*this, iface); break; case MAP_B000: store_b000(*this, iface); break; + case MAP_E100: store_e100(*this, iface); break; } } diff --git a/host/lib/usrp/usrp_e100/mboard_impl.cpp b/host/lib/usrp/usrp_e100/mboard_impl.cpp index e45d7c5a0..9c6317b94 100644 --- a/host/lib/usrp/usrp_e100/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e100/mboard_impl.cpp @@ -21,7 +21,6 @@ #include #include #include -#include #include #include @@ -109,7 +108,7 @@ void usrp_e100_impl::mboard_get(const wax::obj &key_, wax::obj &val){ return; case MBOARD_PROP_EEPROM_MAP: - val = mboard_eeprom_t(); + val = _iface->mb_eeprom; return; default: UHD_THROW_PROP_GET_ERROR(); @@ -159,6 +158,13 @@ void usrp_e100_impl::mboard_set(const wax::obj &key, const wax::obj &val){ )); return; + case MBOARD_PROP_EEPROM_MAP: + // Step1: commit the map, writing only those values set. + // Step2: readback the entire eeprom map into the iface. + val.as().commit(_iface->get_i2c_dev_iface(), mboard_eeprom_t::MAP_E100); + _iface->mb_eeprom = mboard_eeprom_t(_iface->get_i2c_dev_iface(), mboard_eeprom_t::MAP_E100); + return; + default: UHD_THROW_PROP_SET_ERROR(); } } diff --git a/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp b/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp index ad623777e..40c7afabb 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp @@ -22,10 +22,74 @@ #include //ioctl structures and constants #include #include //mutex +#include +#include #include using namespace uhd; +using namespace uhd::usrp; +/*********************************************************************** + * I2C device node implementation wrapper + **********************************************************************/ +class i2c_dev_iface : public i2c_iface{ +public: + i2c_dev_iface(const std::string &node){ + if ((_node_fd = ::open(node.c_str(), O_RDWR)) < 0){ + throw std::runtime_error("Failed to open " + node); + } + } + + ~i2c_dev_iface(void){ + ::close(_node_fd); + } + + void write_i2c(boost::uint8_t addr, const byte_vector_t &bytes){ + byte_vector_t rw_bytes(bytes); + + //setup the message + i2c_msg msg; + msg.addr = addr; + msg.flags = 0; + msg.len = bytes.size(); + msg.buf = &rw_bytes.front(); + + //setup the data + i2c_rdwr_ioctl_data data; + data.msgs = &msg; + data.nmsgs = 1; + + //call the ioctl + UHD_ASSERT_THROW(::ioctl(_node_fd, I2C_RDWR, &data) >= 0); + } + + byte_vector_t read_i2c(boost::uint8_t addr, size_t num_bytes){ + byte_vector_t bytes(num_bytes); + + //setup the message + i2c_msg msg; + msg.addr = addr; + msg.flags = I2C_M_RD; + msg.len = bytes.size(); + msg.buf = &bytes.front(); + + //setup the data + i2c_rdwr_ioctl_data data; + data.msgs = &msg; + data.nmsgs = 1; + + //call the ioctl + UHD_ASSERT_THROW(::ioctl(_node_fd, I2C_RDWR, &data) >= 0); + + return bytes; + } + +private: int _node_fd; +}; + +/*********************************************************************** + * USRP-E100 interface implementation + **********************************************************************/ class usrp_e100_iface_impl : public usrp_e100_iface{ public: @@ -36,13 +100,15 @@ public: /******************************************************************* * Structors ******************************************************************/ - usrp_e100_iface_impl(const std::string &node){ + usrp_e100_iface_impl(const std::string &node): + _i2c_dev_iface(i2c_dev_iface("/dev/i2c-3")) + { //open the device node and check file descriptor if ((_node_fd = ::open(node.c_str(), O_RDWR)) < 0){ - throw std::runtime_error(str( - boost::format("Failed to open %s") % node - )); + throw std::runtime_error("Failed to open " + node); } + + mb_eeprom = mboard_eeprom_t(get_i2c_dev_iface(), mboard_eeprom_t::MAP_E100); } ~usrp_e100_iface_impl(void){ @@ -63,6 +129,13 @@ public: } } + /******************************************************************* + * I2C device node interface + ******************************************************************/ + i2c_iface &get_i2c_dev_iface(void){ + return _i2c_dev_iface; + } + /******************************************************************* * Peek and Poke ******************************************************************/ @@ -183,6 +256,7 @@ public: private: int _node_fd; + i2c_dev_iface _i2c_dev_iface; boost::mutex _ctrl_mutex; }; diff --git a/host/lib/usrp/usrp_e100/usrp_e100_iface.hpp b/host/lib/usrp/usrp_e100/usrp_e100_iface.hpp index b52209a42..12283fb52 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_iface.hpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_iface.hpp @@ -19,6 +19,7 @@ #define INCLUDED_USRP_E100_IFACE_HPP #include +#include #include #include #include @@ -63,6 +64,9 @@ public: */ virtual void ioctl(int request, void *mem) = 0; + //! Get the I2C interface for the I2C device node + virtual uhd::i2c_iface &get_i2c_dev_iface(void) = 0; + /*! * Write a register (32 bits) * \param addr the address @@ -107,6 +111,9 @@ public: size_t num_bits, bool readback ) = 0; + + //motherboard eeprom map structure + uhd::usrp::mboard_eeprom_t mb_eeprom; }; #endif /* INCLUDED_USRP_E100_IFACE_HPP */ -- cgit v1.2.3 From f2d5f0b12bd0e9a29d22a93a6aaa4565021583e4 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 11 Nov 2010 09:20:26 -0800 Subject: usrp_eXXX: Only include i2c-dev.h due to struct definition conflicts. --- host/lib/usrp/usrp_e100/usrp_e100_iface.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp b/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp index 40c7afabb..50ff4a8ff 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp @@ -23,7 +23,6 @@ #include #include //mutex #include -#include #include using namespace uhd; -- cgit v1.2.3 From 791401f979aae3e5909ed0a7a06e176f0c16cd5a Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 11 Nov 2010 10:41:05 -0800 Subject: usrp-e100: split vendor/device field for eeprom, rename fab rev to model, fixed char cast (to treat like integer) --- host/lib/usrp/mboard_eeprom.cpp | 35 ++++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/host/lib/usrp/mboard_eeprom.cpp b/host/lib/usrp/mboard_eeprom.cpp index 444057ad9..842ee01e3 100644 --- a/host/lib/usrp/mboard_eeprom.cpp +++ b/host/lib/usrp/mboard_eeprom.cpp @@ -178,10 +178,11 @@ static void store_b000(const mboard_eeprom_t &mb_eeprom, i2c_iface &iface){ static const boost::uint8_t E100_EEPROM_ADDR = 0x51; struct e100_eeprom_map{ - unsigned int device_vendor; + boost::uint16_t vendor; + boost::uint16_t device; unsigned char revision; unsigned char content; - unsigned char fab_revision[8]; + unsigned char model[8]; unsigned char env_var[16]; unsigned char env_setting[64]; unsigned char serial[10]; @@ -196,41 +197,46 @@ template static const byte_vector_t to_bytes(const T &item){ } static void load_e100(mboard_eeprom_t &mb_eeprom, i2c_iface &iface){ - const size_t num_bytes = offsetof(e100_eeprom_map, fab_revision); + const size_t num_bytes = offsetof(e100_eeprom_map, model); byte_vector_t map_bytes = iface.read_eeprom(E100_EEPROM_ADDR, 0, num_bytes); e100_eeprom_map map; std::memcpy(&map, &map_bytes[0], map_bytes.size()); - mb_eeprom["device_vendor"] = boost::lexical_cast(map.device_vendor); - mb_eeprom["revision"] = boost::lexical_cast(map.revision); - mb_eeprom["content"] = boost::lexical_cast(map.content); + mb_eeprom["vendor"] = boost::lexical_cast(map.vendor); + mb_eeprom["device"] = boost::lexical_cast(map.device); + mb_eeprom["revision"] = boost::lexical_cast(unsigned(map.revision)); + mb_eeprom["content"] = boost::lexical_cast(unsigned(map.content)); #define load_e100_string_xx(key) mb_eeprom[#key] = bytes_to_string(iface.read_eeprom( \ E100_EEPROM_ADDR, offsetof(e100_eeprom_map, key), sizeof(e100_eeprom_map::key) \ )); - load_e100_string_xx(fab_revision); + load_e100_string_xx(model); load_e100_string_xx(env_var); load_e100_string_xx(env_setting); load_e100_string_xx(serial); - load_e100_string_xx(fab_revision); load_e100_string_xx(name); } static void store_e100(const mboard_eeprom_t &mb_eeprom, i2c_iface &iface){ - if (mb_eeprom.has_key("device_vendor")) iface.write_eeprom( - E100_EEPROM_ADDR, offsetof(e100_eeprom_map, device_vendor), - to_bytes(boost::lexical_cast(mb_eeprom["device_vendor"])) + if (mb_eeprom.has_key("vendor")) iface.write_eeprom( + E100_EEPROM_ADDR, offsetof(e100_eeprom_map, vendor), + to_bytes(boost::lexical_cast(mb_eeprom["vendor"])) + ); + + if (mb_eeprom.has_key("device")) iface.write_eeprom( + E100_EEPROM_ADDR, offsetof(e100_eeprom_map, device), + to_bytes(boost::lexical_cast(mb_eeprom["device"])) ); if (mb_eeprom.has_key("revision")) iface.write_eeprom( E100_EEPROM_ADDR, offsetof(e100_eeprom_map, revision), - to_bytes(boost::lexical_cast(mb_eeprom["revision"])) + byte_vector_t(1, boost::lexical_cast(mb_eeprom["revision"])) ); if (mb_eeprom.has_key("content")) iface.write_eeprom( E100_EEPROM_ADDR, offsetof(e100_eeprom_map, content), - to_bytes(boost::lexical_cast(mb_eeprom["content"])) + byte_vector_t(1, boost::lexical_cast(mb_eeprom["content"])) ); #define store_e100_string_xx(key) if (mb_eeprom.has_key(#key)) iface.write_eeprom( \ @@ -238,11 +244,10 @@ static void store_e100(const mboard_eeprom_t &mb_eeprom, i2c_iface &iface){ string_to_bytes(mb_eeprom[#key], sizeof(e100_eeprom_map::key)) \ ); - store_e100_string_xx(fab_revision); + store_e100_string_xx(model); store_e100_string_xx(env_var); store_e100_string_xx(env_setting); store_e100_string_xx(serial); - store_e100_string_xx(fab_revision); store_e100_string_xx(name); } -- cgit v1.2.3 From 926fd69de88725f14c34062a81969a4a833a7f61 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 11 Nov 2010 11:07:39 -0800 Subject: usrp_e100: added byteswapping calls to vendor and device (its NBO) --- host/lib/usrp/mboard_eeprom.cpp | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/host/lib/usrp/mboard_eeprom.cpp b/host/lib/usrp/mboard_eeprom.cpp index 842ee01e3..70f4664a0 100644 --- a/host/lib/usrp/mboard_eeprom.cpp +++ b/host/lib/usrp/mboard_eeprom.cpp @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -201,8 +202,8 @@ static void load_e100(mboard_eeprom_t &mb_eeprom, i2c_iface &iface){ byte_vector_t map_bytes = iface.read_eeprom(E100_EEPROM_ADDR, 0, num_bytes); e100_eeprom_map map; std::memcpy(&map, &map_bytes[0], map_bytes.size()); - mb_eeprom["vendor"] = boost::lexical_cast(map.vendor); - mb_eeprom["device"] = boost::lexical_cast(map.device); + mb_eeprom["vendor"] = boost::lexical_cast(uhd::ntohx(map.vendor)); + mb_eeprom["device"] = boost::lexical_cast(uhd::ntohx(map.device)); mb_eeprom["revision"] = boost::lexical_cast(unsigned(map.revision)); mb_eeprom["content"] = boost::lexical_cast(unsigned(map.content)); @@ -221,12 +222,12 @@ static void store_e100(const mboard_eeprom_t &mb_eeprom, i2c_iface &iface){ if (mb_eeprom.has_key("vendor")) iface.write_eeprom( E100_EEPROM_ADDR, offsetof(e100_eeprom_map, vendor), - to_bytes(boost::lexical_cast(mb_eeprom["vendor"])) + to_bytes(uhd::htonx(boost::lexical_cast(mb_eeprom["vendor"]))) ); if (mb_eeprom.has_key("device")) iface.write_eeprom( E100_EEPROM_ADDR, offsetof(e100_eeprom_map, device), - to_bytes(boost::lexical_cast(mb_eeprom["device"])) + to_bytes(uhd::htonx(boost::lexical_cast(mb_eeprom["device"]))) ); if (mb_eeprom.has_key("revision")) iface.write_eeprom( -- cgit v1.2.3 From be3f1411c5c2ba7714b1531418a57f3be06829bf Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 11 Nov 2010 11:27:01 -0800 Subject: usrp-e100: add serial and name checks to the usrp-e100 discovery routine --- host/lib/usrp/usrp_e100/usrp_e100_impl.cpp | 27 ++++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp b/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp index 8e40458d5..13d31e423 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp @@ -32,13 +32,6 @@ using namespace uhd; using namespace uhd::usrp; namespace fs = boost::filesystem; -/*********************************************************************** - * Helper Functions - **********************************************************************/ -static std::string abs_path(const std::string &file_path){ - return fs::system_complete(fs::path(file_path)).file_string(); -} - /*********************************************************************** * Discovery **********************************************************************/ @@ -59,8 +52,24 @@ static device_addrs_t usrp_e100_find(const device_addr_t &hint){ if (fs::exists(hint["node"])){ device_addr_t new_addr; new_addr["type"] = "usrp-e"; - new_addr["node"] = abs_path(hint["node"]); - usrp_e100_addrs.push_back(new_addr); + new_addr["node"] = fs::system_complete(fs::path(hint["node"])).file_string(); + try{ + usrp_e100_iface::sptr iface = usrp_e100_iface::make(new_addr["node"]); + new_addr["name"] = iface->mb_eeprom["name"]; + new_addr["serial"] = iface->mb_eeprom["serial"]; + if ( + (not hint.has_key("name") or hint["name"] == new_addr["name"]) and + (not hint.has_key("serial") or hint["serial"] == new_addr["serial"]) + ){ + usrp_e100_addrs.push_back(new_addr); + } + } + catch(const std::exception &e){ + uhd::warning::post( + std::string("Ignoring discovered device\n") + + e.what() + ); + } } return usrp_e100_addrs; -- cgit v1.2.3 From 309964637e5eac309a6d9d36300a14a4235f34fb Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Thu, 11 Nov 2010 14:41:21 -0800 Subject: usrp_e : Add missing header file. --- host/lib/usrp/usrp_e100/usrp_e100_impl.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp b/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp index 13d31e423..a3e03056a 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include -- cgit v1.2.3 From 862a3f264671a133d9ff7e5b39d707d105a1dd45 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 17 Nov 2010 11:11:37 -0800 Subject: usrp e100 : Add i2c header back. --- host/lib/usrp/usrp_e100/usrp_e100_iface.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp b/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp index 50ff4a8ff..40c7afabb 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp @@ -23,6 +23,7 @@ #include #include //mutex #include +#include #include using namespace uhd; -- cgit v1.2.3 From 27e128ea70249bf4a79c6957fab14a3c4cad75f8 Mon Sep 17 00:00:00 2001 From: Philip Balister Date: Wed, 17 Nov 2010 11:13:31 -0800 Subject: usrp e100 : Add sleep after loading module. After loading the module, we need to wait until /dev/usrp_e0 is available before proceeding. --- host/lib/usrp/usrp_e100/usrp_e100_impl.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp b/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp index a3e03056a..40ea56466 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp @@ -123,6 +123,7 @@ static device::sptr usrp_e100_make(const device_addr_t &device_addr){ if (fpga_compat_num != USRP_E_COMPAT_NUM or loaded_hash != fpga_hash){ iface.reset(); usrp_e100_load_fpga(usrp_e100_fpga_image); + sleep(1); ///\todo do this better one day. std::cout << boost::format("re-Opening USRP-E on %s") % node << std::endl; iface = usrp_e100_iface::make(node); try{std::ofstream(hash_file_path) << fpga_hash;}catch(...){} -- cgit v1.2.3 From 13ae4786e091d5581baf31c9967dca822ef15e39 Mon Sep 17 00:00:00 2001 From: Nick Foster Date: Mon, 22 Nov 2010 18:26:54 -0800 Subject: E100: clock sync implemented. --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 26 ++++++++++++++++++++++++++ host/lib/usrp/usrp_e100/clock_ctrl.hpp | 15 +++++++++++++++ host/lib/usrp/usrp_e100/mboard_impl.cpp | 30 +++++++++++++++++++++++++++++- host/lib/usrp/usrp_e100/usrp_e100_impl.hpp | 5 ++++- 4 files changed, 74 insertions(+), 2 deletions(-) diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index e99560540..1fb1a7125 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -208,6 +208,32 @@ public: this->send_reg(0x197); this->latch_regs(); } + + /*********************************************************************** + * Clock reference control + **********************************************************************/ + void use_internal_ref(void) { + _ad9522_regs.enable_ref2 = 1; + _ad9522_regs.enable_ref1 = 0; + _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF2; + _ad9522_regs.enb_auto_ref_switchover = ad9522_regs_t::ENB_AUTO_REF_SWITCHOVER_MANUAL; + this->send_reg(0x01C); + } + + void use_external_ref(void) { + _ad9522_regs.enable_ref2 = 0; + _ad9522_regs.enable_ref1 = 1; + _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF1; + _ad9522_regs.enb_auto_ref_switchover = ad9522_regs_t::ENB_AUTO_REF_SWITCHOVER_MANUAL; + this->send_reg(0x01C); + } + + void use_auto_ref(void) { + _ad9522_regs.enable_ref2 = 1; + _ad9522_regs.enable_ref1 = 1; + _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF1; + _ad9522_regs.enb_auto_ref_switchover = ad9522_regs_t::ENB_AUTO_REF_SWITCHOVER_AUTO; + } private: usrp_e100_iface::sptr _iface; diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.hpp b/host/lib/usrp/usrp_e100/clock_ctrl.hpp index 0ae68728e..d613d1473 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.hpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.hpp @@ -82,6 +82,21 @@ public: * \param enb true to enable */ virtual void enable_tx_dboard_clock(bool enb) = 0; + + /*! + * Use the internal TCXO reference + */ + virtual void use_internal_ref(void) = 0; + + /*! + * Use the external SMA reference + */ + virtual void use_external_ref(void) = 0; + + /*! + * Use external if available, internal otherwise + */ + virtual void use_auto_ref(void) = 0; }; diff --git a/host/lib/usrp/usrp_e100/mboard_impl.cpp b/host/lib/usrp/usrp_e100/mboard_impl.cpp index 9c6317b94..03c4385aa 100644 --- a/host/lib/usrp/usrp_e100/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e100/mboard_impl.cpp @@ -39,8 +39,31 @@ void usrp_e100_impl::mboard_init(void){ //init the clock config _clock_config.ref_source = clock_config_t::REF_AUTO; _clock_config.pps_source = clock_config_t::PPS_SMA; + _clock_config.pps_polarity = clock_config_t::PPS_NEG; - //TODO poke the clock config regs + update_clock_config(); +} + +void usrp_e100_impl::update_clock_config(void){ + boost::uint32_t pps_flags = 0; + + //translate pps polarity enums + switch(_clock_config.pps_polarity){ + case clock_config_t::PPS_POS: pps_flags |= UE_FLAG_TIME64_PPS_POSEDGE; break; + case clock_config_t::PPS_NEG: pps_flags |= UE_FLAG_TIME64_PPS_NEGEDGE; break; + default: throw std::runtime_error("unhandled clock configuration pps polarity"); + } + + //set the pps flags + _iface->poke32(UE_REG_TIME64_FLAGS, pps_flags); + + //clock source ref 10mhz + switch(_clock_config.ref_source){ + case clock_config_t::REF_AUTO: _clock_ctrl->use_auto_ref(); + case clock_config_t::REF_INT: _clock_ctrl->use_internal_ref(); + case clock_config_t::REF_SMA: _clock_ctrl->use_external_ref(); + default: throw std::runtime_error("unhandled clock configuration ref source"); + } } /*********************************************************************** @@ -164,6 +187,11 @@ void usrp_e100_impl::mboard_set(const wax::obj &key, const wax::obj &val){ val.as().commit(_iface->get_i2c_dev_iface(), mboard_eeprom_t::MAP_E100); _iface->mb_eeprom = mboard_eeprom_t(_iface->get_i2c_dev_iface(), mboard_eeprom_t::MAP_E100); return; + + case MBOARD_PROP_CLOCK_CONFIG: + _clock_config = val.as(); + update_clock_config(); + return; default: UHD_THROW_PROP_SET_ERROR(); } diff --git a/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp b/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp index fe60ac0be..de158ea5e 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp @@ -102,7 +102,6 @@ private: //configuration shadows uhd::clock_config_t _clock_config; - //TODO otw type recv/send //ad9522 clock control usrp_e100_clock_ctrl::sptr _clock_ctrl; @@ -159,6 +158,10 @@ private: void tx_codec_get(const wax::obj &, wax::obj &); void tx_codec_set(const wax::obj &, const wax::obj &); wax_obj_proxy::sptr _rx_codec_proxy, _tx_codec_proxy; + + //clock control functions and settings + void init_clock_config(void); + void update_clock_config(void); }; #endif /* INCLUDED_USRP_E100_IMPL_HPP */ -- cgit v1.2.3