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author | Matt Ettus <matt@ettus.com> | 2011-03-16 16:50:33 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2011-03-16 16:50:33 -0700 |
commit | 226ca69c6c2c230fd0f1f398d9176d28522b7b59 (patch) | |
tree | 1cc54335f08abcae5cff0db720ce2ce7f6023c57 | |
parent | b357b627fb3f519408ca38ebadc9f4ae6d57de80 (diff) | |
download | uhd-226ca69c6c2c230fd0f1f398d9176d28522b7b59.tar.gz uhd-226ca69c6c2c230fd0f1f398d9176d28522b7b59.tar.bz2 uhd-226ca69c6c2c230fd0f1f398d9176d28522b7b59.zip |
u1e: use icarus verilog for lint
-rwxr-xr-x | usrp2/top/u1e/core_compile | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/usrp2/top/u1e/core_compile b/usrp2/top/u1e/core_compile new file mode 100755 index 000000000..fb1b2a854 --- /dev/null +++ b/usrp2/top/u1e/core_compile @@ -0,0 +1,2 @@ +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1e_core.v 2>&1 + |