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authormattprost <matt.prost@ni.com>2019-12-16 14:43:34 -0600
committerBrent Stapleton <brent.stapleton@ettus.com>2019-12-17 10:13:06 -0800
commitc4d9c9abb2e2e9895b0f2d793208fee021f35f5f (patch)
treed453e04c85188d5ae58f444a9fc82dcae31a0300
parentab305a906f0809e79d765da504618c0bbaa1d8cf (diff)
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tools: typo in x3x0 dpdk fpga_funcverif test
-rwxr-xr-xtools/gr-usrptest/apps/usrp_fpga_funcverif.py6
1 files changed, 3 insertions, 3 deletions
diff --git a/tools/gr-usrptest/apps/usrp_fpga_funcverif.py b/tools/gr-usrptest/apps/usrp_fpga_funcverif.py
index ecaf9b4bc..22dc9bd7d 100755
--- a/tools/gr-usrptest/apps/usrp_fpga_funcverif.py
+++ b/tools/gr-usrptest/apps/usrp_fpga_funcverif.py
@@ -694,8 +694,8 @@ FUNCVERIF_SETTINGS = {
{'--rx_rate': 184.32e6, 'master_clock_rate': '184.32e6', '--channels': '0,1'},
],
},
- 'x3x0_dpdk': {
- '--args': "type=x300,addr={addr},second_addr={second_addr},master_clock_rate={master_clock_rate},{args}",
+ 'x3x0_dpdk': {
+ '--args': "type=x300,addr={addr},second_addr={second_addr},master_clock_rate={master_clock_rate},{args}",
'--seq-threshold': 0,
'--drop-threshold': 0,
'--underrun-threshold': 100,
@@ -710,7 +710,7 @@ FUNCVERIF_SETTINGS = {
{'--rx_rate': 200e6, 'master_clock_rate': '200e6', '--channels': '0,1'},
{'--rx_rate': 184.32e6, 'master_clock_rate': '184.32e6', '--channels': '0,1'},
],
- }
+ },
'e320_1gige': {
'--args': "type=e3xx,addr={addr},master_clock_rate={master_clock_rate},{args}",
'--seq-threshold': 0,