From c4d9c9abb2e2e9895b0f2d793208fee021f35f5f Mon Sep 17 00:00:00 2001 From: mattprost Date: Mon, 16 Dec 2019 14:43:34 -0600 Subject: tools: typo in x3x0 dpdk fpga_funcverif test --- tools/gr-usrptest/apps/usrp_fpga_funcverif.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/gr-usrptest/apps/usrp_fpga_funcverif.py b/tools/gr-usrptest/apps/usrp_fpga_funcverif.py index ecaf9b4bc..22dc9bd7d 100755 --- a/tools/gr-usrptest/apps/usrp_fpga_funcverif.py +++ b/tools/gr-usrptest/apps/usrp_fpga_funcverif.py @@ -694,8 +694,8 @@ FUNCVERIF_SETTINGS = { {'--rx_rate': 184.32e6, 'master_clock_rate': '184.32e6', '--channels': '0,1'}, ], }, - 'x3x0_dpdk': { - '--args': "type=x300,addr={addr},second_addr={second_addr},master_clock_rate={master_clock_rate},{args}", + 'x3x0_dpdk': { + '--args': "type=x300,addr={addr},second_addr={second_addr},master_clock_rate={master_clock_rate},{args}", '--seq-threshold': 0, '--drop-threshold': 0, '--underrun-threshold': 100, @@ -710,7 +710,7 @@ FUNCVERIF_SETTINGS = { {'--rx_rate': 200e6, 'master_clock_rate': '200e6', '--channels': '0,1'}, {'--rx_rate': 184.32e6, 'master_clock_rate': '184.32e6', '--channels': '0,1'}, ], - } + }, 'e320_1gige': { '--args': "type=e3xx,addr={addr},master_clock_rate={master_clock_rate},{args}", '--seq-threshold': 0, -- cgit v1.2.3