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| author | djepson1 <daniel.jepson@ni.com> | 2018-01-05 15:52:59 -0600 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2018-01-05 14:05:17 -0800 |
| commit | 476f888392f42a65ef0b91b63bea61163607adcd (patch) | |
| tree | 4cbb54d63ce84dba7364c0063cd29bf114213072 | |
| parent | 1398aaab348e1702f68977d773c7c7511132412f (diff) | |
| download | uhd-476f888392f42a65ef0b91b63bea61163607adcd.tar.gz uhd-476f888392f42a65ef0b91b63bea61163607adcd.tar.bz2 uhd-476f888392f42a65ef0b91b63bea61163607adcd.zip | |
jesd: mg bug fix: default state of the RX link is scrambled
Reviewed-by: Trung Trang <trung.tran@ettus.com>
| -rw-r--r-- | mpm/python/usrp_mpm/cores/nijesdcore.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/mpm/python/usrp_mpm/cores/nijesdcore.py b/mpm/python/usrp_mpm/cores/nijesdcore.py index 1cde45619..5d1f4e264 100644 --- a/mpm/python/usrp_mpm/cores/nijesdcore.py +++ b/mpm/python/usrp_mpm/cores/nijesdcore.py @@ -50,7 +50,7 @@ class NIMgJESDCore(object): self.cplls_used = 0 self.rx_lanes = 4 self.tx_lanes = 4 - self.bypass_descrambler = True + self.bypass_descrambler = False self.bypass_scrambler = True self.lmfc_divider = 20 # Number of FPGA clock cycles per LMFC period. self.tx_driver_swing = 0b1111 # See UG476, TXDIFFCTRL |