From 476f888392f42a65ef0b91b63bea61163607adcd Mon Sep 17 00:00:00 2001 From: djepson1 Date: Fri, 5 Jan 2018 15:52:59 -0600 Subject: jesd: mg bug fix: default state of the RX link is scrambled Reviewed-by: Trung Trang --- mpm/python/usrp_mpm/cores/nijesdcore.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mpm/python/usrp_mpm/cores/nijesdcore.py b/mpm/python/usrp_mpm/cores/nijesdcore.py index 1cde45619..5d1f4e264 100644 --- a/mpm/python/usrp_mpm/cores/nijesdcore.py +++ b/mpm/python/usrp_mpm/cores/nijesdcore.py @@ -50,7 +50,7 @@ class NIMgJESDCore(object): self.cplls_used = 0 self.rx_lanes = 4 self.tx_lanes = 4 - self.bypass_descrambler = True + self.bypass_descrambler = False self.bypass_scrambler = True self.lmfc_divider = 20 # Number of FPGA clock cycles per LMFC period. self.tx_driver_swing = 0b1111 # See UG476, TXDIFFCTRL -- cgit v1.2.3