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| author | sugandhagupta <sugandha.gupta@ettus.com> | 2017-05-03 16:25:33 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2017-12-22 15:03:52 -0800 |
| commit | 6a2a8bb2f7c7a58c39e83776c1b9fe6692b922ad (patch) | |
| tree | 38deae7853562251a78236d4b7e916cc22449f42 | |
| parent | a0ded71188aa96282736a9bc13a086b71f92d965 (diff) | |
| download | uhd-6a2a8bb2f7c7a58c39e83776c1b9fe6692b922ad.tar.gz uhd-6a2a8bb2f7c7a58c39e83776c1b9fe6692b922ad.tar.bz2 uhd-6a2a8bb2f7c7a58c39e83776c1b9fe6692b922ad.zip | |
mpm: fixed port expander connections
- reversed CLK-MAINREF-SEL0 and SEL1
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/n310.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/n310.py b/mpm/python/usrp_mpm/periph_manager/n310.py index 8cc33cc9c..1bf204218 100644 --- a/mpm/python/usrp_mpm/periph_manager/n310.py +++ b/mpm/python/usrp_mpm/periph_manager/n310.py @@ -48,8 +48,8 @@ class TCA6424(object): 'WB-CDCM-OD1', 'WB-CDCM-OD2', 'PWREN-CLK-MAINREF', - 'CLK-MAINREF-SEL0', 'CLK-MAINREF-SEL1', + 'CLK-MAINREF-SEL0', '12', '13', 'FPGA-GPIO-EN', |