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| author | Matt Ettus <matt@ettus.com> | 2011-04-14 15:35:31 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-05-26 17:31:22 -0700 |
| commit | e9a34b8bd51d639e08f31930266e3425de4f53b3 (patch) | |
| tree | 081672e112fe30359156d2378671ec0ab3367744 | |
| parent | 37cffdd35ab72551696a8d36c16d501b6d502ff1 (diff) | |
| download | uhd-e9a34b8bd51d639e08f31930266e3425de4f53b3.tar.gz uhd-e9a34b8bd51d639e08f31930266e3425de4f53b3.tar.bz2 uhd-e9a34b8bd51d639e08f31930266e3425de4f53b3.zip | |
u1p: need to declare wires
| -rw-r--r-- | usrp2/top/u1plus/u1plus_core.v | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index 6d6fa878c..76a15b271 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -62,6 +62,7 @@ module u1plus_core .in(set_data),.out(),.changed(global_reset)); reset_sync reset_sync(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(wb_rst)); + wire [15:0] test_len; // ///////////////////////////////////////////////////////////////////////////////////// // GPIF Slave to Wishbone Master |