From e9a34b8bd51d639e08f31930266e3425de4f53b3 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 14 Apr 2011 15:35:31 -0700 Subject: u1p: need to declare wires --- usrp2/top/u1plus/u1plus_core.v | 1 + 1 file changed, 1 insertion(+) diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v index 6d6fa878c..76a15b271 100644 --- a/usrp2/top/u1plus/u1plus_core.v +++ b/usrp2/top/u1plus/u1plus_core.v @@ -62,6 +62,7 @@ module u1plus_core .in(set_data),.out(),.changed(global_reset)); reset_sync reset_sync(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(wb_rst)); + wire [15:0] test_len; // ///////////////////////////////////////////////////////////////////////////////////// // GPIF Slave to Wishbone Master -- cgit v1.2.3