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| author | Wade Fife <wade.fife@ettus.com> | 2021-06-10 11:38:47 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2021-06-17 08:16:59 -0500 |
| commit | b85b796cbc1f897a69ded1f3ecfba8ec92684c11 (patch) | |
| tree | b10bb0281ae375ce64b290942c8e3e4446509576 /.gitignore | |
| parent | 648c70ae758ab1d15c7ec6cbe57672e8c27640cd (diff) | |
| download | uhd-b85b796cbc1f897a69ded1f3ecfba8ec92684c11.tar.gz uhd-b85b796cbc1f897a69ded1f3ecfba8ec92684c11.tar.bz2 uhd-b85b796cbc1f897a69ded1f3ecfba8ec92684c11.zip | |
fpga: tools: Put SIM_SRCS at end of compile order
VHDL depends on the compile order. This commit changes the order so
that SIM_SRCS are compiled last with ModelSim to avoid issues with
dependencies.
Diffstat (limited to '.gitignore')
0 files changed, 0 insertions, 0 deletions